Image sensing device

Abstract

The invention relates to an image sensing device. The image sensing device includes a plurality of unit pixels arranged in a row direction or a column direction of a pixel array. A first unit pixel in the plurality of unit pixels comprises a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel which are arranged in a 2 * 2 matrix; a grid-shaped isolation structure formed to surround the first unit pixel and disposed between the first to fourth sub-pixels; a first junction region formed to surround the first transistor region and disposed across the first sub-pixel and the second sub-pixel along a first side of the first unit pixel; and a second junction region formed to surround the second transistor region and disposed across the third sub-pixel and the fourth sub-pixel along a second side parallel to the first side. The length of the first side edge is equal to the length of a third side edge, perpendicular to the first side edge, of the first unit pixel.

Description

Technical Field

[0001] The technologies and implementations disclosed in this patent document generally relate to an image sensing device. Background Art

[0002] An image sensing device is a semiconductor device that is used to capture light of an optical image and convert it into an electrical signal for displaying the captured image and for further processing of the captured image. Recent developments in various industries and sectors, including the automotive, medical, computer, and communications industries, have created various requirements for high-performance image sensing devices in various electronic devices such as smartphones, digital cameras, game consoles, the Internet of Things (IoT), robots, security cameras, and medical micro cameras.

[0003] Image sensing devices can be roughly divided into CCD (charge coupled device) image sensing devices and CMOS (complementary metal oxide semiconductor) image sensing devices. CCD image sensing devices provide better image quality, but compared with CMOS image sensing devices, CCD image sensing devices tend to consume more power and have a larger size. CMOS image sensing devices are smaller in size and consume less power than CCD image sensing devices. In addition, by using CMOS manufacturing technology, CMOS image sensing devices and signal processing circuits can be integrated into a single chip, making it possible to miniaturize electronic devices while achieving a reduction in production costs. These characteristics make CMOS image sensing devices more suitable for implementation in mobile devices. Summary of the invention

[0004] Various embodiments of the disclosed technology are directed to an image sensing device including a symmetrical pixel array to selectively perform a phase difference detection auto focus (PDAF) function.

[0005] The disclosed technology may be implemented in some embodiments to provide an image sensing device capable of reducing its overall size while ensuring a sufficient transistor area.

[0006] According to one embodiment of the disclosed technology, an image sensing device may include a plurality of unit pixels arranged in a row direction or a column direction of a pixel array. A first unit pixel among the plurality of unit pixels may include: a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged in a (2×2) matrix; a grid-like isolation structure formed to surround the first unit pixel and arranged between the first sub-pixel and the fourth sub-pixel; a first junction region formed to surround a first transistor region and to span the first sub-pixel and the second sub-pixel along a first side of the first unit pixel; and a second junction region formed to surround a second transistor region and to span the third sub-pixel and the fourth sub-pixel along a second side parallel to the first side, wherein the length of the first side is equal to the length of a third side of the first unit pixel perpendicular to the first side.

[0007] In some implementations, each of the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel may include two photoelectric conversion elements disposed adjacent to each other and generating photocharges in response to incident light.

[0008] In some implementations, the two photoelectric conversion elements may be arranged adjacent to each other in a row direction or a column direction of the pixel array.

[0009] In some implementations, each of the first to fourth sub-pixels may include a transfer transistor respectively overlapping the two photoelectric conversion elements.

[0010] In some embodiments, each of the photoelectric conversion elements may include a deeply doped region in which impurities are doped to a first depth from a surface of a first unit pixel and a shallowly doped region in which impurities are doped to a second depth from the surface of the first unit pixel, wherein the second depth is closer to the surface of the first unit pixel than the first depth.

[0011] In some implementations, the first unit pixel may include: a first floating diffusion region disposed between the first sub-pixel and the third sub-pixel; and a second floating diffusion region disposed between the second sub-pixel and the fourth sub-pixel.

[0012] In some implementations, the first floating diffusion region and the second floating diffusion region may be arranged along a direction along which the first side extends.

[0013] In some implementations, the first transistor region may include a drive transistor and a select transistor; and the second transistor region includes a gain conversion transistor and a reset transistor.

[0014] In some implementations, each of the first to fourth sub-pixels may be formed in a square shape.

[0015] In some embodiments, a second unit pixel in contact with the first unit pixel may include: a third junction region, which is formed to surround a third transistor region and is arranged along a fifth side of the second unit pixel across a fifth sub-pixel and a sixth sub-pixel; and a fourth junction region, which is formed to surround a fourth transistor region and is arranged along a sixth side parallel to the fifth side across a seventh sub-pixel and an eighth sub-pixel, wherein the fifth side is in contact with a fourth side of the first unit pixel extending in a direction perpendicular to the first side.

[0016] In some implementations, the second unit pixel in contact with the first unit pixel may include a fifth sub-pixel, a sixth sub-pixel, a seventh sub-pixel, and an eighth sub-pixel arranged in a (2×2) matrix. Each of the fifth sub-pixel, the sixth sub-pixel, the seventh sub-pixel, and the eighth sub-pixel may include two photoelectric conversion elements. The photoelectric conversion elements included in each of the fifth sub-pixel, the sixth sub-pixel, the seventh sub-pixel, and the eighth sub-pixel may be arranged to be adjacent to each other in a direction perpendicular to the direction in which the photoelectric conversion elements included in each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are arranged.

[0017] In some implementations, the second unit pixel may further include: a third floating diffusion region, which is disposed between the fifth sub-pixel and the seventh sub-pixel; and a fourth floating diffusion region, which is disposed between the sixth sub-pixel and the eighth sub-pixel, wherein the third floating diffusion region and the fourth floating diffusion region are arranged along the direction in which the photoelectric conversion elements included in each of the fifth sub-pixel, the sixth sub-pixel, the seventh sub-pixel and the eighth sub-pixel are arranged.

[0018] In some implementations, the first transistor region can include a plurality of pixel transistors connected in parallel to each other.

[0019] In some implementations, the pixel transistor may include at least one of a drive transistor, a select transistor, a reset transistor, and a gain conversion transistor.

[0020] In some implementations, the first unit pixel may further include a ground region disposed at a center of the first unit pixel and configured to receive a ground voltage as an input.

[0021] In some implementations, the second transistor region can include a capacitive element.

[0022] In some implementations, the isolation structure may be formed as a trench structure extending from one surface of the semiconductor substrate toward another surface of the semiconductor substrate opposite to the one surface, and wherein the photoelectric conversion element is arranged in the semiconductor substrate.

[0023] In some implementations, the first junction region or the second junction region may be an impurity region extending from another surface of the semiconductor substrate facing the one surface or opposite to the one surface toward the one surface of the semiconductor substrate.

[0024] In some implementations, the first junction region or the second junction region may be formed to at least partially overlap the isolation structure.

[0025] In some implementations, a width of the first junction region or a width of the second junction region is smaller than a width of an isolation structure surrounding the first unit pixel.

[0026] It is to be understood that both the foregoing summary and the following detailed description of the disclosed technology are illustrative and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features and advantageous aspects of the disclosed technology will become apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0028] Figure 1 is a block diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0029] Figure 2 is a schematic diagram showing an example of a first unit pixel included in a pixel array based on some implementations of the disclosed technology.

[0030] Figure 3 is a cross-sectional view showing an example of a first unit pixel taken along a first cutting line based on some implementations of the disclosed technology.

[0031] Figure 4 is a schematic diagram showing an example of a first metal layer connected to a first unit pixel based on some implementations of the disclosed technology.

[0032] Figure 5is a circuit diagram showing an example of a first unit pixel based on some implementations of the disclosed technology.

[0033] Figure 6 is a layout diagram showing examples of first to fourth unit pixels based on some implementations of the disclosed technology. DETAILED DESCRIPTION

[0034] This patent document provides an implementation and example of an image sensing device that may be used in configuration to substantially solve one or more technical problems or engineering problems and alleviate limitations or disadvantages encountered in some other image sensing device designs. Some implementations of the disclosed technology relate to an image sensing device including a symmetrical pixel array to effectively perform a phase difference detection autofocus (PDAF) function. Some implementations of the disclosed technology relate to an image sensing device capable of ensuring a sufficient transistor area while reducing the overall size of the image sensing device. The disclosed technology can be implemented in some embodiments to solve the above-mentioned problems by providing an image sensing device that can improve operating characteristics when performing a phase difference detection autofocus (PDAF) function. The disclosed technology can be implemented in some embodiments to provide an image sensing device including unit pixels, each of which has the same row direction length and column direction length as each other, thereby increasing the degree of freedom in arranging these unit pixels. The disclosed technology can be implemented in some embodiments to provide an image sensing device capable of ensuring symmetry between (1) a pixel signal output from a unit pixel of a photoelectric conversion element adjacent to each other in the row direction of a pixel array and (2) another pixel signal output from a unit pixel of a photoelectric conversion element adjacent to each other in the column direction of a pixel array. In some implementations, the photoelectric conversion element can be configured to detect incident light and generate photocharges corresponding to the incident light.

[0035] Reference will now be made in detail to embodiments of the disclosed technology, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar components. Although the present disclosure allows for various modifications and alternative forms, specific embodiments thereof are illustrated by way of example in the accompanying drawings. However, the present disclosure should not be construed as being limited to the embodiments described herein.

[0036] In the following, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to a specific embodiment, but includes various modifications, equivalents and / or replacements of the embodiments. The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0037] Figure 1is a block diagram illustrating an example of an image sensing device ISD based on some implementations of the disclosed technology.

[0038] As will be referenced below Figure 1 As discussed in the illustrated example, the image sensing device ISD may perform an auto focus (AF) function and may generate phase difference data.

[0039] Reference Figure 1 , the image sensing device ISD in the illustrated example may include an imaging circuit 300 , an image sensor 100 , and a processor 200 .

[0040] The imaging circuit 300 may be a component that receives light. In some implementations, the imaging circuit 300 may include a lens 310 and a lens driver 320.

[0041] In one example, lens 310 may be a single lens. In another example, lens 310 may include a plurality of lenses.

[0042] The lens driver 320 may control the position of the lens 310 according to the control signal of the processor 200. As the position of the lens 310 is adjusted, the distance between the lens 310 and the target object (S) may also be adjusted.

[0043] The processor 200 may transmit a signal for adjusting the position of the lens 310 to the lens driver 320 based on a signal generated by the image sensor 100 .

[0044] The image sensor 100 may include a pixel array 110 , a correlated double sampler (CDS) 120 , an analog-to-digital converter (ADC) 130 , a buffer 140 , a row driver 150 , a timing generator 160 , a control register 170 , and a ramp signal generator 180 .

[0045] In some implementations, the pixel array 110 may include at least one unit pixel. In one embodiment, each unit pixel may include a sub-pixel and a transistor region.

[0046] At least one pair of photoelectric conversion elements included in the unit pixel may be arranged adjacent to each other in a row direction or a column direction of the pixel array. The photoelectric conversion element may generate photocharges corresponding to incident light.

[0047] In some implementations, a phase difference detection auto focus (PDAF) function may be performed using a signal generated by a pair of photoelectric conversion elements that are included in one unit pixel and are adjacent to each other.

[0048] The transistor region may include a plurality of transistors that generate an image signal or a phase difference signal based on photocharges generated in the photoelectric conversion element.

[0049] The photoelectric conversion element may provide an electric signal (eg, an image signal) corresponding to the generated charges to a correlated double sampler (CDS) 120 .

[0050] Light (eg, an optical signal) that passes through the lens 310 and is incident on the pixel array 110 may be converted into an electrical signal. The unit pixels may respectively generate electrical signals corresponding to the target object (S).

[0051] The correlated double sampler (CDS) 120 may sample and hold the electrical signal received from the pixel array 110. The correlated double sampler (CDS) 120 may perform a double sampling operation on a signal level generated based on incident light and a specific noise level, and thus may output a signal level corresponding to a difference between the sampling result signals.

[0052] An analog-to-digital converter (ADC) 130 may convert a received analog signal into a digital signal and may transmit the digital signal to a buffer 140 .

[0053] The buffer 140 may hold or latch the received digital signal and may sequentially output the latched digital signal to the processor 200. The buffer 140 may include a memory for holding the digital signal and a sense amplifier for amplifying the digital signal.

[0054] The row driver 150 may drive a plurality of unit pixels included in the pixel array 110 in response to an output signal of the timing generator 160 .

[0055] For example, the row driver 150 may generate a selection signal to select any one of the row lines. In addition, the row driver 150 may generate a signal (eg, a transfer transistor driving signal, a reset transistor driving signal, a selection transistor driving signal, etc.) to drive a transistor included in a unit pixel.

[0056] The timing generator 160 may control the row driver 150 so that the pixel array 110 may accumulate charges accumulated in response to incident light and temporarily store the accumulated charges or output an electrical signal corresponding to the charges to the outside of the pixel array 110 .

[0057] The timing generator 160 may control the correlated double sampler (CDS) 120 to sample and hold the electrical signal received from the pixel array 110 .

[0058] The control register 170 may generate a control signal based on a signal received from the processor 200 to control the buffer 140 , the timing generator 160 , and the ramp signal generator 180 .

[0059] The ramp signal generator 180 may generate a reference signal that enables an analog-to-digital converter (ADC) 130 to detect a signal in response to a control signal received from the timing generator 160 .

[0060] The processor 200 may receive the output signal of the buffer 140 as an input, so that the processor 200 may generate image data or phase difference data based on the received signal. In addition, the processor 200 may send a control signal for the lens driver 320 using the phase difference data.

[0061] The processor 200 may generate phase difference data for the target object (S) using signals respectively corresponding to a plurality of photoelectric conversion elements included in any unit pixel.

[0062] The processor 200 may generate phase data for the target object (S) by calculating signals generated by a plurality of photoelectric conversion elements included in one unit pixel.

[0063] If the distance between the lens 310 and the target object (S) is considered to be in the "in-focus position", the incident light beams that have reached the photoelectric conversion elements included in the unit pixels may have the same magnitude. Therefore, the signals detected by the photoelectric conversion elements included in one unit pixel may have the same magnitude. Therefore, when the distance between the lens 310 and the target object (S) satisfies the in-focus position, the phase data generated by the processor 200 may be the same.

[0064] On the other hand, when the distance between the lens 310 and the target object (S) does not satisfy the in-focus position, a difference between the paths of the incident light may occur in the horizontal direction or the vertical direction, so that the incident light beams reaching the photoelectric conversion element may have different intensities (e.g., magnitudes) from each other. That is, because the paths of the incident light beams reaching the photoelectric conversion element are different in the horizontal direction or the vertical direction, the intensities of the light reaching each photoelectric conversion element are different. Therefore, the signals detected by the photoelectric conversion elements included in one unit pixel may have different intensities.

[0065] If the distance between the lens 310 and the target object (S) does not satisfy the in-focus position, the processor 200 may calculate a phase difference between the phase data and other phase data, and thus may generate phase difference data.

[0066] The processor 200 may provide a control signal for the lens driver 320 based on the phase difference data, and may perform an auto focus function by adjusting the distance between the target object (S) and the lens 310 and the distance between the pixel array 110 and the lens 310 using the control signal.

[0067] Figure 2 Some implementations based on the disclosed technology are shown in Figure 1 FIG. 1 is a plan view of an example of a first unit pixel (PX1) in the pixel array 110 of FIG.

[0068] Reference Figure 2 , the pixel array 110 may include a plurality of unit pixels. Here, one unit pixel (eg, PX1) may be a minimum unit of a layout structure repeatedly arranged within the pixel array 110.

[0069] The pixel array may include an isolation structure (DI) disposed between a first unit pixel PX1 and another unit pixel adjacent to the first unit pixel PX1, and also disposed between sub-pixels (SP1-SP4) included in the first unit pixel PX1. For example, the isolation structure (DI) may include a first portion disposed between adjacent unit pixels (e.g., PX1 and another unit pixel adjacent to PX1) and a second portion disposed between adjacent sub-pixels (e.g., between SP1 and SP2, between SP2 and SP4, between SP4 and SP3, and between SP3 and SP1).

[0070] For example, the isolation structure (DI) may include a first portion having a grid shape within the pixel array and surrounding each unit pixel (e.g., the first unit pixel PX1) in the pixel array. In addition, the isolation structure (DI) may include a second portion disposed between the plurality of sub-pixels (SP1-SP4).

[0071] One sub-pixel (e.g., SP1) may be located in each grid area defined by an isolation structure (DI) including a horizontal line portion and a vertical line portion. In some implementations, the grid area defined by the isolation structure (DI) may be formed in a square shape in which a length in a row direction of the pixel array is the same as a length in a column direction of the pixel array.

[0072] The isolation structure (DI) may be a trench structure extending from one surface of the semiconductor substrate on which the pixel array is arranged toward another surface of the semiconductor substrate. In some implementations, the isolation structure (DI) may include an insulating material such as silicon oxide.

[0073] The first unit pixel PX1 may include first to fourth sub-pixels (SP1-SP4). Each sub-pixel (e.g., SP1) may include two photoelectric conversion elements (e.g., PD1L, PD1R) and a transfer transistor (e.g., TX1L, TX1R) formed to overlap the photoelectric conversion elements (e.g., PD1L, PD1R).

[0074] Each of the first to fourth sub-pixels ( SP1 - SP4 ) included in the first unit pixel PX1 may include a photoelectric conversion element (eg, PD1L, PD1R) arranged in a row direction of a pixel array.

[0075] The photoelectric conversion element (eg, PD1L, PD1R) and the transfer transistor (eg, TX1L, TX1R) included in each of the first to fourth sub-pixels (SP1-SP4) may be symmetrically arranged with respect to a row direction of the pixel array.

[0076] The image sensing device can generate phase difference data by comparing (1) pixel signals corresponding to the photoelectric conversion elements (PD1L, PD2L, PD3L, PD4L) located on the left side relative to the row direction of the pixel array with (2) pixel signals corresponding to the photoelectric conversion elements (PD1R, PD2R, PD3R, PD4R) located on the right side relative to the row direction of the pixel array.

[0077] The first unit pixel PX1 may include a first transistor region TR1 positioned along a first side of the first unit pixel PX1 and a second transistor region TR2 positioned along a second side parallel to the first side.

[0078] The first transistor region TR1 may include different transistors from the second transistor region TR2 .

[0079] For example, the first transistor region TR1 may include drive transistors (DX1, DX2) and selection transistors (SX1, SX2), and the second transistor region TR2 may include gain conversion transistors (DCGX1, DCGX2) and reset transistors (RX1, RX2).

[0080] The transistors included in the first transistor region TR1 may be arranged symmetrically with respect to the center of the first transistor region TR1. In addition, the transistors included in the second transistor region TR2 may be arranged symmetrically with respect to the center of the second transistor region TR2.

[0081] The driving transistors ( DX1 , DX2 ) disposed in the first transistor region TR1 may be connected in parallel to each other through a metal layer and may operate as one driving transistor.

[0082] Since the combination of the two driving transistors (DX1, DX2) operates as a single driving transistor, each driving transistor can have a larger gate area and noise can be reduced.

[0083] In addition, the selection transistors (SX1, SX2) may be connected to each other through a metal layer so that the selection transistors (SX1, SX2) may operate as a single selection transistor.

[0084] The gain conversion transistors (DCGX1, DCGX2) and the reset transistors (RX1, RX2) provided in the second transistor region TR2 may be respectively connected to each other to operate as a single transistor, and the parasitic capacitance of each transistor may be adjusted according to the connection relationship between these transistors.

[0085] In some implementations, the layout structure may be configured such that the unit pixel PX1 may include an additional capacitance element by arranging a dummy transistor instead of the second gain conversion transistor DCGX2 and the second reset transistor RX2 .

[0086] The first transistor region TR1 may be disposed across the first sub-pixel SP1 and the second sub-pixel SP2 , and the second transistor region TR2 may be disposed across the third sub-pixel SP3 and the fourth sub-pixel SP4 .

[0087] The first unit pixel PX1 may include a first junction region SI1 surrounding the first transistor region TR1 and a second junction region SI2 surrounding the second transistor region TR2 .

[0088] The first junction region SI1 and the second junction region SI2 may be impurity regions extending from the other surface of the semiconductor substrate including the photoelectric conversion element (eg, PD1L, PD1R) toward one surface of the semiconductor substrate opposite to the other surface.

[0089] In other words, the junction regions (eg, SI1 , SI2 ) and the isolation structure (DI) may be arranged to contact different surfaces of the semiconductor substrate.

[0090] In some implementations, at least a portion of the junction regions (eg, SI1 and SI2 ) may be arranged to overlap the isolation structure (DI).

[0091] The width of the junction region (e.g., SI1, SI2) may be smaller than the width of the isolation structure (DI) surrounding the unit pixel (e.g., PX1). The width of the junction region (SI1, SI2) may refer to the longer side of the region occupied by the junction region (SI1, SI2) in the row direction or column direction of the pixel array.

[0092] For example, Figure 2 As shown in , the width of the first junction region SI1 or the width of the second junction region SI2 may refer to the length in the row direction of the pixel array. The length of the first junction region SI1 or the length of the second junction region SI2 in the row direction of the pixel array may be shorter than the length of the isolation structure (DI) in the row direction of the pixel array.

[0093] Since the width of the junction region (eg, SI1, SI2) is formed smaller than the width of the isolation structure (DI) surrounding the unit pixel (eg, PX1), the junction region (eg, SI1, SI2) may be disposed in the unit pixel (eg, PX1).

[0094] The junction region (eg, SI1 ) may be disposed across adjacent sub-pixels (eg, SP1 , SP2 ).

[0095] In addition, the first unit pixel PX1 may include a plurality of floating diffusion regions ( FD1 , FD2 ) and a ground region (VSS) overlapping the isolation structure (DI).

[0096] The floating diffusion region (FD1, FD2) and the ground region (VSS) may be impurity-doped regions that contact the other surface of the semiconductor substrate in the same manner as the first and second junction regions SI1 and SI2.

[0097] The floating diffusion regions (FD1, FD2) and the ground region (VSS) may be arranged in a direction in which the first side of the first unit pixel PX1 extends (eg, a row direction of the pixel array).

[0098] The first floating diffusion region FD1 included in the first unit pixel PX1 may be electrically connected to the transfer transistor (TX1L, TX1R) included in the first sub-pixel SP1 and the transfer transistor (TX3L, TX3R) included in the third sub-pixel SP3. Therefore, the first floating diffusion region FD1 may receive photocharges from the photoelectric conversion element (PD1L, PD1R) included in the first sub-pixel SP1 and the photoelectric conversion element (PD3L, PD3R) included in the third sub-pixel SP3.

[0099] The second floating diffusion region FD2 included in the first unit pixel PX1 can be electrically connected to the transfer transistor (TX2L, TX2R) included in the second sub-pixel SP2 and the transfer transistor (TX4L, TX4R) included in the fourth sub-pixel SP4. Therefore, the second floating diffusion region FD2 can receive photocharges from the photoelectric conversion element (PD2L, PD2R) included in the second sub-pixel SP2 and the photoelectric conversion element (PD4L, PD4R) included in the fourth sub-pixel SP4.

[0100] The first unit pixel PX1 may have a square layout including four sides of the same length. For example, the length W1 of the first side of the first unit pixel PX1 may be equal to the length W3 of the third side of the first unit pixel PX1.

[0101] For example, the first side may be a side extending in the row direction of the pixel array, and the third side may be a side extending in the column direction of the pixel array. The first unit pixel PX1 may include sides having the same length in the row and column directions of the pixel array.

[0102] Figure 3 is a cross-sectional view 400 showing an example of a first unit pixel PX1 taken along a first cutting line AA′ based on some implementations of the disclosed technology.

[0103] Specifically, the vertical positions of the plurality of elements included in the first unit pixel PX1 are Figure 3 Shown in.

[0104] Reference Figure 3 400 , the image sensing device may include a plurality of photoelectric conversion elements (PD1R, PD3R) arranged in a semiconductor substrate SUB.

[0105] The semiconductor substrate SUB may include a surface and another surface facing the one surface or opposite to the one surface. For example, the semiconductor substrate SUB may be a single crystal silicon substrate. In some implementations, the semiconductor substrate SUB may be a P-type bulk substrate or an N-type bulk substrate. In some implementations, the semiconductor substrate SUB may be a substrate formed by growing a P-type epitaxial layer or an N-type epitaxial layer on a P-type bulk substrate. In some implementations, the semiconductor substrate SUB may be a substrate formed by growing a P-type epitaxial layer or an N-type epitaxial layer on an N-type bulk substrate. For ease of description, it is assumed that the semiconductor substrate SUB is a substrate formed by growing a P-type epitaxial layer on a P-type bulk substrate.

[0106] Each of the photoelectric conversion elements (PD1R, PD3R) may be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof. For ease of description, as an example, it is assumed that each of the photoelectric conversion elements (PD1R, PD3R) is a photodiode.

[0107] The photoelectric conversion element (PD1R, PD3R) may be formed as an N-type doped region in the semiconductor substrate SUB by an ion implantation process of implanting N-type ions. The photoelectric conversion element (PD1R, PD3R) may include a structure in which a plurality of doped regions are stacked in a vertical direction.

[0108] The photoelectric conversion elements (PD1R, PD3R) may be arranged across as large an area as possible to improve the light reception (Rx) efficiency of the unit pixel. The photoelectric conversion elements (PD1R, PD3R) may each output a signal corresponding to the incident light.

[0109] In some implementations, each of the plurality of photoelectric conversion elements may include a deeply doped region (PD1RD, PD3RD) and a shallowly doped region (PD1RS, PD3RS). The deeply doped region (PD1RD, PD3RD) and the shallowly doped region (PD1RS, PD3RS) may have a vertically stacked structure. In some implementations, the photoelectric conversion element PD1R may include a vertically stacked deeply doped region PD1RD and a shallowly doped region PD1RS, and the photoelectric conversion element PD3R may include a vertically stacked deeply doped region PD3RD and a shallowly doped region PD3RS. In some implementations, the term "shallowly doped region" may be used to refer to a doped region in which impurities are doped to a certain depth close to the surface of the region, and the term "deeply doped region" may be used to refer to a doped region in which impurities are doped to a depth deeper than the depth of the impurities in the shallowly doped region.

[0110] The shallow doped regions (PD1RS, PD3RS) may be disposed adjacent to the first floating diffusion region FD1 so that photo charges generated by the deeply doped regions (PD1RD, PD3RD) may be easily transferred to the first floating diffusion region FD1.

[0111] The first floating diffusion region FD1 may be a region formed by an ion implantation process of implanting N-type ions into the semiconductor substrate SUB, and may be a region for receiving photocharges generated by the photoelectric conversion element (PD1R, PD3R).

[0112] The photocharges generated by the photoelectric conversion elements (PD1R, PD3R) may be transferred to the first floating diffusion region FD1 through the transfer transistors (TX1R, TX3R).

[0113] Transfer transistors TX1R and TX3R may be arranged to overlap the photoelectric conversion elements PD1R and PD3R, respectively. In some implementations, transfer transistor TX1R may be arranged to overlap the photoelectric conversion element PD1R, and transfer transistor TX3R may be arranged to overlap the photoelectric conversion element PD3R.

[0114] Each of the transfer transistors TX1R and TX3R may include a gate formed to receive a transfer signal and a gate insulating layer formed to electrically isolate the gate and the semiconductor substrate SUB from each other. The gate may include a conductive material such as polysilicon or metal, and the gate insulating layer may include an insulating material such as silicon oxide.

[0115] The photocharges generated by the photoelectric conversion element (PD1R, PD3R) may be transferred to the first floating diffusion region FD1 according to the transfer signal applied to the transfer transistor (TX1R, TX3R). In some implementations, the photocharges generated by the photoelectric conversion element PD1R may be transferred to the first floating diffusion region FD1 according to the transfer signal applied to the transfer transistor TX1R, and the photocharges generated by the photoelectric conversion element PD3R may be transferred to the first floating diffusion region FD1 according to the transfer signal applied to the transfer transistor TX3R.

[0116] The first selection transistor SX1 may be disposed in a region (eg, a first transistor region) defined by the first junction region SI1 , and the first reset transistor RX1 may be disposed in a region (eg, a second transistor region) defined by the second junction region SI2 .

[0117] The first junction region SI1 and the second junction region SI2 may extend from the other surface of the semiconductor substrate SUB toward one surface of the semiconductor substrate SUB. The first junction region SI1 may be formed to electrically isolate an element (e.g., SX1) located in the first transistor region from other elements (e.g., FD1), and the second junction region SI2 may be formed to electrically isolate an element (e.g., RX1) located in the second transistor region from other elements (e.g., FD1).

[0118] In some implementations, the first and second junction regions SI1 and SI2 may be regions doped with P-type impurities on the semiconductor substrate SUB. Since the first and second junction regions SI1 and SI2 are formed, the influence of leakage current occurring in the transistor region may be reduced.

[0119] The first selection transistor SX1 may include a gate formed to receive a selection signal and a gate insulating layer formed to electrically isolate the gate and the semiconductor substrate SUB from each other. In addition, the first reset transistor RX1 may include a gate formed to receive a reset signal and a gate insulating layer formed to electrically isolate the gate and the semiconductor substrate SUB from each other.

[0120] The gate may include a conductive material such as polysilicon or metal, and the gate insulating layer may include an insulating material such as silicon oxide.

[0121] An isolation structure (DI) may be provided between adjacent photoelectric conversion elements (PD1R, PD3R).

[0122] The isolation structure (DI) may have a trench structure extending from one surface of the semiconductor substrate SUB toward another surface of the semiconductor substrate SUB. The isolation structure (DI) may optically and electrically isolate (or separate) adjacent photoelectric conversion elements from each other.

[0123] The isolation structure (DI) may extend in a direction perpendicular to one surface of the semiconductor substrate SUB and may include an insulating material such as silicon oxide or silicon nitride.

[0124] Figure 4 is a schematic diagram showing an example of a first metal layer M1 connected to a first unit pixel PX1 based on some implementations of the disclosed technology.

[0125] Reference Figure 4 , the metal layer M1 and the transistors (eg, DX1, SX1, etc.) may be connected through vertical vias.

[0126] Figure 4 An example of a portion of the first metal layer M1 is shown, and Figure 4 The layout structure of the semiconductor device may be different from the metal layers arranged in the actual semiconductor device.

[0127] exist Figure 4 In the figure, for ease of description, the metal layer connected to the transfer transistors (TX1L, TX1R, TX2L, TX2R, TX3L, TX3R, TX4L, TX4R) and the metal layer connected to the reset transistors (RX1, RX2) and the gain conversion transistors (DCGX1, DCGX2) are omitted.

[0128] In another example, a metal layer connected to the transfer transistors (TX1L, TX1R, TX2L, TX2R, TX3L, TX3R, TX4L, TX4R) or a metal layer connected to the reset transistors (RX1, RX2) and the gain conversion transistors (DCGX1, DCGX2) may be included in a metal layer set in another layer.

[0129] Reference Figure 4 , the first floating diffusion region FD1 and the second floating diffusion region FD2 may be electrically connected to each other through the first metal layer M1.

[0130] The first and second floating diffusion regions FD1 and FD2 connected to each other may be connected to the driving transistors (DX1, DX2) through the first metal layer M1. The first and second driving transistors DX1 and DX2 may operate as one driving transistor.

[0131] The first metal layer M1 may connect the selection transistors ( SX1 , SX2 ) to each other, and a combination of the selection transistors ( SX1 , SX2 ) may operate as a single selection transistor.

[0132] The first metal layer M1 may overlap the isolation structure (DI) and may be connected to the ground region VSS. The first metal layer M1 may be arranged to surround the first unit pixel (PX1), and a ground voltage may be applied to the ground region VSS, thereby reducing parasitic capacitance caused by the first metal layer M1.

[0133] Figure 5 is an equivalent circuit diagram 600 showing an example of a first unit pixel PX1 based on some implementations of the disclosed technology.

[0134] Figure 5 The circuit diagram of FIG. 1 shows a connection relationship between elements (eg, PD1L, TX1L, FD1, etc.) included in the first unit pixel PX1.

[0135] Reference Figure 5 , eight transfer transistors (TX1L-TX4R) are included in the first unit pixel PX1, and the photoelectric conversion elements (PD1L-PD4R) correspond to the transfer transistors (TX1L-TX4R), respectively.

[0136] A transfer control signal (e.g., TS1L) may be applied to the gate of each transfer transistor (e.g., TX1L). Depending on the voltage level of each transfer control signal (TS1L-TS4R), the charge generated by each photoelectric conversion element (PD1L-PD4R) may be transferred to the floating diffusion region (FD1, FD2) through the transfer transistor (TX1L-TX4R) corresponding to the photoelectric conversion element (PD1L-PD4R). In some implementations, depending on the voltage level of the transfer control signal TS1L, the charge generated by the photoelectric conversion element PD1L may be transferred to the floating diffusion region (FD1, FD2) through the transfer transistor TX1L corresponding to the photoelectric conversion element PD1L. Also in this manner, depending on the voltage level of the transfer control signal TS4R, the charge generated by the photoelectric conversion element PD4R may be transferred to the floating diffusion region through the transfer transistor TX4R corresponding to the photoelectric conversion element PD4R.

[0137] (FD1, FD2).

[0138] The first floating diffusion region FD1 connected to the four photoelectric conversion elements (PD1L-PD2R) can be connected to the second floating diffusion region FD2 connected to the other four photoelectric conversion elements (PD3L-PD4R). In other words, the first floating diffusion region FD1 and the second floating diffusion region FD2 can be shared by the eight photoelectric conversion elements (PD1L-PD4R).

[0139] The reset transistors (RX1, RX2) may be connected in parallel to each other and may be controlled by a reset control signal RS. The source / drain of the reset transistors (RX1, RX2) and the floating diffusion regions (FD1, FD2) may be connected to each other. In some implementations, the source / drain of the reset transistor RX1 may be connected to the floating diffusion region FD1, and the source / drain of the reset transistor RX2 may be connected to the floating diffusion region FD2.

[0140] The reset transistor (RX1, RX2) may remove charges from the floating diffusion region (FD1, FD2) and the photoelectric conversion element (PD1L-PD4R) connected to the floating diffusion region (FD1, FD2), and may reset the first unit pixel PX1 to the pixel voltage VDD.

[0141] In some implementations, whether to reset the first unit pixel PX1 may be determined according to a voltage level of a reset control signal RS applied to the reset transistor ( RX1 , RX2 ).

[0142] The driving transistors (DX1, DX2) may be connected in parallel to each other, and the floating diffusion regions (FD1, FD2) may be connected to gates of the driving transistors (DX1, DX2).

[0143] The floating diffusion regions (FD1, FD2) may be connected to gates of the drive transistors (DX1, DX2).

[0144] The drive transistor (DX1, DX2) can operate as a source follower transistor that amplifies a voltage change corresponding to the charge stored in the floating diffusion region (FD1, FD2). One end of the drive transistor (DX1, DX2) can be connected to the pixel voltage VDD, and the other end of the drive transistor (DX1, DX2) can be connected to the selection transistor (SX1, SX2).

[0145] The gain conversion transistors (DCGX1, DCGX2) may be connected between the floating diffusion regions (FD1, FD2) and the capacitive element CAP. In some implementations, the gain conversion transistor DCGX1 may be connected between the floating diffusion region FD1 and the capacitive element CAP, and the gain conversion transistor DCGX2 may be connected between the floating diffusion region FD2 and the capacitive element CAP.

[0146] The gain conversion transistors (DCGX1, DCGX2) may be connected in parallel to each other and may be controlled by a gain control signal DCS.

[0147] One end of the source / drain of the gain conversion transistor (DCGX1, DCGX2) may be connected to the floating diffusion region (FD1, FD2), and the other end of the source / drain of the gain conversion transistor (DCGX1, DCGX2) may be connected to the capacitance element CAP.

[0148] In some implementations, whether the floating diffusion regions FD1 and FD2 are connected to the capacitive element CAP may be determined according to whether the gain conversion transistors DCGX1 and DCGX2 are activated or deactivated.

[0149] For example, when the gain conversion transistor (DCGX1, DCGX2) is activated, the floating diffusion region (FD1, FD2) and the capacitance element CAP may be connected to each other, so that the actual capacity of the floating diffusion region (FD1, FD2) may be increased.

[0150] When the actual capacity of the floating diffusion region (FD1, FD2) increases, the floating diffusion region (FD1, FD2) can be unsaturated even if the amount of photocharge transferred from the photoelectric conversion element (PD1L-PD4R) increases. Therefore, in a high-illuminance environment where a large amount of photocharge appears in the photoelectric conversion element (PD1L-PD4R), the operating characteristics can be improved.

[0151] In a low illumination environment, the gain conversion transistors (DCGX1, DCGX2) can be disabled. When the amount of photocharge generated in the photoelectric conversion element (PD1L-PD4R) is small, the sensitivity of the floating diffusion area (FD1, FD2) can be increased by separating the floating diffusion area (FD1, FD2) and the capacitive element CAP from each other.

[0152] The selection transistors (SX1, SX2) may be connected in parallel to each other to operate as one transistor.

[0153] The selection transistor (SX1, SX2) can determine whether to output a pixel signal (Vout) corresponding to the voltage change amplified by the driving transistor (DX1, DX2). Whether the selection transistor (SX1, SX2) outputs the pixel signal (Vout) can be determined according to the voltage level of the selection control signal SS applied to the gate electrode of the selection transistor (SX1, SX2).

[0154] The output pixel signal (Vout) may be processed by components (eg, image sensor 100 ) included in an image sensing device (eg, ISD) to generate a signal corresponding to incident light.

[0155] Figure 6 is a layout diagram showing an example of first to fourth unit pixels PX1 to PX4 based on some implementations of the disclosed technology.

[0156] Reference Figure 6 , each of the unit pixels PX1 to PX4 based on some implementations of the disclosed technology may be formed in a square shape including two vertical sides having the same length.

[0157] The second unit pixel PX2 and the third unit pixel PX3 contacting the first unit pixel PX1 may have a layout structure obtained by rotating the layout of the first unit pixel PX1 by 90°.

[0158] The second unit pixel PX2 may be isolated or separated from other adjacent unit pixels by an isolation structure (DI). The second unit pixel PX2 may have a square shape in which a row direction length of the pixel array is the same as a column direction length of the pixel array.

[0159] The second unit pixel PX2 may include fifth to eighth subpixels SP5 to SP8. Each subpixel (e.g., SP5) may include two photoelectric conversion elements (e.g., PD5B, PD5T) and a transfer transistor (e.g., TX5B, TX5T) formed to overlap the photoelectric conversion elements (e.g., PD5B, PD5T).

[0160] The sub-pixels included in the second unit pixel PX2 may include photoelectric conversion elements (eg, PD5B, PD5T) arranged in a column direction of the pixel array.

[0161] The photoelectric conversion elements (eg, PD5B, PD5T) and the transfer transistors (eg, TX5B, TX5T) included in the fifth to eighth subpixels SP5 to SP8 may be respectively arranged symmetrically with respect to a column direction of the pixel array.

[0162] Figure 1 The image sensing device (ISD) can generate phase difference data by comparing the pixel signals corresponding to the photoelectric conversion elements (PD5B, PD6B, PD7B, PD8B) located on the lower side relative to the column direction of the pixel array with the pixel signals corresponding to the photoelectric conversion elements (PD5T, PD6T, PD7T, PD8T) located on the upper side relative to the column direction of the pixel array.

[0163] The second unit pixel PX2 may include a third transistor region TR3 positioned along a fifth side of the second unit pixel PX2 and a fourth transistor region TR4 positioned along a sixth side parallel to the fifth side. The fifth side of the second unit pixel PX2 may contact the fourth side of the first unit pixel PX1. The fourth side of the first unit pixel PX1 may be a side of the first unit pixel PX1 facing the third side or opposite to the third side (see Figure 1 ).

[0164] The third transistor region TR3 may extend in a direction perpendicular to the first transistor region TR1 of the first unit pixel PX1. In some implementations, the first transistor region TR1 may extend along a row direction of the pixel array, and the third transistor region TR3 may extend along a column direction of the pixel array.

[0165] For example, the third transistor region TR3 may include drive transistors (DX3, DX4) and selection transistors (SX3, SX4), and the fourth transistor region TR4 may include gain conversion transistors (DCGX3, DCGX4) and reset transistors (RX3, RX4).

[0166] The transistors included in the third transistor region TR3 and the transistors included in the fourth transistor region TR4 may be arranged in symmetrical shapes, respectively.

[0167] In some implementations, the layout structure of the unit pixel PX2 may be configured such that the unit pixel PX2 includes an additional capacitance element by disposing a dummy transistor instead of the fourth gain conversion transistor DCGX4 and the fourth reset transistor RX4 .

[0168] The third transistor region TR3 may be disposed across the fifth sub-pixel SP5 and the sixth sub-pixel SP6 , and the fourth transistor region TR4 may be disposed across the seventh sub-pixel SP7 to the eighth sub-pixel SP8 .

[0169] The second unit pixel PX2 may include a third junction region SI3 surrounding the third transistor region TR3 and a fourth junction region SI4 surrounding the fourth transistor region TR4 .

[0170] The third and fourth junction regions SI3 and SI4 may include impurities and may extend from the other surface of the semiconductor substrate including the photoelectric conversion element (eg, PD5B, PD5T) toward one surface of the semiconductor substrate opposite to the other surface.

[0171] The junction regions (eg, SI3 , SI4 ) and the isolation structure (DI) may be arranged to contact different sides of the semiconductor substrate.

[0172] In some implementations, at least a portion of the junction regions (eg, SI3 and SI4 ) may be arranged to overlap the isolation structure (DI).

[0173] As described above, the width of the junction region (eg, SI3, SI4) may be smaller than the width of the isolation structure (DI) surrounding the unit pixel (eg, PX2). Figure 6As shown, a length of the third junction region SI3 or a length of the fourth junction region SI4 in the column direction of the pixel array may be shorter than a column direction length of an isolation structure (DI) surrounding a unit pixel (eg, PX2).

[0174] In addition, the second unit pixel PX2 may include a plurality of floating diffusion regions ( FD3 , FD4 ) and a ground region VSS overlapping the isolation structure (DI).

[0175] The floating diffusion region (FD3, FD4) and the ground region VSS may be arranged in a direction in which the fifth side of the second unit pixel PX2 is elongated (eg, a column direction of the pixel array).

[0176] The second unit pixel PX2 may include a square layout having a fifth side, a sixth side, a seventh side, and an eighth side. The fifth side of the second unit pixel PX2 may be parallel to the sixth side of the second unit pixel PX2, and the seventh side of the second unit pixel PX2 may be parallel to the eighth side of the second unit pixel PX2. In addition, the fifth side of the second unit pixel PX2 may be perpendicular to the seventh and eighth sides of the second unit pixel PX2.

[0177] The fifth side may be a side extending along the column direction of the pixel array, and the seventh side may be a side extending along the row direction of the pixel array. As described above, the fifth side of the second unit pixel PX2 may contact the fourth side of the first unit pixel PX1.

[0178] The third unit pixel PX3 may have the same layout as the second unit pixel PX2. The fourth unit pixel PX4 may have the same layout as the first unit pixel PX1.

[0179] The image sensing device ISD may include not only photoelectric conversion elements adjacent to each other in the row direction (e.g., PD1L, PD1R), but also photoelectric conversion elements adjacent to each other in the column direction (e.g., PD5B, PD5T), thereby performing a phase difference detection autofocus (PDAF) function in all directions including the up, down, left, and right directions of the pixel array.

[0180] When the layout of each unit pixel is not a square layout, it may be difficult to make the pixel array include both photoelectric conversion elements adjacent to each other in the row direction (for example, PD1L, PD1R) and photoelectric conversion elements adjacent to each other in the column direction (for example, PD5B, PD5T), and it may also be difficult to fully ensure the area where the photoelectric conversion elements will be placed and the area where the transistors will be placed.

[0181] In addition, since each unit pixel has a square layout and adjacent unit pixels have the same layout when rotated by 90°, noise that may be generated due to such a layout can be reduced.

[0182] Since the noise generated by this layout is reduced, the asymmetry between the phase difference detection in the row direction of the pixel array and the phase difference detection in the column direction of the pixel array can be reduced or minimized.

[0183] In other words, the image sensing device can ensure symmetry between a pixel signal output from a unit pixel (e.g., PX1) including photoelectric conversion elements (e.g., PD1L, PD1R) adjacent to each other in the row direction and a pixel signal output from another unit pixel (e.g., PX2) including photoelectric conversion elements (e.g., PD5B, PD5T) adjacent to each other in the column direction, thereby minimizing the amount of noise caused by the directional difference of the phase difference detection autofocus (PDAF) function.

[0184] As is apparent from the above description, an image sensing device based on some implementations of the disclosed technology may improve operating characteristics when performing a phase difference detection auto focus (PDAF) function.

[0185] An image sensing device based on some implementations of the disclosed technology may be formed with unit pixels each of which has the same row-direction length and column-direction length as each other, thereby increasing the degree of freedom in arranging the unit pixels.

[0186] An image sensing device based on some implementations of the disclosed technology can ensure symmetry between a pixel signal output from a unit pixel of photoelectric conversion elements that are adjacent to each other in the row direction of a pixel array and another pixel signal output from a unit pixel of photoelectric conversion elements that are adjacent to each other in the column direction of the pixel array.

[0187] The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized through the above-mentioned patent documents.

[0188] Although a number of illustrative embodiments have been described, it should be understood that modifications and / or enhancements to the disclosed embodiments and other embodiments may be devised based on what is described and / or illustrated in this patent document.

[0189] CROSS-REFERENCE TO RELATED APPLICATIONS

[0190] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2023-0106416, filed on August 14, 2023, the disclosure of which is incorporated by reference in its entirety as a part of the disclosure of this patent document.

Claims

1. An image sensing device, comprising: a plurality of unit pixels, the plurality of unit pixels generating electrical signals based on incident light and arranged in a row direction or a column direction of a pixel array, The plurality of unit pixels include a first unit pixel, wherein the first unit pixel includes: A first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged in a 2×2 matrix; an isolation structure, the isolation structure comprising a first portion and a second portion, the first portion being formed to surround the first unit pixel, and the second portion being disposed between adjacent sub-pixels among the first to fourth sub-pixels; a first junction region formed to surround a first transistor region and disposed across the first sub-pixel and the second sub-pixel along a first side of the first unit pixel; and a second junction region, the second junction region being formed to surround the second transistor region and being disposed across the third sub-pixel and the fourth sub-pixel along a second side parallel to the first side, The length of the first side is equal to the length of a third side of the first unit pixel that is perpendicular to the first side.

2. The image sensing device according to claim 1, wherein: Each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel includes: Two photoelectric conversion elements, which generate photocharges in response to incident light, are disposed adjacent to each other.

3. The image sensing device according to claim 2, wherein: The two photoelectric conversion elements are arranged adjacent to each other in the row direction or the column direction of the pixel array.

4. The image sensing device according to claim 2, wherein: Each of the first to fourth sub-pixels includes a transfer transistor respectively overlapping the two photoelectric conversion elements.

5. The image sensing device according to claim 2, wherein: Each of the photoelectric conversion elements includes a deeply doped region in which impurities are doped to a first depth from a surface of the first unit pixel, and a shallowly doped region in which impurities are doped to a second depth from the surface of the first unit pixel, wherein the second depth is closer to the surface of the first unit pixel than the first depth.

6. The image sensing device according to claim 2, wherein: The first unit pixel includes: a first floating diffusion region disposed between the first sub-pixel and the third sub-pixel; and A second floating diffusion region is provided between the second sub-pixel and the fourth sub-pixel.

7. The image sensing device according to claim 6, wherein: The first floating diffusion region and the second floating diffusion region are arranged along a direction in which the first side extends.

8. The image sensing device according to claim 1, wherein: The first transistor region includes a drive transistor and a select transistor; and The second transistor region includes a gain conversion transistor and a reset transistor.

9. The image sensing device according to claim 1, wherein: Each of the first to fourth sub-pixels is formed in a square shape.

10. The image sensing device according to claim 1, wherein: The plurality of unit pixels include a second unit pixel in contact with the first unit pixel, wherein the second unit pixel includes: a third junction region formed to surround a third transistor region and disposed across a fifth sub-pixel and a sixth sub-pixel along a fifth side of the second unit pixel; and a fourth junction region, the fourth junction region being formed to surround the fourth transistor region and being disposed across the seventh sub-pixel and the eighth sub-pixel along a sixth side parallel to the fifth side, The fifth side is in contact with a fourth side of the first unit pixel extending in a direction perpendicular to the first side.

11. The image sensing device according to claim 3, wherein: The plurality of unit pixels include a second unit pixel in contact with the first unit pixel, wherein the second unit pixel includes: The fifth sub-pixel, the sixth sub-pixel, the seventh sub-pixel and the eighth sub-pixel are arranged in a 2×2 matrix, in, Each of the fifth sub-pixel, the sixth sub-pixel, the seventh sub-pixel, and the eighth sub-pixel includes two photoelectric conversion elements; and The photoelectric conversion elements included in each of the fifth subpixel, the sixth subpixel, the seventh subpixel and the eighth subpixel are arranged to be adjacent to each other in a direction perpendicular to the direction in which the photoelectric conversion elements included in each of the first subpixel, the second subpixel, the third subpixel and the fourth subpixel are arranged.

12. The image sensing device according to claim 11, wherein: The second unit pixel further includes: a third floating diffusion region, the third floating diffusion region being disposed between the fifth sub-pixel and the seventh sub-pixel; and a fourth floating diffusion region, the fourth floating diffusion region being disposed between the sixth sub-pixel and the eighth sub-pixel, The third floating diffusion region and the fourth floating diffusion region are arranged along a direction in which the photoelectric conversion elements included in each of the fifth sub-pixel, the sixth sub-pixel, the seventh sub-pixel, and the eighth sub-pixel are arranged.

13. The image sensing device according to claim 1, wherein: The first transistor region includes a plurality of pixel transistors connected in parallel to each other.

14. The image sensing device according to claim 13, wherein: The pixel transistor includes at least one of a drive transistor, a select transistor, a reset transistor, or a gain conversion transistor.

15. The image sensing device according to claim 1, wherein: The first unit pixel further includes: A ground region is disposed at the center of the first unit pixel and receives a ground voltage as an input.

16. The image sensing device according to claim 1, wherein: The second transistor region includes a capacitive element.

17. The image sensing device according to claim 2, wherein: The isolation structure is formed as a trench structure extending from one surface of a semiconductor substrate toward another surface of the semiconductor substrate opposite to the one surface, and wherein the photoelectric conversion element is arranged in the semiconductor substrate.

18. The image sensing device according to claim 17, wherein: The first junction region or the second junction region is an impurity region extending from the other surface of the semiconductor substrate toward the one surface of the semiconductor substrate.

19. The image sensing device according to claim 18, wherein: The first junction region or the second junction region is formed to at least partially overlap the isolation structure.

20. The image sensing device according to claim 18, wherein: A width of the first junction region or a width of the second junction region is smaller than a width of the isolation structure surrounding the first unit pixel.

Images