Display panel

Abstract

A display panel is provided. The display panel includes a data line and unit pixels, the unit pixels including a first pixel, a second pixel, and a third pixel, in which the first pixel includes: a common electrode including a first lower electrode, a first light shielding pattern, and a second lower electrode; a first upper electrode overlapping the first lower electrode and forming a first capacitor with the first lower electrode; a second upper electrode overlapping the second lower electrode and forming a second capacitor with the second lower electrode; a first transistor including an active pattern overlapping the light shielding pattern and a gate electrode overlapping the active pattern; and a light emitting element, and one end of the gate electrode is electrically connected to the first upper electrode, and the other end of the gate electrode is electrically connected to the second upper electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0111147 filed on August 24, 2023 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a display panel and a display panel including a circuit element having improved reliability. Background Art

[0004] The display panel includes pixels and driving circuits (e.g., scan driving circuits and data driving circuits) for controlling the pixels. Each of the plurality of pixels includes a display element and a pixel driving circuit for controlling the display element. The pixel driving circuit may include an organically connected transistor and at least one capacitor. Summary of the invention

[0005] Embodiments of the present disclosure provide a display panel with improved display quality.

[0006] According to an embodiment, a display panel includes: a substrate layer; a plurality of data lines, which are arranged on the substrate layer, spaced apart from each other in a first direction and each extending in a second direction intersecting the first direction; and unit pixels, which are electrically connected to the plurality of data lines and each include a first pixel, a second pixel and a third pixel that provide light to a pixel area, wherein the first pixel includes: a common electrode, which includes a first lower electrode, a first shading pattern and a second lower electrode arranged in sequence in the second direction; a first upper electrode, which overlaps with the first lower electrode and forms a first capacitor with the first lower electrode; a second upper electrode, which overlaps with the second lower electrode and forms a second capacitor with the second lower electrode; a first transistor, which includes: an active pattern, which overlaps with the first shading pattern; and a gate electrode, which overlaps with the active pattern; and a light-emitting element, which is electrically connected to the first transistor, and one end of the gate electrode is electrically connected to the first upper electrode, and the other end of the gate electrode spaced apart from the one end in the second direction is electrically connected to the second upper electrode.

[0007] The display panel may also include: a first insulating layer, which is arranged on the base layer and covers the common electrode; a second insulating layer, which is arranged on the first insulating layer and covers the first upper electrode and the second upper electrode; and a third insulating layer, which is arranged on the second insulating layer, wherein one end of the gate electrode can be electrically connected to the first upper electrode through a first contact hole defined in the second insulating layer, and the other end of the gate electrode can be electrically connected to the second upper electrode through a second contact hole defined in the second insulating layer.

[0008] The active pattern, the first upper electrode, and the second upper electrode may be disposed at the same layer.

[0009] The active pattern may be arranged between the first upper electrode and the second upper electrode in the second direction.

[0010] The first pixel may further include a second transistor and a third transistor each including an active pattern and a gate electrode.

[0011] Each of the second pixel and the third pixel may include: a capacitor; a first transistor, a second transistor, and a third transistor each including an active pattern and a gate electrode; and a light emitting element.

[0012] The light emitting element included in each of the first pixel, the second pixel, and the third pixel may include a first electrode, a second electrode, and a light emitting layer disposed between the first electrode and the second electrode.

[0013] The display panel may further include a pixel defining film having a plurality of openings defining therein exposing at least a portion of the first electrode of the unit pixel, wherein a pixel region of each of the first pixel, the second pixel, and the third pixel may be defined by a corresponding opening of the plurality of openings.

[0014] The pixel region of the first pixel may be spaced apart from the pixel region of the third pixel in the second direction, and the pixel region of the second pixel may be spaced apart from the pixel regions of the first pixel and the third pixel in a diagonal direction intersecting the first direction and the second direction.

[0015] The first pixel, the second pixel, and the third pixel may provide the same light.

[0016] An area of ​​a pixel region of the first pixel may be smaller than an area of ​​a pixel region of the second pixel and larger than an area of ​​a pixel region of the third pixel.

[0017] At least a portion of the gate electrode may overlap a pixel region of the first pixel.

[0018] Among the multiple data lines, a first data line electrically connected to a first pixel is spaced apart from a second data line electrically connected to a second pixel in a first direction, an active pattern of a first transistor and an active pattern of a second transistor are arranged between the first data line and the second data line, and a third data line electrically connected to a third pixel is spaced apart from the first data line in the first direction, and the second data line is arranged between the third data line and the first data line.

[0019] The display panel may further include a plurality of light shielding patterns overlapping the active pattern included in the second pixel and the active pattern included in the third pixel and spaced apart from each other in the second direction.

[0020] A plurality of light shielding patterns may be disposed between the first data line, the second data line, and the third data line.

[0021] The plurality of data lines and the plurality of light shielding patterns may include the same material.

[0022] An active pattern included in the second transistor of the first pixel may be integrated with the second upper electrode.

[0023] The display panel may further include an encapsulation layer covering the first pixel, the second pixel, and the third pixel and including a first inorganic layer, a second inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer.

[0024] The active pattern, the first upper electrode, and the second upper electrode may include the same material.

[0025] An area of ​​the first upper electrode may be greater than an area of ​​the second upper electrode.

[0026] Technical objectives to be achieved by the present disclosure are not limited to those described herein, and other technical objectives not mentioned herein will be clearly understood by those skilled in the art from the description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0028] Figure 1A is a schematic perspective view of a display panel according to an embodiment of the present disclosure.

[0029] Figure 1B is a schematic perspective view of a curved display panel according to an embodiment of the present disclosure.

[0030] Figure 2A is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0031] Figure 2Bis a schematic plan view of a display panel according to an embodiment of the present disclosure.

[0032] Figure 3 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment of the present disclosure.

[0033] Figure 4 is a schematic enlarged plan view of a display area according to an embodiment of the present disclosure.

[0034] Figure 5A is a schematic plan view according to a stacking (or lamination) order of conductive patterns included in a unit pixel according to an embodiment of the present disclosure.

[0035] Figure 5B is along Figure 5A Schematic cross-sectional view of the display panel taken along line II'.

[0036] Figure 5C is along Figure 5A Schematic cross-sectional view of the display panel taken along line II'.

[0037] 6A to 6F 2 is a schematic plan view illustrating a stacking order of conductive patterns included in a unit pixel according to an embodiment of the present disclosure, distinguished according to each layer. DETAILED DESCRIPTION

[0038] It will be understood that when an element (or region, layer, part, etc.) is referred to in the specification as being "on", "connected to" or "coupled to" another element, the one element can be directly arranged on, directly connected to or directly coupled to the other element mentioned above, or intervening elements may be arranged therebetween.

[0039] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components may be exaggerated in order to effectively describe the technical content. The expression "and / or" includes one or more combinations that the related components can define.

[0040] Although the terms "first", "second", etc. may be used to describe various components, the components should not be limited by the terms. The terms are only used to distinguish one component from another component. For example, without departing from the scope of the present disclosure, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. Unless otherwise clearly indicated in the context, a singular expression may include a plural expression.

[0041] In addition, the terms "lower", "below", "upper", "above", etc. are used to describe the relationship between components illustrated in the drawings. Conceptually relative terms are described based on the directions illustrated in the drawings.

[0042] It will be understood that the terms “comprises,” “includes,” “has,” etc. specify the presence of features, numbers, steps, operations, elements or components, or a combination thereof, described in the specification, and do not exclude the prior existence or additional possibility of one or more other features, numbers, steps, operations, elements or components, or a combination thereof.

[0043] The term "and / or" includes all combinations of one or more that the relevant configurations can define. For example, "A and / or B" can be understood to mean "A, B, or A and B".

[0044] For the purpose of the present disclosure, the phrase “at least one of A and B” may be interpreted as only A, only B, or any combination of A and B. In addition, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z.

[0045] Unless otherwise defined or implied herein, all terms (including technical terms and scientific terms) used in the specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense, unless clearly defined herein.

[0046] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0047] Figure 1A is a schematic perspective view of a display panel according to an embodiment of the present disclosure. Figure 1B is a schematic perspective view of a curved display panel according to an embodiment of the present disclosure. Figure 2A is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure. Figure 2B is a schematic plan view of a display panel according to an embodiment of the present disclosure. Figure 3 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment of the present disclosure. Figure 4 is a schematic enlarged plan view of a display area according to an embodiment of the present disclosure.

[0048] Figure 1A and Figure 1BThe display panels DP and DP-1 illustrated in the figure as light-emitting display panels may be one of a liquid crystal display panel, an electrophoretic display panel, a microelectromechanical system (MEMS) display panel, an electrowetting display panel, an organic light-emitting display panel, an inorganic light-emitting display panel, and a quantum dot display panel. In addition, the display panels DP and DP-1 according to the embodiments of the present disclosure may include ultra-small light-emitting elements. For example, the display panels DP and DP-1 may include micro light-emitting diode (LED) elements and / or nano LED elements, but the present disclosure is not particularly limited thereto.

[0049] refer to Figure 1A , the display panel DP may display an image through the display surface DP-IS. The upper surface of the member arranged on the uppermost side of the display panel DP may be defined as the display surface DP-IS. According to the present disclosure, Figure 2A An upper surface of the window panel WD illustrated in FIG. 4 may be provided as a display surface DP-IS of the display panel DP.

[0050] The display surface DP-IS may be parallel to a plane defined by the first direction DR1 and the second direction DR2. A normal direction of the display surface DP-IS (e.g., a thickness direction of the display panel DP) may indicate a third direction DR3. Hereinafter, a front surface (or upper surface) and a rear surface (or lower surface) of a layer or unit to be described below are distinguished by the third direction DR3.

[0051] The display panel DP may include a display area DA and a non-display area NDA. Figure 2A and Figure 2B ) in the light-emitting layer EML (see Figure 5B ) may be arranged in the display area DA, and the pixels PXnm (see Figure 2A and Figure 2B ) of the light-emitting layer EML (see Figure 5B ) is not arranged in the non-display area NDA, where n and m are natural numbers greater than 0. The non-display area NDA is defined along the edge of the display surface DP-IS. The non-display area NDA may surround the display area DA. In an embodiment of the present disclosure, the non-display area NDA may be omitted or arranged on only one side of the display area DA.

[0052] refer to Figure 1B , the display panel DP-1 according to the embodiment may be bent in the first direction DR1 relative to the virtual axis AX extending in the second direction DR2. However, the present disclosure is not limited thereto, and the virtual axis AX may extend in another direction (e.g., the first direction DR1), or the display panel DP-1 may be bent relative to a plurality of axes extending in the same and / or different directions.

[0053] According to an embodiment, the display panels DP and DP-1 may be rollable display panels, foldable display panels, or slidable display panels. In this case, the display panels DP and DP-1 may be flexible and may be folded or rolled when installed in a display device. Therefore, the display panels DP and DP-1 may include a curved display surface DP-IS or a three-dimensional display surface DP-IS. The three-dimensional display surface DP-IS may include a plurality of display areas DA facing different directions.

[0054] Figure 1A and Figure 1B The unit pixel PXU is illustrated to be arranged in the display area DA. The unit pixel PXU may include at least two pixels PXnm that provide different lights. For example, the unit pixel PXU may be a region in which a pixel PXnm that provides source light is arranged. The light-emitting region, shape, and arrangement form of the pixel PXnm included in the unit pixel PXU are not limited to any specific one. For example, the area of ​​the light-emitting region of the pixel PXnm included in the unit pixel PXU (for example, the size of the pixel PXnm) may be different from each other. In addition, each of the plurality of light-emitting regions may have a circular shape or a polygonal shape on a plane.

[0055] refer to Figure 2A and Figure 2B , the display panel DP according to the present disclosure may include a base layer BS, a circuit element layer DP-CL arranged on the base layer BS, a display element layer DP-OLED, an encapsulation layer TFE, a light control layer OSL and / or a window panel WD. The display panel DP may also include a functional layer such as an anti-reflection layer or a refractive index adjustment layer. The circuit element layer DP-CL may include at least one insulating layer and a circuit element. The insulating layer to be described below may include an organic layer and / or an inorganic layer.

[0056] The base layer BS may include a resin layer, for example, a synthetic resin layer. The synthetic resin layer may include, for example, a thermosetting resin. In particular, the synthetic resin layer may include, for example, at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin. The base layer BS may include, for example, a glass substrate, a metal substrate, an organic / inorganic composite material substrate, etc.

[0057] In the circuit element layer DP-CL, the insulating layer, the semiconductor layer and the conductive layer can be formed by processes such as coating and deposition. Subsequently, the insulating layer, the semiconductor layer and the conductive layer can be selectively patterned by photolithography and etching processes. Semiconductor patterns, conductive patterns, signal lines, etc. can be formed by these processes. Patterns set on the same layer can be formed by the same process.

[0058] The circuit element layer DP-CL may include a driving circuit or a signal line constituting the pixel PX. The display element layer DP-OLED may include a light emitting element OLED included in the pixel PX (see Figure 3 ) and pixel definition film PDL (see Figure 5B ).

[0059] The encapsulation layer TFE may be arranged on the display element layer DP-OLED to protect the light emitting element OLED. The encapsulation layer TFE may include a plurality of inorganic layers and an organic layer arranged between the plurality of inorganic layers. The inorganic layer may protect the light emitting element OLED from moisture and oxygen, and the organic layer may protect the light emitting element OLED from foreign matter such as dust particles.

[0060] The light control layer OSL may include a light control pattern that may change the optical properties of the source light generated by the light emitting element OLED. The light control pattern may include quantum dots and may include a color filter pattern that selectively transmits light that has passed through the light control pattern.

[0061] The window panel WD may be disposed on the display panel DP and transmit an image provided from the display panel DP to the outside. The window panel WD may be distinguished as follows: Figure 1A 1 and 2. The display area DA and the non-display area NDA of the display surface DP-IS illustrated in FIG. A boundary between the display area DA and the non-display area NDA may be defined by a bezel pattern that is disposed under the window panel WD and absorbs light.

[0062] The window panel WD may include a base layer BS and a functional layer disposed on the base layer BS. The functional layer may include a protective layer, an anti-fingerprint layer, etc. The base layer BS of the window panel WD may be made of, for example, glass, sapphire, or plastic.

[0063] Figure 2B The diagram shows the arrangement relationship between the signal lines and the pixels PX11 to PXnm included in the display panel DP on a plane. The signal lines may include one or more scan lines SCL1 to SCLn and one or more data lines DL1 to DLm, where n and m are natural numbers greater than 0.

[0064] Pixels PX11 to PXnm may be arranged in the display area DA. Each of the pixels PX11 to PXnm may be connected to a corresponding scan line among the scan lines SCL1 to SCLn and a corresponding data line among the plurality of data lines DL1 to DLm. Each of the pixels PX11 to PXnm may include a pixel driving circuit and a light emitting element. According to the configuration of the pixel driving circuit of the pixels PX11 to PXnm, more types of signal lines may be provided on the display panel DP.

[0065] The gate driving circuit GDC may be arranged in the non-display area NDA. The gate driving circuit GDC may be integrated into (or integrated with) the display panel DP through a process (e.g., an oxide silicon gate (OSG) driver circuit process or an amorphous silicon gate (ASG) driver circuit process).

[0066] Figure 3 A schematic diagram of an equivalent circuit related to a pixel PXij among the pixels PX11 to PXnm is illustrated as an example, wherein i and j are natural numbers greater than 0.

[0067] The pixel PXij may include a pixel circuit PC and a light emitting element OLED. The pixel circuit PC may include first to third transistors T1 to T3 and a capacitor Cst.

[0068] According to the present disclosure, the pixel PXij may include capacitors Cst (eg, a pair of capacitors Cst) spaced apart from each other and connected through a conductive pattern. A description related thereto will be made below.

[0069] The first transistor T1 to the third transistor T3 may be formed by a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process. Each of the first transistor T1 to the third transistor T3 may include, for example, a silicon semiconductor or an oxide semiconductor. In this case, the oxide semiconductor may include a crystalline or amorphous oxide semiconductor, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc., and the present disclosure is not limited to the embodiments.

[0070] Hereinafter, it will be described that the first to third transistors T1 to T3 are N-type, but the present disclosure is not limited thereto, and each of the first to third transistors T1 to T3 may be a P-type transistor or an N-type transistor according to a signal applied thereto. In this case, the source region and the drain region of the P-type transistor may correspond to the drain region and the source region of the N-type transistor, respectively.

[0071] Figure 3 A pixel PXij connected to an i-th scan line SCLi, an i-th sensing line SSLi, a j-th data line DLj, and a j-th initial line ILj is illustrated as an example.

[0072] The pixel circuit PC may include a first transistor T1 (driving transistor), a second transistor T2 (switching transistor), a third transistor T3 (sensing transistor), and a capacitor Cst. However, the pixel circuit PC may further include additional transistors and additional capacitors, and the present disclosure is not limited to the embodiments.

[0073] The light emitting element OLED may be an organic light emitting element or an inorganic light emitting element including an anode (first electrode) and a cathode (second electrode). The anode of the light emitting element OLED may receive a first voltage ELVDD through a first transistor T1, and the cathode of the light emitting element OLED may receive a second voltage ELVSS. The light emitting element OLED may emit light by receiving the first voltage ELVDD and the second voltage ELVSS.

[0074] The first transistor T1 may include a drain region D1 receiving a first voltage ELVDD, a source region S1 connected to an anode of the light emitting element OLED, and a gate region G1 connected to the capacitor Cst. The first transistor T1 may control a driving current flowing from a voltage line of the first voltage ELVDD through the light emitting element OLED in response to a voltage value stored in the capacitor Cst.

[0075] The second transistor T2 may include a drain region D2 connected to the jth data line DLj, a source region S2 connected to the capacitor Cst, and a gate region G2 receiving the i-th first scan signal SCi. The second transistor T2 may provide the data voltage Vd to the first transistor T1 in response to the i-th first scan signal SCi.

[0076] The third transistor T3 may include a source region S3 connected to the jth initial line ILj, a drain region D3 connected to the anode of the light emitting element OLED, and a gate region G3 receiving the i-th second scan signal SSi. The jth initial line ILj may receive the initial voltage Vintit.

[0077] The capacitor Cst may store various voltage differences according to an input signal. For example, the capacitor Cst may store a voltage corresponding to a difference between a voltage received from the second transistor T2 and the first voltage ELVDD.

[0078] like Figure 4 , light generated by the first pixel PX-R may be provided to the first pixel region PXA-R, light generated by the second pixel PX-G may be provided to the second pixel region PXA-G, and light generated by the third pixel PX-B may be provided to the third pixel region PXA-B. The first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may be provided to the third pixel region PXA-B. Figure 5B This corresponds to the opening PDL-OP in the pixel definition film PDL described in .

[0079] The peripheral area NPXA may be disposed between the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B. The peripheral area NPXA may set a boundary between the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B, and prevent color mixing between the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B.

[0080] Each of the first pixel PX-R, the second pixel PX-G, and the third pixel PX-B may include a light emitting element OLED (see Figure 5B ), and the first pixel PX-R, the second pixel PX-G, and the third pixel PX-B can generate source light having the same color. However, the areas (e.g., sizes) of the light emitting regions of the first pixel PX-R, the second pixel PX-G, and the third pixel PX-B can be the same or different.

[0081] The light emitting elements OLED (see FIG. 1 ) of the first pixel PX-R, the second pixel PX-G and the third pixel PX-B are Figure 5B ) can be converted into light having different colors through the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B, and the converted source light can be emitted. The emitted source light can be Figure 2A The light control pattern in the light control layer OSL described in is converted into light having any one of red, green and blue colors.

[0082] refer to Figure 4 , the first pixel region PXA-R and the third pixel region PXA-B may be disposed on the same row, and the second pixel region PXA-G may be disposed on a row different from the row of the first pixel region PXA-R and the third pixel region PXA-B. For example, the first pixel region PXA-R and the third pixel region PXA-B may be spaced apart from each other in the first direction DR1, and the second pixel region PXA-G may be spaced apart from the first pixel region PXA-R and the third pixel region PXA-B in a direction inclined with respect to each of the first direction DR1 and the second direction DR2.

[0083] According to an embodiment, an area of ​​the first pixel region PXA-R may be smaller than an area of ​​the second pixel region PXA-G and larger than an area of ​​the third pixel region PXA-B.

[0084] In the embodiment, the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B having a square shape are illustrated as an example, but the arrangement form and area of ​​the pixel regions are not limited thereto.

[0085] Figure 4 The arrangement structure of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B inside the unit pixel PXU illustrated in the figure is only an example, but the present disclosure is not limited thereto. In an embodiment of the present disclosure, the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may be arranged in the first direction DR1 and in the same row. In addition, the arrangement of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B of each of the plurality of unit pixels PXU does not necessarily need to be the same.

[0086] Figure 5A is a schematic plan view according to a stacking (or lamination) order of conductive patterns included in a unit pixel according to an embodiment of the present disclosure. Figure 5B is along Figure 5A Schematic cross-sectional view of the display panel taken along line II'. Figure 5C is along Figure 5A Schematic cross-sectional view of the display panel taken along line II'. 6A to 6F Picture shows Figure 5A The components illustrated in the figure can be separated according to each layer.

[0087] refer to Figure 5A , the unit pixel PXU may include a first pixel PX-R, a second pixel PX-G, and a third pixel PX-B. Each of the first pixel PX-R, the second pixel PX-G, and the third pixel PX-B may include a reference pixel PX-R, a second pixel PX-G, and a third pixel PX-B. Figure 3 The pixel circuit PC and the light emitting element OLED are described.

[0088] For example, the first pixel PX-R may include a first transistor T1-R, a second transistor T2-R, and a third transistor T3-R, a first capacitor CST1-R and a second capacitor CST2-R connected to each other, and a first light emitting element OLED-R. The second pixel PX-G may include a first transistor T1-G, a second transistor T2-G, and a third transistor T3-G, a capacitor CST-G, and a second light emitting element OLED-G. The third pixel PX-B may include a first transistor T1-B, a second transistor T2-B, and a third transistor T3-B, a capacitor CST-B, and a third light emitting element OLED-B.

[0089] For ease of description, Figure 5A The first light emitting element OLED-R, the second light emitting element OLED-G and the third light emitting element OLED-B are illustrated instead of the first electrode AE ​​included in the first pixel PX-R, the second pixel PX-G and the third pixel PX-B (see Figure 5B ).

[0090] Source light generated by the first pixel PX-R may be provided to the first pixel region PXA-R, source light generated by the second pixel PX-G may be provided to the second pixel region PXA-G, and source light generated by the third pixel PX-B may be provided to the third pixel region PXA-B.

[0091] Each of the first pixel PX-R, the second pixel PX-G, and the third pixel PX-B may be connected to the first power line ED, the second power line EL (see, e.g., Figure 6C ), scan line SCL and sensing line SSL. In addition, the first pixel PX-R, the second pixel PX-G and the third pixel PX-B can be connected to the first data line DL-R, the second data line DL-G and the third data line DL-B (see Fig. 6A ) in the corresponding data line. The first power line ED can provide a first voltage ELVDD (see Figure 3 ), and the second power line EL can provide a second voltage ELVSS lower than the first voltage ELVDD (see Figure 3 ).

[0092] According to an embodiment, the first data line DL-R, the second data line DL-G, the third data line DL-B, and the second power line EL may be spaced apart from each other in the first direction DR1 and extend in the second direction DR2. The first power line ED, the scan line SCL, and the sensing line SSL may be spaced apart from each other in the second direction DR2 and extend in the first direction DR1.

[0093] refer to Figure 5A and Figure 5B According to an embodiment, the display panel DP may include: a base layer BS; a first insulating layer 10, a second insulating layer 20, and a third insulating layer 30 disposed on the base layer BS; a pixel defining film PDL in which an opening PDL-OP is defined; an encapsulation layer TFE; and a first pixel PX-R.

[0094] The first insulating layer 10 and the second insulating layer 20 may include an inorganic layer. For example, the inorganic layer may include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in plurality and the silicon oxide layer and the silicon nitride layer may be alternately stacked. The third insulating layer 30 may be an organic layer.

[0095] According to an embodiment, the first pixel PX-R may include a first capacitor CST1-R and a second capacitor CST2-R connected to each other, a first transistor T1-R and / or a first light emitting element OLED-R. According to an embodiment, the first pixel PX-R may further include a common electrode CP and a gate electrode GP. The first transistor T1-R may be connected to Figure 3 Therefore, the first pixel PX-R may include Figure 3 The second transistor T2 and the third transistor T3 described in (corresponding to the second transistor T2-R and the third transistor T3-R). Each of the second transistor T2 and the third transistor T3 may include an active pattern and a gate pattern.

[0096] The description of the components included in the first light emitting element OLED-R may be equally applicable to the second light emitting element OLED-G and the third light emitting element OLED-B included in the second pixel PX-G and the third pixel PX-B.

[0097] The common electrode CP may be disposed on the base layer BS. The common electrode CP may include a first lower electrode C1-1, a first light shielding pattern BML-R, and a second lower electrode C2-1 spaced apart from each other in the second direction DR2. The first insulating layer 10 may be disposed on the base layer BS and cover the common electrode CP (or overlap the common electrode CP). The first lower electrode C1-1, the first light shielding pattern BML-R, and the second lower electrode C2-1 may be substantially patterns and will be described separately for ease of description.

[0098] The first upper electrode C1-2, the first active pattern A1-R, and the second upper electrode C2-2 may be disposed on the first insulating layer 10 and spaced apart from each other. The first upper electrode C1-2 may overlap the first lower electrode C1-1 to define a first capacitor CST1-R of the first pixel PX-R. The second upper electrode C2-2 may overlap the second lower electrode C2-1 to define a second capacitor CST2-R of the first pixel PX-R.

[0099] The first light-shielding pattern BML-R may overlap the first active pattern A1-R and receive a bias voltage. The first light-shielding pattern BML-R may receive a first voltage ELVDD (see Figure 3 ). The first light shielding pattern BML-R can prevent the potential caused by the polarization phenomenon from affecting the first transistor T1-R. In addition, the first light shielding pattern BML-R can prevent external light from reaching the first transistor T1-R. In an embodiment of the present disclosure, the first light shielding pattern BML-R may also be a floating electrode isolated from other electrodes or wirings.

[0100] The gate electrode GP may include a first bridge portion BR1, a gate pattern G1-R, and a second bridge portion BR2 sequentially disposed in the second direction DR2. The first bridge portion BR1, the gate pattern G1-R, and the second bridge portion BR2 are substantially patterns and will be described separately for convenience of description.

[0101] The gate pattern G1-R may overlap with the first active pattern A1-R. A portion of the first active pattern A1-R overlapping with the gate pattern G1-R may be defined as a channel region, and one end and the other end of the first active pattern A1-R spaced apart from each other with the channel region interposed therebetween may be defined as a source region and a drain region. The channel region may be a non-doped region or a region doped at a lower concentration than the source region and the drain region. The first active pattern A1-R and the gate pattern G1-R may be defined as a first transistor T1-R included in the first pixel PX-R.

[0102] The first bridge portion BR1 may overlap a portion of the first upper electrode C1 - 2 . The first bridge portion BR1 may be connected to the first upper electrode C1 - 2 through a first contact hole CH1 defined in the second insulating layer 20 .

[0103] The second bridge portion BR2 may overlap a portion of the second upper electrode C2-2. The second bridge portion BR2 may be connected to the second upper electrode C2-2 through a second contact hole CH2 defined in the second insulating layer 20. Therefore, the first active pattern A1-R included in the first transistor T1-R may be disposed between the first capacitor CST1-R and the second capacitor CST2-R connected to each other.

[0104] According to the present disclosure, the first capacitor CST1-R and the second capacitor CST2-R included in the first pixel PX-R may be disposed in different regions, and thus the electrodes included in the first capacitor CST1-R and the second capacitor CST2-R may be disposed in a wide region within the unit pixel PXU. Therefore, a display panel DP including the first pixel PX-R having improved driving characteristics by improving the functions of the first capacitor CST1-R and the second capacitor CST2-R may be provided.

[0105] The pixel definition film PDL may be disposed on the third insulating layer 30. An opening PDL-OP may be defined in the pixel definition film PDL. At least a portion of the first electrode AE ​​may be exposed through the opening PDL-OP. One or more openings PDL-OP may be provided. The opening PDL-OP may be connected to the pixel definition film PDL. Figure 4 The first pixel area PXA-R, the second pixel area PXA-G and the third pixel area PXA-B described in FIG.

[0106] According to an embodiment, the pixel defining film PDL may have a property of absorbing light, and for example, the pixel defining film PDL may have a black color. The pixel defining film PDL may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. The pixel defining film PDL may correspond to a light shielding pattern having a light shielding property.

[0107] The first electrode AE ​​of the first light emitting element OLED-R may be arranged on the third insulating layer 30. The first electrode AE ​​may be patterned separately for each pixel PXnm. The hole control layer HCL may be arranged on the first electrode AE ​​and the pixel defining film PDL. The hole control layer HCL may include a hole transport layer and a hole injection layer. The light emitting layer EML may be arranged on the hole control layer HCL. The electron control layer ECL may be arranged on the light emitting layer EML. The electron control layer ECL may include an electron transport layer and an electron injection layer. The second electrode CE may be arranged on the electron control layer ECL. According to an embodiment, the hole control layer HCL, the light emitting layer EML, the electron control layer ECL, and the second electrode CE may be a common layer formed together in the first pixel PX-R, the second pixel PX-G, and the third pixel PX-B.

[0108] The encapsulation layer TFE may cover the first light emitting element OLED-R. The encapsulation layer TFE may include a first inorganic layer LIL, an organic layer OL, and a second inorganic layer UIL stacked in sequence. The first inorganic layer LIL and the second inorganic layer UIL may include, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Each of the first inorganic layer LIL and the second inorganic layer UIL may have a multilayer structure. The organic layer OL may include an acrylic organic layer, but the present disclosure is not limited thereto.

[0109] The first inorganic layer LIL and the second inorganic layer UIL may protect the first light emitting element OLED-R from moisture and oxygen, and the organic layer OL may protect the first light emitting element OLED-R from foreign substances such as dust particles.

[0110] refer to Figure 5C According to an embodiment, the display panel DP-a may include a base layer BS, a first insulating layer 10, a second insulating layer 20 and a third insulating layer 30 disposed on the base layer BS, a pixel defining film PDL in which an opening PDL-OP is defined, an encapsulation layer TFE and / or a first pixel PX-R.

[0111] According to an embodiment, the first pixel PX-R may include a first capacitor CST1-R and a second capacitor CST2-R connected to each other, a first transistor T1-R, and a first light emitting element OLED-R. According to an embodiment, the first pixel PX-R may further include a common electrode CP and a bridge electrode BR. Figure 5B The differences are in the configuration described in .

[0112] The common electrode CP may be disposed on the base layer BS. The common electrode CP may include a first lower electrode C1-1, a first light shielding pattern (not shown), and a second lower electrode C2-1 spaced apart from each other in the second direction DR2. The first insulating layer 10 may be disposed on the base layer BS and cover the common electrode CP.

[0113] The bridge electrode BR may be disposed on the base layer BS. The bridge electrode BR and the common electrode CP may be formed by the same process and include the same material. The bridge electrode BR may be spaced apart from the common electrode CP.

[0114] The first upper electrode C1 - 2 , the first active pattern A1 -R, and the second upper electrode C2 - 2 may be disposed on the first insulating layer 10 and spaced apart from each other.

[0115] A portion of the first upper electrode C1-2 may overlap the first lower electrode C1-1 to define a first capacitor CST1-R of the first pixel PX-R. Another portion of the first upper electrode C1-2 may overlap the bridge electrode BR. The first upper electrode C1-2 may be connected to the bridge electrode BR through a third contact hole CH3 defined in the first insulating layer 10.

[0116] A portion of the second upper electrode C2-2 may overlap the second lower electrode C2-1 to define a second capacitor CST2-R of the first pixel PX-R. Another portion of the second upper electrode C2-2 may overlap the bridge electrode BR. The second upper electrode C2-2 may be connected to the bridge electrode BR through a fourth contact hole CH4 defined in the first insulating layer 10.

[0117] The first active pattern A1-R may be disposed between the first upper electrode C1-2 and the second upper electrode C2-2. The gate pattern G1-R may be disposed on the second insulating layer 20 overlapping the first active pattern A1-R.

[0118] 6A to 6F 1 is a schematic plan view illustrating a stacking order of conductive patterns included in a unit pixel according to an embodiment of the present disclosure, which is distinguished according to each layer. Specifically, 6A to 6F The diagram is distinguished according to each layer Figure 5A Schematic plan view of the stacking sequence of the conductive patterns described in FIG.

[0119] refer to Figure 5A , Figure 5B and Fig. 6A , the first conductive layer MSL1 may be arranged on the base layer BS (see Figure 5B ) and is covered by the first insulating layer 10. Fig. 6A Also illustrated are a plurality of first contact holes CNT1 defined in the first insulating layer 10 and overlapping the first conductive layer MSL1 .

[0120] The first conductive layer MSL1 may include a first data line DL-R, a common electrode CP, a first sensing pattern SS-1, a first scanning pattern SC-1, an initial line IL, a power line EBR, a second sensing pattern SS-2, a second scanning pattern SC-2, a second light-shielding pattern BML-G, a third light-shielding pattern BML-B, a second data line DL-G, a third data line DL-B and / or a first line E-1.

[0121] The first data line DL-R may extend in the second direction DR2.

[0122] The common electrode CP may be spaced apart from the first data line DL-R in the first direction DR1 and extend in the second direction DR2. The common electrode CP may include a first lower electrode C1-1, a first light blocking pattern BML-R, and a second lower electrode C2-1 sequentially disposed in the second direction DR2.

[0123] The first sensing pattern SS- 1 and the first scan pattern SC- 1 may be spaced apart from each other in the second direction DR2 with the common electrode CP interposed therebetween.

[0124] The initial line IL may be spaced apart from the common electrode CP in the first direction DR1 and extend in the second direction DR2.

[0125] The power line EBR may be spaced apart from the initial line IL in the first direction DR1 and extend in the second direction DR2.

[0126] The second light-shielding pattern BML-G may be spaced apart from the power line EBR in the first direction DR1. The third light-shielding pattern BML-B may be spaced apart from the second light-shielding pattern BML-G in the second direction DR2.

[0127] The second sensing pattern SS-2 and the second scanning pattern SC-2 may be spaced apart from each other in the second direction DR2 with the second light-shielding pattern BML-G and the third light-shielding pattern BML-B interposed therebetween.

[0128] The second data line DL-G may be spaced apart from the second and third light blocking patterns BML-G and BML-B in the first direction DR1 and extend in the second direction DR2. The third data line DL-B may be spaced apart from the second data line DL-G in the first direction DR1 and extend in the second direction DR2.

[0129] The first line E- 1 may be spaced apart from the third data line DL-B in the first direction DR1 and extend in the second direction DR2 .

[0130] Each of the first data line DL-R, the second data line DL-G, the third data line DL-B, the initial line IL, the power line EBR, and the first line E-1 may extend in the second direction DR2 and may be commonly arranged in a plurality of unit pixels PXU disposed in the second direction DR2.

[0131] refer to Figure 5A , Figure 5B and Figure 6B , the second conductive layer MSL2 may be arranged on the first insulating layer 10 (see Figure 5B ) and is covered by a second insulating layer 20 (see Figure 5B )cover.

[0132] The second conductive layer MSL2 may include: a first active pattern A1-R, a second active pattern A2-R, and a third active pattern A3-R included in the first pixel PX-R; a first active pattern A1-G, a second active pattern A2-G, and a third active pattern A3-G included in the second pixel PX-G; and a first active pattern A1-B, a second active pattern A2-B, and a third active pattern A3-B included in the third pixel PX-B. The second conductive layer MSL2 according to the embodiment may include a first upper electrode C1-2, a second upper electrode C2-2, a second capacitor pattern CSP-G, and a third capacitor pattern CSP-B.

[0133] The second capacitor pattern CSP-G and the second active pattern A2-G of the second pixel PX-G may be integrated with each other and may be provided as an integrated pattern, and the third capacitor pattern CSP-B and the second active pattern A2-B of the third pixel PX-B may be integrated with each other and may be provided as an integrated pattern.

[0134] The first active pattern A1-R of the first pixel PX-R may overlap the first light shielding pattern BML-R. The first upper electrode C1-2 may overlap the first lower electrode C1-1 to define a first capacitor CST1-R of the first pixel PX-R, and the second upper electrode C2-2 may overlap the second lower electrode C2-1 to define a second capacitor CST2-R of the first pixel PX-R.

[0135] The second active pattern A2-R of the first pixel PX-R may be integrated with the second upper electrode C2-2.

[0136] The third active pattern A3 -R of the first pixel PX-R may be spaced apart from the first upper electrode C1 - 2 in the second direction DR2 and may be arranged between the first sensing pattern SS- 1 and the first lower electrode C1 - 1 on a plane.

[0137] A portion of the first active pattern A1 -G of the second pixel PX-G may overlap the second light-shielding pattern BML-G, and another portion may be disposed between the power line EBR and the second light-shielding pattern BML-G on a plane.

[0138] The second capacitor pattern CSP-G of the second pixel PX-G may overlap the second light blocking pattern BML-G, and the second active pattern A2-G may protrude from the second capacitor pattern CSP-G in the first direction DR1. The second active pattern A2-G may not overlap the second light blocking pattern BML-G.

[0139] The third capacitor pattern CSP-B of the third pixel PX-B may overlap the third light blocking pattern BML-B, and the second active pattern A2-B may protrude from the third capacitor pattern CSP-B in the first direction DR1. The second active pattern A2-B may not overlap the third light blocking pattern BML-B.

[0140] The third active pattern A3-G of the second pixel PX-G may extend in the first direction DR1. One end and the other end of the third active pattern A3-G spaced apart from each other in the first direction DR1 may not overlap the power line EBR, and a portion therebetween may overlap the power line EBR.

[0141] The third active pattern A3-B of the third pixel PX-B may be spaced apart from the third active pattern A3-G of the second pixel PX-G in the second direction DR2 and extend in the first direction DR1. One end and the other end of the third active pattern A3-B spaced apart from each other in the first direction DR1 may not overlap with the power line EBR, and a portion between the one end and the other end may overlap with the power line EBR.

[0142] refer to Figure 5A , Figure 5B and Figure 6C , the third conductive layer MSL3 may be disposed on the second insulating layer 20 and covered by the third insulating layer 30 . Figure 6C Also illustrated are a plurality of second contact holes CNT2 defined in the second insulating layer 20 and overlapping the second conductive layer MSL2 .

[0143] The third conductive layer MSL3 may include: a first power line ED; a second power line EL; a sensing line SSL; a scan line SCL; a first bridge pattern BP1-R, a first bridge pattern BP1-G and a first bridge pattern BP1-B; a second bridge pattern BP2-R, a second bridge pattern BP2-G and a second bridge pattern BP2-B; a gate electrode GP; a first gate pattern G1-G and a first gate pattern G1-B; a second gate pattern G2-R, a second gate pattern G2-G and a second gate pattern G2-B; a third bridge pattern BP3-R and a third bridge pattern BP3-B; a third gate pattern G3-R, a third gate pattern G3-G and a third gate pattern G3-B; ​​a first initial pattern IP1 and a second initial pattern IP2 and / or a first power pattern EP1 and a second power pattern EP2.

[0144] The first power line ED may extend in the first direction DR1. The first power line ED may be connected to the power line EBR through the first contact hole CNT1. The first power pattern EP1 and the second power pattern EP2 may be spaced apart from each other in the first direction DR2 and overlap the power line EBR. Each of the first power pattern EP1 and the second power pattern EP2 may be connected to the power line EBR through the first contact hole CNT1, and connected to the first power line ED through the power line EBR.

[0145] The first power pattern EP1 may be connected to the first active patterns A1 -G through the second contact holes CNT2 .

[0146] A portion of the second power pattern EP2 may be connected to the first active pattern A1-R through the second contact hole CNT2. Another portion of the second power pattern EP2 may be connected to the first active pattern A1-B through the second contact hole CNT2.

[0147] The second power line EL may extend in the second direction DR2. The second power line EL may be connected to the first line E-1 through the first contact hole CNT1.

[0148] The sensing line SSL may extend in the first direction DR1. The sensing line SSL may overlap the first sensing pattern SS-1 and the second sensing pattern SS-2. The sensing line SSL may be connected to the first sensing pattern SS-1 and the second sensing pattern SS-2 through the first contact hole CNT1.

[0149] The scan line SCL may extend in the first direction DR1. The scan line SCL may overlap the first scan pattern SC-1 and the second scan pattern SC-2. The scan line SCL may be connected to the first scan pattern SC-1 and the second scan pattern SC-2 through the first contact hole CNT1.

[0150] The first bridge pattern BP1-R may overlap the first active pattern A1-R included in the first pixel PX-R, and a portion of the first bridge pattern BP1-R may be connected to the first active pattern A1-R through the second contact hole CNT2. Another portion of the first bridge pattern BP1-R may be connected to the first light shielding pattern BML-R of the common electrode CP through the first contact hole CNT1.

[0151] The first bridge pattern BP1-G may overlap with the first active pattern A1-G included in the second pixel PX-G, and a portion of the first bridge pattern BP1-G may be connected to the first active pattern A1-G through the second contact hole CNT2. Another portion of the first bridge pattern BP1-G may be connected to the third active pattern A3-G through the second contact hole CNT2. Another portion of the first bridge pattern BP1-G may be connected to the second light-shielding pattern BML-G through the first contact hole CNT1.

[0152] The first bridge pattern BP1-B may overlap the first active pattern A1-B included in the third pixel PX-B, and a portion of the first bridge pattern BP1-B may be connected to the first active pattern A1-B through the second contact hole CNT2. Another portion of the first bridge pattern BP1-B may be connected to the third light-shielding pattern BML-B through the first contact hole CNT1.

[0153] The second bridge pattern BP2-R may overlap the second active pattern A2-R included in the first pixel PX-R, and a portion of the second bridge pattern BP2-R may be connected to the second active pattern A2-R through the second contact hole CNT2. Another portion of the second bridge pattern BP2-R may be connected to the first data line DL-R through the first contact hole CNT1.

[0154] The second bridge pattern BP2-G may overlap the second active pattern A2-G included in the second pixel PX-G, and a portion of the second bridge pattern BP2-G may be connected to the second active pattern A2-G through the second contact hole CNT2. Another portion of the second bridge pattern BP2-G may be connected to the second data line DL-G through the first contact hole CNT1.

[0155] The second bridge pattern BP2-B may overlap the second active pattern A2-B included in the third pixel PX-B, and a portion of the second bridge pattern BP2-B may be connected to the second active pattern A2-B through the second contact hole CNT2. Another portion of the second bridge pattern BP2-B may be connected to the third data line DL-B through the first contact hole CNT1.

[0156] The first bridge pattern BP1 -R may be connected to the first light-shielding pattern BML-R of the common electrode CP through the first contact hole CNT1 .

[0157] According to the present disclosure, the gate electrode GP may include a first bridge portion BR1, a first gate pattern G1-R, and a second bridge portion BR2 sequentially disposed in the second direction DR2. The first bridge portion BR1, the first gate pattern G1-R, and the second bridge portion BR2 may be substantially patterns and will be described separately for convenience of description.

[0158] The first gate pattern G1-R may overlap the first active pattern A1-R. The first bridge portion BR1 may overlap a portion of the first upper electrode C1-2. The first bridge portion BR1 may be connected to the first upper electrode C1-2 through the second contact hole CNT2.

[0159] The second bridge portion BR2 may overlap a portion of the second upper electrode C2-2. The second bridge portion BR2 may be connected to the second upper electrode C2-2 through the second contact hole CNT2.

[0160] The first gate pattern G1-G may overlap the first active pattern A1-G. The first gate pattern G1-G may be connected to the second capacitor pattern CSP-G through the second contact hole CNT2.

[0161] The first gate pattern G1-B may overlap the first active pattern A1-B. The first gate pattern G1-B may be connected to the third capacitor pattern CSP-B through the second contact hole CNT2.

[0162] The second gate pattern G2-R may overlap the second active pattern A2-R. The second gate pattern G2-R may be a portion protruding from the scan line SCL in the second direction DR2.

[0163] The second gate pattern G2-G may overlap the second active pattern A2-G. The second gate pattern G2-B may overlap the second active pattern A2-B. The second gate pattern G2-G and the second gate pattern G2-B may be different portions protruding from the scan line SCL in the second direction DR2.

[0164] The third gate pattern G3-R may overlap the third active pattern A3-R. The third gate pattern G3-R may be a portion protruding from the sensing line SSL in the second direction DR2.

[0165] The third gate pattern G3-G may overlap the third active pattern A3-G. The third gate pattern G3-B may overlap the third active pattern A3-B. The third gate pattern G3-G and the third gate pattern G3-B may be different portions protruding from the sensing line SSL in the second direction DR2.

[0166] The third bridge pattern BP3-R may overlap the third active pattern A3-R. A portion of the third bridge pattern BP3-R may be connected to the third active pattern A3-R through the second contact hole CNT2, and another portion of the third bridge pattern BP3-R may be connected to the first lower electrode C1-1 through the first contact hole CNT1.

[0167] The third bridge pattern BP3-B may overlap the third active pattern A3-B. A portion of the third bridge pattern BP3-B may be connected to the third active pattern A3-B through the second contact hole CNT2, and another portion of the third bridge pattern BP3-B may be connected to the third light blocking pattern BML-B through the first contact hole CNT1.

[0168] The first preliminary pattern IP1 and the second preliminary pattern IP2 may overlap the preliminary line IL. The first preliminary pattern IP1 may be connected to the preliminary line IL through the first contact hole CNT1 and connected to the third active patterns A3-R, A3-G, and A3-B through the second contact hole CNT2.

[0169] The second preliminary pattern IP2 may be spaced apart from the first preliminary pattern IP1 in the second direction DR2 and connected to the preliminary line IL through the first contact hole CNT1.

[0170] refer to Figure 5A , Figure 5B , Fig.6D and Fig. 6E The third insulating layer 30 may be disposed on the second insulating layer 20 and cover the third conductive layer MSL3. The third contact hole CNT3 may be defined in the third insulating layer 30.

[0171] The contact hole CNT-R may expose the third bridge pattern BP3-R, the contact hole CNT-G may expose the first bridge pattern BP1-G, and the contact hole CNT-B may expose the third bridge pattern BP3-B. The contact hole CNT-S may expose the second power line EL.

[0172] refer to Fig. 6E , the fourth conductive layer MSL4 may be disposed on the third insulating layer 30. The fourth conductive layer MSL4 may include: a power pattern EL-S; and a first electrode AE-R, a first electrode AE-G, and a first electrode AE-B.

[0173] The first electrode AE-R may be connected to the third bridge pattern BP3-R through the contact hole CNT-R, the first electrode AE-G may be connected to the first bridge pattern BP1-G through the contact hole CNT-G, and the first electrode AE-B may be connected to the third bridge pattern BP3-B through the contact hole CNT-B. The power pattern EL-S may be connected to the second power line EL through the contact hole CNT-S.

[0174] refer to Figure 5A , Figure 5B and Fig. 6F , the pixel definition film PDL may be arranged on the fourth conductive layer MSL4. The first opening PXA-R, the second opening PXA-G, the third opening PXA-B, and the power opening OP-E may be defined in the pixel definition film PDL. The first opening PXA-R, the second opening PXA-G, and the third opening PXA-B may be disposed on the fourth conductive layer MSL4. Figure 4 The first pixel area PXA-R, the second pixel area PXA-G and the third pixel area PXA-B described in FIG.

[0175] The first opening PXA-R may expose at least a portion of the first electrode AE-R, the second opening PXA-G may expose at least a portion of the first electrode AE-G, and the third opening PXA-B may expose at least a portion of the first electrode AE-B. The power opening OP-E may expose at least a portion of the second power line EL, and Figure 5B The second electrode CE described in can be connected to the power opening OP-E.

[0176] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure belongs will be able to make various modifications and changes.Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0177] The embodiments disclosed in this disclosure are not intended to limit the technical spirit of the disclosure, but are intended to describe the technical spirit of the disclosure, and the scope of the technical spirit of the disclosure is not limited by these embodiments. The protection scope of the disclosure shall be interpreted by the accompanying claims, and shall be interpreted as all technical spirits within the equivalent scope are included in the scope of the disclosure.

Claims

1. A display panel, comprising: a plurality of data lines disposed on the base layer, spaced apart from each other in a first direction and extending in a second direction intersecting the first direction; as well as a unit pixel electrically connected to the plurality of data lines and including a first pixel, a second pixel, and a third pixel each configured to provide light to the pixel area, Wherein, the first pixel comprises: A common electrode, the common electrode comprising a first lower electrode, a first light shielding pattern, and a second lower electrode arranged in sequence in the second direction; a first upper electrode, the first upper electrode overlapping the first lower electrode and configured with the first lower electrode to form a first capacitor; a second upper electrode, the second upper electrode overlapping the second lower electrode and configured with the second lower electrode to form a second capacitor; A first transistor, the first transistor comprising: an active pattern, the active pattern overlapping the first light shielding pattern, and a gate electrode overlapping the active pattern; and a light emitting element electrically connected to the first transistor, and One end of the gate electrode is electrically connected to the first upper electrode, and the other end of the gate electrode spaced apart from the one end in the second direction is electrically connected to the second upper electrode.

2. The display panel according to claim 1, further comprising: a first insulating layer, the first insulating layer being arranged on the base layer and covering the common electrode; a second insulating layer disposed on the first insulating layer and covering the first upper electrode and the second upper electrode; as well as a third insulating layer, the third insulating layer being arranged on the second insulating layer, Wherein, the one end of the gate electrode is electrically connected to the first upper electrode through a first contact hole defined in the second insulating layer, and the other end of the gate electrode is electrically connected to the second upper electrode through a second contact hole defined in the second insulating layer.

3. The display panel according to claim 2, wherein: The active pattern, the first upper electrode, and the second upper electrode are disposed at the same layer.

4. The display panel according to claim 3, wherein: The active pattern is arranged between the first upper electrode and the second upper electrode in the second direction.

5. The display panel according to claim 1, wherein: The first pixel further includes a second transistor and a third transistor, each of the second transistor and the third transistor including an active pattern and a gate electrode.

6. The display panel according to claim 5, wherein: Each of the second pixel and the third pixel includes: a capacitor; a first transistor, a second transistor, and a third transistor, each of which includes an active pattern and a gate electrode; and a light emitting element.

7. The display panel according to claim 6, wherein: The light emitting element included in each of the first pixel, the second pixel, and the third pixel includes: a first electrode; a second electrode; and a light emitting layer disposed between the first electrode and the second electrode.

8. The display panel according to claim 7, further comprising: a pixel defining film, wherein a plurality of openings exposing at least a portion of the first electrode of the unit pixel are defined in the pixel defining film, The pixel area of ​​each of the first pixel, the second pixel and the third pixel is defined by a corresponding opening of the plurality of openings.

9. The display panel according to claim 8, wherein: The pixel region of the first pixel is spaced apart from the pixel region of the third pixel in the second direction, and The pixel region of the second pixel is spaced apart from the pixel region of the first pixel and the pixel region of the third pixel in a diagonal direction intersecting the first direction and the second direction.

10. The display panel according to claim 9, wherein: The first pixel, the second pixel, and the third pixel provide the same light.

11. The display panel according to claim 10, wherein: An area of ​​the pixel region of the first pixel is smaller than an area of ​​the pixel region of the second pixel and larger than an area of ​​the pixel region of the third pixel.

12. The display panel according to claim 10, wherein: At least a portion of the gate electrode overlaps the pixel region of the first pixel.

13. The display panel according to claim 6, wherein: Among the plurality of data lines, a first data line electrically connected to the first pixel is spaced apart from a second data line electrically connected to the second pixel in the first direction, the active pattern of the first transistor and the active pattern of the second transistor are arranged between the first data line and the second data line, and A third data line electrically connected to the third pixel and the first data line are spaced apart from each other in the first direction, and the second data line is disposed between the third data line and the first data line.

14. The display panel according to claim 13, further comprising: A plurality of light shielding patterns overlap the active pattern included in the second pixel and the active pattern included in the third pixel and are spaced apart from each other in the second direction.

15. The display panel according to claim 14, wherein: The plurality of light shielding patterns are disposed between the first data line, the second data line, and the third data line.

16. The display panel according to claim 15, wherein: The plurality of data lines and the plurality of light shielding patterns include the same material.

17. The display panel according to claim 5, wherein: The active pattern included in the second transistor of the first pixel is integrated with the second upper electrode.

18. The display panel according to claim 1, further comprising: An encapsulation layer covers the first pixel, the second pixel, and the third pixel and includes a first inorganic layer, a second inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer.

19. The display panel according to claim 1, wherein: The active pattern, the first upper electrode, and the second upper electrode include the same material.

20. The display panel according to claim 1, wherein: An area of ​​the first upper electrode is greater than an area of ​​the second upper electrode.

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