Method for manufacturing electronic device

Abstract

The invention discloses a manufacturing method of an electronic device. The manufacturing method comprises the following steps: providing a substrate; disposing a conductive layer on the substrate; a patterning step is carried out to pattern the conductive layer, so that the conductive layer forms a grid structure with a plurality of grid units, and the patterned conductive layer at least comprises a first part and a second part; and carrying out an electroplating step to electroplate at least one of the first part and the second part, and enabling the first part and the second part to be different in thickness after the electroplating step.

Description

Technical Field

[0001] The present invention relates to a manufacturing method of an electronic device, and in particular to a manufacturing method for improving the display quality and yield of the electronic device. Background Art

[0002] With the evolution and development of electronic devices, electronic devices have become indispensable items in today's society. Among them, electronic devices with display functions (such as display panels and display devices) can provide more convenient information transmission or image display. In order to make electronic devices such as display panels and display devices have good display quality and improve their manufacturing yield, the industry is committed to developing manufacturing methods for these electronic devices and / or manufacturing methods for structures set in these electronic devices to improve existing display problems and manufacturing problems. Summary of the invention

[0003] An object of the present invention is to provide a method for manufacturing an electronic device.

[0004] In one embodiment, the present invention provides a method for manufacturing an electronic device, which includes: providing a substrate; setting a conductive layer on the substrate; performing a patterning step to pattern the conductive layer so that the conductive layer forms a grid structure having a plurality of grid units, and the patterned conductive layer includes at least a first part and a second part; and performing an electroplating step to electroplate at least one of the first part and the second part, and the thickness of the first part and the second part after the electroplating step is different.

[0005] In one embodiment, the present invention further provides a method for manufacturing an electronic device, comprising: providing a substrate; and performing an inkjet printing step to form a conductive layer on the substrate. The conductive layer comprises a grid structure having a plurality of grid units, and the conductive layer comprises at least a first portion and a second portion, and the first portion and the second portion have different thicknesses. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. 4 is a cross-sectional schematic diagram of a display unit of an electronic device according to an embodiment of the present invention.

[0007] Figure 2 FIG. 4 is a schematic top view of a display unit of an electronic device according to an embodiment of the present invention.

[0008] Figure 3 FIG. 1 is a schematic top view of a grid structure of a conductive layer of an electronic device according to an embodiment of the present invention.

[0009] Figure 4 FIG. 1 is a schematic top view of a grid structure of a conductive layer of an electronic device according to another embodiment of the present invention.

[0010] Figures 5 to 7Schematic diagram of the structure of the manufacturing method of the electronic device at different stages according to the first embodiment of the present invention.

[0011] Figure 8 FIG. 1 is a schematic diagram showing the relationship between current density and metal growth rate in the electroplating step of the method for manufacturing an electronic device according to the first embodiment of the present invention.

[0012] Figures 9 to 13 Schematic diagram of the structure of the manufacturing method of the electronic device at different stages according to the second embodiment of the present invention.

[0013] Figure 14 to Figure 15 Schematic diagram of the structure of the manufacturing method of the electronic device in different stages according to the third embodiment of the present invention.

[0014] Figures 16 to 18 Schematic diagram of the structure of the manufacturing method of the electronic device in different stages according to the fourth embodiment of the present invention.

[0015] Figures 19 to 23 Schematic diagram of the structure of the manufacturing method of the electronic device in different stages according to the fifth embodiment of the present invention.

[0016] Figure 24 to Figure 25 Schematic diagram of the structure of the manufacturing method of the electronic device in different stages according to the sixth embodiment of the present invention.

[0017] Explanation of reference numerals: 100-electronic device; 110-substrate; 120, 140, 160-conductive layer; 120_1-first conductive sublayer; 120_2-second conductive sublayer; 120_3-third conductive sublayer; 120A-first part; 120B-second part; 120C-third part; 120M-grid unit; 122-co-alignment structure; 122a-first sub-part; 122b-second sub-part; 122c-third sub-part; 122d-fourth sub-part; 124-scanning line; 126-floating structure; 130-first insulating layer; 144-data line; 150-second insulating layer; 162-pixel electrode; 162a, 162b, 162c, 162d-region; 164-co-linear connection structure; 170-opposite substrate; BM -shading layer; CCL-color conversion layer; CH-channel layer; D1, D2, X, Y, Z-directions; DE-drain; DML-display medium layer; DU-display unit; ECL-circuit element layer; GE-gate; GP-gap; I1-first current; I2-second current; MK-metal ink; ML1, ML2-metal layer; MS-grid structure; NZ-nozzle; OE-opposite electrode; PR-photoresist layer; PR1-first part; PR2-second part; SE-source; SK1-first conductive stack; SK2-second conductive stack; SK3-third conductive stack; SL-slit; SM-semiconductor layer; SW-switching element; T1-first thickness; T2-second thickness; T3-third thickness; VA1, VA2, VA3-conductive connection structure. DETAILED DESCRIPTION

[0018] The present invention can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to facilitate the understanding of the readers and the simplicity of the drawings, the multiple drawings in the present invention only depict a portion of the image display device, and the specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the drawings are only for illustration and are not intended to limit the scope of the present invention.

[0019] Certain words are used throughout the specification and the appended claims to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components with different names. The present invention is not intended to distinguish between components with the same function but different names.

[0020] In the present specification and claims, the words "include", "contain", "have" and the like are open-ended words, and therefore should be interpreted as "including but not limited to..." Therefore, when the terms "include", "contain" and / or "have" are used in the description of the present invention, they specify the existence of corresponding features, regions, steps, operations and / or components, but do not exclude the existence of one or more corresponding features, regions, steps, operations and / or components.

[0021] Directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", etc., are only referenced to the directions of the drawings. Therefore, the directional terms used are used to illustrate, but not to limit the present invention. In the drawings, each figure depicts the general characteristics of the methods, structures and / or materials used in a particular embodiment. However, these drawings should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative size, thickness and position of each film layer, region and / or structure may be reduced or enlarged.

[0022] When a corresponding component (such as a film layer or region) is referred to as being "on another component", it may be directly on the other component, or other components may exist between the two. On the other hand, when a component is referred to as being "directly on another component", there is no component between the two. In addition, when a component is referred to as being "on another component", the two have a vertical relationship, and the component may be above or below the other component, and the vertical relationship depends on the orientation of the device.

[0023] It should be understood that when a component or a film layer is referred to as being "connected to" another component or a film layer, it can be directly connected to the other component or film layer, or there can be an intervening component or film layer between the two. When a component is referred to as being "directly connected to" another component or a film layer, there can be no intervening component or film layer between the two. In addition, when a component is referred to as being "coupled to another component (or a variation thereof)", it can be directly connected to the other component, indirectly connected (e.g., electrically connected) to the other component through one or more components.

[0024] It should be understood that in the specification and claims, the term "horizontal direction" refers to a direction parallel to a horizontal plane, the term "horizontal plane" refers to a surface parallel to directions X and Y in the drawings, and the term "vertical direction" refers to a direction parallel to direction Z in the drawings, wherein directions X, Y, and Z are perpendicular to each other. In the specification and claims, the term "top view" refers to a viewing result viewed along a vertical direction, and the term "cross-section" refers to a viewing result when a structure is cut along a vertical direction and viewed from a horizontal direction.

[0025] It should be understood that in the specification and claims, the term “overlap” refers to the overlap of two components in the direction Z, and if not specified, the term “overlap” includes partial overlap or complete overlap.

[0026] It should be understood that in the specification and claims, the term "thickness" refers to the maximum distance between two opposite surfaces of a component in the direction Z, and the thickness of the component can be measured by any suitable method. For example, the thickness of the component can be measured by a microscope (e.g., an optical microscope, a scanning electron microscope (SEM)).

[0027] The terms "approximately" or "same" are generally interpreted to mean within plus or minus 20% of a given value, or within plus or minus 10%, plus or minus 5%, plus or minus 3%, plus or minus 2%, plus or minus 1%, or plus or minus 0.5% of a given value.

[0028] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify the elements. They do not imply or represent any previous ordinal numbers of the element (or elements), nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make the element with a certain name clearly distinguishable from another element with the same name. The same words may not be used in the claims and the specification. Accordingly, the first component in the specification may be the second component in the claims.

[0029] It should be noted that the following embodiments may replace, reorganize, or mix features in several different embodiments to complete other embodiments without departing from the spirit of the present invention. Features between embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0030] In the present invention, the electronic device may be exemplified as a non-self-luminous display panel or a self-luminous display panel according to requirements, and may be exemplified as a color display panel or a monochrome display panel according to requirements. In the present invention, the electronic components in the electronic device may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light emitting diode (LED) or a photodiode. The light emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (miniLED), a micro LED, or a quantum dot light emitting diode (quantum dot LED), but is not limited thereto. The transistor may include, for example, a top gate thin film transistor, a bottom gate thin film transistor, or a dual gate thin film transistor, but is not limited thereto. The electronic device may also include, according to requirements, a fluorescence material, a phosphor material, a quantum dot (QD) material, or other suitable materials, but is not limited thereto. The electronic device may also have peripheral systems such as a driving system, a control system, a light source system, etc. to support the devices and components in the display panel. In the present invention, the display panel may be included in the electronic device, and the electronic device may also include a light-emitting device, an antenna device, a sensing device, a splicing device or any combination thereof, but not limited thereto. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, the sensing device may be a sensing device for sensing capacitance, light, heat or ultrasound, and the splicing device may be a display panel splicing device or an antenna splicing device, but not limited thereto.

[0031] In the present invention, the electronic device is described by taking a non-self-luminous color display panel as an example, but the invention is not limited thereto.

[0032] Please refer to Figures 1 to 3 , Figure 1 is a cross-sectional schematic diagram of a display unit of an electronic device according to an embodiment of the present invention, Figure 2 is a schematic top view of a display unit of an electronic device according to an embodiment of the present invention, Figure 3 FIG. 1 is a schematic top view of a grid structure of a conductive layer of an electronic device according to an embodiment of the present invention. Figure 1 and Figure 2As shown, the electronic device 100 may include a plurality of display units DU, wherein the display unit DU may be used as the smallest unit of the display screen, such as a sub-pixel (Sub-pixel) displaying a single color, but the present invention is not limited thereto. In the present embodiment, since the electronic device 100 is a color display panel, a plurality of display units DU may form a display group (or referred to as a pixel), and the display units DU in the display group may correspond to different colors, and the number and color of the display units DU included in the display group may be changed according to demand (e.g., a display group may include a green display unit, a red display unit, and a blue display unit, but is not limited thereto). In other embodiments, when the electronic device 100 is a monochrome display panel, the display units DU may correspond to the same color.

[0033] In the present invention, the number, arrangement and shape of the display units DU can be adjusted according to the requirements. Figure 2 In the embodiment, the display units DU may be substantially rectangular, and the display units DU are arranged in a matrix in the directions X and Y, but the present invention is not limited thereto.

[0034] like Figure 1 and Figure 2 As shown, the electronic device 100 may include a substrate 110 and may optionally include an opposing substrate 170, wherein the substrate 110 and the opposing substrate 170 may each be a hard substrate or a flexible substrate, and the materials of the substrate 110 and the opposing substrate 170 may include, for example, glass, quartz, ceramic, sapphire, polymer (e.g., polyimide (PI), polyethylene terephthalate (PET)), other suitable materials or combinations thereof according to their types. In some embodiments, the structures and elements included in the display unit DU may be disposed on the substrate 110 and / or between the substrate 110 and the opposing substrate 170. It should be noted that the normal direction of the substrate 110 and the normal direction of the opposing substrate 170 may be parallel to the direction Z.

[0035] Since the electronic device 100 is a non-self-luminous display panel, Figure 1As shown, the electronic device 100 may include a display medium layer DML, which is disposed between the substrate 110 and the opposing substrate 170. The display medium layer DML may include suitable materials according to the type of the electronic device 100, such as liquid crystal molecules or other suitable display medium materials, but is not limited thereto. The display medium material included in the display medium layer DML may be adjusted in any suitable manner to adjust the state of the portion of the display medium layer DML corresponding to each display unit DU, thereby correspondingly adjusting the light transmittance in each display unit DU. For example, in some embodiments, the state of the display medium layer DML may be controlled by an electric field and / or an electric signal.

[0036] In the present invention, the electrodes for controlling the state of the display medium layer DML can be designed according to the requirements. For example, the multiple electrodes for controlling the display medium layer DML can be arranged on the opposite sides of the display medium layer DML (that is, part of the electrodes are arranged between the display medium layer DML and the substrate 110, and part of the electrodes are arranged between the display medium layer DML and the opposite substrate 170, so that the display medium layer DML is arranged between these electrodes), but it is not limited thereto. For example, the multiple electrodes for controlling the display medium layer DML can be arranged on the same side of the display medium layer DML, but it is not limited thereto. In some embodiments, each display unit DU may include at least two electrodes for controlling the display medium layer DML, so that the state of the display medium material of the corresponding display unit DU in the display medium layer DML can be adjusted according to the electrical signal (such as grayscale signal) received by the electrode, thereby adjusting the light transmittance of each display unit DU. In the following text, the electrodes for controlling the state of the display medium layer DML can be arranged on the opposite sides of the display medium layer DML, but the present invention is not limited thereto.

[0037] like Figure 1 and Figure 2 As shown, the circuit element layer ECL may be disposed on the substrate 110 and exist between the substrate 110 and the display medium layer DML, wherein the circuit element layer ECL may include at least one conductive layer, at least one insulating layer, at least one semiconductor layer or a combination thereof to form electronic components in the circuit element layer ECL (e.g., electronic components in the display unit DU). Examples of materials for the conductive layer may include metals, transparent conductive materials (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), etc.), other suitable conductive materials or a combination thereof, and examples of materials for the insulating layer may include silicon oxide (SiO x ), Silicon Nitride (SiN y ), silicon oxynitride (SiO x N y), organic insulating materials (such as photosensitive resins), other suitable insulating materials or combinations thereof, examples of materials for the semiconductor layer may include polysilicon, amorphous silicon, metal-oxide semiconductor semiconductors, other suitable semiconductor materials or combinations thereof, but are not limited thereto. It should be noted that the conductive layer and the insulating layer may be designed as a single-layer structure or a multi-layer structure according to requirements. For example, in Figure 1 and Figure 2 In the figure, the circuit element layer ECL may include a conductive layer 120, a first insulating layer 130, a semiconductor layer SM, a conductive layer 140, a second insulating layer 150 and a conductive layer 160, which are sequentially arranged on the substrate 110, wherein the conductive layer 120 may include at least one metal layer, the conductive layer 140 may include at least one metal layer, and the conductive layer 160 may be a transparent conductive layer, but is not limited thereto.

[0038] The circuit element layer ECL may include any suitable electronic components and is formed by the film layers in the circuit element layer ECL. Figure 1 and Figure 2 In the embodiment, the circuit element layer ECL may include a switch element SW, which is disposed in the display unit DU, wherein the switch element SW may be a top gate thin film transistor, a bottom gate thin film transistor, a dual gate thin film transistor or other suitable switch elements ( Figure 1 and Figure 2 The switch element SW in the embodiment is a bottom-gate thin film transistor. For example, the conductive layer 120 may include a gate GE of the switch element SW, the first insulating layer 130 may include a gate insulating layer of the switch element SW, the semiconductor layer SM may include a channel layer CH of the switch element SW, and the conductive layer 140 may include a source SE and a drain DE of the switch element SW, but the invention is not limited thereto. Figure 1 and Figure 2 Although only one switch element SW is shown to be disposed in the display unit DU, the number of switch elements SW in the display unit DU can be designed according to requirements.

[0039] exist Figures 1 to 3In the present invention, the circuit element layer ECL also includes a scan line 124 and a data line 144, wherein the scan line 124 can be used to transmit a switch signal to control the opening and closing of the switch element SW, and the data line 144 is used to transmit an electrical signal related to the display screen (such as a grayscale signal). For example, the scan line 124 can be electrically connected to the gate GE of the switch element SW, and the data line 144 can be electrically connected to the source SE of the switch element SW, but it is not limited to this. In the present invention, the conductive layer 120 includes the scan line 124 (that is, the scan line 124 and the gate GE can be formed by the same film layer), and the conductive layer 140 includes the data line 144 (that is, the data line 144 and the source SE can be formed by the same film layer). Therefore, in Figures 1 to 3 In the embodiment, a portion of the scan line 124 and a portion of the data line 144 may be disposed in the display unit DU. Figures 1 to 3 In the embodiment, the scan line 124 may be (substantially) parallel to the direction X, so that the scan line 124 may pass through at least two display units DU in the direction X, and the data line 144 may be (substantially) parallel to the direction Y, so that the data line 144 may pass through at least two display units DU in the direction Y, but the present invention is not limited thereto.

[0040] In the present invention, the conductive layer 120 of the circuit element layer ECL further includes a common voltage structure 122 for receiving a common voltage or grounding, wherein at least a portion of the common voltage structure 122 is disposed in the display unit DU, and the common voltage structure 122 and the scan line 124 are separated from each other and are not electrically connected to each other. In the present invention, the common voltage structure 122 can have any suitable pattern according to requirements. For example, in Figures 1 to 3 In the embodiment, the co-aligned structure 122 may include a first sub-portion 122a, a second sub-portion 122b and a third sub-portion 122c. The first sub-portion 122a may be directly connected to the second sub-portion 122b and the third sub-portion 122c. The first sub-portion 122a may be (substantially) parallel to the direction X, and the second sub-portion 122b and the third sub-portion 122c may be (substantially) parallel to the direction Y and opposite to each other in the direction X, so that the co-aligned structure 122 has a U-shaped pattern, but is not limited thereto. For example, in Figure 4In the embodiment, the co-aligned structure 122 may include a first sub-portion 122a, a second sub-portion 122b, a third sub-portion 122c, and a fourth sub-portion 122d. The first sub-portion 122a and the fourth sub-portion 122d may be directly connected to the second sub-portion 122b and the third sub-portion 122c. The first sub-portion 122a and the fourth sub-portion 122d may be (substantially) parallel to the direction X and opposite to each other in the direction Y. The second sub-portion 122b and the third sub-portion 122c may be (substantially) parallel to the direction Y and opposite to each other in the direction X, so that the co-aligned structure 122 has a closed shape (e.g., a square shape), but not limited thereto. In some embodiments, the co-aligned structure 122 may overlap or be adjacent to at least one edge of the display unit DU, but not limited thereto. For example, in Figures 1 to 4 In the embodiment, the co-aligned structure 122 may overlap three edges of the display unit DU, and the scan line 124 may overlap or be adjacent to another edge of the display unit DU, but is not limited thereto.

[0041] like Figures 1 to 4 As shown in FIG. 1 , the common alignment structures 122 in different display units DU may be electrically connected to each other. Figures 1 to 4 In the embodiment, the co-aligned structures 122 in the adjacent display units DU in the direction X can be electrically connected to each other through the first sub-portions 122a of the co-aligned structures 122, but the present invention is not limited thereto. Figures 1 to 4 In the display units DU adjacent to each other in the direction Y, the third sub-portion 122c (or the fourth sub-portion 122d) of one common-position structure 122 can be electrically connected to the first sub-portion 122a of another common-position structure 122 through the conductive structure of other film layers (for example, the common-line connection structure 164 of the conductive layer 160 crosses the scan line 124 and is electrically connected between the two common-position structures 122), but is not limited thereto.

[0042] Depend on Figures 1 to 4 It can be known that the common position structure 122 and the scan line 124 formed by the conductive layer 120 of the circuit element layer ECL through the patterning step can form a mesh structure MS similar to a mesh, and the mesh structure MS can include a plurality of mesh units 120M, and one display unit DU can correspond to one mesh unit 120M (for example, the related electrodes and other components of one display unit DU are set within the range of one mesh unit 120M). For example, in Figures 1 to 3 In the example, the co-aligned structure 122 and the scan line 124 may form a square-shaped grid unit 120M in a top view (since the co-aligned structure 122 and the scan line 124 are separated from each other, Figures 1 to 3 The grid unit 120M shown is composed of two separate parts), wherein the co-alignment structure 122 may include three edges of the grid unit 120M, and the scan line 124 may include one edge of the grid unit 120M, but is not limited thereto. Figure 4 In the embodiment, the co-aligned structure 122 may form a square-shaped grid unit 120M in a top view, wherein the co-aligned structure 122 may include four edges (ie, all edges) of the grid unit 120M, but is not limited thereto. According to the above, the co-aligned structure 122 may include at least one edge of the grid unit 120M.

[0043] From another perspective, Figures 1 to 4 In the embodiment, since the plurality of co-aligned structures 122 are disposed adjacent to each other and / or connected to each other (e.g., the co-aligned structures 122 adjacent to each other in the direction X are connected to each other through the first sub-portions 122a, and the co-aligned structures 122 adjacent to each other in the direction Y are disposed adjacent to each other), these grid units 120M may be combined into a grid structure MS (i.e., the conductive layer 120 may include a grid structure MS having a plurality of grid units 120M). In addition, since the co-aligned structures 122 in the display units DU adjacent to each other in the direction X are continuously arranged along the direction X, and the scan line 124 may pass through at least two display units DU in the direction X, the scan line 124 may correspond to at least two grid units 120M (e.g., Figure 3 The scan line 124 may include a portion of the corresponding grid unit 120M, Figure 4 The scan line 124 may be adjacent to the corresponding grid unit 120M in the direction Y). For example, the scan line 124 may correspond to the grid units 120M arranged in a row in the direction X, but is not limited thereto.

[0044] exist Figure 1 and Figure 2 In the embodiment, the conductive layer 160 of the circuit element layer ECL may include a pixel electrode 162, which is disposed in the display unit DU, wherein the pixel electrode 162 is used to receive a grayscale signal to control the state of the display medium layer DML, so that each display unit DU can generate light with a corresponding light intensity according to the grayscale signal received by its pixel electrode 162, thereby enabling the electronic device 100 to display a picture. Figure 1 and Figure 2 In the embodiment, the pixel electrode 162 may be electrically connected to the drain DE of the switch element SW to receive the grayscale signal, but the present invention is not limited thereto. Figure 1 and Figure 2 In the embodiment, the pixel electrode 162 may include a plurality of slits SL to enhance the control effect of the pixel electrode 162 on the state of the display medium layer DML, thereby enhancing the display quality of the screen of the electronic device 100. Figure 2In the embodiment, the pixel electrode 162 may have four regions 162a, 162b, 162c, and 162d arranged in a 2x 2 matrix, the slits SL in the regions 162a and 162c may extend along a direction D1, and the slits SL in the regions 162b and 162d may extend along a direction D2, wherein the directions D1 and D2 are not parallel to each other, the directions D1 and D2 are perpendicular to the direction Z, and the directions D1 and D2 are not parallel to the directions X and Y, but the invention is not limited thereto. It should also be noted that, in some embodiments, the edge of the pixel electrode 162 may partially overlap with the co-location structure 122 to reduce light leakage, but the invention is not limited thereto.

[0045] Optionally, in Figures 1 to 3 In the embodiment, the circuit element layer ECL further includes a floating structure 126 disposed in the display unit DU to improve the display quality of the electronic device 100 (e.g., the display quality of the electronic device 100 at a side viewing angle), wherein the floating structure 126 may be in a floating state without being electrically connected to any electronic element. Figures 1 to 3 In the embodiment, the floating structure 126 may be a strip-shaped structure extending along the direction Y, and the floating structure 126 may be disposed between the region 162a and the region 162b of the pixel electrode 162 and between the region 162c and the region 162d of the pixel electrode 162 in a top view, so as to reduce light leakage and improve the contrast of the display image, but the present invention is not limited thereto. Figures 1 to 3 In the present invention, the floating structure 126 may be included in the conductive layer 120 and is not electrically connected to the common alignment structure 122 and the scan line 124, wherein the floating structure 126 may be disposed between the second sub-portion 122b and the third sub-portion 122c of the common alignment structure 122 in a top view, but is not limited thereto.

[0046] According to the above, if Figure 1 As shown, the conductive layer 120 may include a scan line 124 , a common-level structure 122 , and a floating structure 126 , such that the scan line 124 , the common-level structure 122 , and the floating structure 126 belong to the same conductive layer.

[0047] In the present invention, the circuit element layer ECL may also include other required structures according to requirements. Figure 1 and Figure 2 In the embodiment, the circuit element layer ECL further comprises a conductive connection structure, which is arranged in the connection hole of the insulating layer to connect different conductive layers in the circuit element layer ECL. Figure 1 and Figure 2In the embodiment, the pixel electrode 162 can be electrically connected to the drain DE of the switch element SW through the conductive connection structure VA1, and the co-linear connection structure 164 can be electrically connected to the third sub-portion 122c (or the third sub-portion 122c) of the co-level structure 122 through the conductive connection structures VA2 and VA3. Figure 4 The fourth sub-portion 122d) and the first sub-portion 122a of another co-aligned structure 122, but the present invention is not limited thereto.

[0048] exist Figure 1 In the embodiment, the electronic device 100 may further include an opposite electrode OE disposed between the opposite substrate 170 and the display medium layer DML, wherein the opposite electrode OE is transparent and includes a transparent conductive material (e.g., indium tin oxide, indium zinc oxide, etc.). In some embodiments, the electric field generated by the opposite electrode OE and the pixel electrode 162 may be used to adjust the state of the display medium layer DML. For example, the opposite electrode OE may receive a common signal, but is not limited thereto.

[0049] In the present invention, the electronic device 100 may also include other required film layers, components and / or structures according to needs. In some embodiments, when the electronic device 100 is a color display panel, the electronic device 100 may also include a color conversion layer CCL, which is disposed between the substrate 110 and the opposite substrate 170 to convert or filter light (e.g., white light) into light of different colors, wherein the color conversion layer CCL may include a color filter, a quantum dot (QD) material, a fluorescent material, a phosphorescent material, other suitable materials or any combination thereof, but is not limited thereto. Figure 1 As shown, the color conversion layer CCL may be disposed between the display medium layer DML and the opposite substrate 170. In other embodiments, the color conversion layer CCL is disposed above the opposite substrate 170, so that the opposite substrate 170 is located between the display medium layer DML and the color conversion layer CCL. In other embodiments, the color conversion layer CCL may be disposed between the display medium layer DML and the substrate 110 together with the circuit element layer ECL.

[0050] In some embodiments, the electronic device 100 may further include a light shielding layer BM having light shielding properties to shield areas with poor display effects and improve the display quality of the electronic device 100, wherein the light shielding layer BM may include, for example, black photoresist, black ink, black resin, black pigment, other suitable materials or combinations thereof. The light shielding layer BM may be in the same layer as the color conversion layer CCL, that is, the upper surface or lower surface of the light shielding layer BM and the color conversion layer CCL may contact the same other film layer (such as the opposing substrate 170 and / or the opposing electrode OE), and the position of the light shielding layer BM may change with the color conversion layer CCL. For example, in Figure 1In the embodiment, the light shielding layer BM may be disposed between the display medium layer DML and the opposite substrate 170, but is not limited thereto. In some embodiments, the light shielding layer BM may have a plurality of openings to define the light emitting area of ​​the display unit DU and to separate the display unit DU in a plan view.

[0051] like Figure 1 As shown, the present invention can make the structures in the conductive layer 120 have different thicknesses through process design. In some embodiments, Figure 1 As shown, the co-aligned structure 122 may have a first thickness T1, the scan line 124 may have a second thickness T2, and the floating structure 126 may have a third thickness T3, and the first thickness T1, the second thickness T2 and the third thickness T3 are different from each other. In some embodiments, since the scan line 124 needs to have a low impedance characteristic and the floating structure 126 has no electrical requirements, the second thickness T2 of the scan line 124 may be greater than the first thickness T1 of the co-aligned structure 122, and the first thickness T1 of the co-aligned structure 122 may be greater than the third thickness T3 of the floating structure 126. For example, the first thickness T1 of the co-aligned structure 122 may be 600 angstroms. The second thickness T2 of the scan line 124 may be greater than or equal to 6000 angstroms, for example, the second thickness T2 may be 6000 angstroms to 9000 angstroms (6000 angstroms ≤ T2 ≤ 9000 angstroms), and the third thickness T3 of the floating structure 126 may be 200 angstroms to 400 angstroms (200 angstroms ≤ T3 ≤ 400 angstroms), but is not limited thereto. Accordingly, the thicknesses of the co-aligned structure 122, the scan line 124, and the floating structure 126 may correspond to their electrical requirements.

[0052] There may be manufacturing errors (such as alignment errors, film layer offsets, etc.) during the manufacturing process of the electronic device 100. Since the edges of the structures in the conductive layer generally have chamfers (such as Figure 1 As shown, there is a slope at the edge of the structure of the conductive layer), therefore, when the thickness of the conductive layer is greater, the conductive layer has a greater impact on the display medium material in the display medium layer DML, so that the display quality of the display image will decrease as the thickness of the conductive layer increases (for example, the tilt angle of the liquid crystal molecules becomes larger and the light leakage phenomenon increases). For example, when manufacturing errors occur, the degree of water ripples (mura) of the display image will increase as the thickness of the conductive layer increases. Since part of the structure in the conductive layer 120 of the present invention has a thinner thickness, even if the electronic device 100 has a manufacturing error during the manufacturing process, the design of the present invention can reduce the light leakage caused by the conductive layer 120 and / or reduce the impact of the conductive layer 120 on the display medium material in the display medium layer DML, thereby improving the display quality of the display image (i.e., reducing mura).

[0053] On the other hand, since the edges of the structures in the conductive layer generally have chamfers, when the thickness of the conductive layer increases, the area of ​​the upper surface (i.e., the horizontal surface) of the conductive layer decreases, so that the contact area between the photoresist layer used in the subsequent process and the upper surface of the conductive layer decreases, thereby causing the photoresist layer to be easily peeled off from the conductive layer, resulting in a decrease in the yield of the electronic device. In the present invention, since some structures in the conductive layer 120 have a thinner thickness, the contact area between the upper surface of these structures and the photoresist layer can be increased to reduce the probability of the photoresist layer peeling off from the conductive layer 120, thereby improving the yield of the electronic device 100.

[0054] In addition, if Figure 1 As shown, since part of the structure of the conductive layer 120 of the present invention has a thinner thickness, the distance between the conductive layers on two opposite sides of the display medium layer DML (e.g., the conductive layer 160 and the opposite electrode OE) can be increased to reduce the probability of the two conductive layers being short-circuited (e.g., the two conductive layers are conductive during the manufacturing process) and thus being damaged, thereby improving the yield of the electronic device 100.

[0055] The manufacturing method of the electronic device 100 will be described below, wherein the manufacturing method of the present invention is not limited to the following text and drawings. In some embodiments, any other suitable steps may be added before or after one of the existing steps of the manufacturing method, and / or some steps may be performed simultaneously or separately.

[0056] In the following manufacturing methods, examples of processes for forming the film layer and / or structure may include atomic layer deposition (ALD), chemical vapor deposition (CVD), coating processes, other suitable processes or combinations thereof. Examples of patterning processes may include photolithography processes, etching processes, any other suitable processes or combinations thereof, wherein the etching process may be a wet etching process, a dry etching process, any other suitable etching process or combinations thereof.

[0057] Please refer to Figures 5 to 8 , Figures 5 to 7 Schematic diagram of the structure of the manufacturing method of the electronic device in different stages according to the first embodiment of the present invention, Figure 8 FIG. 1 is a schematic diagram showing the relationship between the current density and the metal growth rate in the electroplating step of the method for manufacturing an electronic device according to the first embodiment of the present invention. Figure 5As shown, a substrate 110 is provided first, and a first conductive sublayer 120_1 in a conductive layer 120 is formed on the substrate 110, wherein the first conductive sublayer 120_1 may include metal (e.g., molybdenum (Mo), aluminum (Al), copper (Cu)), a transparent conductive material (e.g., indium tin oxide (ITO)), other suitable conductive materials or a combination thereof, and the first conductive sublayer 120_1 may be designed as a single-layer structure or a multi-layer structure according to requirements. For example, in Figure 5 In the embodiment, the first conductive sub-layer 120_1 may be a multi-layer structure including a metal layer ML1 (eg, molybdenum) and a metal layer ML2 (eg, aluminum or copper), but is not limited thereto.

[0058] like Figure 5 and Figure 6 As shown, a patterning step (e.g., a lithography process) is performed to pattern the first conductive sublayer 120_1, so that the first conductive sublayer 120_1 (i.e., the conductive layer 120) includes a first portion 120A, a second portion 120B, and a third portion 120C, wherein the first portion 120A may form a co-aligned structure 122 in a subsequent process, the second portion 120B may form a scan line 124 in a subsequent process, and the third portion 120C may form a floating structure 126 in a subsequent process. Moreover, after the patterning step, the first conductive sublayer 120_1 (i.e., the conductive layer 120) has a grid structure MS (see above) of a plurality of grid units 120M.

[0059] In detail, Figure 5 In the process, a photoresist layer PR is formed on the first conductive sublayer 120_1, and then the photoresist layer PR is patterned by a yellow light process and a development process. Figure 6 As shown, an etching process is performed on the first conductive sub-layer 120_1, and the photoresist layer PR is removed to complete the patterning step of the first conductive sub-layer 120_1.

[0060] like Figure 7 and Figure 8 As shown, an electroplating step is performed to energize the first conductive sublayer 120_1 to electroplate at least one of the first portion 120A, the second portion 120B, and the third portion 120C, and the first portion 120A, the second portion 120B, and the third portion 120C have different thicknesses after the electroplating step, thereby forming a common alignment structure 122, a scan line 124, and a floating structure 126 with different thicknesses. For example, in Figure 7In the electroplating step, the first portion 120A and the second portion 120B may be energized (i.e., the first portion 120A and the second portion 120B are coupled to an external device that provides current), and the third portion 120C is not energized, so that the second conductive sublayer 120_2 of the conductive layer 120 is formed on the first portion 120A and the second portion 120B but not on the third portion 120C; that is, in Figure 7 In the embodiment, the first portion 120A (i.e., the common alignment structure 122) and the second portion 120B (i.e., the scan line 124) of the conductive layer 120 are stacked structures of the first conductive sub-layer 120_1 and the second conductive sub-layer 120_2, and the third portion 120C (i.e., the floating structure 126) of the conductive layer 120 is a structure formed by the first conductive sub-layer 120_1, but the present invention is not limited thereto. It should be noted that the second conductive sub-layer 120_2 can be a metal layer including any suitable metal (e.g., aluminum or copper).

[0061] exist Figure 7 and Figure 8 In the electroplating step, the first portion 120A may be coupled to the first current I1, and the second portion 120B may be coupled to the second current I2, and the current density (or current strength) of the first current I1 and the second current I2 is different, so that the metal growth rate of the first portion 120A and the second portion 120B in the electroplating step is different (that is, the formation speed of the second conductive sublayer 120_2 on the first portion 120A and the second portion 120B is different), so as to cause the thickness of the second conductive sublayer 120_2 on the first portion 120A to be different from the thickness of the second conductive sublayer 120_2 on the second portion 120B, thereby causing the first portion 120A (that is, the co-aligned structure 122) and the second portion 120B (that is, the scan line 124) to have different thicknesses after electroplating. Figure 7 and Figure 8 In the embodiment, the current density (or current intensity) of the second current I2 is greater than the current density (or current intensity) of the first current I1, so that the second thickness T2 of the second portion 120B (i.e., the scan line 124) is greater than the first thickness T1 of the first portion 120A (i.e., the common alignment structure 122). In addition, since the third portion 120C (i.e., the floating structure 126) does not have the second conductive sublayer 120_2, the second thickness T2 of the second portion 120B (i.e., the scan line 124) and the first thickness T1 of the first portion 120A (i.e., the common alignment structure 122) are both greater than the third thickness T3 of the third portion 120C (i.e., the floating structure 126).

[0062] In some embodiments (such as Figure 7As shown, the first portion 120A of the conductive layer 120 (i.e., the co-aligned structure 122) can be formed into a first conductive stack SK1 after the electroplating step, the second portion 120B of the conductive layer 120 (i.e., the scan line 124) can be formed into a second conductive stack SK2 after the electroplating step, and the third portion 120C of the conductive layer 120 (i.e., the floating structure 126) can be selectively a third conductive stack SK3, and at least one of the first conductive stack SK1, the second conductive stack SK2, and the third conductive stack SK3 can have a multi-layer conductive structure. For example, in Figure 7 In the embodiment, the first conductive stack SK1 , the second conductive stack SK2 and the third conductive stack SK3 may all be multi-layer conductive structures, and these multi-layer conductive structures may all include different conductive materials (eg, molybdenum, aluminum and copper), but not limited thereto.

[0063] Compared to the manufacturing method of an electronic device including a conductive layer having only a single thickness, the manufacturing method of the electronic device 100 of the present embodiment does not need to increase the number of photomasks and the number of etching processes, so that the manufacturing cost of the electronic device 100 of the present embodiment can be well controlled and saved. In addition, the manufacturing method of the electronic device 100 of the present embodiment only needs to form the conductive layer 120 having different thicknesses through a single electroplating step, so the manufacturing cost of the electronic device 100 of the present embodiment can be well controlled and saved.

[0064] The electronic device and the method for manufacturing the electronic device of the present invention are not limited to the above-mentioned embodiments. Other embodiments will be disclosed below. However, in order to simplify the description and highlight the differences between each embodiment and the above-mentioned embodiments, the present invention uses the same reference numerals to mark the same elements and will not repeat the repeated parts.

[0065] Please refer to Figures 9 to 13 , Figures 9 to 13 FIG. 1 is a schematic diagram of a method for manufacturing an electronic device according to a second embodiment of the present invention at different stages, wherein Figures 9 to 13 Only the manufacturing method of the first portion 120A (ie, the common alignment structure 122) and the second portion 120B (ie, the scan line 124) of the electronic device 100 is shown. Figures 9 to 13 As shown, compared to Figures 5 to 8 In the first embodiment shown, the manufacturing method of the electronic device 100 of this embodiment forms the conductive layer 120 with different thicknesses by using photoresist layers PR of different thicknesses and performing multiple electroplating processes in the electroplating step. The manufacturing method of the electronic device 100 of this embodiment will be described in detail below.

[0066] like Fig. 9 As shown, a first conductive sublayer 120_1 in the conductive layer 120 is formed on the substrate 110. For example, Fig. 9In the embodiment, the first conductive sub-layer 120_1 may be a single-layer structure (not patterned) (eg, the first conductive sub-layer 120_1 may include indium tin oxide), but is not limited thereto.

[0067] like Fig. 9 As shown, a photoresist layer PR is formed on the first conductive sublayer 120_1, and then the photoresist layer PR is patterned by a yellow light process and a development process, wherein the patterned photoresist layer PR may have at least two thicknesses. In some embodiments, the photoresist layer PR may be defined into at least three parts by a gray tone mask, and these parts receive light of different light intensities in the yellow light process, so that the photoresist layer PR has different thicknesses. For example (such as Fig. 9 As shown), in the yellow light process, the photoresist layer PR (e.g., including negative photoresist material) can be defined into a first portion PR1, a second portion PR2 and a third portion (without photoresist layer PR) through a grayscale mask, wherein the light intensity irradiated to the first portion PR1 is greater than the light intensity irradiated to the second portion PR2, and the light intensity irradiated to the second portion PR2 is greater than the light intensity irradiated to the third portion (e.g., the third portion is not irradiated with light). Therefore, after the development process, the thickness of the first portion PR1 is greater than the thickness of the second portion PR2, and the third portion exposes the first conductive sub-layer 120_1 due to the removal of the photoresist layer PR, but not limited to this. It should be noted that if the photoresist layer PR uses a positive photoresist material, the exposure energy of the first portion PR1 is the smallest, and the exposure energy of the third portion is the largest, so that the photoresist layer PR located in the third portion is removed. Fig. 9 , the third portion of the photoresist layer PR corresponds to the second portion 120B (i.e., the scan line 124) of the first conductive sublayer 120_1 of the conductive layer 120 in the direction Z, and the second portion PR2 of the photoresist layer PR corresponds to the first portion 120A (i.e., the co-aligned structure 122) of the first conductive sublayer 120_1 of the conductive layer 120 in the direction Z.

[0068] like Fig.10 As shown, the first electroplating process in the electroplating step is performed to energize the first conductive sublayer 120_1. Since the second portion 120B of the first conductive sublayer 120_1 is not shielded by the photoresist layer PR, the second portion 120B of the first conductive sublayer 120_1 is electroplated to grow the electroplated metal on the second portion 120B, so that the second conductive sublayer 120_2 is formed on the second portion 120B of the first conductive sublayer 120_1. It should be noted that the second conductive sublayer 120_2 can be a metal layer containing any suitable metal (e.g., aluminum or copper).

[0069] like Fig.11 As shown, an etching step is performed to thin the photoresist layer PR. Fig.11In the embodiment, the first portion PR1 of the photoresist layer PR is thinned, and the second portion PR2 of the photoresist layer PR is removed to expose the first portion 120A of the first conductive sub-layer 120_1 of the conductive layer 120. For example, the etching step may include a dry etching process, but is not limited thereto.

[0070] like Fig.12 As shown, the second electroplating process in the electroplating step is performed to energize the first conductive sublayer 120_1. Since the first portion 120A and the second portion 120B of the first conductive sublayer 120_1 are not shielded by the photoresist layer PR, the first portion 120A and the second portion 120B of the first conductive sublayer 120_1 are electroplated to grow the electroplated metal on the first portion 120A and the second portion 120B, so that the third conductive sublayer 120_3 is formed on the first portion 120A and the second portion 120B. It should be noted that the third conductive sublayer 120_3 can be a metal layer including any suitable metal (e.g., aluminum or copper).

[0071] like Fig.13 As shown, the photoresist layer PR is removed by a photoresist removal step, wherein the photoresist removal step may include a wet etching process, but is not limited thereto.

[0072] like Fig.13 As shown, a patterning step is performed to pattern the first conductive sub-layer 120_1. For example, the patterning step may be another etching step to etch the first conductive sub-layer 120_1 that is not shielded by the second conductive sub-layer 120_2 and / or the third conductive sub-layer 120_3. For example, since the material of the first conductive sub-layer 120_1 is different from that of the second conductive sub-layer 120_2 and the third conductive sub-layer 120_3, the etching step may use a solvent that only etches the material of the first conductive sub-layer 120_1 to perform an etching process, but is not limited thereto.

[0073] According to the above, in the electroplating step, the first portion 120A (i.e., the co-aligned structure 122) receives a first number of electroplating processes to form a first conductive stack SK1, and the second portion 120B (i.e., the scan line 124) receives a second number of electroplating processes to form a second conductive stack SK2, and the first number is different from the second number. Figures 9 to 13 In the illustrated embodiment, the second number is greater than the first number, such that the second thickness T2 of the second portion 120B (ie, the scan line 124) is greater than the first thickness T1 of the first portion 120A (ie, the co-aligned structure 122). Fig.13In the figure, the first conductive stack SK1 of the first part 120A of the conductive layer 120 (i.e., the co-positioning structure 122) may include the first conductive sub-layer 120_1 and the third conductive sub-layer 120_3 to be a multi-layer conductive structure, and the second conductive stack SK2 of the second part 120B of the conductive layer 120 (i.e., the scanning line 124) may include the first conductive sub-layer 120_1, the second conductive sub-layer 120_2 and the third conductive sub-layer 120_3 to be a multi-layer conductive structure, and these multi-layer conductive structures may include different conductive materials (e.g., indium tin oxide, molybdenum, aluminum and copper), but are not limited to this.

[0074] Compared to the manufacturing method of the electronic device including a conductive layer with only a single thickness, the manufacturing method of the electronic device 100 of this embodiment does not need to increase the number of masks, so that the manufacturing cost of the electronic device 100 of this embodiment can be well controlled and saved.

[0075] Please refer to Figure 14 to Figure 15 , Figure 14 to Figure 15 FIG. 1 is a schematic diagram of a method for manufacturing an electronic device according to a third embodiment of the present invention at different stages, wherein Figure 14 to Figure 15 Only the manufacturing method of the first portion 120A (ie, the common alignment structure 122) and the second portion 120B (ie, the scan line 124) of the electronic device 100 is shown. Fig.14 and Fig.15 As shown, in the manufacturing method of the electronic device 100 of the present embodiment, the conductive layer 120 with different thicknesses is formed by inkjet printing.

[0076] like Fig.14 and Fig.15 As shown, a substrate 110 is provided first, and an inkjet printing step is performed. In the inkjet printing step, a nozzle NZ sprays the metal ink MK onto a corresponding position (such as Fig.14 Then, a curing process (eg, heating or irradiation) is performed to cure the metal ink MK to form a conductive layer 120 (eg, Fig.15 In the present invention, the metal ink MK may include any suitable metal material. For example, the metal ink MK may include copper, silver (Ag), gold (Au), other suitable metal materials or combinations thereof.

[0077] like Fig.14 and Fig.15As shown, in the inkjet printing step, the thickness of each position in the conductive layer 120 can be controlled by controlling the amount of metal sprayed per unit area of ​​the metal ink MK, so as to form a first portion 120A (i.e., the co-aligned structure 122), a second portion 120B (i.e., the scanning line 124), and a third portion 120C (i.e., the floating structure 126) with different thicknesses, wherein the less the amount of metal sprayed per unit area, the thinner the film thickness formed. In other words, the amount of metal received per unit area of ​​the metal ink MK in the area corresponding to the first portion 120A (i.e., the co-aligned structure 122) (i.e., the location of the first portion 120A), the amount of metal received per unit area of ​​the metal ink MK in the area corresponding to the second portion 120B (i.e., the scanning line 124) (i.e., the location of the second portion 120B), and the amount of metal received per unit area of ​​the metal ink MK in the area corresponding to the third portion 120C (i.e., the floating structure 126) (i.e., the location of the third portion 120C) are all different. For example, the nozzle NZ may spray metal ink MK with different spraying amounts and / or different concentrations to form the first portion 120A (i.e., the co-aligned structure 122 ), the second portion 120B (i.e., the scan line 124 ) and the third portion 120C (i.e., the floating structure 126 ) of the conductive layer 120 .

[0078] Compared to the manufacturing method of an electronic device including a conductive layer having only a single thickness, the manufacturing method of the electronic device 100 of the present embodiment does not need to increase the number of masks and the number of film layer formation processes (e.g., deposition processes), so that the manufacturing cost of the electronic device 100 of the present embodiment can be well controlled and saved.

[0079] Please refer to Figures 16 to 18 , Figures 16 to 18 FIG. 1 is a schematic diagram of a method for manufacturing an electronic device according to a fourth embodiment of the present invention at different stages, wherein Figures 16 to 18 Only the manufacturing method of the first portion 120A (ie, the common alignment structure 122) and the second portion 120B (ie, the scan line 124) of the electronic device 100 is shown. Figures 16 to 18 As shown, compared to Figure 14 to Figure 15 In the third embodiment shown, the inkjet printing step of the manufacturing method of the electronic device 100 of this embodiment is an electrohydrodynamic printing step. Fig.16 and Fig.17 As shown, a first conductive sublayer 120_1 in the conductive layer 120 is formed on the substrate 110. For example, Fig.16 and Fig.17 In the embodiment, the first conductive sub-layer 120_1 may be a single-layer structure (eg, the first conductive sub-layer 120_1 may include indium tin oxide), but is not limited thereto.

[0080] like Fig.16 and Fig.17 As shown, an inkjet printing (i.e., electrohydrodynamic printing) step is performed, the first conductive sublayer 120_1 and the metal ink MK are energized (e.g., voltage is applied), and the nozzle NZ sprays the metal ink MK on the corresponding position on the first conductive sublayer 120_1 according to the pattern required for the conductive layer 120, and then a curing process (e.g., heating or irradiation) is performed to cure the metal ink MK to form the second conductive sublayer 120_2. Fig.16 and Fig.17 In the inkjet printing step, the thickness of each position in the second conductive sublayer 120_2 can be controlled by controlling the amount of metal sprayed by the metal ink MK per unit area, so that the first part 120A (i.e., the co-positioning structure 122), the second part 120B (i.e., the scanning line 124) and the third part 120C (i.e., the floating structure 126) have different thicknesses, wherein the less the amount of metal sprayed per unit area, the thinner the thickness of the formed film layer.

[0081] like Fig.18 As shown, a patterning step is performed to pattern the first conductive sublayer 120_1. For example, the patterning step may be an etching step to etch the first conductive sublayer 120_1 that is not shielded by the second conductive sublayer 120_2. For example, since the material of the first conductive sublayer 120_1 is different from that of the second conductive sublayer 120_2, the etching step may use a solvent that only etches the material of the first conductive sublayer 120_1 to perform an etching process, but the invention is not limited thereto. Fig.18 In the first part 120A of the conductive layer 120 (i.e., the co-positioning structure 122) and the second part 120B of the conductive layer 120 (i.e., the scanning line 124), the first conductive stack SK1 of the first part 120A (i.e., the co-positioning structure 122) may include a first conductive sublayer 120_1 and a thinner second conductive sublayer 120_2, and the second conductive stack SK2 of the second part 120B (i.e., the scanning line 124) may include a first conductive sublayer 120_1 and a thicker second conductive sublayer 120_2.

[0082] Since the formation of the conductive layer 120 includes an electrohydrodynamic printing step, the formed structure (eg, conductive trace) may have a smaller width and higher precision.

[0083] Please refer to Figures 19 to 23 , Figures 19 to 23 Schematic diagram of the structure of the manufacturing method of the electronic device in different stages according to the fifth embodiment of the present invention, wherein Figures 19 to 23 Only the manufacturing method of the first portion 120A (ie, the common alignment structure 122) and the second portion 120B (ie, the scan line 124) of the electronic device 100 is shown. Figures 19 to 23 As shown, compared to Figure 14 to Figure 15 In the third embodiment shown, before the inkjet printing step is performed, a photoresist layer PR having a plurality of gaps may be formed on the substrate 110. In the inkjet printing step, the nozzle NZ sprays the metal ink MK into the gaps GP of the photoresist layer PR, so that the first portion 120A (i.e., the co-aligned structure 122), the second portion 120B (i.e., the scan line 124), and the third portion 120C (i.e., the floating structure 126) having different thicknesses in the conductive layer 120 may be respectively formed in different gaps GP of the photoresist layer PR.

[0084] In detail, Fig.19 In the embodiment, the photoresist layer PR is patterned according to the pattern required by the conductive layer 120, so that the gap GP corresponds to the area where the conductive layer 120 is to be formed. Figure 20 to Figure 22 As shown, in the inkjet printing step, the nozzle NZ can control the amount of metal (such as the amount of metal ink MK sprayed per unit area) according to the required thickness of each position of the conductive layer 120. Fig. 20 Then, a curing process (eg, heating or irradiation) is performed to cure the metal ink MK to form a conductive layer 120 (eg, Fig.21 and Fig. 22 As shown in Fig.23 As shown in FIG. 1 , the photoresist layer PR is removed by a photoresist removal step. Due to the patterned photoresist layer PR, the pattern of the conductive layer 120 formed by the nozzle NZ in this embodiment can be relatively smooth. Fig.14 The pattern of the conductive layer 120 in the third embodiment shown is more precise.

[0085] In some embodiments, Fig. 22 As shown, after the photoresist layer PR is patterned to form the gap GP, in the cross section, the size of the upper surface of the photoresist layer PR is larger than the size of the lower surface (i.e., the cross-sectional profile of the photoresist layer PR is a trapezoid with a larger upper base than the lower base), so that the formed conductive layer 120 has a suitable cross-sectional profile (i.e., the size of the upper surface of the conductive layer 120 is smaller than the size of the lower surface, so that its cross-sectional profile is a trapezoid with a smaller upper base than the lower base), so as to improve the success rate of subsequent processes (e.g., formation of subsequent film layers), thereby improving the yield of the electronic device 100. In addition, due to the design of the cross-sectional profile of the photoresist layer PR, the photoresist layer PR is easily removed, so as to improve the yield of the electronic device 100.

[0086] Please refer to Figure 24 to Figure 25 , Figure 24 to Figure 25 Schematic diagram of the structure of the manufacturing method of the electronic device in different stages according to the sixth embodiment of the present invention, wherein Figure 24 to Figure 25 Only the manufacturing method of the first portion 120A (ie, the common alignment structure 122) and the second portion 120B (ie, the scan line 124) of the electronic device 100 is shown. Figure 24 to Figure 25 As shown, compared to Figures 19 to 23 In the fifth embodiment shown, the inkjet printing step of the manufacturing method of the electronic device 100 of this embodiment is an electrohydrodynamic printing step. Figure 24 to Figure 25 As shown in FIG. 1 , before forming the photoresist layer PR, a first conductive sublayer 120_1 in the conductive layer 120 is formed on the substrate 110. For example, Figure 24 to Figure 25 In the embodiment, the first conductive sub-layer 120_1 may be a single-layer structure (eg, the first conductive sub-layer 120_1 may include indium tin oxide), but is not limited thereto.

[0087] like Figure 24 to Figure 25 As shown, an inkjet printing (i.e., electrohydrodynamic printing) step is performed, the first conductive sublayer 120_1 and the metal ink MK are energized (e.g., voltage is applied), and the metal ink MK is sprayed into the gap GP of the photoresist layer PR through the nozzle NZ, so that the first portion 120A (i.e., the co-aligned structure 122), the second portion 120B (i.e., the scanning line 124), and the third portion 120C (i.e., the floating structure 126) with different thicknesses in the conductive layer 120 can be respectively formed in different gaps GP of the photoresist layer PR. Next, a curing process (e.g., heating or irradiation) is performed to cure the metal ink MK to form the second conductive sublayer 120_2. Figure 24 to Figure 25 In the inkjet printing step, the thickness of each position in the second conductive sublayer 120_2 can be controlled by controlling the amount of metal sprayed by the metal ink MK per unit area, so that the first part 120A (i.e., the co-positioning structure 122), the second part 120B (i.e., the scanning line 124) and the third part 120C (i.e., the floating structure 126) have different thicknesses, wherein the less the amount of metal sprayed per unit area, the thinner the thickness of the formed film layer.

[0088] Thereafter, the photoresist layer PR is removed by a photoresist removal step (eg, Fig.17 Then, a patterning step is performed to pattern the first conductive sublayer 120_1 (for example, as shown in FIG. Fig.18 For example, the patterning step may be an etching step to etch the first conductive sublayer 120_1 that is not shielded by the second conductive sublayer 120_2. Fig.18In the first portion 120A (i.e., the co-aligned structure 122) of the conductive layer 120 and the second portion 120B (i.e., the scan line 124) of the conductive layer 120, the first conductive stack SK1 of the first portion 120A (i.e., the co-aligned structure 122) may include a first conductive sublayer 120_1 and a thinner second conductive sublayer 120_2, and the second conductive stack SK2 of the second portion 120B (i.e., the scan line 124) may include a first conductive sublayer 120_1 and a thicker second conductive sublayer 120_2. Due to the patterned photoresist layer PR, the pattern of the conductive layer 120 formed by the nozzle NZ in this embodiment can be relatively thin. Fig.16 The pattern of the conductive layer 120 in the fourth embodiment is shown to be more precise.

[0089] In summary, since different structures in the conductive layer of the electronic device of the present invention have different thicknesses, the display screen of the electronic device and the yield of the electronic device can be improved. In addition, according to the manufacturing method of the electronic device of the present invention, an electronic device including conductive layers with different thicknesses can be manufactured while the manufacturing cost is well controlled and saved.

[0090] Although the embodiments of the present invention and their advantages have been disclosed as above, it should be understood that any person skilled in the art with ordinary knowledge should be able to make changes, substitutions and modifications without departing from the spirit and scope of the present invention. In addition, the scope of protection of the present invention is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art with ordinary knowledge can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure of the present invention, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to the present invention. Therefore, the scope of protection of the present invention includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of the present invention also includes the combination of each claim and embodiment. The scope of protection of the present invention shall be determined by the attached claims.

[0091] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for manufacturing an electronic device, characterized in that: include: providing a substrate; Disposing a conductive layer on the substrate; Performing a patterning step to pattern the conductive layer so that the conductive layer forms a grid structure having a plurality of grid units, and the patterned conductive layer at least includes a first portion and a second portion; as well as An electroplating step is performed to electroplate at least one of the first portion and the second portion, and the first portion and the second portion have different thicknesses after the electroplating step.

2. The manufacturing method according to claim 1, characterized in that The patterning step is an etching step.

3. The manufacturing method according to claim 1, characterized in that: In the electroplating step, the first portion is coupled to a first current, the second portion is coupled to a second current, and the first current and the second current have different current densities.

4. The manufacturing method according to claim 1, characterized in that: In the electroplating step, the first portion undergoes a first number of electroplating processes to form a first conductive stack, and the second portion undergoes a second number of electroplating processes to form a second conductive stack, and the first number of times is different from the second number of times.

5. The manufacturing method according to claim 4, characterized in that: At least one of the first conductive stack and the second conductive stack has a multi-layer conductive structure, and the multi-layer conductive structure includes different conductive materials.

6. The manufacturing method according to claim 1, characterized in that: The electronic device includes a plurality of display units, one of the plurality of display units corresponds to one of the plurality of grid units, the first portion of the conductive layer includes at least one edge of one of the plurality of grid units, and the second portion of the conductive layer corresponds to at least two of the plurality of grid units.

7. The manufacturing method according to claim 1, characterized in that: The conductive layer is a metal layer.

8. A method for manufacturing an electronic device, characterized in that: include: providing a substrate; as well as performing an inkjet printing step to form a conductive layer on the substrate; The conductive layer includes a grid structure having a plurality of grid units. The conductive layer includes at least a first portion and a second portion. The first portion and the second portion have different thicknesses.

9. The manufacturing method according to claim 8, characterized in that: In the inkjet printing step, the amount of metal received per unit area of ​​the metal ink by the region corresponding to the first portion is different from the amount of metal received per unit area of ​​the metal ink by the region corresponding to the second portion.

10. The manufacturing method according to claim 8, characterized in that: Also includes: Before performing the inkjet printing step, forming a photoresist layer on the substrate, wherein the photoresist layer has a plurality of gaps; The first portion and the second portion of the conductive layer formed by the inkjet printing step are formed in the plurality of gaps in the photoresist layer.

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