Magnetic random access memory and preparation method thereof

Abstract

The invention provides a magnetic random access memory and a preparation method thereof. The preparation method comprises the following steps: providing a substrate; sequentially depositing a track layer, a magnetic tunnel junction preparation layer and a hard mask layer on the substrate; patterning the hard mask layer, and etching the magnetic tunnel junction preparation layer according to the hard mask layer to obtain a magnetic tunnel junction; depositing a dielectric layer covering the magnetic tunnel junction on the track layer; removing the dielectric layer on the surface of the track layer to enable the residual dielectric layer to coat the magnetic tunnel junction; a low-resistivity material is deposited, a filling layer is formed, and the resistivity of the low-resistivity material is smaller than that of the material of the track layer; the part, wrapping the magnetic tunnel junction, in the filling layer is removed, a composite track layer is formed, and the composite track layer comprises a track layer and the filling layer; and the composite track layer is etched, so that the etched composite track layer is separated at the two sides of the residual dielectric layer. According to the invention, the shunting problem caused by introduction of low-resistivity metal can be solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a magnetic random access memory and a preparation method thereof. Background Art

[0002] The optimization of the preparation process of SOT-MRAM (spin-orbit torque magnetic random access memory) is one of the main difficulties in the current industrialization. An obvious structural feature of SOT-MRAM is that it has a track layer with a thickness of only a few nanometers, while when etching the MTJ (magnetic tunnel junction), it is necessary to etch multiple layers of metal about 30nm thick. In this way, in the process of etching the MTJ, it is easy to damage the structure of the track layer, thereby affecting the efficiency of the SOT. Therefore, how to effectively reduce the resistance of the track layer and improve the uniformity of the track layer resistance while ensuring that the SOT efficiency is not reduced is an urgent problem to be solved in the current SOT-MRAM preparation process.

[0003] To solve the above problems, the prior art is to connect a low-resistivity metal material in parallel or in series with the track layer to reduce the resistance of the track layer. However, the prior art does not consider the problem of track layer resistance uniformity, resulting in that although the overall resistance of the track layer is reduced, the shunting problem caused by the low-resistivity metal is also introduced. Summary of the invention

[0004] To solve the above problems, the magnetic random access memory and its preparation method provided by the present invention form a composite track layer, thereby reducing the effective resistance and CV (coefficient of variation) distribution of the track layer and solving the shunt problem caused by the introduction of low resistivity metal.

[0005] In a first aspect, the present invention provides a method for preparing a magnetic random access memory, comprising:

[0006] providing a substrate;

[0007] Depositing a track layer, a magnetic tunnel junction preparation layer and a hard mask layer in sequence on the substrate;

[0008] Patterning the hard mask layer, and etching the magnetic tunnel junction preparation layer according to the hard mask layer to obtain a magnetic tunnel junction;

[0009] depositing a dielectric layer covering the magnetic tunnel junction on the track layer;

[0010] removing the dielectric layer on the surface of the track layer so that the remaining dielectric layer covers the sidewall of the magnetic tunnel junction;

[0011] Depositing a low-resistivity material to form a filling layer, wherein the resistivity of the low-resistivity material is less than the resistivity of the material of the track layer;

[0012] Removing a portion of the filling layer covering the magnetic tunnel junction to form a composite track layer, the composite track layer comprising a track layer and a filling layer;

[0013] The composite track layer is etched so that the etched composite track layer is separated on both sides of the remaining dielectric layer.

[0014] Optionally, the step of removing a portion of the filling layer covering the magnetic tunnel junction to form a composite track layer includes:

[0015] Etching the filling layer on the side wall of the magnetic tunnel junction to separate the filling layer on the surface of the track layer from the filling layer on the magnetic tunnel junction;

[0016] An insulating layer covering the magnetic tunnel junction is formed on the filling layer, and the insulating layer is planarized to remove the filling layer on the magnetic tunnel junction and expose the hard mask layer. The remaining filling layer and the track layer form a composite track layer.

[0017] Optionally, the step of etching the composite track layer so that the etched composite track layer is separated on both sides of the remaining dielectric layer includes:

[0018] Depositing a top electrode material on the insulating layer to form a top electrode layer;

[0019] Patterning the top electrode layer to form a top electrode, with the remaining dielectric layer exposed on opposite sides of the top electrode, the top electrode completely covering the magnetic tunnel junction, and both ends of the top electrode away from the magnetic tunnel junction being located on the inner side of the composite track layer;

[0020] The composite track layer is cut according to the pattern of the top electrode.

[0021] Optionally, before the step of depositing a low resistivity material to form a filling layer, the method further comprises:

[0022] The track layer on the outer peripheral side of the remaining dielectric layer is removed.

[0023] Optionally, the substrate is provided with a bottom electrode, the bottom electrode penetrates the substrate, and the composite track layer is connected to the bottom electrode.

[0024] Optionally, the filling layer is connected to the bottom electrode.

[0025] Optionally, the steps of patterning the hard mask layer and etching the magnetic tunnel junction preparation layer according to the hard mask layer to obtain the magnetic tunnel junction include:

[0026] patterning the hard mask layer to obtain a plurality of hard masks;

[0027] Etching the magnetic tunnel junction preparation layer according to the multiple hard masks to obtain multiple magnetic tunnel junctions;

[0028] The step of etching the composite track layer so that the etched composite track layer is separated on both sides of the remaining dielectric layer comprises:

[0029] Depositing a top electrode material on the insulating layer to form a top electrode layer, wherein the top electrode layer is connected to a plurality of hard masks;

[0030] Patterning the top electrode layer so that both ends of the patterned top electrode layer are located inside the composite track layer;

[0031] cutting the composite track layer according to the pattern of the top electrode layer;

[0032] The top electrode layer is patterned again to form a plurality of top electrodes, and the remaining dielectric layer is exposed on opposite sides of the top electrodes, and the top electrodes completely cover the magnetic tunnel junctions.

[0033] Optionally, the material of the track layer includes at least one of W, Ta, Pt and BiSe;

[0034] The low resistivity material includes at least one of Al, W and Cu;

[0035] The thickness of the filling layer or / and the filling layer is in the range of 5nm-20nm.

[0036] Optionally, the cross-sectional shape of the magnetic tunnel junction is circular or elliptical.

[0037] In a second aspect, the present invention provides a magnetic random access memory, which is prepared by the method as described in any one of the above items.

[0038] The magnetic random access memory and preparation method provided in the embodiments of the present invention form a composite track layer by depositing low-resistivity material and connecting it in parallel with part of the high-resistance material of the track layer. While reducing the effective resistance and CV distribution of the track layer, it solves the shunt problem caused by the introduction of low-resistivity metal, and improves the writing efficiency of the track layer and the uniformity of the resistance of the track layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figures 1 to 16 It is a cross-sectional view of the embodiment in the first aspect of the present application at various stages of preparing a magnetic random access memory, wherein: Figure 6 , Figure 8 , Fig.10 , Fig.12 and Fig.15 All are cross-sections of the magnetic tunnel junction in the horizontal direction, and the rest are vertical cross-sections;

[0041] Fig.17 A cross-sectional view of a magnetic random access memory according to an embodiment of the second aspect of the present application;

[0042] Figures 18 to 20 It is a cross-sectional view of various stages of preparing a magnetic random access memory according to an embodiment of the third aspect of the present application, wherein: Fig.19 To perform a cross section of the magnetic tunnel junction in the horizontal direction after executing step S108, Fig.18 and Fig. 20 All are vertical cross-section views.

[0043] Reference numerals:

[0044] 1. Substrate; 11. Bottom electrode; 2. Composite track layer; 21. Track layer; 22. Filling layer; 3. Magnetic tunnel junction preparation layer; 31. Magnetic tunnel junction; 4. Hard mask layer; 41. Hard mask; 5. Dielectric layer; 6. Insulating layer; 7. Top electrode layer; 71. Top electrode; 8. Protective layer. DETAILED DESCRIPTION

[0045] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0047] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0048] It should be noted that when an element is referred to as being "fixedly connected" to another element, it may be directly on the other element or there may also be a central element. When an element is considered to be "connected" to another element, it may be directly connected to the other element or there may be a central element at the same time. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0049] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0050] In a first aspect, an embodiment of the present invention provides a method for preparing a magnetic random access memory, the method comprising steps S101 to S108:

[0051] Step S101: Combination Figure 1 , providing a substrate 1.

[0052] The substrate 1 is provided with a bottom electrode 11, which penetrates the substrate 1; the material of the bottom electrode 11 is a conductive material, including but not limited to at least one of Cu, W and Ta; the material of the substrate 1 includes but is not limited to silicon oxide or silicon nitride.

[0053] In an optional embodiment, the bottom electrode 11 includes: a first connection portion and a second connection portion. The first connection portion is located below the second connection portion and connected to the second connection portion. The bottom end of the first connection portion is exposed on the lower surface of the substrate 1, and the second connection portion is exposed on the upper surface of the substrate 1. The first connection portion and the second connection portion are different conductive materials.

[0054] Step S102: Combination Figure 2 , a track layer 21 , a magnetic tunnel junction preparation layer 3 and a hard mask layer 4 are sequentially deposited on a substrate 1 .

[0055] Specifically, a track layer 21, a magnetic tunnel junction preparation layer 3 and a hard mask layer 4 are sequentially grown and deposited on the substrate 1 from bottom to top using a physical or chemical vapor deposition method. The magnetic tunnel junction preparation layer 3 is used to prepare a magnetic tunnel junction 31, including but not limited to a free layer, a barrier layer and a reference layer. Among them, the barrier layer material can be MgO or AlOx, etc.; the material of the track layer 21 includes but is not limited to at least one of W, Ta, Pt and BiSe.

[0056] Step S103: Combination Figure 3 , patterning the hard mask layer 4, and etching the magnetic tunnel junction preparation layer 3 according to the hard mask layer 4 to obtain a magnetic tunnel junction 31 (MTJ).

[0057] The hard mask layer 4 can be patterned and the magnetic tunnel junction preparation layer 3 can be etched by ion beam or reactive ion etching. The cross-sectional shape of the magnetic tunnel junction 31 is circular or elliptical, so that the magnetic tunnel junction 31 can be prevented from forming a pinning center around it, which is not conducive to the reversal of the magnetic moment of the free layer. In this embodiment, the number of magnetic tunnel junctions 31 is one and its cross-sectional shape is circular.

[0058] It should be noted that, combined with Figure 4 When etching the magnetic tunnel junction preparation layer 3, over-etching may usually be introduced, and uneven etching of the track layer 21 may occur within the chip, which is not specifically limited in this embodiment.

[0059] Step S104: Combination Figure 5 and Figure 6 , a dielectric layer 5 covering the magnetic tunnel junction 31 is deposited on the track layer 21 .

[0060] The dielectric layer 5 can be deposited by physical or chemical vapor deposition; the material of the dielectric layer 5 is an insulating material, such as silicon oxide or silicon nitride; and the dielectric layer 5 can be a single-layer structure or a multi-layer structure. In this embodiment, the dielectric layer 5 is a double-layer structure, including a first dielectric sublayer and a second dielectric sublayer. The materials of the first dielectric sublayer and the second dielectric sublayer are different from each other.

[0061] The formation process of the first dielectric sublayer and the second dielectric sublayer includes: firstly depositing the first dielectric sublayer on the track layer 21, and then depositing the second dielectric sublayer covering the first dielectric sublayer.

[0062] Step S105: Combination Figure 7 and Figure 8 , the dielectric layer 5 on the surface of the track layer 21 is removed so that the remaining dielectric layer 5 covers the side wall of the magnetic tunnel junction 31 .

[0063] in, Figure 7 The over-etching phenomenon is reflected in the figure; the dielectric layer 5 can be removed by ion beam or reactive ion etching.

[0064] It should be noted that the portion of the dielectric layer 5 that is connected to the track layer 21 and covers the side wall of the magnetic tunnel junction 31 belongs to the remaining dielectric layer 5; the portion of the dielectric layer 5 above the hard mask can be removed in step S105, or can be removed together with the portion of the filling layer 22 above it through a planarization process in step S107. In this embodiment, the portion of the dielectric layer 5 above the hard mask is removed in step S105.

[0065] In addition, an over-engraving phenomenon may also be introduced in step S105, which is not specifically limited in this embodiment.

[0066] Step S106: Combination Fig. 9 and Fig.10 , deposit low resistivity material to form a filling layer 22.

[0067] Among them, the low-resistivity material can be deposited using physical or chemical vapor deposition; the resistivity of the low-resistivity material is less than the resistivity of the material of the track layer 21; the low-resistivity material includes but is not limited to at least one of Al, W and Cu, and the thickness range of the filling layer 22 is 2nm-30nm, such as 8nm, 10nm, 15nm and 18nm, but is not limited to this.

[0068] Step S107: Combination Fig.11 , Fig.12 and Fig.13 , remove the portion of the filling layer 22 that covers the magnetic tunnel junction 31 to form a composite track layer 2.

[0069] The composite track layer 2 includes a track layer 21 and a remaining filling layer 22; the composite track layer 2 is connected to the bottom electrode 11. The portion of the filling layer 22 that is connected to the track layer 21 and covers the side wall of the magnetic tunnel junction 31 belongs to the remaining filling layer 22.

[0070] In an optional embodiment, the step of removing the portion of the filling layer 22 covering the magnetic tunnel junction 31 to form a composite track layer 2 includes: etching the filling layer 22 on the side wall of the magnetic tunnel junction 31 using an ion beam etching method to separate the filling layer 22 on the surface of the track layer 21 from the filling layer 22 on the magnetic tunnel junction 31; forming an insulating layer 6 covering the magnetic tunnel junction 31 on the filling layer 22, and flattening the insulating layer 6 to remove the filling layer 22 on the magnetic tunnel junction 31 and expose the hard mask layer 4, and the remaining filling layer 22 and the track layer 21 form a composite track layer 2.

[0071] It should be noted that the dielectric layer 5 on the hard mask 41 may also be removed during the planarization process of the insulating layer 6 .

[0072] Step S108: Combination Fig.14 and Fig.15 , the composite track layer 2 is etched so that the strip-shaped composite track layer 2 after etching is separated on both sides of the remaining dielectric layer 5.

[0073] It can be understood that the width of the composite track layer 2 after etching is smaller than the critical dimension (CD) of the dielectric layer 5. In addition, the width of the composite track layer 2 after etching is larger than the critical dimension (CD) of the magnetic tunnel junction 31.

[0074] In this embodiment, the width of the etched composite track layer 2 is smaller than the outer wall size of the dielectric layer 5 in the same horizontal plane and in the same direction, and the width of the etched composite track layer 2 is larger than the outer wall size of the magnetic tunnel junction 31 in the same horizontal plane and in the same direction. By limiting the width of the composite track layer 2, the low-resistivity metal material on the opposite sides of the magnetic tunnel junction 31 is ensured to be separated, the shunting problem caused by the introduction of the low-resistivity metal is solved, and the writing efficiency of the track layer 21 and the uniformity of the resistance of the track layer 21 are improved.

[0075] In an optional embodiment, the step of etching the composite track layer 2 so that the etched composite track layer 2 is separated on both sides of the remaining dielectric layer 5 includes: depositing a top electrode material on the insulating layer 6 to form a top electrode layer 7; patterning the top electrode layer 7 to form a top electrode 71; and cutting the composite track layer 2 according to the pattern of the top electrode 71 to expose the substrate 1.

[0076] The geometric center of the top electrode 71 coincides with the geometric center of the magnetic tunnel junction 31 in the vertical direction; the remaining dielectric layer 5 is exposed on opposite sides of the top electrode 71; both ends of the top electrode 71 away from the magnetic tunnel junction 31 are located on the inner side of the composite track layer 2; the top electrode 71 completely covers the magnetic tunnel junction 31. In other words, the width of the composite track layer 2 and the corresponding top electrode 71 after etching are greater than the critical size of the magnetic tunnel junction 31, that is, the width of the composite track layer 2 after etching is greater than the outer wall size of the magnetic tunnel junction 31 in the same horizontal plane and in the same direction. By limiting the width of the composite track layer 2, damage to the magnetic tunnel junction 31 can be avoided when etching the composite track layer 2.

[0077] The composite track layer 2 is patterned by the top electrode 71, so that the shape of the composite track layer 2 after etching is consistent with the shape of the top electrode 71, which reduces the difficulty of etching the composite track layer 2, thereby reducing the production cost of the magnetic random access memory. By isolating the composite track layer 2, the memory devices composed of the magnetic tunnel junction 31 and the composite track layer 2 can be isolated from each other.

[0078] Combination Fig.16After the step of cutting the composite track layer 2 according to the pattern of the top electrode 71 to expose the substrate 1, the method further includes: depositing an insulating material to form a protective layer 8 covering the top electrode 71; and flattening the protective layer 8 to expose the top electrode 71. The top electrode 71 is subsequently interconnected using a dual damascene process.

[0079] In a second aspect, an embodiment of the present invention provides a magnetic random access memory, which is different from the method in the first aspect in that: Fig.17 Before the step of depositing the low resistivity material to form the filling layer 22 , the method further includes: removing the track layer 21 on the outer peripheral side of the remaining dielectric layer 5 .

[0080] By removing the peripheral track layer 21 of the dielectric layer 5 coated on the side wall of the magnetic tunnel junction 31, the remaining dielectric layer 5 and the track layer 21 directly below the magnetic tunnel junction 31 are retained, so that the filling layer 22 is deposited on the upper surface of the substrate 1. In this way, the influence of the over-etching phenomenon on the structure and performance of the composite track layer 2 is eliminated when etching the magnetic tunnel junction 31 and the dielectric layer 5. At the same time, based on this optional embodiment, after executing step S106, the filling layer 22 is connected to the bottom electrode 11.

[0081] In a third aspect, an embodiment of the present invention provides a method for preparing a magnetic random access memory, which is different from the method in the first aspect in that: Fig.18 , Fig.19 and Fig. 20 The steps of patterning the hard mask layer 4 and etching the magnetic tunnel junction preparation layer 3 according to the hard mask layer 4 to obtain the magnetic tunnel junction 31 include: patterning the hard mask layer 4 to obtain a plurality of hard masks 41; etching the magnetic tunnel junction preparation layer 3 according to the plurality of hard masks 41 to obtain a plurality of magnetic tunnel junctions 31. At the same time, the step of etching the composite track layer 2 so that the etched composite track layer 2 is separated on both sides of the remaining dielectric layer 5 includes: depositing a top electrode material on the insulating layer 6 to form a top electrode layer 7; the top electrode layer 7 is in the shape of a strip and is connected to the plurality of hard masks 41; patterning the top electrode layer 7 so that both ends of the patterned top electrode layer 7 are located on the inner side of the composite track layer 2; cutting the composite track layer 2 according to the pattern of the top electrode layer 7 to expose the substrate 1; and patterning the top electrode layer 7 again to form a plurality of top electrodes 71.

[0082] The remaining dielectric layer 5 is exposed on opposite sides of the top electrode 71 ; the top electrode 71 completely covers the magnetic tunnel junction 31 ; and the geometric center of the top electrode 71 coincides with the geometric center of the corresponding magnetic tunnel junction 31 in the vertical direction.

[0083] After the step of patterning the top electrode layer 7 again to form a plurality of top electrodes 71, the method further includes: depositing an insulating material to form a protective layer 8 covering the top electrodes 71; and planarizing the protective layer 8 to expose the top electrodes 71. Subsequently, the top electrodes 71 are interconnected using a dual damascene process.

[0084] It should be noted that, in this embodiment, the substrate 1, the second dielectric sub-layer, the insulating layer 6 and the protective layer 8 are made of the same material, which is silicon nitride, but the present invention is not limited thereto.

[0085] The preparation method of the magnetic random access memory provided by the present invention has a simple preparation process and low cost. By depositing a low-resistivity material on the periphery of the magnetic tunnel junction 31, the effective resistance of the track layer 21 is reduced, and the power consumption of the device is effectively reduced; at the same time, the CV distribution of the resistance of the track layer 21 within the chip is reduced; in addition, the preparation method reduces the shunting effect caused by the deposition of the low-resistance material by limiting the width of the composite track layer 2; the preparation method uses a self-alignment method to etch the dielectric layer 5 and the filling layer 22, effectively controlling the number of masks used, and further reducing the complexity of the preparation method.

[0086] In a fourth aspect, an embodiment of the present invention provides a magnetic random access memory, which is prepared by the method in any of the above aspects, see Fig.16 , Fig.17 and Fig. 20 .

[0087] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0088] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0089] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for preparing a magnetic random access memory, characterized in that: include: Providing a substrate (1); A track layer (21), a magnetic tunnel junction preparation layer (3) and a hard mask layer (4) are sequentially deposited on the substrate (1); Patterning the hard mask layer (4), and etching the magnetic tunnel junction preparation layer (3) based on the hard mask layer (4) to obtain a magnetic tunnel junction (31); Depositing a dielectric layer (5) covering the magnetic tunnel junction (31) on the track layer (21); Removing the dielectric layer (5) on the surface of the track layer (21) so that the remaining dielectric layer (5) covers the side wall of the magnetic tunnel junction (31); Depositing a low-resistivity material to form a filling layer (22), wherein the resistivity of the low-resistivity material is lower than the resistivity of the material of the track layer (21); Removing the portion of the filling layer (22) that covers the magnetic tunnel junction (31) to form a composite track layer (2), wherein the composite track layer (2) comprises the track layer (21) and the filling layer (22); The composite track layer (2) is etched so that the composite track layer (2) after etching is separated on both sides of the remaining dielectric layer (5).

2. The method according to claim 1, characterized in that The step of removing the portion of the filling layer (22) covering the magnetic tunnel junction (31) to form a composite track layer (2) comprises: Etching the filling layer (22) on the side wall of the magnetic tunnel junction (31) so as to separate the filling layer (22) on the surface of the track layer (21) from the filling layer (22) on the magnetic tunnel junction (31); An insulating layer (6) covering the magnetic tunnel junction (31) is formed on the filling layer (22), and the insulating layer (6) is planarized to remove the filling layer (22) on the magnetic tunnel junction (31) and expose the hard mask layer (4), and the remaining filling layer (22) and the track layer (21) form the composite track layer (2).

3. The method according to claim 2, characterized in that The step of etching the composite track layer (2) so that the composite track layer (2) after etching is separated on both sides of the remaining dielectric layer (5) comprises: Depositing a top electrode material on the insulating layer (6) to form a top electrode layer (7); The top electrode layer (7) is patterned to form a top electrode (71), the remaining dielectric layer (5) is exposed on two opposite sides of the top electrode (71), the top electrode (71) completely covers the magnetic tunnel junction (31), and both ends of the top electrode (71) away from the magnetic tunnel junction (31) are located on the inner side of the composite track layer (2); The composite track layer (2) is cut according to the pattern of the top electrode (71).

4. The method according to claim 1, characterized in that: Before the step of depositing the low resistivity material to form the filling layer (22), the method further comprises: The track layer (21) on the outer peripheral side of the remaining dielectric layer (5) is removed.

5. The method according to claim 4, characterized in that The substrate (1) is provided with a bottom electrode (11), the bottom electrode (11) penetrates the substrate (1), and the composite track layer (2) is connected to the bottom electrode (11).

6. The method according to claim 5, characterized in that The filling layer (22) is connected to the bottom electrode (11).

7. The method according to claim 2, characterized in that The steps of patterning the hard mask layer (4) and etching the magnetic tunnel junction preparation layer (3) according to the hard mask layer (4) to obtain a magnetic tunnel junction (31) include: Patterning the hard mask layer (4) to obtain a plurality of hard masks (41); Etching the magnetic tunnel junction preparation layer (3) according to the multiple hard masks (41) to obtain multiple magnetic tunnel junctions (31); The step of etching the composite track layer (2) so that the composite track layer (2) after etching is separated on both sides of the remaining dielectric layer (5) comprises: Depositing a top electrode material on the insulating layer (6) to form a top electrode layer (7), wherein the top electrode layer (7) is connected to the plurality of hard masks (41); Patterning the top electrode layer (7) so that both ends of the patterned top electrode layer (7) are located inside the composite track layer (2); cutting the composite track layer (2) according to the pattern of the top electrode layer (7); The top electrode layer (7) is patterned again to form a plurality of top electrodes (71), with the remaining dielectric layer (5) exposed on opposite sides of the top electrode (71), and the top electrode (71) completely covering the magnetic tunnel junction (31).

8. The method according to any one of claims 1 to 7, characterized in that The material of the track layer (21) includes at least one of W, Ta, Pt and BiSe; The low resistivity material includes at least one of Al, W and Cu; Or / and the thickness of the filling layer (22) is in the range of 5nm-20nm.

9. The method according to any one of claims 1 to 7, characterized in that The cross-sectional shape of the magnetic tunnel junction (31) is circular or elliptical.

10. A magnetic random access memory, characterized in that: The magnetic random access memory is prepared by the method as described in any one of claims 1 to 9.

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