Package including integrated device and first metallization coupled to second metallization

Abstract

A package includes: a first integrated device; a first metallization portion coupled to the first integrated device; a second integrated device; a second metallization portion coupled to the second integrated device and the first metallization portion; and an encapsulation layer coupled to the first metallization portion, the second integrated device, and the second metallization portion. The first metallization portion includes at least one first dielectric layer and a first plurality of metallization interconnects. The second metallization portion includes at least one second dielectric layer and a second plurality of metallization interconnects.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional application S / N. 17 / 879,594 filed in the U.S. Patent Office on August 2, 2022, the entire contents of which are incorporated herein by reference as if fully set forth in its entirety below and for all applicable purposes.

[0003] field

[0004] Various features are directed to packages having metallizations and integrated devices.

[0005] background

[0006] A package may include a substrate and an integrated device. These components are coupled together to provide a package that can perform various electrical functions. There is a need to provide a package with better performance and to reduce the overall size of the package.

[0007] Overview

[0008] Various features are directed to packages having metallizations and integrated devices.

[0009] An example provides a package, including: a first integrated device; a first metallization portion, the first metallization portion is coupled to the first integrated device; a second integrated device; a second metallization portion, the second metallization portion is coupled to the second integrated device and the first metallization portion; and an encapsulation layer, the encapsulation layer is coupled to the first metallization portion, the second integrated device, and the second metallization portion. The first metallization portion includes at least one first dielectric layer and a first plurality of metallization interconnects. The second metallization portion includes at least one second dielectric layer and a second plurality of metallization interconnects.

[0010] Another example provides a device including: a first package, a second integrated device, a second metallization portion, and an encapsulation layer, the encapsulation layer coupled to the first package, the second integrated device, and the second metallization portion. The first package includes a first integrated device and a first metallization portion, the first metallization portion is coupled to the first integrated device. The second metallization portion is coupled to the second integrated device and the first metallization portion of the first package. The first metallization portion includes at least one first dielectric layer and a first plurality of metallization interconnects. The second metallization portion includes at least one second dielectric layer and a second plurality of metallization interconnects.

[0011] Another example provides a method for manufacturing a package. The method provides a first package, the first package includes a first integrated device and a first metallization portion, the first metallization portion is coupled to the first integrated device. The first metallization portion includes at least one first dielectric layer and a first plurality of metallization interconnects. The method provides a second integrated device. The method forms an encapsulation layer over the first package and the second integrated device. The method forms a second metallization portion over the second integrated device, the first metallization portion of the first package, and the encapsulation layer.

[0012] The second metallization portion includes at least one second dielectric layer and a second plurality of metallization interconnects. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Various features, characteristics and advantages will become apparent when the detailed description set forth below is read in conjunction with the accompanying drawings in which like reference numerals designate corresponding features throughout.

[0015] Figure 1 An exemplary cross-sectional profile view of a package including a first metallization and a second metallization is illustrated.

[0016] Figure 2 An exemplary cross-sectional profile view of a package including a first metallization and a second metallization is illustrated.

[0017] Figure 3 An exemplary cross-sectional profile view of a package including a first metallization and a second metallization is illustrated.

[0018] Figures 4A-4F An exemplary process for manufacturing a package including a first metallization and a second metallization is illustrated.

[0019] Figures 5A-5F An exemplary process for manufacturing a package including a first metallization and a second metallization is illustrated.

[0020] Figure 6 An exemplary flow chart of a method for manufacturing a package including a first metallization and a second metallization is illustrated.

[0021] Figure 7A-7B An exemplary process for fabricating a metallized portion is illustrated.

[0022] Figure 8 An exemplary flow chart of a method for manufacturing a metallization is illustrated.

[0023] Fig. 9 Various electronic devices are illustrated into which the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein may be integrated.

[0024] Detailed Description

[0025] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those of ordinary skill in the art that these aspects can be practiced without these specific details. For example, circuits may be shown with block diagrams to avoid burying these aspects in unnecessary details. In other examples, well-known circuits, structures, and techniques may not be shown in detail to avoid burying these aspects of the present disclosure.

[0026] The present disclosure describes a package, which includes: a first integrated device; a first metallization portion, the first metallization portion is coupled to the first integrated device; a second integrated device; a second metallization portion, the second metallization portion is coupled to the second integrated device and the first metallization portion; and an encapsulation layer, the encapsulation layer is coupled to the first metallization portion, the second integrated device, and the second metallization portion. The first metallization portion includes at least one first dielectric layer and a first plurality of metallization interconnects. The second metallization portion includes at least one second dielectric layer and a second plurality of metallization interconnects.

[0027] Exemplary package including a first metallization portion and a second metallization portion

[0028] Figure 1 An exemplary cross-sectional view of a package 100 including a first metallization portion and a second metallization portion is illustrated. The package 100 is coupled to a board 101 through a plurality of solder interconnects 117. The board 101 includes at least one board dielectric layer 110 and a plurality of board interconnects 112. The board 101 may include a printed circuit board (PCB). The package 100 is coupled to a plurality of board interconnects 112 of the board 101 through the plurality of solder interconnects 117.

[0029] Package 100 includes metallization 102, integrated device 104, integrated device 106, passive device 107, passive device 109, encapsulation layer 108, and solder resist layer 124. Integrated device 104 is coupled to metallization 102. Integrated device 106 is coupled to metallization 102. Passive device 107 and passive device 109 are each coupled to metallization 102. Encapsulation layer 108 is coupled to metallization 102. For example, encapsulation layer 108 is coupled to a surface of metallization 102. Encapsulation layer 108 is coupled to integrated device 104, integrated device 106, passive device 107, and passive device 109. Encapsulation layer 108 encapsulates integrated device 104, integrated device 106, passive device 107, and passive device 109.

[0030] The metallization 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 122. The metallization 102 may include a redistribution portion (e.g., a first redistribution portion). The metallization 102 may include a first side and a second side. The first side may be a top side and the second side may be a bottom side. The plurality of metallization interconnects 122 may include a plurality of redistribution interconnects (e.g., a first plurality of redistribution interconnects). The metallization 102 may be a front side metallization of the package 100 (e.g., a front side redistribution portion). The metallization 102 may be a metallization interconnect device (e.g., a front side metallization interconnect device). A solder resist layer 124 is coupled to a surface of the metallization 102.

[0031] The integrated device 106 is coupled to the metallization portion 102. For example, the integrated device 106 is coupled to a plurality of metallization interconnects 122 of the metallization portion 102. At least some of the metallization interconnects from the plurality of metallization interconnects 122 may be coupled to (eg, contact) interconnects of the integrated device 106.

[0032] The integrated device 104 includes a metallization 140, an integrated device 105, an encapsulation layer 158, an underfill 145, and a plurality of solder interconnects 150. The integrated device 105 may include a bare die (e.g., a semiconductor bare die). The integrated device 105 may include a chip. The integrated device 104 may be an integrated device package (e.g., a first package, a first integrated device package). The integrated device 105 is coupled to the metallization 140 through a plurality of solder interconnects 150. The underfill 145 may be located between the integrated device 105 and the metallization 140. The metallization 140 includes at least one dielectric layer 141 and a plurality of metallization interconnects 142. The integrated device 105 is coupled to a plurality of metallization interconnects 142 of the plurality of metallizations 140 through a plurality of solder interconnects 150. The encapsulation layer 158 is coupled to the integrated device 105 and the metallization 140. The encapsulation layer 158 encapsulates at least the integrated device 105 and the underfill 145. Encapsulation layer 158 may be coupled to encapsulation layer 108. For example, the outer surface of encapsulation layer 158 may contact the inner surface of encapsulation layer 108. Encapsulation layer 108 and / or encapsulation layer 158 may include a molding, a resin and / or an epoxy resin. Encapsulation layer 108 and / or encapsulation layer 158 may be an encapsulation device. Encapsulation layer 108 and / or encapsulation layer 158 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Encapsulation layer 108 and encapsulation layer 158 may include the same and / or similar encapsulation materials. In some implementations, encapsulation layer 108 and encapsulation layer 158 may include different encapsulation materials. In some implementations, there may be an interface between encapsulation layer 108 and encapsulation layer 158.

[0033] As mentioned above, the integrated device 104 is coupled to the metallization portion 102. Figure 1As shown in FIG. 1 , the metallization 140 is coupled to the metallization 102. The plurality of metallization interconnects 142 of the metallization 140 are coupled to the plurality of metallization interconnects 122 of the metallization 102. The metallization 140 may be a first metallization. The metallization 102 may be a second metallization.

[0034] The metallization 140 may include a redistribution portion (e.g., a second redistribution portion). The metallization 140 may include a first side and a second side. The first side may be a top side and the second side may be a bottom side. The plurality of metallization interconnects 142 may include a plurality of redistribution interconnects (e.g., a second plurality of redistribution interconnects). The metallization 140 may be a metallization interconnect device (e.g., a first metallization interconnect device). The plurality of metallization interconnects 142 may include a first plurality of metallization interconnects. The at least one dielectric layer 141 may include at least one first dielectric layer. The integrated device 105 is coupled to the top side of the metallization 140. The top side of the metallization 140 faces the integrated device 105. However, in some implementations, the integrated device 105 may be coupled to the bottom side of the metallization 140. In this example, the top side of the metallization 140 may be coupled to the metallization 102.

[0035] The metallization portion 102 may include a redistribution portion (e.g., a second redistribution portion). The metallization portion 102 may include a first side and a second side. The first side may be a top side and the second side may be a bottom side. The plurality of metallization interconnects 122 may include a plurality of redistribution interconnects (e.g., a second plurality of redistribution interconnects). The metallization portion 102 may be a metallization interconnect device (e.g., a second metallization interconnect device). The plurality of metallization interconnects 122 may include a second plurality of metallization interconnects. The at least one dielectric layer 120 may include at least one second dielectric layer. The bottom side of the metallization portion 140 is coupled to the bottom side of the metallization portion 102. The bottom side of the metallization portion 102 faces the integrated device 105. At least in the following Figure 7A-7B The concept of bottom side and / or top side of the metallization portion is further described in.

[0036] As mentioned above, the metallization portion (e.g., 102, 140) may include a redistribution portion that includes a redistribution interconnect (e.g., a redistribution layer (RDL) interconnect). The redistribution interconnect may include a portion having a U-shape or a V-shape. The terms "U-shaped" and "V-shaped" should be interchangeable. The terms "U-shaped" and "V-shaped" may refer to the side profile shape of an interconnect and / or a redistribution interconnect. A U-shaped interconnect (e.g., a U-shaped side profile interconnect) and a V-shaped interconnect (e.g., a V-shaped side profile interconnect) may have a top and a bottom. The bottom of a U-shaped interconnect (or a V-shaped interconnect) may be coupled to the top of another U-shaped interconnect (or a V-shaped interconnect). Note that the metallization portion 102 and the metallization portion 140 are shown as metallization interconnects having different shapes. In some implementations, the plurality of metallization interconnects 142 of the metallization portion 140 may have shapes like and / or similar to Figure 1 The cross-sectional shape of the plurality of metallization interconnects 122 of the metallization portion 102 is shown in FIG. In some implementations, the plurality of metallization interconnects 122 of the metallization portion 102 may have a shape similar to and / or similar to Figure 1 The cross-sectional shape of the plurality of metallization interconnects 142 of the metallization portion 140 is shown in FIG.

[0037] The metallization 140 may be coupled to the metallization 102 such that the bottom side of the metallization 140 is coupled to the bottom side of the metallization 102. However, different implementations may couple the metallization 140 to the metallization 102 differently. For example, in some implementations, the metallization 140 may be coupled to the metallization 102 such that the top side of the metallization 140 is coupled to the bottom side of the metallization 102. Figure 7B The description and illustrations in FIG. 5 are meant as examples of bottom and top sides of metallizations.

[0038] As mentioned above, the metallization portion 140 may include a redistribution portion (e.g., a first redistribution portion), and the metallization portion 102 may include a redistribution portion (e.g., a second redistribution portion). In some implementations, the bottom / bottom side of the first redistribution portion is directly coupled to the bottom / bottom side of the second redistribution portion.

[0039] In some implementations, the metallization 140 and / or the metallization 102 may be formed and / or defined as continuous and / or contiguous metallizations. For example, the at least one dielectric layer 141 and the at least one dielectric layer 120 may be considered as part of the same dielectric layer. In some implementations, the at least one dielectric layer 141 and the at least one dielectric layer 120 may include the same dielectric material (e.g., polyimide (PI)). In some implementations, there may be an interface between the dielectric layer of the metallization 140 and the dielectric layer of the metallization 102. In some implementations, the metallization 140 and the metallization 102 may be considered as two separate metallizations coupled to each other.

[0040] The metallization 140 may have a smaller footprint than the metallization 102. For example, the metallization 140 may have a width that is smaller than the width of the metallization 102. In some implementations, the metallization 140 may have a surface plan area that is smaller than the surface plan area of ​​the metallization 102. In some implementations, the metallization 140 is coupled to the metallization 102 such that there is no solder interconnection between the metallization 140 and the metallization 102. Thus, at least some of the metallization interconnections of the metallization 140 may be in direct contact (e.g., touching) with at least some of the metallization interconnections of the metallization 102. This may help provide a thinner package with a smaller form factor.

[0041] The integrated device 105 is configured to be electrically coupled to the integrated device 106 through at least one electrical path (e.g., for input / output signals) including (i) at least one solder interconnect from the plurality of solder interconnects 150, (ii) at least one metallization interconnect from the plurality of metallization interconnects 142, and (iii) at least one metallization interconnect from the plurality of metallization interconnects 122. Thus, the integrated device 105 is configured to be electrically coupled to the integrated device 106 through the metallization 140 and the metallization 102 such that at least one electrical path between the integrated device 105 and the integrated device 106 extends through the metallization 140 and the metallization 102.

[0042] The electrical path between board 101 and integrated device 105 may include (i) at least one board interconnect from multiple board interconnects 112, (ii) at least one solder interconnect from multiple solder interconnects 117, (iii) at least one metallization interconnect from multiple metallization interconnects 122, (iv) at least one metallization interconnect from multiple metallization interconnects 142, and (v) at least one solder interconnect from multiple solder interconnects 150.

[0043] The integrated device 105 is configured to be electrically coupled to the passive device 107 through at least one electrical path (e.g., for power) including (i) at least one solder interconnect from the plurality of solder interconnects 150, (ii) at least one metallization interconnect from the plurality of metallization interconnects 142, and (iii) at least one metallization interconnect from the plurality of metallization interconnects 122. Thus, the integrated device 105 is configured to be electrically coupled to the passive device 107 through the metallization portion 140 and the metallization portion 102.

[0044] Similarly, the integrated device 105 is configured to be electrically coupled to the passive device 109 through at least one electrical path (e.g., for power) that includes (i) at least one solder interconnect from the plurality of solder interconnects 150, (ii) at least one metallization interconnect from the plurality of metallization interconnects 142, and (iii) at least one metallization interconnect from the plurality of metallization interconnects 122. Thus, the integrated device 105 is configured to be electrically coupled to the passive device 109 through the metallization portion 140 and the metallization portion 102.

[0045] Passive device 107 and passive device 109 may each include a pad (not shown) that may be coupled to (e.g., contact) metallization portion 102. For example, passive device 107 and passive device 109 may each include a pad (not shown) that may be coupled to a metallization interconnect of metallization portion 102.

[0046] Figure 1 The package 100 illustrates an example of a package including at least two metallization portions (eg, two redistribution portions) that facilitate providing a package with an overall smaller thickness. Figure 2 and 3 Other examples of packages are illustrated that include at least two metallizations that help provide a package with an overall smaller thickness.

[0047] Figure 2 A package 200 including a first metallization portion and a second metallization portion is illustrated. The package 200 includes the package 100 and an integrated device 204. The integrated device 204 is coupled to the package 100 via a plurality of solder interconnects 240. The package 200 may include a package-on-package (PoP). The package 200 is coupled to the board 101 via a plurality of solder interconnects 117. The board 101 includes at least one board dielectric layer 110 and a plurality of board interconnects 112. The board 101 may include a printed circuit board (PCB). The package 200 is coupled to a plurality of board interconnects 112 of the board 101 via a plurality of solder interconnects 117.

[0048] Figure 2 The package 100 is similar to Figure 1 Package 100. Figure 2 The package 100 includes Figure 1 The package 100 includes a metallization portion 102, an integrated device 104, an integrated device 106, a passive device 107, a passive device 109, an encapsulation layer 108, a plurality of through-mold vias (TMVs) 280, a plurality of interconnects 282, a solder resist layer 124, and a solder resist layer 224. The plurality of through-mold vias 280 are coupled in the encapsulation layer 108 and extend through the thickness (e.g., the entire thickness) of the encapsulation layer 108. The plurality of through-mold vias 280 are coupled to the metallization portion 102. The plurality of through-mold vias 280 are coupled to the plurality of metallization interconnects 122. The plurality of interconnects 282 are coupled to the surface (e.g., the top surface) of the encapsulation layer 108. The plurality of interconnects 282 are coupled to the plurality of through-mold vias 280. The integrated device 204 is coupled to the plurality of interconnects 282 via a plurality of solder interconnects 240. The solder resist layer 224 is coupled to a surface (eg, a top surface) of the encapsulation layer 108. The plurality of through-mold vias 280 are examples of a plurality of through-mold interconnects.

[0049] The integrated device 105 is configured to be electrically coupled to the integrated device 204 through at least one electrical path (e.g., for input / output signals) including (i) at least one solder interconnect from the plurality of solder interconnects 150, (ii) at least one metallization interconnect from the plurality of metallization interconnects 142, (iii) at least one metallization interconnect from the plurality of metallization interconnects 122, (iv) at least one via from the plurality of through-mold vias 280, (v) at least one interconnect from the plurality of interconnects 282, and (vi) at least one solder interconnect from the plurality of solder interconnects 240. Thus, the integrated device 105 is configured to be electrically coupled to the integrated device 204 through the metallization 140 and the metallization 102 such that at least one electrical path between the integrated device 105 and the integrated device 204 extends through at least the metallization 140 and the metallization 102.

[0050] The integrated device 106 is configured to be electrically coupled to the integrated device 204 through at least one electrical path (e.g., for input / output signals) that includes (i) at least one metallization interconnect from the plurality of metallization interconnects 122, (ii) at least one via from the plurality of through-mold vias 280, (iii) at least one interconnect from the plurality of interconnects 282, and (iv) at least one solder interconnect from the plurality of solder interconnects 240. Thus, the integrated device 106 is configured to be electrically coupled to the integrated device 204 through the metallization portion 102 such that at least one electrical path between the integrated device 106 and the integrated device 204 extends at least through the metallization portion 102.

[0051] Figure 3A package 300 including a first metallization portion and a second metallization portion is illustrated. The package 300 includes the package 100 and the integrated device 204. The integrated device 204 is coupled to the package 100 via a plurality of solder interconnects 240. The package 300 may include a package-on-package (PoP). The package 300 is coupled to the board 101 via a plurality of solder interconnects 117. The board 101 includes at least one board dielectric layer 110 and a plurality of board interconnects 112. The board 101 may include a printed circuit board (PCB). The package 300 is coupled to a plurality of board interconnects 112 of the board 101 via a plurality of solder interconnects 117.

[0052] Figure 3 The package 100 is similar to Figure 1 Package 100. Figure 3 The package 100 includes Figure 1 The package 100 includes a metallization portion 102, an integrated device 104, an integrated device 106, a passive device 107, a passive device 109, an encapsulation layer 108, a plurality of through-mold solder interconnects 380, a plurality of interconnects 282, a solder resist layer 124, and a solder resist layer 224. The plurality of through-mold solder interconnects 380 are located in the encapsulation layer 108 and extend through the thickness (e.g., the entire thickness) of the encapsulation layer 108. The plurality of through-mold solder interconnects 380 are coupled to the metallization portion 102. The plurality of through-mold solder interconnects 380 are coupled to the plurality of metallization interconnects 122. The plurality of interconnects 282 are coupled to the surface (e.g., the top surface) of the encapsulation layer 108. The plurality of interconnects 282 are coupled to the plurality of through-mold solder interconnects 380. The integrated device 204 is coupled to the plurality of interconnects 282 via the plurality of solder interconnects 240. The solder resist layer 224 is coupled to a surface (eg, a top surface) of the encapsulation layer 108 .

[0053] The plurality of through-mold solder interconnects 380 may include a through-mold solder interconnect 380a and a through-mold solder interconnect 380b. The through-mold solder interconnect 380a is coupled to the through-mold solder interconnect 380b. The through-mold solder interconnect 380a may have a diameter (e.g., a first diameter) larger than a diameter (e.g., a second diameter) of the through-mold solder interconnect 380b. The through-mold solder interconnect 380a may have a width (e.g., a first width) larger than a width (e.g., a second width) of the through-mold solder interconnect 380b. The plurality of through-mold solder interconnects 380 are examples of the plurality of through-mold interconnects.

[0054] The integrated device 105 is configured to be electrically coupled to the integrated device 204 through at least one electrical path (e.g., for input / output signals) including (i) at least one solder interconnect from the plurality of solder interconnects 150, (ii) at least one metallization interconnect from the plurality of metallization interconnects 142, (iii) at least one metallization interconnect from the plurality of metallization interconnects 122, (iv) at least one solder interconnect from the plurality of through-mold solder interconnects 380, (v) at least one interconnect from the plurality of interconnects 282, and (vi) at least one solder interconnect from the plurality of solder interconnects 240. Thus, the integrated device 105 is configured to be electrically coupled to the integrated device 204 through the metallization 140 and the metallization 102 such that at least one electrical path between the integrated device 105 and the integrated device 204 extends through at least the metallization 140 and the metallization 102.

[0055] The integrated device 106 is configured to be electrically coupled to the integrated device 204 through at least one electrical path (e.g., for input / output signals) that includes (i) at least one metallization interconnect from the plurality of metallization interconnects 122, (ii) at least one solder interconnect from the plurality of through-mold solder interconnects 380, (iii) at least one interconnect from the plurality of interconnects 282, and (iv) at least one solder interconnect from the plurality of solder interconnects 240. Thus, the integrated device 106 is configured to be electrically coupled to the integrated device 204 through the metallization portion 102 such that at least one electrical path between the integrated device 106 and the integrated device 204 extends at least through the metallization portion 102.

[0056] The integrated device (e.g., 104, 105, 106, 204) may include a die (e.g., a bare semiconductor die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, an integrated device based on gallium arsenide (GaAs), a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or a combination thereof. The integrated device (e.g., 104, 105, 106, 204) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. The integrated device may be an example of an electrical component and / or an electrical device. In some implementations, the integrated device may be a core particle. The core particles can be manufactured using a process that provides better yields than other processes used to manufacture other types of integrated devices, which can reduce the overall cost of manufacturing the core particles. Different core particles can have different sizes and / or shapes. Different core particles can be configured to provide different functions. Different core particles can have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several core particles can be used to perform the functionality of one or more chips (e.g., one or more integrated devices). Relative to using a single chip to perform all the functions of a package, using several core particles that perform several functions can reduce the overall cost of the package.

[0057] The package (e.g., 100, 200, 300) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The package (e.g., 100, 200, 300) may be configured to provide wireless fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The package (e.g., 100, 200, 300) may be configured to support a global system for mobile communications (GSM), a universal mobile telecommunications system (UMTS), and / or long term evolution (LTE). The package (e.g., 100, 200, 300) may be configured to transmit and receive signals having different frequencies and / or communication protocols.

[0058] Exemplary process for manufacturing a package including a first metallization and a second metallization

[0059] In some implementations, manufacturing the package includes several processes. Figures 4A-4F Exemplary processes for providing or manufacturing a package are described. In some implementations, Figures 4A-4F The process may be used to provide or manufacture package 200. However, Figures 4A-4FThe process may be used to manufacture any package (eg, 100) described in the present disclosure.

[0060] It should be noted that Figures 4A-4F The process of one or more stages may be combined to simplify and / or clarify the process for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be replaced or substituted without departing from the scope of the present disclosure.

[0061] like Figure 4A , stage 1 illustrates a state after integrated device 104, integrated device 106, passive device 107, and passive device 109 are placed on carrier 400. A pick-and-place process may be used to place integrated device 104, integrated device 106, passive device 107, and passive device 109 on carrier 400. Carrier 400 may include a tape. Integrated device 104 includes metallization 140, a plurality of solder interconnects 150, an underfill 145, integrated device 105, and an encapsulation layer 158.

[0062] Stage 2 illustrates a state after forming encapsulation layer 108. Encapsulation layer 108 may be formed over carrier 400, integrated device 104, integrated device 106, passive device 107, and passive device 109. Encapsulation layer 108 may be coupled to carrier 400, integrated device 104, integrated device 106, passive device 107, and passive device 109. Encapsulation layer 108 may encapsulate integrated device 104, integrated device 106, passive device 107, and passive device 109.

[0063] The encapsulation layer 108 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 108 may be an encapsulation device. The encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, a polishing process and / or a grinding process may be performed on the encapsulation layer 108 to at least provide a flatter surface of the encapsulation layer 108.

[0064] Stage 3 illustrates a state after a plurality of cavities 480 are formed in the encapsulation layer 108. The plurality of cavities 480 may be formed using an etching process (eg, photolithography) and / or a laser process.

[0065] like Figure 4B , stage 4 illustrates a state after forming a plurality of through-mold vias 280 in a plurality of cavities 480. The plurality of through-mold vias 280 may be through-hole interconnects formed by a pasting process and / or a plating process.

[0066] Stage 5 illustrates a state after forming a plurality of interconnects 282 over the encapsulation layer 108. A plating process and a patterning process may be used to form the plurality of interconnects 282. The plurality of interconnects 282 may be coupled to the plurality of through-mold vias 280.

[0067] Stage 6 illustrates a state after the solder resist layer 224 is formed over the encapsulation layer 108 and the plurality of interconnects 282. Deposition, lamination, exposure, development, and / or etching processes may be used to form and pattern the solder resist layer 224.

[0068] As in Figure 4C , stage 7 illustrates a state after removing, decoupling, and / or separating the carrier 400. The carrier 400 may be decoupled from the encapsulation layer 108. Different implementations may decouple the carrier 400 from the encapsulation layer 108 differently. The carrier 400 may be peeled and / or ground off from the encapsulation layer 108.

[0069] Stage 8 illustrates a state after dielectric layer 410 is formed and coupled to encapsulation layer 108, integrated device 106, passive device 107, passive device 109, and metallization portion 140 of integrated device 104. Deposition and / or lamination processes may be used to form dielectric layer 410. Dielectric layer 410 may be coupled to at least one dielectric layer 141.

[0070] Stage 9 illustrates a state after forming a plurality of cavities 412 in the dielectric layer 410. Exposure, development, and / or etching processes may be used to form the plurality of cavities 412.

[0071] like Figure 4D , stage 10 illustrates a state after a plurality of metallization interconnects 414 are formed in and on the dielectric layer 410. A plating process and a patterning process may be used to form the plurality of metallization interconnects 414. The plurality of metallization interconnects 414 may be coupled to the plurality of through-mold vias 280, the integrated device 106, the passive device 107, the passive device 109, and metallization interconnects from the plurality of metallization interconnects 142. For example, the plurality of metallization interconnects 414 may be formed such that the plurality of metallization interconnects 4141 are coupled to (e.g., contact) the plurality of through-mold vias 280, at least one interconnect of the integrated device 106, at least one interconnect of the passive device 107, at least one interconnect of the passive device 109, and / or at least one metallization interconnect from the plurality of metallization interconnects 142.

[0072] Stage 11 illustrates a state after dielectric layer 420 is formed and coupled to dielectric layer 410. Dielectric layer 420 may be formed using a deposition and / or lamination process. Note that dielectric layer 410 and dielectric layer 420 may be represented by dielectric layer 120.

[0073] like Figure 4EAs shown in FIG. 1 , stage 12 illustrates a state after forming a plurality of cavities 422 in dielectric layer 120. Exposure, development, and / or etching processes may be used to form the plurality of cavities 422.

[0074] Stage 13 illustrates a state after forming a plurality of metallization interconnects 424 in and on dielectric layer 420. A plating process and a patterning process may be used to form the plurality of metallization interconnects 424. The plurality of metallization interconnects 424 may be coupled to the plurality of metallization interconnects 414. The plurality of metallization interconnects 414 and the plurality of metallization interconnects 424 may be represented by a plurality of metallization interconnects 122. The plurality of metallization interconnects 122 and the at least one dielectric layer 120 may form a metallization portion 102. The metallization portion 102 may be a second metallization portion. The metallization portion 102 may be used in conjunction with Figure 7A-7B The method described is the same and / or similar to the method described. Stage 13 illustrates the bottom side of the metallization 102 being coupled to the bottom side of the metallization 140 .

[0075] like Figure 4F , stage 14 illustrates a state after forming a solder resist layer 124 over portions of the metallization 102, the at least one dielectric layer 120, and / or the plurality of metallization interconnects 122. Deposition, lamination, exposure, development, and / or etching processes may be used to form and pattern the solder resist layer 124.

[0076] Stage 15 illustrates a state after the plurality of solder interconnects 117 are coupled to the metallization 102. The plurality of solder interconnects 117 may be coupled to a first side (e.g., top side) of the metallization 102. A solder reflow process may be used to couple the plurality of solder interconnects 117 to the plurality of metallization interconnects 122 of the metallization 102.

[0077] Exemplary process for manufacturing a package including a first metallization and a second metallization

[0078] In some implementations, manufacturing the package includes several processes. Figures 5A-5F Exemplary processes for providing or manufacturing a package are described. In some implementations, Figures 5A-5F The process may be used to provide or manufacture package 300. However, Figures 5A-5F The process may be used to manufacture any package (eg, 100) described in the present disclosure.

[0079] It should be noted that Figures 5A-5F The process of one or more stages may be combined to simplify and / or clarify the process for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be replaced or substituted without departing from the scope of the present disclosure.

[0080] like Figure 5A , stage 1 illustrates a state after integrated device 104, integrated device 106, passive device 107, and passive device 109 are placed on carrier 400. A pick-and-place process may be used to place integrated device 104, integrated device 106, passive device 107, and passive device 109 on carrier 400. Carrier 400 may include a tape. Integrated device 104 includes metallization 140, a plurality of solder interconnects 150, an underfill 145, integrated device 105, and an encapsulation layer 158.

[0081] Phase 2 illustrates a state after providing a plurality of solder interconnects 510 on the carrier 400. A reflow process may be used to provide and / or form the plurality of solder interconnects 510.

[0082] Stage 3 illustrates a state after forming an encapsulation layer 550. The encapsulation layer 550 may be formed on and / or around the carrier 400, the integrated device 106, the passive device 107, the passive device 109, and the plurality of solder interconnects 510. The encapsulation layer 550 may be coupled to the carrier 400, the integrated device 104, the integrated device 106, the passive device 107, the passive device 109, and the plurality of solder interconnects 510. The encapsulation layer 550 may encapsulate at least a portion of the integrated device 104, at least a portion of the integrated device 106, at least a portion of the passive device 107, at least a portion of the passive device 109, and / or at least a portion of the plurality of solder interconnects 510.

[0083] The encapsulation layer 550 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 550 may be an encapsulation device. The encapsulation layer 550 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0084] like Figure 5B As shown in FIG. 4 , stage 4 illustrates a state after providing the plurality of solder interconnects 580. A reflow process may be used to provide and / or form the plurality of solder interconnects 580. The plurality of solder interconnects 580 may be coupled to the plurality of solder interconnects 510.

[0085] Stage 5 illustrates a state after forming an encapsulation layer 590. The encapsulation layer 590 may be formed over the encapsulation layer 550, the integrated device 106, the passive device 107, the passive device 109, the plurality of solder interconnects 510, and the plurality of solder interconnects 580. The encapsulation layer 590 may be coupled to the encapsulation layer 550, the integrated device 104, the integrated device 106, the passive device 107, the passive device 109, the plurality of solder interconnects 510, and the plurality of solder interconnects 580. The encapsulation layer 590 may encapsulate at least a portion of the integrated device 104, at least a portion of the integrated device 106, at least a portion of the passive device 107, at least a portion of the passive device 109, at least a portion of the plurality of solder interconnects 510, and / or at least a portion of the plurality of solder interconnects 580. The plurality of solder interconnects 510 and the plurality of solder interconnects 580 may be represented by a plurality of through-mold solder interconnects 380. Encapsulation layer 590 may include a molded part, a resin, and / or an epoxy resin. Encapsulation layer 590 may be an encapsulation device. Encapsulation layer 590 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. There may or may not be an interface between encapsulation layer 550 and encapsulation layer 590. Encapsulation layer 550 and / or encapsulation layer 590 may be denoted as encapsulation layer 108.

[0086] Stage 6 illustrates a state after removing portions of the encapsulation layer 108 and portions of the plurality of through-mold solder interconnects 380. In some implementations, a polishing process and / or a grinding process may be performed on the encapsulation layer 108 and the plurality of through-mold solder interconnects 380 to at least planarize the surfaces of the encapsulation layer 108 and the plurality of through-mold solder interconnects 380.

[0087] like Figure 5C As shown in FIG. 1 , stage 7 illustrates a state after forming a plurality of interconnects 282 over the encapsulation layer 108. A plating process and a patterning process may be used to form the plurality of interconnects 282. The plurality of interconnects 282 may be coupled to a plurality of through-mold solder interconnects 380.

[0088] Stage 8 illustrates a state after the solder resist layer 224 is formed over the encapsulation layer 108 and the plurality of interconnects 282. Deposition, lamination, exposure, development, and / or etching processes may be used to form and pattern the solder resist layer 224.

[0089] Stage 9 illustrates a state after the carrier 400 is removed, decoupled, and / or separated. The carrier 400 may be decoupled from the encapsulation layer 108. Different implementations may decouple the carrier 400 from the encapsulation layer 108 differently. The carrier 400 may be peeled and / or ground off from the encapsulation layer 108.

[0090] like Figure 5D, stage 10 illustrates a state after dielectric layer 410 is formed and coupled to encapsulation layer 108, integrated device 106, passive device 107, passive device 109, and metallization portion 140 of integrated device 104. Deposition and / or lamination processes may be used to form dielectric layer 410. Dielectric layer 410 may be coupled to at least one dielectric layer 141.

[0091] Stage 11 illustrates a state after a plurality of cavities 412 are formed in the dielectric layer 410. Exposure, development, and / or etching processes may be used to form the plurality of cavities 412.

[0092] Stage 12 illustrates a state after a plurality of metallization interconnects 414 are formed in and on the dielectric layer 410. A plating process and a patterning process may be used to form the plurality of metallization interconnects 414. The plurality of metallization interconnects 414 may be coupled to the plurality of through-mold solder interconnects 380, the integrated device 106, the passive device 107, the passive device 109, and metallization interconnects from the plurality of metallization interconnects 142. For example, the plurality of metallization interconnects 414 may be formed such that the plurality of metallization interconnects 414 are coupled to (e.g., contact) the plurality of through-mold solder interconnects 380, at least one interconnect of the integrated device 106, at least one interconnect of the passive device 107, at least one interconnect of the passive device 109, and / or at least one metallization interconnect from the plurality of metallization interconnects 142.

[0093] like Figure 5E As shown in FIG. 1 , stage 13 illustrates a state after dielectric layer 420 is formed and coupled to dielectric layer 410. Dielectric layer 420 may be formed using a deposition and / or lamination process. Note that dielectric layer 410 and dielectric layer 420 may be represented by dielectric layer 120.

[0094] Stage 14 illustrates a state after forming a plurality of cavities 422 in the dielectric layer 120. Exposure, development, and / or etching processes may be used to form the plurality of cavities 422.

[0095] Stage 15 illustrates a state after forming a plurality of metallization interconnects 424 in and on dielectric layer 420. A plating process and a patterning process may be used to form the plurality of metallization interconnects 424. The plurality of metallization interconnects 424 may be coupled to the plurality of metallization interconnects 414. The plurality of metallization interconnects 414 and the plurality of metallization interconnects 424 may be represented by a plurality of metallization interconnects 122. The plurality of metallization interconnects 122 and the at least one dielectric layer 120 may form a metallization portion 102. The metallization portion 102 may be a second metallization portion. The metallization portion 102 may be used in conjunction with Figure 7A-7B The methods described are the same and / or similar to those described.

[0096] like Fig. 5F, stage 16 illustrates a state after forming a solder resist layer 124 over portions of the metallization 102, the at least one dielectric layer 120, and / or the plurality of metallization interconnects 122. Deposition, lamination, exposure, development, and / or etching processes may be used to form and pattern the solder resist layer 124.

[0097] Stage 17 illustrates a state after coupling the plurality of solder interconnects 117 to the metallization 102. The plurality of solder interconnects 117 may be coupled to a first side (e.g., top side) of the metallization 102. A solder reflow process may be used to couple the plurality of solder interconnects 117 to the plurality of metallization interconnects 122 of the metallization 102.

[0098] Exemplary flow chart of a method for manufacturing a package comprising a first metallization and a second metallization

[0099] In some implementations, manufacturing the package includes several processes. Figure 6 An exemplary flow chart of a method 600 for providing or manufacturing a package is illustrated. In some implementations, Figure 6 The method 600 may be used to provide or manufacture the Figure 2 However, the method 600 may be used to provide or manufacture any package (eg, 100, 200, 300) described in the present disclosure.

[0100] It should be noted that Figure 6 The method 600 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified.

[0101] The method (at 605) provides a carrier (e.g., 400). The method (at 605) places at least one integrated device and / or at least one passive device on the carrier. A pick-and-place process may be used to place and / or couple the integrated devices and / or passive devices to the carrier. For example, the method may place and / or couple the integrated device 104, the integrated device 106, the passive device 107, and the passive device 109 to the carrier 400. The integrated device 104 includes a metallization 140 (e.g., a first metallization), a plurality of solder interconnects 150, an underfill 145, an integrated device 105 (e.g., a first integrated device), and an encapsulation layer 158. The carrier 400 may include a tape. Thus, in one example, the method includes a first integrated device and a first package coupled to a first metallization of the first integrated device. The first metallization includes at least one first dielectric layer and a first plurality of metallization interconnects. The method may also provide a second integrated device. Figure 4A Phase 1 and Figure 5AStage 1 of the present invention illustrates and describes an example of providing a carrier and placing integrated devices and / or passive devices on the carrier.

[0102] The method optionally forms (at 610) a plurality of solder interconnects on the carrier (eg, 510). A reflow process may be used to provide and / or form the plurality of solder interconnects. Figure 5A Stage 2 of the present invention illustrates and describes an example of forming multiple solder interconnects.

[0103] The method forms (at 615) an encapsulation layer (e.g., 108, 550). For example, the encapsulation layer (e.g., 108, 550) may be formed over the carrier 400, the integrated device 106, the passive device 107, the passive device 109, and the plurality of solder interconnects 510 (if present). The encapsulation layer may be coupled to the carrier 400, the integrated device 104, the integrated device 106, the passive device 107, the passive device 109, and the plurality of solder interconnects 510. The encapsulation layer may encapsulate at least a portion of the integrated device 104, at least a portion of the integrated device 106, at least a portion of the passive device 107, at least a portion of the passive device 109, and / or at least a portion of the plurality of solder interconnects 510. Thus, in one example, the method forms an encapsulation layer over the first package and the second integrated device. The encapsulation layer may include a molding, a resin, and / or an epoxy. The encapsulation layer may be an encapsulation device. The encapsulation layer may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Figure 4A Phase 2 and Figure 5A Stage 3 of illustrative and describes an example of forming an encapsulation layer. In some implementations, the method may return (at 610) to optionally form a plurality of solder interconnects (eg, 580). Figure 5B The example of forming a plurality of solder interconnections is illustrated and described in stage 4 of . In such an example, the method may then (at 615) form another encapsulation layer (eg, 590). Figure 5B Stage 5 of the present invention illustrates and describes an example of forming an encapsulation layer. The plurality of solder interconnects located in the encapsulation layer may be a form of a plurality of through-mold interconnects. In some implementations, a polishing process and / or a grinding process may be performed on the encapsulation layer and the plurality of through-mold solder interconnects (if present) to at least flatten the surfaces of the encapsulation layer and the plurality of through-mold solder interconnects. Figure 5C Stage 6 illustrates and describes an example of removing portions of the encapsulation layer and portions of the solder interconnects.

[0104] The method optionally forms (at 620) a plurality of through-mold interconnects in the encapsulation layer and forms (at 620) interconnects (e.g., 282) over a surface of the encapsulation layer. Forming the plurality of through-mold interconnects may include forming a plurality of through-mold vias 280. Forming the plurality of through-mold interconnects includes forming a plurality of cavities in the encapsulation layer and forming interconnects (e.g., vias) in the plurality of cavities. Figure 4AStage 3 to Figure 4B Stage 5 of the present invention illustrates and describes an example of forming multiple through-mold interconnects and interconnects. Figure 5C Stage 7 of the present invention illustrates and describes an example of forming interconnects above the surface of the encapsulation layer.

[0105] The method forms a solder resist layer over the encapsulation layer and the plurality of interconnects (at 625). For example, a solder resist layer 224 may be formed over the encapsulation layer 108 and the plurality of interconnects 282. Deposition, lamination, exposure, development, and / or etching processes may be used to form and pattern the solder resist layer 224. Figure 4B Stage 6 and Figure 5C Stage 8 of FIG. 1 illustrates and describes an example of forming a solder mask layer.

[0106] The method removes the carrier (at 630). For example, the carrier 400 may be removed, decoupled, and / or separated from the encapsulation layer 108. Different implementations may decouple the carrier 400 from the encapsulation layer 108 differently. The carrier 400 may be ground away from the encapsulation layer 108. Figure 4B Stage 7 and Figure 5C Stage 9 of illustrates an example of removing a carrier.

[0107] The method forms (at 635) a metallization portion on the surface of the encapsulation layer, at least one integrated device, at least one passive device, and another metallization. For example, the metallization portion 102 (e.g., a second metallization portion) may be formed on the surface of the encapsulation layer 108, the integrated device 106, the metallization portion 140, the passive device 107, and the passive device 109. Forming the metallization portion includes forming at least one dielectric layer and a plurality of metallization interconnects. Thus, in one example, the method forms a second metallization portion on the second integrated device, the first metallization portion of the first package, and the encapsulation layer. The second metallization portion includes at least one second dielectric layer and a second plurality of metallization interconnects. Figure 4C Stage 8 to Figure 4E Stage 13 of FIG. 1 illustrates an example of forming a metallization portion. Figure 5D Stages 10 to Figure 5E Stage 15 of FIG. 1 illustrates an example of forming a metallization portion.

[0108] The method forms a solder resist layer on a metallization portion (e.g., a second metallization portion) and couples a plurality of solder interconnects to the metallization portion (at 640). For example, a solder resist layer 124 may be formed on the metallization portion 102 and a plurality of solder interconnects 117 may be coupled to the metallization portion 102. Figure 4F Stage 14 and Fig. 5F Stage 16 of the present invention illustrates and describes an example of forming a solder mask layer.

[0109] In some implementations, several packages are manufactured simultaneously. In such cases, the method may singulate the packages (eg, 100, 200, 300).

[0110] Exemplary Process for Making Metallized Portions

[0111] In some implementations, fabricating the metallization includes several processes. Figure 7A-7B Exemplary processes for providing or manufacturing metallized portions are described. In some implementations, Figure 7A-7B The process may be used to provide or manufacture the metallization portion 102. However, Figure 7A-7B The process may be used to fabricate any metallization portion (eg, 140 ) described in the present disclosure.

[0112] It should be noted that Figure 7A-7B The process of one or more stages may be combined to simplify and / or clarify the process for providing or manufacturing the metallization portion. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be replaced or substituted without departing from the scope of the present disclosure. Figure 7A-7B The process may be used to manufacture metallization portions on one or more components (fabricated on the integrated device and / or another metallization portion) instead of the carrier.

[0113] As shown in FIG. 12A , stage 1 illustrates a state after providing a carrier 700. A seed layer 701 and an interconnect 702 may be located on the carrier 700. The interconnect 702 may be located on the seed layer 701. The interconnect 702 may be formed using a plating process and an etching process. In some implementations, the carrier 700 may be provided with a seed layer 701 and a metal layer that is patterned to form the interconnect 702. The interconnect 702 may represent at least some of the metallization interconnects from the plurality of metallization interconnects 122.

[0114] Stage 2 illustrates a state after dielectric layer 720 is formed over carrier 700, seed layer 701, and interconnect 702. Dielectric layer 720 may be formed using a deposition and / or lamination process. Dielectric layer 720 may include prepreg and / or polyimide. Dielectric layer 720 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0115] Stage 3 illustrates a state after a plurality of cavities 720 are formed in the dielectric layer 710. The plurality of cavities 710 may be formed using an etching process (eg, a photolithography process) or a laser process.

[0116] Stage 4 illustrates a state after interconnect 712 is formed in and on dielectric layer 720 (including in and on multiple cavities 710). For example, through holes, pads, and / or traces may be formed. A plating process may be used to form the interconnect. Stage 4 illustrates that certain portions of interconnect 712 may have a U-shape or a V-shape. The terms "U-shape" and "V-shape" should be interchangeable. The terms "U-shape" and "V-shape" may refer to the side profile shape of an interconnect and / or a redistribution interconnect. A U-shaped interconnect (e.g., a U-shaped side profile interconnect) and a V-shaped interconnect (e.g., a V-shaped side profile interconnect) may have a top and a bottom. The bottom of a U-shaped interconnect (or a V-shaped interconnect) may be coupled to the top of another U-shaped interconnect (or a V-shaped interconnect).

[0117] Stage 5 illustrates a state after dielectric layer 722 is formed over dielectric layer 720 and interconnect 712. Dielectric layer 722 may be formed using a deposition and / or lamination process. Dielectric layer 722 may include prepreg and / or polyimide. Dielectric layer 722 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0118] like Figure 7B , stage 6 illustrates a state after a plurality of cavities 730 are formed in the dielectric layer 722. The plurality of cavities 730 may be formed using an etching process (eg, a photolithography process) or a laser process.

[0119] Stage 7 illustrates a state after interconnect 714 is formed in and on dielectric layer 722 (including in and on multiple cavities 730). For example, through holes, pads, and / or traces may be formed. A plating process may be used to form the interconnect. Stage 7 illustrates that certain portions of interconnect 714 may have a U-shape or a V-shape. The terms "U-shape" and "V-shape" should be interchangeable. The terms "U-shape" and "V-shape" may refer to the side profile shape of an interconnect and / or a redistribution interconnect. A U-shaped interconnect (e.g., a U-shaped side profile interconnect) and a V-shaped interconnect (e.g., a V-shaped side profile interconnect) may have a top and a bottom. The bottom of a U-shaped interconnect (or a V-shaped interconnect) may be coupled to the top of another U-shaped interconnect (or a V-shaped interconnect).

[0120] Stage 8 illustrates a state after the carrier 700 is decoupled (e.g., separated, removed, ground away) from the at least one dielectric layer 120 and the seed layer 701, portions of the seed layer 701 are removed (e.g., etched away), leaving the metallization portion 102 including the at least one dielectric layer 120 and the plurality of metallization interconnects 122. The at least one dielectric layer 120 may represent the dielectric layer 720 and / or the dielectric layer 722. The plurality of metallization interconnects 122 may represent interconnects 702, 712, and / or 714. As mentioned above, the plurality of metallization interconnects 122 may include a plurality of redistribution interconnects. The plurality of metallization interconnects 122 may have a thickness in the range of about 3-7 microns. For example, one or more redistribution interconnects from the plurality of metallization interconnects 122 may have a thickness in the range of about 3-7 microns, which is less than the thickness of the interconnects from the package substrate (e.g., 304). Similar or identical dimensions may apply to the plurality of metallization interconnects 142 from the metallization portion 140. Stage 8 illustrates what may be considered the top side / top and what may be considered the bottom side / bottom of the metallization 102. The metallization 140 may have a top side / top and a bottom side / bottom in a similar manner.

[0121] Different implementations may use different processes to form the metal layer(s) and / or interconnects. In some implementations, the metal layer(s) may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spraying process, and / or a plating process.

[0122] Exemplary flow chart of a method for manufacturing a metallized portion

[0123] In some implementations, fabricating the metallization includes several processes. Figure 8 An exemplary flow chart of a method 800 for providing or manufacturing a metallization portion is illustrated. In some implementations, Figure 8 The method 800 may be used to provide or manufacture the metallization portion(s) of the present disclosure. For example, Figure 8 The method 800 may be used to manufacture the metallization portion 102 .

[0124] It should be noted that Figure 8 The method 800 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a metallization portion. In some implementations, the order of the processes may be changed or modified.

[0125] The method provides (at 805) a carrier (e.g., 700). Different implementations may use different materials for the carrier 700. The carrier 700 may include a seed layer (e.g., 701). The seed layer 701 may include a metal (e.g., copper). The carrier may include a substrate, glass, quartz, and / or a carrier tape. Fig. 7AStage 1 of the present invention illustrates and describes an example of providing a carrier having a seed layer.

[0126] The method forms (at 810) interconnects over the carrier 700 and the seed layer 701 and patterns them. The metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some implementations, the carrier and the seed layer may include a metal layer. The metal layer is located over the seed layer, and the metal layer may be patterned to form the interconnects (e.g., 122). Fig. 7A Stage 1 of the present invention illustrates and describes an example of forming and patterning interconnects over a seed layer and a carrier.

[0127] The method forms (at 815) a dielectric layer 720 over the interconnect 702, the seed layer 701, and the carrier 700. The dielectric layer 720 may be formed using a deposition and / or lamination process. The dielectric layer 720 may include a prepreg and / or a polyimide. The dielectric layer 720 may include a photoimageable dielectric. Forming the dielectric layer 720 may also include forming a plurality of cavities (e.g., 710) in the dielectric layer 720. The plurality of cavities may be formed using an etching process (e.g., photolithography) or a laser process. Fig. 7A Stages 2-3 of FIG. 1 illustrate and describe an example of forming a dielectric layer and forming a cavity in the dielectric layer.

[0128] The method forms (at 820) interconnects in and on the dielectric layer. For example, interconnect 712 may be formed in and on dielectric layer 720. A plating process may be used to form the interconnect. Forming the interconnect may include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnect may also include forming the interconnect in a cavity of the dielectric layer. Portions of the interconnect formed may have a U-shape or a V-shape. The terms "U-shape" and "V-shape" should be interchangeable. The terms "U-shape" and "V-shape" may refer to the side profile shape of an interconnect and / or a redistribution interconnect. A U-shaped interconnect (e.g., a U-shaped side profile interconnect) and a V-shaped interconnect (e.g., a V-shaped side profile interconnect) may have a top and a bottom. The bottom of a U-shaped interconnect (or a V-shaped interconnect) may be coupled to the top of another U-shaped interconnect (or a V-shaped interconnect). Fig. 7A Stage 4 of the present invention illustrates and describes an example of forming interconnects in and above a dielectric layer.

[0129] The method forms (at 825) a dielectric layer 722 over the dielectric layer 720 and the interconnect 712. The dielectric layer 722 may be formed using a deposition and / or lamination process. The dielectric layer 722 may include prepreg and / or polyimide. The dielectric layer 722 may include a photoimageable dielectric. Forming the dielectric layer 722 may also include forming a plurality of cavities (e.g., 730) in the dielectric layer 722. The plurality of cavities may be formed using an etching process (e.g., photolithography) or a laser process. Figure 7A-7B Stages 5-6 of illustrative examples of forming a dielectric layer and forming a cavity in the dielectric layer are illustrated and described.

[0130] The method forms (at 830) interconnects in and on the dielectric layer. For example, interconnect 714 may be formed in and on dielectric layer 722. A plating process may be used to form the interconnect. Forming the interconnect may include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnect may also include forming the interconnect in a cavity of the dielectric layer. Portions of the interconnect formed may have a U-shape or a V-shape. The terms "U-shape" and "V-shape" should be interchangeable. The terms "U-shape" and "V-shape" may refer to the side profile shape of an interconnect and / or a redistribution interconnect. A U-shaped interconnect (e.g., a U-shaped side profile interconnect) and a V-shaped interconnect (e.g., a V-shaped side profile interconnect) may have a top and a bottom. The bottom of a U-shaped interconnect (or a V-shaped interconnect) may be coupled to the top of another U-shaped interconnect (or a V-shaped interconnect). Figure 7B Stage 7 of illustrative embodiments illustrates and describes an example of forming interconnects in and over a dielectric layer.

[0131] The method decouples (at 835) the carrier (e.g., 700) from the seed layer (e.g., 701). The carrier 700 may be separated and / or ground away. The method may also remove (at 835) portions of the seed layer (e.g., 701). Portions of the seed layer 701 may be removed using an etching process. Figure 7B Stage 8 of the present invention illustrates and describes an example of decoupling the carrier and removing the seed layer.

[0132] Different implementations may use different processes to form the metal layer(s). In some implementations, the metal layer(s) may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spraying process, and / or a plating process.

[0133] Exemplary Electronic Devices

[0134] Fig. 9 Various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or systems-on-chip (SoC) are illustrated. For example, a mobile phone device 902, a laptop computer device 904, a fixed location terminal device 906, a wearable device 908, or a motor vehicle 910 may include a device 900 as described herein. The device 900 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Fig. 9The devices 902, 904, 906, and 908, and the vehicle 910 illustrated in the figure are merely exemplary. Other electronic devices can also feature the device 900, including, but not limited to, a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), devices enabled with a global positioning system (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0135] Figure 1-3 One or more of the components, processes, features, and / or functions illustrated in , 4A-4F, 5A-5F, 6, 7A-7B, and 8-9 may be rearranged and / or combined into a single component, process, feature, or function, or may be implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figure 1-3 , 4A-4F, 5A-5F, 6, 7A-7B, and 8-9 and their corresponding descriptions in this disclosure are not limited to die and / or IC. In some implementations, Figure 1-3 , 4A-4F, 5A-5F, 6, 7A-7B and / or 8-9 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink and / or an interposer.

[0136] Note that the drawings in this disclosure may represent actual representations and / or conceptual representations of various components, assemblies, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, for clarity, not all components and / or parts are shown. In some instances, the positioning, location, size, and / or shape of the various components and / or assemblies in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0137] The wording "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any implementation or aspect described herein as "exemplary" is not necessarily to be interpreted as superior or superior to other aspects of the present disclosure. Likewise, the term "aspect" does not require that all aspects of the present disclosure include the features, advantages, or modes of operation discussed. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered to be coupled to each other - even if they are not in direct physical contact with each other. Object A coupled to object B may be coupled to at least a portion of object B. The term "electrically coupled" may mean that two objects are coupled together directly or indirectly so that an electric current (e.g., signal, power, ground) can be transferred between the two objects. Two electrically coupled objects may or may not have an electric current transfer between the two objects. The use of the terms "first", "second", "third", and "fourth" (and / or anything higher than the fourth) is arbitrary. Any component described may be a first component, a second component, a third component, or a fourth component. For example, the component referred to as the second component may be the first component, the second component, the third component, or the fourth component. The terms "encapsulate", "encapsulate" and / or any derivatives thereof refer to an object that may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may be considered a bottom component, and vice versa. As described in the present disclosure, a first component located "above" a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of the second component, wherein the second surface is opposite to the first surface. Further note that the term "above" as used in the context of a component being located above another component in the present application may be used to indicate that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, a first component being above a second component may mean: (1) the first component is above the second component, but not directly contacting the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component that is "in" a second component may be partially in the second component or completely in the second component. A value of about X-XX may mean a value between X and XX (inclusive). The value(s) between X and XX may be discrete or continuous. As used in the present disclosure, the term "about 'value X'" or "approximately value X" means within ten percent of 'value X'.For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0138] In some implementations, interconnection is an element or component that allows or facilitates electrical connection between two points, elements and / or components in a device or package. In some implementations, interconnection may include traces (e.g., trace interconnection), through holes (e.g., through hole interconnection), pads (e.g., pad interconnection), solder pillars, metallization layers, redistribution layers, and / or under bump metallization (UBM) layers / interconnection. In some implementations, interconnection may include conductive materials that can be configured to provide electrical paths for signals (e.g., data signals), grounding and / or power. Interconnection may include more than one element or component. Interconnection may be defined by one or more interconnections. Interconnection may include one or more metal layers. Interconnection may be part of a circuit. Different implementations may use different processes and / or procedures to form interconnection. In some implementations, chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, sputtering processes, spraying, and / or electroplating processes may be used to form interconnection.

[0139] It should also be noted that the various disclosures contained herein may be described as processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although a flow chart may describe an operation as a sequential process, many operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process terminates when its operations are completed.

[0140] Further examples are described below to facilitate understanding of the present disclosure.

[0141] Aspect 1: A package comprises: a first integrated device; a first metallization portion, the first metallization portion is coupled to the first integrated device, wherein the first metallization portion comprises: at least one first dielectric layer; and a first plurality of metallization interconnects; a second integrated device; a second metallization portion, the second metallization portion is coupled to the second integrated device and the first metallization portion, wherein the second metallization portion comprises: at least one second dielectric layer; and a second plurality of metallization interconnects; and an encapsulation layer, the encapsulation layer is coupled to the first metallization portion, the second integrated device and the second metallization portion.

[0142] Aspect 2: A package as in Aspect 1, wherein the first metallization portion comprises a first redistribution portion, wherein the first plurality of metallization interconnects comprises a first plurality of redistribution interconnects, wherein the second metallization portion comprises a second redistribution portion, and wherein the second plurality of metallization interconnects comprises a second plurality of redistribution interconnects.

[0143] Aspect 3: The package of aspect 2, wherein a first portion of a first redistribution interconnect from the first plurality of redistribution interconnects comprises a side profile having a U-shape or a V-shape, and wherein a second portion of a second redistribution interconnect from the second plurality of redistribution interconnects comprises a side profile having a U-shape or a V-shape.

[0144] Aspect 4: The package of aspect 3, wherein a bottom of the first redistribution portion is directly coupled to a bottom of the second redistribution portion.

[0145] Aspect 5: The package of aspects 1 to 4, further comprising a first encapsulation layer coupled to the first integrated device, wherein the encapsulation layer is a second encapsulation layer coupled to the first encapsulation layer, and wherein the first integrated device is coupled to the first metallization portion through a plurality of solder interconnects.

[0146] Aspect 6: The package of aspects 1 to 5, further comprising a plurality of through-mold vias coupled to the second metallization, wherein the plurality of through-mold vias are located in the encapsulation layer.

[0147] Aspect 7: The package of aspects 1 to 6, further comprising a plurality of through-mold solder interconnects coupled to the second metallization, wherein the plurality of through-mold solder interconnects are located in the encapsulation layer.

[0148] Aspect 8: The package of Aspects 1 to 7, further comprising: a plurality of through-mold interconnects extending through the thickness of the encapsulation layer, wherein the plurality of through-mold interconnects are coupled to the second metallization portion; a plurality of interconnects coupled to the surface of the encapsulation layer; and a third integrated device coupled to the plurality of interconnects via a plurality of solder interconnects.

[0149] Aspect 9: A package as in Aspect 8, wherein the third integrated device is configured to be electrically coupled to the first integrated device via an electrical path comprising at least one solder interconnect from a plurality of solder interconnects, at least one interconnect from a plurality of interconnects, at least one interconnect from a plurality of through-mold interconnects, at least one metallized interconnect from a second plurality of metallized interconnects, and at least one metallized interconnect from a first plurality of metallized interconnects.

[0150] Aspect 10: A package as in Aspect 9, wherein the third integrated device is configured to be electrically coupled to the second integrated device via another electrical path, the other electrical path comprising at least one other solder interconnect from the plurality of solder interconnects, at least one other interconnect from the plurality of interconnects, at least one other interconnect from the plurality of through-mold interconnects, and at least one other metallization interconnect from the second plurality of metallization interconnects.

[0151] Aspect 11: The package of aspects 8 to 10, wherein the plurality of through-mold interconnects comprises a plurality of through-mold vias and / or a plurality of through-mold solder interconnects.

[0152] Aspect 12: A device comprising: a first package, the first package comprising: a first integrated device; and a first metallization portion, the first metallization portion coupled to the first integrated device, wherein the first metallization portion comprises: at least one first dielectric layer; and a first plurality of metallization interconnects; a second integrated device; a second metallization portion, the second metallization portion coupled to the second integrated device and the first metallization portion of the first package, wherein the second metallization portion comprises: at least one second dielectric layer; and a second plurality of metallization interconnects; and an encapsulation layer coupled to the first package, the second integrated device, and the second metallization portion.

[0153] Aspect 13: The apparatus of aspect 12, wherein the first metallization portion comprises a first redistribution portion, wherein the first plurality of metallization interconnects comprises a first plurality of redistribution interconnects, wherein the second metallization portion comprises a second redistribution portion, and wherein the second plurality of metallization interconnects comprises a second plurality of redistribution interconnects.

[0154] Aspect 14: The apparatus of aspects 12 to 13, wherein the first integrated device is coupled to the first metallization via a plurality of solder interconnects, wherein the first package comprises a first encapsulation layer, and wherein the encapsulation layer is a second encapsulation layer coupled to the first encapsulation layer.

[0155] Aspect 15: The apparatus of aspects 12 to 14, further comprising: a plurality of through-mold vias coupled to the second metallization, wherein the plurality of through-mold vias are located in the encapsulation layer.

[0156] Aspect 16: The apparatus of aspects 12 to 14, further comprising: a plurality of through-mold solder interconnects coupled to the second metallization, wherein the plurality of through-mold solder interconnects are located in the encapsulation layer.

[0157] Aspect 17: The apparatus of aspect 16, wherein the plurality of through-mold solder interconnects comprises a first plurality of through-mold solder interconnects and a second plurality of through-mold solder interconnects, and wherein the first plurality of through-mold solder interconnects is coupled to the second plurality of through-mold solder interconnects.

[0158] Aspect 18: The apparatus of aspect 17, wherein the first plurality of through-mold solder interconnects comprises a first width, and wherein the second plurality of through-mold solder interconnects comprises a second width.

[0159] Aspect 19: The apparatus of aspect 17, wherein a second plurality of through-mold solder interconnects are coupled to the second metallization.

[0160] Aspect 20: The device as in Aspects 16 to 19, further comprising: a plurality of interconnects coupled to a surface of the encapsulation layer, wherein the plurality of interconnects are coupled to a plurality of through-mold solder interconnects, and a solder resist layer formed on the surface of the encapsulation layer and on at least some of the interconnects from the plurality of interconnects.

[0161] Aspect 22: A method for manufacturing a package, comprising: providing a first package, the first package comprising: a first integrated device, and a first metallization portion, the first metallization portion coupled to the first integrated device, wherein the first metallization portion comprises: at least one first dielectric layer; and a first plurality of metallization interconnects; providing a second integrated device; forming an encapsulation layer over the first package and the second integrated device; and forming a second metallization portion over the second integrated device, the first metallization portion of the first package and the encapsulation layer, wherein the second metallization portion comprises: at least one second dielectric layer; and a second plurality of metallization interconnects.

[0162] Aspect 23: The method of aspect 22, wherein the first integrated device is coupled to the first metallization via a plurality of solder interconnects, wherein the first package includes a first encapsulation layer, and wherein the encapsulation layer is a second encapsulation layer coupled to the first encapsulation layer.

[0163] Aspect 24: The method of aspects 22 to 23, further comprising: forming a plurality of through-mold vias in the encapsulation layer, wherein the second metallization portion is coupled to the plurality of through-mold vias.

[0164] Aspect 25: The method of aspects 22 to 23, further comprising: forming a plurality of through-mold solder interconnects, wherein the second metallization portion is coupled to the plurality of through-mold solder interconnects, wherein the encapsulation layer is formed such that the encapsulation layer encapsulates the plurality of through-mold solder interconnects.

[0165] The various features of the present disclosure described herein may be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative rather than limiting the scope of the claims. Thus, the teachings of the present disclosure may be readily applied to other types of devices, and many replacements, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package comprising: a first integrated device; A first metallization portion, the first metallization portion is coupled to the first integrated device, wherein the first metallization portion comprises: at least one first dielectric layer; and a first plurality of metallization interconnects; a second integrated device; A second metallization portion, the second metallization portion is coupled to the second integrated device and the first metallization portion, wherein the second metallization portion comprises: at least one second dielectric layer; and a second plurality of metallization interconnects; and An encapsulation layer is coupled to the first metallization portion, the second integrated device, and the second metallization portion.

2. The package according to claim 1, wherein the first metallization portion comprises a first redistribution portion, wherein the first plurality of metallization interconnects comprises a first plurality of redistribution interconnects, wherein the second metallization portion comprises a second redistribution portion, and Wherein the second plurality of metallization interconnects comprises a second plurality of redistribution interconnects.

3. The package as claimed in claim 2, wherein a first portion of a first redistribution interconnect from the first plurality of redistribution interconnects comprises a side profile having a U-shape or a V-shape, and Wherein a second portion of a second redistribution interconnect from the second plurality of redistribution interconnects comprises a side profile having a U-shape or a V-shape. 4 . The package of claim 3 , wherein a bottom of the first redistribution portion is directly coupled to a bottom of the second redistribution portion.

5. The package of claim 1, further comprising: a first encapsulation layer, the first encapsulation layer being coupled to the first integrated device, wherein the encapsulation layer is a second encapsulation layer coupled to the first encapsulation layer, and The first integrated device is coupled to the first metallization portion via a plurality of solder interconnects.

6. The package of claim 1, further comprising: A plurality of through-mold vias are coupled to the second metallization, wherein the plurality of through-mold vias are located in the encapsulation layer.

7. The package of claim 1, further comprising: A plurality of through-mold solder interconnects are coupled to the second metallization, wherein the plurality of through-mold solder interconnects are located in the encapsulation layer.

8. The package of claim 1, further comprising: a plurality of through-die interconnects extending through a thickness of the encapsulation layer, wherein the plurality of through-die interconnects are coupled to the second metallization; a plurality of interconnects coupled to a surface of the encapsulation layer; as well as A third integrated device is coupled to the plurality of interconnects via a plurality of solder interconnects.

9. The package of claim 8, wherein the third integrated device is configured to be electrically coupled to the first integrated device via an electrical path comprising at least one solder interconnect from the plurality of solder interconnects, at least one interconnect from the plurality of interconnects, at least one interconnect from the plurality of through-mold interconnects, at least one metallization interconnect from the second plurality of metallization interconnects, and at least one metallization interconnect from the first plurality of metallization interconnects.

10. The package of claim 9, wherein the third integrated device is configured to be electrically coupled to the second integrated device via another electrical path, the other electrical path comprising at least one other solder interconnect from the plurality of solder interconnects, at least one other interconnect from the plurality of interconnects, at least one other interconnect from the plurality of through-mold interconnects, and at least one other metallization interconnect from the second plurality of metallization interconnects.

11. The package of claim 8, wherein the plurality of through-mold interconnects comprises a plurality of through-mold vias and / or a plurality of through-mold solder interconnects.

12. A device comprising: A first package, the first package comprising: a first integrated device, and A first metallization portion, the first metallization portion is coupled to the first integrated device, wherein the first metallization portion comprises: at least one first dielectric layer; and a first plurality of metallization interconnects; a second integrated device; A second metallization portion coupled to the second integrated device and the first metallization portion of the first package, wherein the second metallization portion comprises: at least one second dielectric layer; and a second plurality of metallization interconnects; and An encapsulation layer is coupled to the first package, the second integrated device, and the second metallization.

13. The device as claimed in claim 12, wherein the first metallization portion comprises a first redistribution portion, wherein the first plurality of metallization interconnects comprises a first plurality of redistribution interconnects, wherein the second metallization portion comprises a second redistribution portion, and Wherein the second plurality of metallization interconnects comprises a second plurality of redistribution interconnects.

14. The device according to claim 12, wherein the first integrated device is coupled to the first metallization portion via a plurality of solder interconnects, wherein the first package comprises a first encapsulation layer, and The encapsulation layer is a second encapsulation layer coupled to the first encapsulation layer.

15. The apparatus of claim 12, further comprising a plurality of through-mold vias coupled to the second metallization, wherein the plurality of through-mold vias are located in the encapsulation layer.

16. The apparatus of claim 12, further comprising a plurality of through-mold solder interconnects coupled to the second metallization, wherein the plurality of through-mold solder interconnects are located in the encapsulation layer.

17. The device according to claim 16, wherein the plurality of through-mold solder interconnects comprises a first plurality of through-mold solder interconnects and a second plurality of through-mold solder interconnects, and Wherein the first plurality of through-mold solder interconnects are coupled to the second plurality of through-mold solder interconnects.

18. The device according to claim 17, wherein the first plurality of through-mold solder interconnects comprises a first width, and Wherein the second plurality of through-mold solder interconnects comprises a second width.

19. The apparatus of claim 17, wherein the second plurality of through-mold solder interconnects are coupled to the second metallization.

20. The apparatus of claim 16, further comprising: a plurality of interconnects coupled to a surface of the encapsulation layer, wherein the plurality of interconnects are coupled to the plurality of through-mold solder interconnects; as well as A solder resist layer is formed over the surface of the encapsulation layer and over at least some of the interconnects from the plurality of interconnects.

21. The device of claim 12, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

22. A method for manufacturing a package, comprising: A first package is provided, the first package comprising: a first integrated device, and A first metallization portion, the first metallization portion is coupled to the first integrated device, wherein the first metallization portion comprises: at least one first dielectric layer; and a first plurality of metallization interconnects; providing a second integrated device; forming an encapsulation layer over the first package and the second integrated device; and forming a second metallization over the second integrated device, the first metallization of the first package, and the encapsulation layer, wherein the second metallization comprises: at least one second dielectric layer; and A second plurality of metallization interconnects.

23. The method of claim 22, wherein the first integrated device is coupled to the first metallization portion via a plurality of solder interconnects, wherein the first package comprises a first encapsulation layer, and The encapsulation layer is a second encapsulation layer coupled to the first encapsulation layer.

24. The method of claim 22, further comprising: A plurality of through-mold vias are formed in the encapsulation layer, wherein the second metallization is coupled to the plurality of through-mold vias.

25. The method of claim 22, further comprising: A plurality of through-mold solder interconnects are formed, wherein the second metallization is coupled to the plurality of through-mold solder interconnects, wherein the encapsulation layer is formed such that the encapsulation layer encapsulates the plurality of through-mold solder interconnects.

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