Surface processing method for irregular large-size cadmium zinc telluride substrate slice

Abstract

The invention discloses a surface processing method of an irregular large-size tellurium-zinc-cadmium substrate slice. The surface processing method comprises the following steps: S1, cleaning an irregular large-size tellurium-zinc-cadmium wafer with an A surface and a B surface; s2, using a sapphire wafer as a substrate; s3, waxing and pasting are carried out, so that the tellurium-zinc-cadmium wafer and the sapphire wafer are attached and fixedly bonded together; s4, single-side thinning is conducted through a thinning machine, specifically, S41, the tellurium-zinc-cadmium wafer and the sapphire wafer which are attached, bonded and fixed together are placed on a workbench of the thinning machine, the inclination angle of the end face of a grinding wheel relative to the workbench is 0.0057 degrees, and S42, multi-step machining is conducted through the grinding wheel; s5, CMP polishing is conducted through a single polishing machine; s6, waxing: taking down the tellurium-zinc-cadmium wafer and the sapphire wafer from the single polishing machine, and removing white paraffin between the A surface of the tellurium-zinc-cadmium wafer and the sapphire wafer; and S7, the step S1 to the step S6 are repeated, surface processing is conducted on the A face of the tellurium-zinc-cadmium wafer, and finally the tellurium-zinc-cadmium wafer with TTV smaller than or equal to 2 micrometers and Ra smaller than or equal to 1 nm is obtained.

Description

Technical Field

[0001] The present disclosure relates to the field of cadmium zinc telluride materials, and more specifically to a surface processing method for an irregular large-sized cadmium zinc telluride substrate sheet. Background Art

[0002] Cadmium zinc telluride substrate is made of cadmium zinc telluride (Cd 1-x Zn x Te, x = 0.04, CZT) crystal as the material. Its excellent photoelectric performance can be used at room temperature, and its application areas are mainly concentrated in infrared detectors and high-energy detectors. As a substrate material, its surface quality requirements are very high, generally the surface roughness is required to be less than 1nm, the surface flatness TTV is less than 3μm, and Ra≤1nm.

[0003] Cadmium zinc telluride materials are brittle and have low hardness. Cadmium zinc telluride single crystal materials are mostly irregular wafers due to the large randomness of grain growth control. In the process of making substrate wafers, the surface needs to be polished. To achieve substrate wafers with high-quality surface requirements, multiple polishing is usually performed.

[0004] In traditional processing technology, the crystal needs to be sliced, and then the wafer is ground. After grinding, the first polishing is performed to remove the damaged layer of the ground surface, and then the second polishing is performed to trim the surface roughness. Double-sided polishing cannot solve the polishing problem of irregular wafers. Using a single-polishing machine polishing process, due to the rotation of the polishing disk and the polishing head, the linear speed of the wafer surface decreases from the edge to the center point, and the material removal rate of the wafer surface is the same. In this case, the wafer surface forms a convex state with low edges and high middles, which forms a common collapsed edge state. During long-term polishing, the edge is also prone to collapse.

[0005] The existing processing technologies have solutions to solve the polishing edge chipping, TTV difference and edge collapse when polishing large-sized irregular CdZnTe substrates, but there is no processing solution that can effectively solve the three problems at the same time.

[0006] With the development of CdZnTe crystal growth technology, the demand for CdZnTe substrate arrays is increasing. However, the surface protrusions and edge collapse caused by traditional polishing seriously affect the utilization rate of substrates, which also leads to rising costs. Therefore, it is necessary to improve the processing technology for irregular large-sized substrates. Summary of the invention

[0007] In view of the problems existing in the background technology, an object of the present disclosure is to provide a surface processing method for an irregular large-sized CdZnTe substrate sheet, which can simultaneously solve the problems of edge chipping, TTV and edge collapse.

[0008] Thus, a surface processing method for an irregular large-sized CdZnTe substrate comprises the following steps: S1, wafer cleaning: cleaning the irregular large-sized CdZnTe wafer with the AB surface distinguished; S2, providing a substrate: using a sapphire wafer as a substrate, the size of the sapphire wafer being such that the surface profile of the sapphire wafer covers the CdZnTe wafer, and the surface TTV of the sapphire wafer is ≤1μm; S3, waxing the wafer, comprising the following sub-steps: S31, applying white paraffin wax on the surface of the sapphire wafer on a waxing machine. , S32, making the A surface of the CdZnTe wafer and the sapphire wafer aligned and bonded together, S33, pressurized cooling, by pressurized cooling, the CdZnTe wafer and the sapphire wafer are bonded and fixed together; S4, single-sided thinning by a thinning machine, including sub-steps: S41, placing the CdZnTe wafer and the sapphire wafer bonded and fixed together on the workbench of the thinning machine, the end face of the grinding wheel relative to the workbench is 0.0057°, and in the direction relative to the workbench, the projection of the end face of the grinding wheel is The shadow covers the rotation center of the workbench. S42, grinding the B surface of the CdZnTe wafer with a grinding wheel. The grinding wheel processing adopts multi-step processing. The B surface TTV of the CdZnTe wafer after processing is 1-3μm, concave from the edge to the center point, and the surface roughness is ≤10nm; S5, single-polishing machine CMP polishing, including sub-steps: S51, installing the single-sided thinned CdZnTe wafer and the sapphire wafer on the pressure head, S52, installing the pressure head on the single-polishing machine, passing the polishing pad on the polishing disk and on the polishing Polishing liquid is sprayed between the light pad and the pressure head for polishing, S53, the surface roughness of the B surface of the CdZnTe wafer after polishing is Ra<1nm, and the TTV is 0-1μm; S6, wax removal: the CdZnTe wafer and the sapphire wafer are taken out from the single polishing machine, and the white paraffin between the A surface of the CdZnTe wafer and the sapphire wafer is removed; S7, steps S1 to S6 are repeated to perform surface processing on the A surface of the CdZnTe wafer, and finally the CdZnTe wafer is obtained with TTV≤2μm and Ra≤1nm.

[0009] The beneficial effects of the present disclosure are as follows: in the surface processing method of the irregular large-size CdZnTe substrate sheet according to the present disclosure, in the single-sided thinning of the thinning machine in step S4, the inclination angle of the end face of the grinding wheel relative to the worktable is 0.0057° through the sub-step S4, and the projection of the end face of the grinding wheel in the direction relative to the worktable covers the rotation center of the worktable. After the multi-step processing of the grinding wheel in sub-step S42, the B surface of the processed CdZnTe wafer is concave from the edge to the center point, thereby avoiding the convex (collapsed edge) state of low edge and high middle in the background technology, thereby avoiding edge collapse; on the basis of step S4, single-polishing machine CMP polishing is further performed in step S5 to achieve the surface roughness Ra<1nm and TTV of 0-1μm on the B surface; by repeating steps S1 to S6 in step S7, the CdZnTe wafer is finally obtained with TTV≤2μm, Ra≤1nm, and no edge collapse or collapsed edge. That is to say, the surface processing method of the irregular large-size CdZnTe substrate sheet disclosed in the present invention can solve the problems of edge chipping, TTV and edge collapse at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic flow chart of a surface processing method of an irregular large-size cadmium zinc telluride substrate sheet according to the present disclosure.

[0011] Figure 2 It is a schematic diagram of waxing patch.

[0012] Figure 3 It is a schematic diagram of single-sided thinning by a thinning machine.

[0013] Figure 4 It is the projection of the grinding wheel and workbench in the up and down directions.

[0014] Figure 5 It is a schematic diagram of CMP polishing by a single polishing machine.

[0015] The description of the accompanying drawings is as follows.

[0016] 100 CdZnTe wafer 22 grinding wheel

[0017] 200 sapphire wafer 221 end face

[0018] 300 White Paraffin 23 Thinning Machine Suction Cup

[0019] 1 waxing machine 3 single polishing machine

[0020] 11 heating table 31 pressure head

[0021] 12 pressure plates 32 polishing discs

[0022] 2 Thinning machine 33 Polishing pad

[0023] 21 workbench 34 single polishing machine suction cup

[0024] 211 rotating center 35 polishing liquid injection tube DETAILED DESCRIPTION

[0025] The accompanying drawings show embodiments of the present disclosure, and it will be understood that the disclosed embodiments are merely examples of the present disclosure, and the present disclosure can be implemented in various forms. Therefore, the specific details disclosed herein should not be interpreted as limiting, but merely as the basis for the claims and as a representative basis for teaching ordinary technicians in the field to implement the present disclosure in various ways.

[0026] [Surface processing method of irregular large-size cadmium zinc telluride substrate]

[0027] Reference Figures 1 to 5 According to the present disclosure, the surface processing method of the irregular large-size CdZnTe substrate sheet comprises the following steps:

[0028] S1, wafer cleaning: cleaning the irregular large-sized CdZnTe wafer 100 with the AB surface clearly distinguished;

[0029] S2, providing a substrate: using a sapphire wafer 200 as a substrate, the size of the sapphire wafer 200 is such that the surface profile of the sapphire wafer 200 covers the CdZnTe wafer 100, and the surface TTV of the sapphire wafer 200 is ≤1 μm;

[0030] S3, waxing the patch, including sub-steps:

[0031] S31, applying white paraffin wax 300 on the surface of the sapphire wafer 200 in the waxing machine 1;

[0032] S32, aligning the A surface of the CdZnTe wafer 100 and the sapphire wafer 200;

[0033] S33, pressurized cooling, through which the CdZnTe wafer 100 and the sapphire wafer 200 are bonded and fixed together;

[0034] S4, thinning machine single-sided thinning, including sub-steps:

[0035] S41, placing the CdZnTe wafer 100 and the sapphire wafer 200 bonded and fixed together on the workbench 21 of the thinning machine 2, the end face 221 of the grinding wheel 22 has an inclination angle of 0.0057° relative to the workbench 21, and in the direction relative to the workbench 21, the projection of the end face 221 of the grinding wheel 22 covers the rotation center 211 of the workbench 21;

[0036] S42, grinding the B surface of the CdZnTe wafer 100 using the grinding wheel 22, wherein the grinding wheel 22 is processed in multiple steps, and the B surface of the CdZnTe wafer 100 after processing has a TTV of 1-3 μm, is concave from the edge to the center, and has a surface roughness of ≤10 nm;

[0037] S5, single polishing machine CMP polishing, including sub-steps:

[0038] S51, mounting the single-sided thinned CdZnTe wafer 100 and the sapphire wafer 200 onto the pressing head 31;

[0039] S52, installing the press head 31 on the single polishing machine 3, and polishing by spraying polishing liquid between the polishing pad 33 and the press head 31 through the polishing pad 33 on the polishing plate 32;

[0040] S53, the surface roughness Ra of the B surface of the polished CdZnTe wafer 100 is less than 1 nm, and the TTV is 0-1 μm;

[0041] S6, wax removal: remove the CdZnTe wafer 100 and the sapphire wafer 200 from the single polishing machine 3, and remove the white wax 300 between the A surface of the CdZnTe wafer 100 and the sapphire wafer 200;

[0042] S7 , repeating steps S1 to S6 , performing surface processing on the A surface of the CdZnTe wafer 100 , and finally obtaining the CdZnTe wafer 100 with TTV≤2μm and Ra≤1nm.

[0043] In the surface processing method of the irregular large-size CdZnTe substrate according to the present disclosure, in the single-sided thinning of the thinning machine in step S4, the inclination angle of the end face 221 of the grinding wheel 22 relative to the worktable 21 is 0.0057°, and the projection of the end face 221 of the grinding wheel 22 in the direction relative to the worktable 21 covers the rotation center 211 of the worktable 21. After the multi-step processing of the grinding wheel 22 in sub-step S42, the processed CdZnTe wafer 100 The B surface is concave from the edge to the center point, thus avoiding the convex (collapsed edge) state of low edge and high middle in the background technology, thereby avoiding edge collapse; on the basis of step S4, further single polishing machine CMP polishing of step S5 is performed to achieve the surface roughness Ra<1nm and TTV of 0-1μm of the B surface; through step S7, repeating steps S1 to S6, finally obtaining a CdZnTe wafer 100 with TTV≤2μm, Ra≤1nm, and no edge collapse or edge collapse. That is to say, the surface processing method of irregular large-size CdZnTe substrate according to the present disclosure can solve the three problems of edge collapse, TTV and edge collapse at the same time.

[0044] In step S1, for example, alcohol is used for cleaning.

[0045] In step S2, for example, the sapphire wafer 200 has a diameter of 5 inches and a thickness of 2 mm.

[0046] In one example, sub-step S31 is: placing the sapphire wafer 200 on the heating table 11 of the waxing machine 1, heating the heating table 11 to 55-60°C, placing white paraffin 300 on the surface of the sapphire wafer 200, and waiting for the white paraffin 300 to melt, and then placing the prepared CdZnTe wafer 100 on the sapphire wafer 200. In one example, the centering in sub-step S32 is performed by aligning the cross coordinates of the center of the circle on the surface of the sapphire wafer 200 in step S2 by a laser marking machine and the coordinates of the cross marks on the A and B surfaces after cleaning with a marker pen in step S1. In one example, the operation in sub-step S33 is: start the pressing plate 12 of the waxing machine 1, squeeze out the excess white paraffin 300 between the sapphire wafer 200 and the cadmium zinc telluride wafer 100, the pressing pressure of the pressing plate 12 is 20N, the pressing time of the pressing plate 12 is 3-5min, and the heating table 11 of the waxing machine 1 is cooled naturally after the pressing. Further, after cooling, the sapphire wafer 200 and the cadmium zinc telluride wafer 100 that are bonded and fixed together are taken out, and the overall TTV of the two is measured to be ≤2μm.

[0047] In one example, in sub-step S41, the CdZnTe wafer 100 and the sapphire wafer 200 that are bonded and fixed together are placed on the thinning machine suction cup 23 of the workbench 21 of the thinning machine 2. The thinning machine suction cup 23 and the sapphire wafer 200 have the same diameter, and the thinning machine suction cup 23 sucks and fixes the sapphire wafer 200. For example, the grinding wheel 22 is a 4000 mesh silicon carbide grinding wheel. Figure 2 As shown, in one example, in sub-step S41, the projected profile of the end face 221 of the grinding wheel 22 exceeds the rotation center 211 of the workbench 21 by 1-2 μm. In one example, in sub-step S42, the wheel speed of the grinding wheel 22 is 2000 r / min, the speed of the workbench 21 is 100 r / min, and the grinding wheel 22 is processed in three steps. In the first step, the processing amount is 20 μm, the processing speed is 0.5 μm / s, and the surface protrusions are removed first; in the second step, the processing amount is 50 μm, the processing speed is 0.5 μm / s, and the damaged layer is removed; in the third step, the processing amount is 10 μm, the processing speed is 0.3 μm / s, and the surface roughness is trimmed.

[0048] In one example, in sub-step S51, the pressure of the pressure head 31 is 45-65N. For example, in sub-step S52, the polishing pad 33 is a damping cloth, and the polishing liquid is sodium dichloroisocyanurate: sodium bicarbonate: sodium benzenesulfonate: anhydrous sodium sulfate: nano silicon oxide with a particle size of 60-80nm: water, which is mixed and prepared by mass 10:2:1:10:0.08:1000. In one example, in sub-step S52, the rotation speed of the pressure head 31 is 50r / min, the rotation speed of the polishing disc 32 is 150r / min, the flow rate of the polishing liquid is 300-500mL / min, the polishing time is 3-5min, and the removal amount is 3-4μm.

[0049] In one example, step S6 is: remove the CdZnTe wafer 100 and the sapphire wafer 200 from the single polishing machine 3, use a heating furnace (not shown) to melt the white wax 300 between the CdZnTe wafer 100 and the sapphire wafer 200, remove the CdZnTe wafer 100 from the sapphire wafer 200, put the CdZnTe wafer 100 into a container (not shown) containing a wax remover, and clean the white wax 300. For example, the wax remover is orange juice.

[0050] [test]

[0051] Example 1

[0052] The surface processing method of the irregular large-size CdZnTe substrate sheet of Example 1 adopts the steps (also refer to Figures 2 to 5 ):

[0053] S1, wafer cleaning: clean the irregular large-sized CdZnTe wafer 100 with the A and B surfaces clearly distinguished, and after cleaning, use a marker to draw coordinates on the A and B surfaces in a cross, wherein alcohol is used for cleaning;

[0054] S2, providing a substrate: using a sapphire wafer 200 with a diameter of 5 inches and a thickness of 2 mm as the substrate, the size of the sapphire wafer 200 is such that the surface profile of the sapphire wafer 200 covers the CdZnTe wafer 100, the surface TTV of the sapphire wafer 200 is 1 μm, and the center of the surface of the sapphire wafer 200 is laser-marked with a cross coordinate by a laser marking machine;

[0055] S3, waxing the patch, uses the following sub-steps:

[0056] S31, placing the sapphire wafer 200 on the heating platform 11 of the waxing machine 1, and heating the platform

[0057] 11 Heat to 55° C. and place white paraffin 300 on the surface of the sapphire wafer 200;

[0058] S32, wait for the white paraffin 300 to melt, and then place the prepared CdZnTe wafer 100 on the sapphire wafer 200, so that the A surface of the CdZnTe wafer 100 is aligned with the sapphire wafer 200, wherein the alignment is performed by aligning the cross coordinates marked by a laser marker on the center of the surface of the sapphire wafer 200 in step S2 with the coordinates marked on the cross mark on the A surface and the B surface after cleaning in step S1 using a marker pen;

[0059] S33, pressurized cooling, start the pressing plate 12 of the waxing machine 1, squeeze out the excess white paraffin 300 between the sapphire wafer 200 and the cadmium zinc telluride wafer 100, the pressing pressure of the pressing plate 12 is 20N, the pressing time of the pressing plate 12 is 4 minutes, and the heating stage of the waxing machine 1 is turned on after pressurization.

[0060] 11. Natural cooling. The CdZnTe wafer 100 and the sapphire wafer 200 are bonded and fixed together by pressurized cooling. After cooling, the bonded and fixed sapphire wafer 200 and the CdZnTe wafer 100 are taken out and the overall TTV of the two is measured to be 2 μm.

[0061] S4, thinning machine single-sided thinning, using the following sub-steps:

[0062] S41, placing the CdZnTe wafer 100 and the sapphire wafer 200 bonded and fixed together on the thinning machine suction cup 23 of the workbench 21 of the thinning machine 2, the thinning machine suction cup 23 and the sapphire wafer 200 have the same diameter, the thinning machine suction cup 23 adsorbs and fixes the sapphire wafer 200, the inclination angle of the end face 221 of the grinding wheel 22 relative to the workbench 21 is 0.0057°, the grinding wheel 22 is a 4000 mesh silicon carbide grinding wheel, in the direction relative to the grinding wheel 22 and the workbench 21 (i.e., the vertical direction), the projection of the end face 221 of the grinding wheel 22 covers the rotation center 211 of the workbench 21, and the contour of the projection of the end face 221 of the grinding wheel 22 exceeds the rotation center 21 of the workbench 21

[0063] The rotation center 211 is 1.5 μm;

[0064] S42, grinding the B surface of the CdZnTe wafer 100 with the grinding wheel 22, the wheel speed of the grinding wheel 22 is 2000r / min, the speed of the workbench 21 is 100r / min, the grinding wheel 22 is processed in three steps, the first step, the processing amount is 20μm, the processing speed is 0.5μm / s, the surface protrusions are removed first; the second step, the processing amount is 50μm, the processing speed is 0.5μm / s, the damaged layer is removed; the third step, the processing amount is 10μm, the processing speed is 0.3um / s, the surface roughness is trimmed; the TTV of the B surface of the CdZnTe wafer 100 after processing is 1.5μm, concave from the edge to the center, and the surface roughness is 10nm;

[0065] S5, single polishing machine CMP polishing, using the following sub-steps:

[0066] S51, mounting the single-sided thinned CdZnTe wafer 100 and the sapphire wafer 200 on the single-polishing machine suction cup 34 of the pressing head 31, and the single-polishing machine suction cup 34 adsorbs and fixes the CdZnTe wafer 100 and the sapphire wafer 200;

[0067] S52, install the pressure head 31 on the single polishing machine 3, the pressure of the pressure head 31 is 55N, and polishing is performed by spraying the polishing liquid between the polishing pad 33 and the pressure head 31 through the polishing pad 33 on the polishing disk 32, wherein the polishing pad 33 is a damping cloth, and the polishing liquid is a mixture of sodium dichloroisocyanurate: sodium bicarbonate: sodium benzenesulfonate: anhydrous sodium sulfate: nano silicon oxide with a particle size of 70nm: water in a mass ratio of 10:2:1:10:0.08:1000, the rotation speed of the pressure head 31 is 50r / min, the rotation speed of the polishing disk 32 is 150r / min, the flow rate of the polishing liquid in the polishing liquid spray pipe 35 is 400mL / min, the polishing time is 4min, and the removal amount is 3.5μm;

[0068] S53, the surface roughness of the B surface of the polished CdZnTe wafer 100 is Ra=0.6 nm, and the TTV is 1.0 μm;

[0069] S6, wax removal: remove the CdZnTe wafer 100 and the sapphire wafer 200 from the single polishing machine 3, use a heating furnace to melt the white wax 300 between the CdZnTe wafer 100 and the sapphire wafer 200, remove the CdZnTe wafer 100 from the sapphire wafer 200, put the CdZnTe wafer 100 into a container containing a wax remover, and remove the white wax 300 between the A surface of the CdZnTe wafer 100 and the sapphire wafer 200, wherein the wax remover is orange juice;

[0070] S7 , repeating steps S1 to S6 , performing surface processing on the A surface of the CdZnTe wafer 100 , and finally obtaining the CdZnTe wafer 100 with TTV≤2μm and Ra≤1nm.

[0071] The above detailed description is used to describe multiple exemplary embodiments, but this document is not intended to be limited to the explicitly disclosed combinations. Therefore, unless otherwise stated, the various features disclosed herein can be combined together to form multiple additional combinations that are not shown for the sake of simplicity.

Claims

1. A surface processing method for an irregular large-size cadmium zinc telluride substrate sheet, characterized in that: Includes steps: S1, wafer cleaning: cleaning an irregular large-sized CdZnTe wafer (100) with distinct AB surfaces; S2, providing a substrate: using a sapphire wafer (200) as a substrate, the size of the sapphire wafer (200) being such that the surface profile of the sapphire wafer (200) covers the cadmium zinc telluride wafer (100), and the surface TTV of the sapphire wafer (200) is ≤1 μm; S3, waxing the patch, including sub-steps: S31, applying white paraffin wax (300) on the surface of the sapphire wafer (200) in a waxing machine (1); S32, aligning the A surface of the cadmium zinc telluride wafer (100) with the sapphire wafer (200); S33, pressurized cooling, wherein the cadmium zinc telluride wafer (100) and the sapphire wafer (200) are bonded and fixed together by pressurized cooling; S4, thinning machine single-sided thinning, including sub-steps: S41, placing the cadmium zinc telluride wafer (100) and the sapphire wafer (200) bonded and fixed together on the workbench (21) of the thinning machine (2), the inclination angle of the end face (221) of the grinding wheel (22) relative to the workbench (21) is 0.0057°, and in the direction relative to the workbench (21), the projection of the end face (221) of the grinding wheel (22) covers the rotation center (211) of the workbench (21); S42, grinding the B surface of the cadmium zinc telluride wafer (100) using a grinding wheel (22), wherein the grinding wheel (22) is processed in multiple steps, and the B surface of the cadmium zinc telluride wafer (100) after processing has a TTV of 1-3 μm, is concave from the edge to the center, and has a surface roughness of ≤10 nm; S5, single polishing machine CMP polishing, including sub-steps: S51, installing a single-sided thinned cadmium zinc telluride wafer (100) and a sapphire wafer (200) onto a pressing head (31); S52, installing the pressure head (31) on the single polishing machine (3), and polishing by passing the polishing pad (33) on the polishing plate (32) and spraying the polishing liquid between the polishing pad (33) and the pressure head (31); S53, the surface roughness of the B surface of the polished CdZnTe wafer (100) is Ra<1nm, and the TTV is 0-1μm; S6, wax removal: remove the CdZnTe wafer (100) and the sapphire wafer (200) from the single polishing machine (3), and remove the white wax (300) between the A surface of the CdZnTe wafer (100) and the sapphire wafer (200); S7, repeating steps S1 to S6, performing surface processing on the A surface of the CdZnTe wafer (100), and finally obtaining a CdZnTe wafer (100) with TTV≤2μm and Ra≤1nm.

2. The surface processing method of the irregular large-size CdZnTe substrate sheet according to claim 1, characterized in that: In step S1, the cleaning is done by wiping with alcohol.

3. The surface processing method of the irregular large-size CdZnTe substrate sheet according to claim 1, characterized in that: In step S2, the sapphire wafer (200) has a diameter of 5 inches and a thickness of 2 mm.

4. The surface processing method of the irregular large-size CdZnTe substrate sheet according to claim 1, characterized in that: Sub-step S31 is: placing the sapphire wafer (200) on the heating platform (11) of the waxing machine (1), heating the heating platform (11) to 55-60° C., placing white paraffin (300) on the surface of the sapphire wafer (200), waiting for the white paraffin (300) to melt, and then placing the prepared cadmium zinc telluride wafer (100) on the sapphire wafer (200); and / or The centering in sub-step S32 is performed by aligning the cross coordinates marked by a laser marker on the center of the surface of the sapphire wafer (200) in step S2 with the coordinates marked on the cross marks on the A and B surfaces after cleaning in step S1 using a marker pen; and / or The operation in sub-step S33 is: starting the pressing plate (12) of the waxing machine (1) to squeeze out the excess white paraffin (300) between the sapphire wafer (200) and the cadmium zinc telluride wafer (100), the pressing pressure of the pressing plate (12) is 20N, the pressing time of the pressing plate (12) is 3-5 minutes, and after the pressing, the heating table (11) of the waxing machine (1) is cooled naturally; and / or After cooling, the sapphire wafer (200) and the cadmium zinc telluride wafer (100) that are bonded and fixed together are taken out, and the overall TTV of the two is measured to be ≤2 μm.

5. The surface processing method of the irregular large-size CdZnTe substrate sheet according to claim 1, characterized in that: In sub-step S41, the cadmium zinc telluride wafer (100) and the sapphire wafer (200) bonded and fixed together are placed on a thinning machine suction cup (23) on a working table (21) of a thinning machine (2). The thinning machine suction cup (23) and the sapphire wafer (200) have the same diameter, and the thinning machine suction cup (23) adsorbs and fixes the sapphire wafer (200).

6. The surface processing method of the irregular large-size CdZnTe substrate sheet according to claim 1, characterized in that: In sub-step S41, the projected profile of the end surface (221) of the grinding wheel (22) exceeds the rotation center (211) of the workbench (21) by 1-2 μm.

7. The surface processing method of the irregular large-size CdZnTe substrate sheet according to claim 6, characterized in that: In sub-step S41, the grinding wheel (22) is a 4000-mesh silicon carbide grinding wheel.

8. The surface processing method of the irregular large-size CdZnTe substrate sheet according to claim 7, characterized in that: In sub-step S42, the rotation speed of the grinding wheel (22) is 2000 r / min, and the rotation speed of the workbench (21) is 100 r / min. The grinding wheel (22) is processed in three steps. In the first step, the processing volume is 20μm and the processing speed is 0.5μm / s to remove the raised parts of the surface first; In the second step, the processing volume is 50 μm and the processing speed is 0.5 μm / s to remove the damaged layer; The third step is to trim the surface roughness with a processing volume of 10μm and a processing speed of 0.3um / s.

9. The surface processing method of the irregular large-size CdZnTe substrate sheet according to claim 1, characterized in that: In sub-step S52, the pressure of the pressure head (31) is 45-65N; and / or In sub-step S52, the polishing pad (33) is a damping cloth, and the polishing liquid is a mixture of sodium dichloroisocyanurate: sodium bicarbonate: sodium benzenesulfonate: anhydrous sodium sulfate: nano silicon oxide with a particle size of 60-80 nm: water in a mass ratio of 10:2:1:10:0.08:1000; and / or In sub-step S52, the rotation speed of the pressure head (31) is 50 r / min, the rotation speed of the polishing disc (32) is 150 r / min, the flow rate of the polishing liquid is 300-500 mL / min, the polishing time is 3-5 min, and the removal amount is 3-4 μm.

10. The surface processing method of the irregular large-size CdZnTe substrate sheet according to claim 1, characterized in that: Step S6 comprises: removing the CdZnTe wafer (100) and the sapphire wafer (200) from the single polishing machine (3), using a heating furnace to melt the white wax (300) between the CdZnTe wafer (100) and the sapphire wafer (200), removing the CdZnTe wafer (100) from the sapphire wafer (200), placing the CdZnTe wafer (100) in a container containing a wax remover, and cleaning the white wax (300); and / or The wax remover is orange juice.

Images