Data generation for task execution by robotic device

Abstract

The invention discloses data generation for task execution of a robotic device. Devices, systems, and techniques for generating data to train a robotic device to execute a task are disclosed. In at least one embodiment, one or more first videos for a robotic device to perform a task are used to generate one or more second videos for the robotic device to perform the task in a different manner than depicted in the one or more first videos.

Description

Technical Field

[0001] At least one embodiment involves processing resources to generate data for training a robot using information from one or more demonstrations of a robot performing a first task, and modifying the one or more demonstrations to generate additional demonstrations for training the robot to perform a second task. For example, the processor includes one or more circuits to use one or more first videos of a robotic apparatus performing a task to generate one or more second videos of the robotic apparatus performing the task in a manner different from that depicted in the one or more first videos. Background Art

[0002] Without sufficient training data, training a robotic device to perform a task can be ineffective. For example, in order for a robot to perform a task, sufficient training data is required to help improve the robot's accuracy. A lack of available training data can lead to poor performance. Collecting sufficient training data covering different tasks is often expensive, time-consuming, and sometimes impractical, as the objects and environments associated with each task may vary. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Various embodiments according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0004] Figure 1 An example system for generating videos to train a robot according to at least one embodiment is shown;

[0005] Figure 2 An example system using one or more presentations and dividing each presentation into one or more subtasks is shown in accordance with at least one embodiment;

[0006] Figure 3 An example system for generating new trajectories for new videos used to train a robot is shown in accordance with at least one embodiment;

[0007] Figure 4 An example process for modifying a demonstration to generate a new demonstration for training a robot in accordance with at least one embodiment is shown;

[0008] Figure 5 An example process for generating demonstrations based on successful simulated demonstrations to train a robot is shown in accordance with at least one embodiment;

[0009] Figure 6 shows examples of processors and modules according to at least one embodiment;

[0010] Figure 7is a block diagram illustrating a driver and / or runtime including one or more libraries to provide one or more application programming interfaces (APIs) according to at least one embodiment;

[0011] Figure 8A illustrates logic according to at least one embodiment;

[0012] Figure 8B illustrates logic according to at least one embodiment;

[0013] Figure 9 illustrates the training and deployment of a neural network according to at least one embodiment;

[0014] Figure 10 An example data center system is shown in accordance with at least one embodiment;

[0015] Figure 11A An example of an autonomous vehicle according to at least one embodiment is shown;

[0016] Figure 11B According to at least one embodiment, Figure 11A Examples of camera positions and fields of view for autonomous vehicles;

[0017] Figure 11C According to at least one embodiment Figure 11A A block diagram of an example system architecture for an autonomous vehicle;

[0018] Figure 11D is a diagram illustrating a method for one or more cloud-based servers and Figure 11A A diagram of a system for communicating between autonomous vehicles;

[0019] Figure 12 is a block diagram illustrating a computer system according to at least one embodiment;

[0020] Figure 13 is a block diagram illustrating a computer system according to at least one embodiment;

[0021] Figure 14 A computer system according to at least one embodiment is shown;

[0022] Figure 15 A computer system according to at least one embodiment is shown;

[0023] Figure 16A A computer system according to at least one embodiment is shown;

[0024] Figure 16B A computer system according to at least one embodiment is shown;

[0025] Figure 16C A computer system according to at least one embodiment is shown;

[0026] Figure 16D A computer system according to at least one embodiment is shown;

[0027] Figure 16E and Figure 16F illustrates a shared programming model according to at least one embodiment;

[0028] Figure 17 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0029] Figures 18A-18B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0030] Figures 19A-19B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0031] Figure 20 A computer system according to at least one embodiment is shown;

[0032] Figure 21A A parallel processor according to at least one embodiment is shown;

[0033] Figure 21B shows a partition unit according to at least one embodiment;

[0034] Figure 21C illustrates a processing cluster according to at least one embodiment;

[0035] Figure 21D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0036] Figure 22 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0037] Figure 23 A graphics processor according to at least one embodiment is shown;

[0038] Figure 24 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0039] Figure 25 A deep learning application processor according to at least one embodiment is shown;

[0040] Figure 26 is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

[0041] Figure 27 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0042] Figure 28 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0043] Figure 29 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0044] Figure 30 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0045] Figure 31 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0046] Figure 32A-Figure 32B Thread execution logic is shown that includes an array of processing elements of a graphics processor core, in accordance with at least one embodiment.

[0047] Figure 33 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0048] Figure 34 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0049] Figure 35 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0050] Figure 36 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0051] Figure 37 is an example data flow diagram of a high-level computing pipeline according to at least one embodiment;

[0052] Figure 38 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline in accordance with at least one embodiment;

[0053] Figure 39 includes an example illustration of a high-level computational pipeline for processing imaging data in accordance with at least one embodiment;

[0054] Figure 40A including an example data flow diagram of a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0055] Figure 40BAn example data flow diagram including a virtual instrument supporting a CT scanner according to at least one embodiment;

[0056] Figure 41A A data flow diagram illustrating a process for training a machine learning model according to at least one embodiment; and

[0057] Figure 41B is an example illustration of a client-server architecture for enhancing an annotation tool using a pre-trained annotation model, according to at least one embodiment. DETAILED DESCRIPTION

[0058] In at least one embodiment, systems and methods implemented in accordance with the present disclosure are used to use one or more first videos of a robotic apparatus performing a task to generate one or more second videos of the robotic apparatus performing the task in a manner different from that depicted in the one or more first videos to control the robot and / or otherwise perform the operations discussed herein.

[0059] In at least one embodiment, a system including software executed by one or more processors (such as the following) Figure 1 In at least one embodiment, the system generates videos (e.g., recorded demonstrations) to train a neural network (e.g., a policy or robot manipulation policy) to control a robot. In at least one embodiment, the system uses existing videos of a robot performing a task to generate new (e.g., additional) videos of the robot or a different robot performing a task different from the task performed in the existing videos. In at least one embodiment, the system detects objects in a scene of a video of the robot performing the task, identifies subtasks of the robot performing the task to determine shorter segments of the video, each segment corresponding to a different subtask, and identifies the trajectory of the robot and the identified objects during each subtask. In at least one embodiment, a subtask comprises actions performed by the robot to perform the task. In at least one embodiment, a task comprises performing a sequence of subtasks.

[0060] In at least one embodiment, to generate a new video, the system determines modifications to the scene, such as a different starting position for an object, determines an object to replace in the scene, and determines modifications to the trajectory of a robot performing the task that will be effective for the new object and the new position of the replaced object. In at least one embodiment, the new object, new position, and modified trajectory are used as input to cause the robot to perform the task in a simulator, and any simulation of the robot performing the task (different from the task identified in the existing video) is used to generate the new video. In at least one embodiment, the new object, new position, and modified trajectory are set for the robotic device to perform the task (different from the task identified in the existing video) to generate the new video.

[0061] In at least one embodiment, a video of a robot placing a coffee cup into a cabinet can be used to generate a new (e.g., additional) video of the robot placing the coffee cup into the cabinet. In at least one embodiment, the system generates the new (e.g., additional) video by: a) identifying an object, such as a coffee cup, in the existing video; b) determining subtasks of the task, such as the robot approaching the coffee cup, moving the robot's arm to position its gripper to grip the coffee cup, gripping the coffee cup, and so on; c) determining a trajectory of the robot's gripper during the subtask; d) selecting a new and different coffee cup to replace the coffee cup in the video (e.g., the cup can be selected from a plurality of coffee cups available in a simulator); e) determining a new starting position for the new coffee cup in the generated video; f) determining how to modify a previously determined trajectory associated with the subtask to account for the new starting position of the new coffee cup; g) performing a simulation of the robot performing the task with the new coffee cup using the determined new coffee cup, the new starting position, and the modified trajectory; and h) using the task simulation to generate a new video of the robot performing the task with the new coffee cup.

[0062] In the preceding and following descriptions, various techniques are described. For purposes of explanation, specific configurations and details are set forth to provide a thorough understanding of possible ways to implement the techniques. However, it will also be apparent that the techniques described below can be practiced in different configurations without these specific details. Furthermore, well-known features may be omitted or simplified to avoid obscuring the described techniques.

[0063] Figure 1 An example system 100 is shown for receiving a message from a user 102 (although Figure 1 Only one user is depicted in the figure, but there may be more than one user) initially through the existing set of demonstrations 104 performed by teleoperation to collect and generate training data 108. In at least one embodiment, user 102 uses a remote operation system ( Figure 1 102) uses a robotic device to perform one or more tasks, and the remote operation system can be a system that is part of the system 100 or a separate system from the system 100. In at least one embodiment, one or more videos are recorded when the robotic device uses the remote operation system to perform the tasks instructed by the user 102. In at least one embodiment, the recorded videos include a demonstration set (also referred to herein as the existing demonstration set 104). In at least one embodiment, the user 102 can also be a computing device configured to receive user input to control the remote operation system. In at least one embodiment, the system 100 uses the remote operation system to generate the existing demonstration set 104. In at least one embodiment, the existing demonstration set 104 is provided to the system 100 from another remote system or database.

[0064] In at least one embodiment, system 100 includes a system 106 that generates training data 108 for training a robot. In at least one embodiment, system 106 can be software executed by system 100. In at least one embodiment, system 106 selects and uses at least one demonstration from an existing set of demonstrations 104, spatially transforms each object-centered segment according to a trajectory identified in the one demonstration from the existing set of demonstrations 104, stitches the segments together to generate a new trajectory, and instructs the robot to follow the new trajectory to collect new demonstrations (e.g., additional training data 108). In at least one embodiment, the newly generated demonstrations (e.g., additional training data 108) can be recorded as videos by one or more cameras. In at least one embodiment, each of the second set of videos can include demonstrations with diverse scene configurations 110, diverse objects 112, and / or diverse robot hardware 114. In at least one embodiment, the video data includes one or more depth images, robot sensory data, audio sensory data, and / or other data modalities. In at least one embodiment, the generated new demonstrations (e.g., additional training data 108) are used to train the robot's control system using imitation learning techniques.

[0065] In at least one embodiment, system 106 is used for a wide range of long-view and high-precision tasks requiring different manipulation skills (e.g., pick and place, insertion, and articulation). In at least one embodiment, system 160 is used to perform other tasks, including but not limited to: Basic Tasks (Stacking, Stack Three): a set of box stacking tasks; Contact-Rich Tasks (Square, Threading, Coffee, Three-Piece Assembly, Hammer Cleaning, Cup Cleaning): a set of tasks involving contact-rich behaviors (e.g., insertion or drawer articulation); Mobile Manipulation Tasks (Moving Kitchen): requiring base and arm motion; and Factory Tasks (Nut and Bolt Assembly, Gear Assembly, Frame Assembly): a set of high-precision assembly tasks in a factory. In at least one embodiment, system 100 and system 106 are a collection of one or more hardware and / or software computing resources, wherein instructions, when executed, implement one or more communication processes, such as the communication processes described herein. In at least one embodiment, system 100 and system 106 are software programs executed on computer hardware, applications executed on computer hardware, and / or variants thereof.

[0066] In at least one embodiment, one or more processes of system 100 and system 106 are performed by any suitable processing system or unit (e.g., a graphics processing unit (GPU), a general-purpose GPU (GPGPU), a parallel processing unit (PPU), a central processing unit (CPU)), a data processing unit (DPU) (described below) in any suitable manner, including sequential, parallel, and / or variations thereof. In at least one embodiment, system 100 uses a machine learning training framework (e.g., PyTorch, TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, and / or other training frameworks) to implement and perform the operations described herein to generate one or more portions of an image based at least in part on less than the entire portion of the one or more portions using one or more neural networks. In at least one embodiment, training a neural network model includes, for example, using a server (e.g., an NVIDIA DGX server) that also includes at least one GPU (e.g., an 8A 100 40GB GPU, AMD MI200, Vegal10, Vego20, and Arcturus), an optimizer (e.g., an Adam Optimizer), or a discriminator architecture (e.g., a discriminator architecture from face-vid2vid for training using a GAN loss).

[0067] In at least one embodiment, system 100 and system 106 each include one or more modules or units. In at least one embodiment, system 100 includes one or more modules and / or units, such as Figure 6 One or more modules described in Figure 6In at least one embodiment, the system uses one or more first videos of a robotic device performing a task to generate one or more second videos of the robotic device performing a task different from that depicted in the one or more first videos. In at least one embodiment, the module or unit includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform the functions as described. In at least one embodiment, the module or unit includes one or more circuits that form part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), etc.). In at least one embodiment, the controller includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform the functions as described. In at least one embodiment, the software includes a software package, code, a programming language, a driver, instructions, an instruction set, or some combination thereof. In at least one embodiment, the hardware includes hardwired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution unit circuitry, firmware with stored instructions executed by programmable circuitry, or some combination thereof. In at least one embodiment, system 100 and system 106 perform one or more processes, such as in conjunction with Figures 2 to 7 The processes described.

[0068] In at least one embodiment, the system 100 and the system 106 each include one or more modules, which include one or more logical units. In at least one embodiment, the system 100 and the system 106 each include a data collection module 604, a data generation module 606 and / or a robot control module 608, for example Figure 6 . In at least one embodiment, the data collection module 604 and the data generation module 606 belong to the same module. In at least one embodiment, the logic unit includes firmware logic, hardware logic, or some combination thereof, configured to provide any of the functionality further described herein. In at least one embodiment, the logic unit includes circuitry that forms part of a larger system (e.g., an IC, SoC, CPU, GPU, DPU). In at least one embodiment, the logic unit includes logic circuitry for implementing firmware and / or hardware to use one or more neural networks to generate one or more portions of an image based at least in part on less than an entire portion of the one or more portions and / or otherwise perform the operations discussed herein.

[0069] In at least one embodiment, system 100 and system 106 each include one or more engines, each comprising modules (and / or logic units) as described above and further herein. In at least one embodiment, a component comprises a module (and / or logic unit) as further described herein. In at least one embodiment, an engine comprises software logic, firmware logic, hardware logic, or some combination thereof, configured to provide any of the functionality further described herein. In at least one embodiment, a component comprises software logic, firmware logic, hardware logic, or some combination thereof, configured to provide any of the functionality further described herein. In at least one embodiment, operations performed by hardware and / or firmware may alternatively be implemented via a software module, which may be embodied as a software package, code, and / or instruction set. In at least one embodiment, a logic unit may also utilize a portion of software to implement its functionality. In at least one embodiment, system 100 and system 106 each include a machine-readable medium having stored thereon a set of instructions that, if executed by one or more processors, cause the one or more processors to use at least one or more neural networks to generate one or more portions of an image based at least in part on less than the entire portion of the one or more portions and / or otherwise perform the operations described herein.

[0070] In at least one embodiment, Figure 1 In the embodiment of the present invention, at least three different human demonstrations 104 of placing coffee and a coffee cup into a coffee machine are shown as Demo 1, Demo 2, and Demo 3. In at least one embodiment, in each of Demos 1-3, curved arrows illustrate one or more trajectories of a robotic arm performing a subtask using at least one coffee pod and a cup. In at least one embodiment, the trajectories include motions of the robot grasping an object (e.g., a coffee pod or a coffee cup) and moving the object from an initial position in an environment to another position. In at least one embodiment, Demos 1-3 differ from each other in the initial position of the coffee pod and / or coffee cup relative to the coffee machine and the trajectories used to move the coffee pod and coffee cup from the initial position to another position (e.g., in the coffee machine).

[0071] In at least one embodiment, the system 100 collects demonstrations 104 provided by one or more teleoperators and further collects new demonstrations generated by the system 106. In at least one embodiment, given a new scenario, the system 106 generates a new demonstration by segmenting the existing set of demonstrations 104 into subtasks and performing a series of mathematical operations, such as transforming and interpolating selected subtasks to adapt to the new scenario (e.g., the new context and / or environment in which the robot will perform the task). In at least one embodiment, the system 100 causes the robotic device to perform a task that is different from the tasks in the existing set of demonstrations 104. In at least one embodiment, after the robot successfully simulates and performs a subtask, the system 100 generates the next new subtask by repeating the same process until the final subtask in the new scenario is successfully completed. In at least one embodiment, the system 100 stitches together the successfully generated new subtasks to generate a new demonstration, and then records the new demonstration as a video.

[0072] In at least one embodiment, imitation learning from human demonstrations 104 can be used to train a robot. In at least one embodiment, system 100 uses an existing set of demonstrations 104 and adapts these demonstrations to a new context to generate a new destination. In at least one embodiment, a context is the environment in which the robot is to perform a task. For example, if the robot is trained to perform a task in a context, the different context may have objects to manipulate in different locations, obstacles in the environment in different locations, different lighting conditions, a different configuration of objects, a different task than the task performed in the context, and / or other differences. In at least one embodiment, system 100 uses images (e.g., videos) from a different (e.g., first) context to generate images of a context (e.g., a second context) in which the robot is to imitate the task. In at least one embodiment, system 106 identifies objects and object trajectories from images of the first context in the existing set of demonstrations 104, determines the object's location in the second context, modifies the identified trajectory to align with the determined location, and then performs a simulation of the robot performing the task in the second context to generate images of the robot performing the task in the second context.

[0073] In at least one embodiment, system 106 (sometimes referred to herein as MimicGen) can generate task data with different initial state distributions, objects, and robot arms (assuming the robots share the convention of an end-effector control frame). In at least one embodiment, the scene configurations 110 are diversified by placing the objects on which the robot needs to perform the task at different locations relative to the end-effector (e.g., robot arm). In at least one embodiment, as Figure 1As shown, diversifying scene configuration 110 includes modifying an existing presentation with a new context by placing a coffee bag and a coffee cup at different positions and orientations relative to the position and orientation of a robotic device (e.g., a robotic arm). In at least one embodiment, diversifying objects 112 includes modifying an existing presentation with a new context by placing objects with different shapes, sizes, and / or colors in the scene that are different from the objects used in the existing presentation. In at least one embodiment, the existing presentation is also referred to herein as a source presentation or a source dataset. In at least one embodiment, diversifying robotic hardware 114 includes modifying an existing presentation with a new context by using different robotic arms with grippers of different lengths, shapes, and sizes, different numbers of fingers, etc. In at least one embodiment, the robotic arms are diversified by assuming a convention that all robotic arms share an end effector control frame.

[0074] Figure 2 An example system 200 is shown that uses one or more presentations 104 and divides each presentation into one or more subtasks according to at least one embodiment. In at least one embodiment, the system 200 takes an existing presentation set 104 (e.g., Figure 1 In at least one embodiment, the system 200 (using Figure 1 One or more processors, circuits, modules, etc. described above) parse a demonstration (e.g., demonstration 1, ..., demonstration N) into multiple segments (e.g., subtask 1 202, subtask 2 204, ..., subtask M 206). In at least one embodiment, each of the segments 202, 204, 206 is an object-centric segment. In at least one embodiment, the object-centric subtask is a subtask of the robot's trajectory relative to the object. In at least one embodiment, as Figure 2 As shown, Demo 1 includes subtask 1 202, which corresponds to moving the robotic arm toward the handle of the coffee cup and grasping the handle, subtask 2 204 corresponding to the robotic arm picking up the coffee cup, moving the coffee cup toward the coffee machine and placing the coffee cup on the cup station in the coffee machine, and subtask M 206 corresponding to retracting the robotic arm to the original position.

[0075] In at least one embodiment, each of the existing set of demonstrations (e.g., Demo 1, Demo 2, ..., and Demo N) has a different initial scene configuration with respect to the placement of the cup, coffee pod, and coffee machine. In at least one embodiment, for each demonstration, the subtask Figure 2, presented in columns. In at least one embodiment, subtask 1 202 is common across all demonstrations: Demo 1, ..., Demo N, because subtask 1 202 corresponds to moving the robotic arm from its home position toward the coffee cup and grasping the handle. In at least one embodiment, the trajectory of subtask 1 in Demo 1 differs from the trajectory of subtask 1 202 in Demo 2 and from the trajectory of subtask 1 in Demo N. In at least one embodiment, subtask 2 204 is common across all demonstrations: Demo 1, ..., Demo N, because subtask 2 204 corresponds to the robotic arm picking up the coffee cup, moving it toward the coffee machine, and placing it on the coffee machine's cup station. In at least one embodiment, the trajectory of subtask 2 204 in Demo 1 differs from the trajectory of subtask 2 204 in Demo 2 and from the trajectory of subtask 2 204 in Demo N. In at least one embodiment, subtask M 206 is common across all demonstrations: Demo 1, ..., Demo N, because subtask M 206 corresponds to retracting the robotic arm to its home position. In at least one embodiment, the trajectory of subtask M 206 in Demo 1 is different from the trajectory of subtask 1 202 in Demo 1 and also different from the trajectory of subtask 1 202 in Demo N.

[0076] Figure 3 An example system 300 is shown for generating new trajectories for training a new video of a robot. In at least one embodiment, the system 300 is similar to the system 100 (described above). Figure 1 In at least one embodiment, given the current observation 302 of the coffee cup, coffee bag, and coffee machine configuration (the scene in the existing demonstration, as described above), new trajectories and segments are generated. Figure 1 ), the system 300 first selects a segment from the current observation 302. In at least one embodiment, the current observation corresponds to Figure 2, which includes moving a robotic arm toward a coffee cup to grasp the handle. In at least one embodiment, given a current observation 302 and a reference segment from an existing demonstration (also referred to herein as a source dataset or dataset), system 300 simulates 304 the reference segment from current observation 302 to generate a new segment 306. In at least one embodiment, system 300 transforms one or more trajectories of one or more subtasks from reference segment 304. In at least one embodiment, system 300 performs interpolation, if necessary, to adapt the robot's initial position to the transformed trajectory in generated segment 306. In at least one embodiment, given a transformed trajectory 308 (e.g., a new trajectory) after performing the transformation and interpolation operations, system 300 causes the robotic arm to execute the transformed trajectory 308 in simulation. In at least one embodiment, if all segments execute successfully without any collisions or errors, system 300 generates a new destination and records the new demonstration using one or more cameras, which can be stored in a database. In at least one embodiment, the recorded demonstrations are then used to train the robot to perform these new tasks (which are different from the tasks currently being observed 302 or tasks related to the existing set of demonstrations).

[0077] In at least one embodiment, the task of modifying an existing demonstration to generate a new demonstration can be viewed as a Markov decision process (MDP). In at least one embodiment, the robot manipulation policy π maps the state space S to the action space A. In at least one embodiment, the imitation dataset consists of N demonstrations Each of these are sampled from the initial state distribution D. In at least one embodiment, behavioral cloning is used to train a policy π, whose goal is

[0078] In at least one embodiment, by the task The source dataset consists of a small set of human demonstrations collected on Used to generate large datasets on the same task or task variations (where the initial state distribution D of the robot arm can change.) In at least one embodiment, to generate a new demonstration: (1) sample a starting state from the task for which data needs to be generated, (2) select a demonstration and make adjustments to generate a new robot trajectory τ′. (3) The robot executes the trajectory τ′ on the current scene. If the task is successfully completed, the state and action sequence are added to the generated dataset.

[0079] In at least one embodiment, the action space A consists of the incremental pose commands of the end effector controller and the gripper open / close commands. In at least one embodiment, the equivalence between the incremental pose actions and the controller target poses makes the actions in the demonstration a sequence of target poses for the end effector controller.

[0080] In at least one embodiment, It's a task In at least one embodiment, it is assumed that a task consists of a series of object-centric subtasks. Composition, where each subtask The manipulations in are relative to the coordinate system of a single object

[0081] In at least one embodiment, it is assumed that it can be observed that during data collection, each subtask Related objects at the beginning posture.

[0082] Figure 4 An example process 400 is shown for training a robot by modifying a demonstration to generate a new demonstration according to at least one embodiment. In at least one embodiment, the process 400 begins 402 when the processor 602 calls (see Figure 6 In at least one embodiment, the processor 602 uses Figure 6 One or more modules described in Figure 64-608 in the embodiment of the present invention) executes one or more steps 402-410 in process 400. In at least one embodiment, one or more steps in process 400 are combined in other ways, performed in series and / or performed in parallel. In at least one embodiment, part or all of process 400 (or any other process described herein, or its variants and / or combinations) is executed under the control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that is jointly executed on one or more processors by hardware, software, or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program that includes multiple computer-readable instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to perform process 300 are not stored using only transient signals (e.g., propagating transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuits (e.g., buffers, caches, and queues) within the transient signal transceiver. In at least one embodiment, process 400 is at least partially performed on a computer system (e.g., a computer system described elsewhere in this disclosure). In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) performs process 400.

[0083] In at least one embodiment, process 400 retrieves 404 one or more previously recorded demonstrations of a robotic apparatus performing a task, partitions 406 the task into a plurality of subtasks, where each subtask comprises one or more trajectories for the robotic apparatus to perform the task, and generates 408 one or more new demonstrations of the robotic apparatus performing a task different from the task in the previously recorded demonstrations.

[0084] In at least one embodiment, the processor performing process 400 includes acquiring 404 a previously recorded demonstration of a robotic device performing a task. In at least one embodiment, the robot is trained to perform manipulation behaviors using imitation learning techniques from human demonstrations. In at least one embodiment, a human operator remotely operates a robotic arm via a control interface to generate a demonstration of the robot performing the manipulation task, and uses the data to train a controller of the robot to perform the task. In at least one embodiment, the present invention relates to Figure 4 The demonstration described corresponds to Figure 1 The existing demonstration set 104 described in.

[0085] In at least one embodiment, an existing video of the robot is divided into smaller segments, and the trajectory of an object in the existing video is determined for each video segment. In at least one embodiment, after determining the new position of the object for the video to be generated, the trajectory of each segment is modified according to the new position. In at least one embodiment, as an example, an object in the robot video is moved from the left side of the table, and for the video to be generated, the object will be located on the right side of the table, and the trajectory of the video segment showing the robot moving the object from the left side of the table is modified to be consistent with moving the object from the right side of the table. In at least one embodiment, the new trajectory is then spliced ​​(i.e., concatenated) and then used in the simulator so that in the simulation, the object and the robot follow the spliced ​​trajectory.

[0086] In at least one embodiment, the processor performing process 400 includes segmenting 406 the task into a plurality of subtasks, wherein each subtask comprises one or more trajectories for the robotic device to perform the task. In at least one embodiment, the system parses the demonstration into segments—one segment for each object-centric subtask in the task. In at least one embodiment, the system in step 406 corresponds to Figure 1 In at least one embodiment, each task is composed of a series of object-centric subtasks. In at least one embodiment, if It's a task The object set in the task consists of a series of object-centered subtasks Composition, where each subtask The operations in are relative to the coordinate system of a single object

[0087] In at least one embodiment, each trajectory τ in the source presentation of the dataset is parsed into segments where each segment τ i Corresponding to a subtask In at least one embodiment, in order to parse the source presentation into segments of each subtask, it is assumed that there is access to indicators that allow automatic detection of the end of each subtask. In at least one embodiment, each trace has been divided into a continuous sequence of segments τ=(τ1,τ2,...,τ M ), one fragment per subtask.

[0088] In at least one embodiment, the processor executing process 400 includes generating 408 one or more new demonstrations of the robotic device performing tasks different from the tasks in the previously recorded demonstrations. Figures 1 to 3Generating a new demonstration is described. In at least one embodiment, the new demonstration is recorded as a video and used to train the robot to perform a task different from the task performed in the previously recorded demonstration in 404.

[0089] In at least one embodiment, process 400 continues to execute steps 404 to 408 in a loop until a threshold number of successful demonstrations is reached or exceeded during the simulation. In at least one embodiment, the threshold may be 100 successful demonstrations, and once the threshold is reached, process 400 ends 410.

[0090] According to at least one embodiment, Figure 5 An example process 500 is shown for generating a demonstration based on a successful simulated demonstration to train a robot. In at least one embodiment, the process 500 begins when called by the processor 602 (see Figure 6 In at least one embodiment, the processor 602 uses Figure 6 One or more modules described in Figure 6 604-608 in the process 500) performs one or more steps 502-510 in the process 500. In at least one embodiment, one or more steps in the process 500 are combined in other ways, performed in series and / or performed in parallel. In at least one embodiment, some or all of the process 500 (or any other process described herein, or its variants and / or combinations) are performed under the control of one or more computer systems configured with computer-executable instructions and are implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that is executed together on one or more processors, through hardware, software, or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program that includes multiple computer-readable instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to perform the process 500 are not stored using only transient signals (e.g., propagating transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within the transient signal transceiver. In at least one embodiment, process 400 is performed at least in part on a computer system (e.g., a computer system described elsewhere in this disclosure). In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) performs process 500.

[0091] In at least one embodiment, process 500 retrieves data from a dataset (e.g., as described above). Figure 1A reference demonstration is selected 502 from the existing demonstration set described in [ 502 ], a new subtask is generated 504 for the new scenario, a robot is caused 506 to execute the newly generated subtask, and a determination is made 508 as to whether the generation of the new subtask based on the selected reference demonstration is complete. In at least one embodiment, if all new subtasks have not been generated, steps 502-506 are repeated. In at least one embodiment, if all new subtasks have been generated, all successfully simulated newly generated subtasks are recorded 510 as new demonstrations.

[0092] In at least one embodiment, given a new scene and / or configuration, the process 500 selects 502 a reference demonstration from the dataset. In at least one embodiment, the new scene or configuration is due to a different location of objects in the robot workspace, different objects (where objects from the first scene are replaced with new objects from the second scene), and / or different robot hardware. In at least one embodiment, the new scene in step 502 corresponds to Figure 1 In at least one embodiment, a system (e.g., Figure 1 The system 100 described in

[15] selects a source demonstration j (and corresponding fragment) at the beginning of each subtask. In at least one embodiment, a hyperparameter determines how often source demonstration selection occurs in each subtask. In at least one embodiment, the hyperparameter addresses the issue of source subtasks being incompatible with different strategies, e.g., if two demonstrations are Figure 1 If there are different object grasps for the cup in a set of human demonstrations 104, each grasp may require a different placement strategy. In at least one embodiment, if the subtasks selected from the sources are incompatible, the system selects a single source demonstration j at the beginning of the data generation episode and fixes it (so all source subtask segments come from the same demonstration, In at least one embodiment, the system parses the source data set into ) corresponding to the fragment, where In at least one embodiment, in each subtask Initially, the system starts with the set The corresponding segments are selected from the source presentation j∈{1,2....,N}. The segments can be selected randomly or using the associated object poses. In at least one embodiment, in the random selection, it is sufficient to select only one source presentation j∈{1,2....,N}, since this uniquely identifies the subtask segment for the current subtask. In at least one embodiment, in the nearest neighbor selection strategy, the system selects the segments of the objects in the current scene. Posture With each source demo clip Initial object pose at the start The demos are compared and sorted (in ascending order) by pose distance (to evaluate the pose distance of each demo segment, the system adds the L2 position distance to the delta rotation angle value (axis-angle form) between the two object rotations). Then, in at least one embodiment, the first n n objects in the sorted list are sorted. k A demonstration is selected uniformly randomly from the members.

[0093] In at least one embodiment, process 500 generates 502 new subtasks by transforming and interpolating the trajectories of the subtasks in the reference demonstration to fit the new scene at step 502. Selected source subtask fragment τ i is the target pose sequence of the robot arm. In at least one embodiment, is a uniform 4x4 matrix. In at least one embodiment, Among them C t is the controller's target pose frame at time step t, W is the world frame, and K is the length of the segment. In at least one embodiment, since this motion is assumed to be relative to the object at the start of the segment, The pose (frame O0 has pose ), τ i The new pose of the corresponding object in the current scene (frame O'0 has pose ) is transformed so that the relative pose between the target pose frame and the object frame is preserved at each time step This produces the transformed sequence In at least one embodiment, in order to determine the new pose of the corresponding object in the current scene (frame O′0 has pose ) transform T so that the target pose frame and Relative pose of objects between frames Can be achieved through and and setting them equal to calculate, we get In at least one embodiment, by Left multiplication Rearrange to get This is the set of equations used to transform the source fragment. In at least one embodiment, as an example, Figure 3 The source and transformed segments in the approach the cup in a consistent manner. In at least one embodiment, the first target pose of the new segment Possibly far from the current robot arm pose in the new scene (where E is the end effector frame). In at least one embodiment, the system i Add an interpolation segment at the beginning of to start from the current end effector pose Linear interpolation to fragment The beginning of.

[0094] In at least one embodiment, process 500 causes 506 the robot to perform the newly generated subtask in step 504. In at least one embodiment, the system performs the new segment τ′ by taking the target pose at each time step, transforming it into an incremental pose action (as described above), pairing it with the appropriate gripper open / close action from the source segment, and performing the new action i .

[0095] In at least one embodiment, process 500 determines 508 whether the robot has successfully simulated the task using all new subtasks based on the reference demonstration. In at least one embodiment, if the robot has not successfully performed the newly generated subtasks, process 500 repeats steps 502 through 506 for the new scenario. In at least one embodiment, if the newly generated subtasks have been successfully performed, process 500 moves to step 510.

[0096] In at least one embodiment, process 500 repeats steps 502 through 506 for the next subtask of the new scene. In at least one embodiment, the above steps are repeated for each subtask until the last segment is completed. In at least one embodiment, the system checks for successful tasks after all segments have been executed and only retains successful demonstrations.

[0097] In at least one embodiment, if the answer to 508 is no, the system continues to loop between steps 508 and 508 until all new subtasks of the new scenario are generated. In at least one embodiment, if the answer to 508 is yes, the system executes step 510.

[0098] In at least one embodiment, process 500 records 510 the robot's successful completion of the newly generated subtask in the dataset as a new demonstration.

[0099] Figure 6 An example 600 of a processor and modules according to at least one embodiment is shown. In at least one embodiment, the processor 602 executes one or more processes (such as those described herein) to generate a new robot demonstration based at least in part on some human demonstration. In at least one embodiment, the processor 602 executes Figure 1 In at least one embodiment, the processor 502 executes one or more processes (e.g., Figure 1-5 related description process).

[0100] In at least one embodiment, processor 602 includes one or more processors (e.g., Figures 26 to 41B). In at least one embodiment, the processor 602 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof. In at least one embodiment, the processor 602 includes a data collection module 604, a data generation module 606, and / or a robot control module 608. In at least one embodiment, the data collection module 604, the data generation module 606, and / or the robot control module 608 are part of the processor 602 and / or one or more other processors. In at least one embodiment, the data collection module 604, the data generation module 606, and / or the robot control module 608 are distributed among multiple processors, which communicate via a bus, a network, by writing to a shared memory, and / or any suitable communication process (such as the communication process described herein).

[0101] In at least one embodiment, as used in any implementation described herein, unless the context clearly dictates otherwise or clearly to the contrary, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein may include, for example, hardwired circuits, programmable circuits, state machine circuits, fixed function circuits, execution unit circuits, and / or firmware that stores instructions executed by programmable circuits, alone or in any combination. In at least one embodiment, modules may be embodied collectively or individually as circuits that constitute part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), etc.). In at least one embodiment, a module performs one or more processes in conjunction with any suitable processing unit and / or combination of processing units (e.g., one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof).

[0102] In at least one embodiment, the data collection module 604 is a module that collects human demonstrations and / or automatically newly generated demonstrations and stores them for future training by the robot control module. In at least one embodiment, the data collection module 604 performs one or more processes, such as the processes described herein, by at least including or otherwise encoding instructions that cause the execution of the one or more processes or are otherwise usable for the execution of the one or more processes (e.g., by the processor 602). In at least one embodiment, the data collection module 604 obtains or is otherwise equipped with one or more data collection systems (e.g., by one or more systems (e.g., with Figure 1 In at least one embodiment, the data collection module 604 collects data through one or more processes (e.g., Figure 1-5In at least one embodiment, the data collected by the data collection module 604 is collected using any suitable training process (e.g., with Figure 8A and / or Figure 8B The robot control module 608 is trained using the process described in the related literature.

[0103] In at least one embodiment, the data generation module 606 is a module that generates a new demonstration based on some source demonstration provided by a human or previously generated data collected by the data collection module 604. In at least one embodiment, the data generation module 606 performs one or more processes (e.g., the processes described herein) by at least including or otherwise encoding instructions that cause the execution of the one or more processes or are otherwise usable to perform the one or more processes (e.g., executed by the processor 602). In at least one embodiment, the data generation module 606 generates a new scene with diverse scene configurations, diverse objects, and / or diverse robot hardware, selects one or more previous demonstrations from the dataset collected by the data collection module 604, splits the selected demonstrations into subtasks, generates new subtasks based on the subtasks in the selected demonstration by performing a series of transformations and / or interpolation operations, and stitches the newly generated subtasks together to generate a new demonstration. In at least one embodiment, the data generation module 606 obtains or is otherwise equipped with one or more data generation systems (e.g., through one or more systems (e.g., with Figure 1 In at least one embodiment, the data generation module 606 generates data by one or more processes (e.g., Figure 1-5 In at least one embodiment, the data generated by the data generation module 606 uses any suitable training process (e.g., Figure 8A and / or Figure 8B The process described in the related text) trains the robot control module 608.

[0104] In at least one embodiment, the robot control module 608 is a module responsible for making decisions about the robot's motion and / or trajectory when encountering a new scene. In at least one embodiment, the robot control module 608 performs one or more processes (such as those described herein) by at least including or otherwise encoding instructions that cause (e.g., by the processor 602) to be executed or otherwise operable to perform the one or more processes. In at least one embodiment, the robot control module 608 obtains training data from previously stored datasets collected by the data collection module 604 to enable the robot to perform a task and / or a series of subtasks, such as Figures 1 to 5In at least one embodiment, the robot control module is one or more neural networks. In at least one embodiment, after the data generation module 606 generates each new subtask, the robot control module 608 is instructed to have the robot perform the newly generated subtask, and if the subtask is successfully completed, the data collection module 604 collects and stores the newly generated subtask.

[0105] Figure 7 is a block diagram illustrating a driver and / or runtime including one or more libraries to provide one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, software program 702 is a software module, such as Figure 6 The software modules described in Figure 6 In at least one embodiment, the software program 602 includes one or more software modules. In at least one embodiment, the software modules are as follows: Figure 6 702 . In at least one embodiment, one or more APIs 710 are software instruction sets that, if executed, cause one or more processors to perform one or more computing operations. In at least one embodiment, one or more APIs 710 are distributed or otherwise provided as part of one or more libraries 706 , runtime 704 , driver 704 , and / or any other software and / or executable code group further described herein. In at least one embodiment, one or more APIs 710 perform one or more computing operations in response to a call from a software program 702 . In at least one embodiment, a software program 702 is a collection of software code, commands, instructions, or other text sequences that instructs a computing device to perform one or more computing operations and / or call one or more other instruction sets, such as APIs 710 or API functions 712 , to be executed. In at least one embodiment, the functionality provided by one or more APIs 710 includes software functions 712 , such as software functions that can be used to accelerate one or more portions of a software program 702 using one or more parallel processing units (PPUs) (e.g., graphics processing units (GPUs)). In at least one embodiment, the software program is a compiler.

[0106] In at least one embodiment, the API 710 is a hardware interface to one or more circuits for performing one or more computing operations. In at least one embodiment, the one or more software APIs 710 described herein are implemented as one or more circuits for performing the following operations in conjunction with Figure 2-7 In at least one embodiment, one or more software programs 702 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform the above-described combined Figures 1 to 6 One or more techniques described.

[0107] In at least one embodiment, a software program 702 (e.g., a user-implemented software program) utilizes one or more application programming interfaces (APIs) 710 to perform various computational operations, such as memory reservations, matrix multiplications, arithmetic operations, or any computational operations performed by a parallel processing unit (PPU) (e.g., a graphics processing unit (GPU)), as further described herein. In at least one embodiment, the one or more APIs 710 provide a set of callable functions 712, referred to herein as APIs, API functions, and / or functions, that individually perform one or more computational operations, such as computational operations associated with parallel computing. In at least one embodiment, the one or more APIs 710 provide functions 712 to cause a neural network 716 to train a robot using a modified demonstration (from a video provided by a human demonstration) and / or otherwise perform the operations described herein. In at least one embodiment, the one or more APIs 710 provide functions 712 to cause a neural network 716 to perform one or more operations, such as by returning the called function to a processor, wherein the processor calls the neural network.

[0108] In at least one embodiment, one or more software programs 702 interact or otherwise communicate with one or more APIs 710 to perform one or more computing operations using one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more computing operations using one or more PPUs include at least one or more groups of computing operations that are at least partially performed by the one or more PPUs for acceleration. In at least one embodiment, the one or more software programs 702 interact with one or more APIs 710 to facilitate parallel computing using remote or local interfaces.

[0109] In at least one embodiment, an interface is software instructions that, if executed, provide access to one or more functions 712 provided by one or more APIs 710. In at least one embodiment, a software program 702 uses a native interface when a software developer compiles one or more software programs 702 in conjunction with one or more libraries 706 that include or otherwise provide access to the one or more APIs 710. In at least one embodiment, the one or more software programs 702 are statically compiled in conjunction with precompiled libraries 706 or uncompiled source code that include instructions to implement the one or more APIs 710. In at least one embodiment, the one or more software programs 702 are dynamically compiled and linked to the one or more precompiled libraries 706 that include the one or more APIs 710 using a linker.

[0110] In at least one embodiment, a software program 702 uses a remote interface when a software developer executes a software program that utilizes or otherwise communicates with a library 706 including one or more APIs 710 over a network or other remote communication medium. In at least one embodiment, the one or more libraries 706 including the one or more APIs 710 are executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, the one or more libraries 706 including the one or more APIs 710 are executed by any other computing host that provides the one or more APIs 710 to the one or more software programs 702.

[0111] In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 to allocate and otherwise manage memory used by the software programs 702. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 to allocate and otherwise manage memory used by one or more portions of the software programs 702 for acceleration using one or more PPUs (e.g., GPUs or any other accelerators or processors described further herein). These software programs 702 request a neural network to generate one or more portions of an image based at least in part on the one or more portions.

[0112] In at least one embodiment, API 710 is an API for facilitating parallel computing. In at least one embodiment, API 710 is any other API described further herein. In at least one embodiment, API 710 is provided by a driver and / or runtime 704. In at least one embodiment, API 710 is provided by a CUDA user-mode driver. In at least one embodiment, API 710 is provided by a CUDA runtime. In at least one embodiment, driver 704 is data values ​​and software instructions that, if executed, execute or otherwise facilitate the execution of one or more functions 712 of API 710 during the loading and execution of one or more portions of software program 702. In at least one embodiment, runtime 704 is data values ​​and software instructions that, if executed, execute or otherwise facilitate the execution of one or more functions 712 of API 710 during the execution of software program 702. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 implemented or otherwise provided by a driver and / or runtime 704 to perform combined arithmetic operations by the one or more software programs 702 during execution by one or more PPUs (e.g., GPUs).

[0113] In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by a driver and / or runtime 704 to perform combined arithmetic operations for one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more APIs 710 provide combined arithmetic operations through the driver and / or runtime 704, as described above. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by the driver and / or runtime 704 to allocate or otherwise reserve one or more memory blocks 714 for one or more PPUs (e.g., GPUs). In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by the driver and / or runtime 704 to allocate or otherwise reserve memory blocks. In at least one embodiment, the one or more APIs 710 are used to perform combined arithmetic operations, as described below in conjunction with Figures 1 to 6 Any one of the above.

[0114] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to those skilled in the art that the inventive concept can be practiced without one or more of these specific details.

[0115] logic

[0116] Figure 8A Logic 815 is shown, as described elsewhere herein, which may be used in one or more devices to perform operations such as those discussed herein in accordance with at least one embodiment. In at least one embodiment, logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic 815 is reasoning and / or training logic. Figure 8A and / or Figure 8B Detailed information is provided regarding logic 815. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide the functionality or operations described herein, where the logic may collectively or individually be embodied as circuitry forming part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), or one or more processors (e.g., CPU, GPU).

[0117] In at least one embodiment, logic 815 may include, but is not limited to, code and / or data storage 801 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 815 may include or be coupled to code and / or data storage 801 for storing graph code or other software to control timing and / or sequence, wherein weights and / or other parameter information are loaded to configure logic including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 801 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 801 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0118] In at least one embodiment, any portion of code and / or data storage 801 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 801 may be cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 801 is internal or external to a processor, e.g., or including DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0119] In at least one embodiment, logic 815 may include, but is not limited to, code and / or data storage 805 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 805 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, logic 815 may include or be coupled to code and / or data storage 805 for storing graph code or other software to control the timing and / or sequence in which weight and / or other parameter information is loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0120] In at least one embodiment, code (such as graph code) causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 805 can be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 805 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 805 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 805 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other type of storage, can depend on the available on-chip or off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of the neural network, or some combination of these factors.

[0121] In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be separate storage structures. In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be the same storage structure. In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 801 and code and / or data storage 805 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0122] In at least one embodiment, logic 815 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 810 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 820, which are functions of input / output and / or weight parameter data stored in code and / or data storage 801 and / or code and / or data storage 805. In at least one embodiment, the activations stored in activation storage 820 are generated based on linear algebra and / or matrix-based math performed by ALU 810 in response to executing instructions or other code, with weight values ​​stored in code and / or data storage 805 and / or code and / or data storage 801 used as operands, as well as other values ​​such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 805 or code and / or data storage 801 or other on-chip or off-chip storage.

[0123] In at least one embodiment, one or more ALUs 810 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 810 may be external to the processor or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, ALUs 810 may be included within an execution unit of a processor or otherwise included in an ALU bank accessible by the execution units of the processor, which may be within the same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 801, code and / or data storage 805, and activation storage 820 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 820 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0124] In at least one embodiment, activation storage 820 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 820 can be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 820 is internal or external to the processor, for example, or including DRAM, SRAM, flash memory, or some other storage type, can depend on the available storage on-chip versus off-chip, the latency requirements for performing training and / or inference functions, the batch size of data used in inferring and / or training neural networks, or some combination of these factors.

[0125] In at least one embodiment, Figure 8A The logic 815 shown in FIG. 8 may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 8A The illustrated logic 815 may be used in conjunction with central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or other hardware such as a field programmable gate array ("FPGA").

[0126] Figure 8B Logic 815 is shown in accordance with at least one embodiment. In at least one embodiment, logic 815 is inference and / or training logic. In at least one embodiment, logic 815 may include, but is not limited to, hardware logic where computing resources are dedicated or otherwise used exclusively with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 8B The logic 815 shown in FIG can be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 8BThe logic 815 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, the logic 815 includes, but is not limited to, code and / or data storage 801 and code and / or data storage 805, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 8B In at least one embodiment shown in FIG, code and / or data storage 801 and code and / or data storage 805 are each associated with dedicated computing resources, such as computing hardware 802 and computing hardware 806, respectively. In at least one embodiment, computing hardware 802 and computing hardware 806 each include one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 801 and code and / or data storage 805, respectively, with the results being stored in activation storage 820.

[0127] In at least one embodiment, each of the code and / or data stores 801 and 805 and the corresponding computing hardware 802 and 806 corresponds to a different layer of a neural network, such that activations from one storage / computation pair 801 / 802 of the code and / or data store 801 and computing hardware 802 are provided as inputs to the next storage / computation pair 805 / 806 of the code and / or data store 805 and computing hardware 806, reflecting the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 801 / 802 and 805 / 806 can correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) can be included in the logic 815 after or in parallel with the storage / computation pairs 801 / 802 and 805 / 806.

[0128] Neural network training and deployment

[0129] Figure 9The training and deployment of a deep neural network according to at least one embodiment is shown. In at least one embodiment, an untrained neural network 906 is trained using a training dataset 902. In at least one embodiment, the training framework 904 is the PyTorch framework, while in other embodiments, the training framework 904 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 904 trains the untrained neural network 906 and enables it to be trained using the processing resources described herein to generate a trained neural network 908. In at least one embodiment, the weights can be randomly selected or selected by pre-training using a deep belief network. In at least one embodiment, the training can be performed in a supervised, partially supervised, or unsupervised manner.

[0130] In at least one embodiment, untrained neural network 906 is trained using supervised learning, where training dataset 902 includes inputs paired with expected outputs for the inputs, or where training dataset 902 includes inputs with known outputs and the outputs of neural network 906 are manually graded. In at least one embodiment, untrained neural network 906 is trained in a supervised manner, processing inputs from training dataset 902 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through untrained neural network 906. In at least one embodiment, training framework 904 adjusts the weights that control untrained neural network 906. In at least one embodiment, training framework 904 includes tools for monitoring the degree to which untrained neural network 906 converges toward a model (such as trained neural network 908) suitable for generating correct answers (such as results 914) based on input data (such as new dataset 912). In at least one embodiment, the training framework 904 repeatedly trains the untrained neural network 906 while adjusting the weights to refine the output of the untrained neural network 906 using a loss function and an adjustment algorithm (such as stochastic gradient descent). In at least one embodiment, the training framework 904 trains the untrained neural network 906 until the untrained neural network 906 reaches a desired accuracy. In at least one embodiment, the trained neural network 908 can then be deployed to implement any number of machine learning operations.

[0131] In at least one embodiment, unsupervised learning is used to train the untrained neural network 906, wherein the untrained neural network 906 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 902 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 906 can learn the groupings within the training dataset 902 and can determine how the individual inputs relate to the untrained dataset 902. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in the trained neural network 908, which can perform operations useful for reducing the dimensionality of the new dataset 912. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the new dataset 912 that deviate from the normal pattern of the new dataset 912.

[0132] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 902. In at least one embodiment, the training framework 904 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 908 to adapt to new datasets 912 without forgetting the knowledge that was infused into the trained neural network 908 during initial training.

[0133] In at least one embodiment, the training framework 904 is a framework that is processed in conjunction with a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit such as that developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes logic 815 or uses logic 815 to perform the operations described herein. In at least one embodiment, an SoC, an integrated circuit, or a processor uses OpenVINO to perform the operations described herein.

[0134] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations (such as human vision simulation, speech recognition, natural language processing, recommendation systems, and / or variations thereof). In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variations thereof.

[0135] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., people and / or objects), monocular depth estimation, image restoration, style transfer, action recognition, colorization, and / or variations thereof.

[0136] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command-line tool that facilitates the transition between training and deployment of a neural network model. In at least one embodiment, the model optimizer optimizes a neural network model for execution on various devices and / or processing units, such as GPUs, CPUs, PPUs, GPGPUs, and / or variations thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes layers from the model used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying the model's inputs (e.g., resizing the model's inputs), modifying the size of the model's inputs (e.g., modifying the model's batch size), modifying the model's structure (e.g., modifying the model's layers), normalization, standardization, quantization (e.g., converting the model's weights from a first representation, such as floating point, to a second representation, such as integers), and / or variations thereof.

[0137] In at least one embodiment, OpenVINO includes one or more software libraries for reasoning, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or any suitable programming language library. In at least one embodiment, the inference engine is used to reason about input data. In at least one embodiment, the inference engine implements various classes to reason about input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions to process intermediate representations, set input and / or output formats, and / or execute models on one or more devices.

[0138] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or parts of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (for example, executing a first set of layers on a first device (e.g., a GPU) and executing a second set of layers on a second device (e.g., a CPU)).

[0139] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or variations thereof. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0140] Data Center

[0141] Figure 10 An example data center 1000 is shown in which at least one embodiment may be used. In at least one embodiment, data center 1000 includes a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

[0142] In at least one embodiment, Figure 10As shown, the data center infrastructure layer 1010 may include a resource coordinator 1012, grouped computing resources 1014, and node computing resources ("node CRs") 1016(1)-1016(N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, the node CRs 1016(1)-1016(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1018(1)-1018(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1016(1)-1016(N) may be a server having one or more of the above-mentioned computing resources.

[0143] In at least one embodiment, the grouped computing resources 1014 may include separate groups of node CRs housed in one or more racks (not shown), or may be housed in a number of racks in data centers (also not shown) at various geographic locations. In at least one embodiment, the separate groups of node CRs within the grouped computing resources 1014 may include computing, network, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0144] In at least one embodiment, resource coordinator 1012 may configure or otherwise control one or more nodes CR 1016(1)-1016(N) and / or grouped computing resources 1014. In at least one embodiment, resource coordinator 1012 may comprise a software design infrastructure ("SDI") management entity for data center 1000. In at least one embodiment, resource coordinator 1012 may comprise hardware, software, or some combination thereof.

[0145] In at least one embodiment, Figure 10As shown, the framework layer 1020 includes a job scheduler 1022, a configuration manager 1024, a resource manager 1026, and a distributed file system 1028. In at least one embodiment, the framework layer 1020 may include a framework that supports software 1032 of the software layer 1030 and / or one or more applications 1042 of the application layer 1040. In at least one embodiment, the software 1032 or the application 1042 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1020 may be, but is not limited to, a type of free and open source software web application framework, such as Apache Spark, which may utilize the distributed file system 1028 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1022 may include a Spark driver to facilitate scheduling workloads supported by the various layers of the data center 1000. In at least one embodiment, the configuration manager 1024 may be capable of configuring different layers, such as the software layer 1030 and the framework layer 1020 including Spark and a distributed file system 1028 for supporting large-scale data processing. In at least one embodiment, the resource manager 1026 may be capable of managing the mapping or allocation of clustered or grouped computing resources to support the distributed file system 1028 and the job scheduler 1022. In at least one embodiment, the clustered or grouped computing resources may include the grouped computing resources 1014 at the data center infrastructure layer 1010. In at least one embodiment, the resource manager 1026 may coordinate with the resource coordinator 1012 to manage these mapped or allocated computing resources.

[0146] In at least one embodiment, the software 1032 included in the software layer 1030 may include software used by at least portions of the nodes CRs 1016(1)-1016(N), the grouped computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0147] In at least one embodiment, the one or more applications 1042 included in the application layer 1040 may include one or more types of applications used by at least portions of the nodes CRs 1016(1)-1016(N), the grouped computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0148] In at least one embodiment, any of the configuration manager 1024, resource manager 1026, and resource coordinator 1012 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve the data center operator of the data center 1000 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0149] In at least one embodiment, data center 1000 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by computing weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1000. In at least one embodiment, the resources described above with respect to data center 1000 may be used to infer or predict information using a trained machine learning model corresponding to one or more neural networks using weight parameters computed using one or more training techniques described herein.

[0150] In at least one embodiment, the data center can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0151] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8BDetails are provided regarding logic 815. In at least one embodiment, logic 815 can be used in data center 1000 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0152] In at least one embodiment, in at least one embodiment, Figure 10 One or more methods, systems or processes described in the foregoing are used to use various algorithms, formulas and processes (e.g., in combination with Figure 1 In at least one embodiment, the present invention provides a method for generating a second video of a robotic device performing a task using one or more first videos of the robotic device performing the task in a manner different from that depicted in the one or more first videos, and / or otherwise performing the operations described herein. Figure 10 One or more systems described in are used to implement such as Figure 1-7 One or more systems and / or processes such as those described.

[0153] autonomous vehicles

[0154] Figure 11A An example of an autonomous vehicle 1100 is shown in accordance with at least one embodiment. In at least one embodiment, autonomous vehicle 1100 (alternatively referred to herein as "vehicle 1100") can be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1100 can be a semi-tractor-trailer truck for hauling cargo. In at least one embodiment, vehicle 1100 can be an aircraft, a robotic vehicle, or another type of vehicle.

[0155] Autonomous vehicles may be described according to the automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation, “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, dated June 15, 2018, Standard No. J3016-201609, dated September 30, 2016, and previous and future versions of such standards). In at least one embodiment, the vehicle 1100 may be capable of one or more of Levels 1 to 5 according to the autonomous driving levels. For example, in at least one embodiment, the vehicle 1100 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0156] In at least one embodiment, the vehicle 1100 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 1100 may include, but is not limited to, a propulsion system 1150, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, the propulsion system 1150 may be connected to a drive train of the vehicle 1100, which may include, but is not limited to, a transmission, for enabling propulsion of the vehicle 1100. In at least one embodiment, the propulsion system 1150 may be controlled in response to receiving a signal from a throttle / accelerator 1152.

[0157] In at least one embodiment, when propulsion system 1150 is operating (e.g., when vehicle 1100 is in motion), a steering system 1154 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1100 (e.g., along a desired path or route). In at least one embodiment, steering system 1154 may receive signals from steering actuator 1156. In at least one embodiment, a steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1146 may be used to operate vehicle brakes in response to signals received from brake actuator 1148 and / or brake sensors.

[0158] In at least one embodiment, one or more controllers 1136, which may include, but are not limited to, one or more system-on-chips ("SoCs") ( Figure 11A) and / or a graphics processing unit (“GPU”) to provide signals (e.g., representing commands) to one or more components and / or systems of vehicle 1100. For example, in at least one embodiment, one or more controllers 1136 can send signals to operate vehicle brakes via brake actuator 1148, operate steering system 1154 via one or more steering actuators 1156, and operate propulsion system 1150 via one or more throttle / accelerator 1152. In at least one embodiment, one or more controllers 1136 can include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1100. In at least one embodiment, one or more controllers 1136 can include a first controller for autonomous driving functionality, a second controller for functional safety functionality, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, two or more controllers may handle a single function, and / or any combination thereof.

[0159] In at least one embodiment, the one or more controllers 1136 provide signals for controlling one or more components and / or systems of the vehicle 1100 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1158 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1160, one or more ultrasonic sensors 1162, one or more LIDAR sensors 1164, one or more inertial measurement unit (IMU) sensors 1166 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1196, one or more stereo cameras 1168, one or more wide-angle cameras 1170 (e.g., fisheye cameras), one or more infrared cameras 1172, one or more surround cameras 1174 (e.g., 360-degree cameras), telemetry cameras (e.g., gyroscopes), and the like. Figure 11A Not shown), mid-range camera ( Figure 11A), one or more speed sensors 1144 (e.g., for measuring the speed of the vehicle 1100), one or more vibration sensors 1142, one or more steering sensors 1140, one or more brake sensors (e.g., as part of a brake sensor system 1146), and / or other sensor types.

[0160] In at least one embodiment, one or more controllers 1136 may receive input (e.g., represented by input data) from a dashboard 1132 of the vehicle 1100 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface (“HMI”) display 1134, an audible annunciator, a speaker, and / or via other components of the vehicle 1100. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Figure 11A ), location data (e.g., the location of the vehicle 1100, such as on a map), directions, the locations of other vehicles (e.g., an occupancy grid), information about objects and the states of objects sensed by the one or more controllers 1136, etc. For example, in at least one embodiment, the HMI display 1134 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers the vehicle has, is, or will make (e.g., changing lanes now, reaching exit 34B in two miles, etc.).

[0161] In at least one embodiment, the vehicle 1100 further includes a network interface 1124 that can communicate over one or more networks using one or more wireless antennas 1126 and / or one or more modems. For example, in at least one embodiment, the network interface 1124 can be capable of communicating over Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, and the like. In at least one embodiment, the one or more wireless antennas 1126 can also enable communication between objects in the environment (e.g., vehicles, mobile devices, and the like) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, and the like) and / or one or more low power wide area networks ("LPWAN") (such as protocols such as LoRaWAN, SigFox, and the like).

[0162] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8BDetails are provided regarding logic 815. In at least one embodiment, logic 815 can be used in vehicle 1100 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0163] In at least one embodiment, Figure 11A One or more methods, systems or processes are described for using various algorithms, formulas and processes (e.g., in combination with Figure 1 In at least one embodiment, the present invention provides a method for generating a second video of a robotic device performing a task using one or more first videos of the robotic device performing the task in a manner different from that depicted in the one or more first videos, and / or otherwise performing the operations described herein. Figure 11A One or more systems described in are used to implement such as Figure 1-7 One or more systems and / or processes such as those described.

[0164] Figure 11B According to at least one embodiment, Figure 11A 1100. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located in different locations on the vehicle 1100.

[0165] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1100. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or combinations thereof. In at least one embodiment, the color filter array may include a red-clear-clear-clear ("RCCC") filter array, a red-clear-clear-blue ("RCCB") filter array, a red-blue-green-clear ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a clear pixel camera, such as one having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to increase photosensitivity.

[0166] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0167] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, so as to remove stray light and reflected light from within the vehicle 1100 (e.g., reflected light from the dashboard reflecting in the windshield mirror), which may interfere with the camera's image data capture capabilities. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras can also be integrated into the four pillars at each corner of the cabin.

[0168] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes portions of the environment in front of the vehicle 1100 can be used for surround vision to help identify the path ahead and obstacles, as well as assist in providing information critical to generating an occupancy grid and / or determining a preferred vehicle path with the assistance of one or more controllers 1136 and / or control SoCs. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (such as traffic sign recognition).

[0169] In at least one embodiment, a variety of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("Complementary Metal Oxide Semiconductor") color imager. In at least one embodiment, a wide-angle camera 1170 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Figure 11BOnly one wide-angle camera 1170 is shown, but in other embodiments, there can be any number (including zero) of wide-angle cameras on the vehicle 1100. In at least one embodiment, any number of remote cameras 1198 (e.g., a pair of telescopic stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, one or more remote cameras 1198 can also be used for object detection and classification and basic object tracking.

[0170] In at least one embodiment, any number of stereo cameras 1168 may also be included in the forward-facing configuration. In at least one embodiment, one or more stereo cameras 1168 may include an integrated control unit including an extensible processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle 1100's environment, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1168 may include, but are not limited to, a compact stereo vision sensor that may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle 1100 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1168 may be used in addition to or in place of those described herein.

[0171] In at least one embodiment, cameras having a field of view of portions of the environment including the sides of the vehicle 1100 (e.g., side view cameras) can be used for surround view, which provides information for creating and updating occupancy grids and generating side impact collision warnings. For example, in at least one embodiment, surround cameras 1174 (e.g., Figure 11B The four surround cameras shown) can be positioned on the vehicle 1100. In at least one embodiment, the one or more surround cameras 1174 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, the four fisheye cameras can be located on the front, rear, and sides of the vehicle 1100. In at least one embodiment, the vehicle 1100 can use three surround cameras 1174 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0172] In at least one embodiment, a camera having a field of view that includes portions of the environment behind the vehicle 1100 (e.g., a rearview camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating an occupancy grid. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1198 and / or one or more mid-range cameras 1176, one or more stereo cameras 1168, one or more infrared cameras 1172, etc.), as described herein.

[0173] In at least one embodiment, Figure 11B One or more methods, systems or processes are described for using various algorithms, formulas and processes (e.g., in combination with Figure 1 In at least one embodiment, the present invention provides a method for generating a second video of a robotic device performing a task using one or more first videos of the robotic device performing the task in a manner different from that depicted in the one or more first videos, and / or otherwise performing the operations described herein. Figure 11B One or more systems described in are used to implement such as Figure 1-7 One or more systems and / or processes such as those described.

[0174] Figure 11C is a diagram illustrating a method according to at least one embodiment Figure 11A A block diagram of an example system architecture for an autonomous vehicle 1100 is provided. In at least one embodiment, Figure 11C Each of the components, features, and systems of vehicle 1100 is shown as being connected via bus 1102. In at least one embodiment, bus 1102 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, CAN can be a network internal to vehicle 1100 that assists in controlling various features and functions of vehicle 1100, such as brake actuation, acceleration, braking, steering, wipers, etc. In at least one embodiment, bus 1102 can be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 1102 can be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1102 can be an ASIL B compliant CAN bus.

[0175] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, there may be any number of buses forming bus 1102, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions, and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality, and a second bus may be used for actuation control. In at least one embodiment, each bus in bus 1102 may communicate with any component of vehicle 1100, and two or more buses in bus 1102 may communicate with corresponding components. In at least one embodiment, each of any number of systems on a chip (“SoCs”) 1104 (e.g., SoC 1104(A) and SoC 1104(B)), each of one or more controllers 1136, and / or each computer within the vehicle can access the same input data (e.g., inputs from sensors of the vehicle 1100) and can be connected to a common bus, such as a CAN bus.

[0176] In at least one embodiment, the vehicle 1100 may include one or more controllers 1136, such as those described herein with respect to Figure 11A In at least one embodiment, the controller 1136 can be used for a variety of functions. In at least one embodiment, the controller 1136 can be coupled to any of the various other components and systems of the vehicle 1100 and can be used to control the vehicle 1100, the artificial intelligence of the vehicle 1100, the infotainment and / or other functions of the vehicle 1100.

[0177] In at least one embodiment, the vehicle 1100 may include any number of SoCs 1104. In at least one embodiment, each of the SoCs 1104 may include, but is not limited to, a central processing unit ("CPU(s)") 1106, a graphics processing unit ("GPU(s")) 1108, one or more processors 1110, one or more caches 1112, one or more accelerators 1114, one or more data stores 1116, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 1104 may be used to control the vehicle 1100 in a variety of platforms and systems. For example, in at least one embodiment, the one or more SoCs 1104 may be combined in a system (e.g., a system of the vehicle 1100) along with a high-definition ("HD") map 1122 that may be downloaded from one or more servers (e.g., a system of the vehicle 1100) via a network interface 1124. Figure 11C ) to obtain map refreshes and / or updates.

[0178] In at least one embodiment, one or more CPUs 1106 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 1106 may include multiple cores and / or a second level ("L2") cache. For example, in at least one embodiment, one or more CPUs 1106 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, one or more CPUs 1106 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, one or more CPUs 1106 (e.g., CCPLEX) may be configured to support simultaneous cluster operations, such that any combination of clusters of one or more CPUs 1106 may be active at any given time.

[0179] In at least one embodiment, one or more CPUs 1106 may implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware blocks when idle to save dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core may be independently power gated; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 1106 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state to enter for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, wherein work is offloaded to the microcode.

[0180] In at least one embodiment, one or more GPUs 1108 may include an integrated GPU (alternatively referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 1108 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1108 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1108 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache having at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512KB of storage capacity). In at least one embodiment, one or more GPUs 1108 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1108 may use one or more computing application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1108 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0181] In at least one embodiment, one or more GPUs 1108 may be power optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 1108 may be fabricated on fin field-effect transistor (“FinFET”) circuits. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g., a warp scheduler) or sequencer, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths for providing efficient execution of workloads using a mix of compute and addressing operations. In at least one embodiment, the streaming microprocessor can include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor can include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0182] In at least one embodiment, one or more GPUs 1108 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem, configured to provide a peak memory bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as fifth generation graphics double data rate type synchronous random access memory ("GDDR5"), may be used in addition to or in place of HBM memory.

[0183] In at least one embodiment, one or more GPUs 1108 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to allow one or more GPUs 1108 to directly access the page tables of one or more CPUs 1106. In at least one embodiment, when the memory management unit ("MMU") of a GPU in one or more GPUs 1108 experiences a miss, an address translation request may be sent to the one or more CPUs 1106. In response, in at least one embodiment, two of the one or more CPUs 1106 may look up the virtual-to-physical mapping of the address in their page tables and send the translation back to the one or more GPUs 1108. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory for both the one or more CPUs 1106 and the one or more GPUs 1108, thereby simplifying programming the one or more GPUs 1108 and porting applications to the one or more GPUs 1108.

[0184] In at least one embodiment, one or more GPUs 1108 may include any number of access counters that can track the frequency with which one or more GPUs 1108 access the memory of other processors. In at least one embodiment, the one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of sharing memory ranges between processors.

[0185] In at least one embodiment, one or more SoCs 1104 may include any number of caches 1112, including those described herein. For example, in at least one embodiment, one or more caches 1112 may include a level 3 ("L3") cache that may be used for both (e.g., connected to) one or more CPUs 1106 and one or more GPUs 1108. In at least one embodiment, one or more caches 1112 may include a write-back cache that may track the state of each line, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB of memory or more, depending on the embodiment, although smaller cache sizes may be used.

[0186] In at least one embodiment, one or more SoCs 1104 may include one or more accelerators 1114 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1104 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1108 and offload some tasks of one or more GPUs 1108 (e.g., to free up more cycles of one or more GPUs 1108 to perform other tasks). In at least one embodiment, one or more accelerators 1114 may be used for target workloads that are sufficiently stable to withstand acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, the CNN may include a region-based or region-based convolutional neural network (“RCNN”) and a fast RCNN (e.g., as used for object detection) or other types of CNNs.

[0187] In at least one embodiment, one or more accelerators 1114 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, one or more DLAs may be further optimized for a specific set of neural network types and floating-point operations and inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and generally significantly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and recognition and detection using data from a microphone; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for protection and / or safety related events.

[0188] In at least one embodiment, one or more DLAs can perform any function of one or more GPUs 1108, and by using an inference accelerator, for example, a designer can target any function to either one or more DLAs or one or more GPUs 1108. For example, in at least one embodiment, a designer can focus CNN processing and floating-point operations on one or more DLAs and leave other functions to one or more GPUs 1108 and / or one or more accelerators 1114.

[0189] In at least one embodiment, one or more accelerators 1114 may include a programmable vision accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1138, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0190] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0191] In at least one embodiment, the DMA can enable components of the PVA to access system memory independently of one or more CPUs 1106. In at least one embodiment, the DMA can support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0192] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can operate as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as, for example, a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed.

[0193] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Thus, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even different algorithms on a sequence of images or portions of an image. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security.

[0194] In at least one embodiment, one or more accelerators 1114 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to one or more accelerators 1114. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0195] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may conform to the International Organization for Standardization ("ISO") 26262 or the International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0196] In at least one embodiment, one or more SoCs 1104 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and extent of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0197] In at least one embodiment, one or more accelerators 1114 may have a wide range of uses for autonomous driving. In at least one embodiment, the PVA may be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the ability of the PVA at low power and low latency is well matched to the algorithmic domain that requires predictable processing. In other words, the PVA excels at semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, such as in vehicle 1100, the PVA may be designed to run classic computer vision algorithms because they can be efficient at object detection and integer math operations.

[0198] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, but this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0199] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used to perform time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0200] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence measurement for each object detection. In at least one embodiment, the confidence can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, the confidence measurement enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a high confidence detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 1166 associated with vehicle 1100 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1164 or one or more RADAR sensors 1160).

[0201] In at least one embodiment, one or more SoCs 1104 may include one or more data stores 1116 (e.g., memory). In at least one embodiment, one or more data stores 1116 may be on-chip memory of one or more SoCs 1104 that may store neural networks to be executed on one or more GPUs 1108 and / or DLAs. In at least one embodiment, one or more data stores 1116 may have a capacity large enough to store multiple instances of a neural network for redundancy and safety. In at least one embodiment, one or more data stores 1116 may include one or more L2 or L3 caches.

[0202] In at least one embodiment, one or more SoCs 1104 may include any number of processors 1110 (e.g., embedded processors). In at least one embodiment, one or more processors 1110 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and associated secure execution. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1104 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, manage one or more SoCs 1104 thermal and temperature sensors, and / or manage one or more SoCs 1104 power states. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1104 may use the ring oscillator to detect the temperature of one or more CPUs 1106, one or more GPUs 1108, and / or one or more accelerators 1114. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor can enter a temperature fault routine and place one or more SoCs 1104 into a lower power state and / or place the vehicle 1100 into a driver's safe parking mode (e.g., bringing the vehicle 1100 to a safe stop).

[0203] In at least one embodiment, one or more processors 1110 may further include a set of embedded processors that can serve as an audio processing engine, which can be an audio subsystem that implements full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0204] In at least one embodiment, one or more processors 1110 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0205] In at least one embodiment, one or more processors 1110 may further include a safety cluster engine, which may include but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safety mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may function as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1110 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1110 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of the camera processing pipeline.

[0206] In at least one embodiment, one or more processors 1110 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by a video playback application to produce a final image for use in a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1170, one or more surround cameras 1174, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of SoC 1104, the neural network being configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and place calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain features are available to the driver when the vehicle is operating in autonomous mode that would otherwise be disabled.

[0207] In at least one embodiment, the video image compositor can include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, in the presence of motion in the video, the noise reduction appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, in the presence of motion in the image or portion of an image, the temporal noise reduction performed by the video image compositor can use information from previous images to reduce noise in the current image.

[0208] In at least one embodiment, the video image compositor can also be configured to perform stereo rectification on the input stereo footage frames. In at least one embodiment, the video image compositor can also be used for user interface composition when the operating system desktop is being used, and does not require the one or more GPUs 1108 to continuously render new surfaces. In at least one embodiment, when the one or more GPUs 1108 are powered and active for 3D rendering, the video image compositor can be used to offload the one or more GPUs 1108 to improve performance and responsiveness.

[0209] In at least one embodiment, one or more of the SoCs 1104 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 1104 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0210] In at least one embodiment, one or more of the SoCs 1104 may further include a wide range of peripheral interfaces for enabling communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1104 may be configured to process data from cameras (e.g., connected via a Gigabit multimedia serial link and an Ethernet channel), sensors (e.g., one or more LIDAR sensors 1164, one or more RADAR sensors 1160, etc., which may be connected via an Ethernet channel), data from the bus 1102 (e.g., vehicle 1100 speed, steering wheel position, etc.), data from one or more GNSS sensors 1158 (e.g., connected via an Ethernet bus or a CAN bus), and the like. In at least one embodiment, one or more of the SoCs 1104 may further include dedicated high-performance large-scale memory controllers, which may include their own DMA engines and may be used to offload one or more of the CPUs 1106 from routine data management tasks.

[0211] In at least one embodiment, one or more SoCs 1104 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and provides a platform for flexible, reliable driving software stacks and deep learning tools. In at least one embodiment, one or more SoCs 1104 can be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1114, when combined with one or more CPUs 1106, one or more GPUs 1108, and one or more data stores 1116, can provide a fast, efficient platform for Level 3-5 autonomous vehicles.

[0212] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute various processing algorithms on various visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous vehicles.

[0213] The embodiments described herein allow for the execution of multiple neural networks simultaneously and / or sequentially, and for the results to be combined to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1120) may include text and word recognition, thereby allowing for the reading and understanding of traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that is capable of recognizing, interpreting, and providing semantic understanding of signs, and passing this semantic understanding to a path planning module running on the CPU complex.

[0214] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign stating "Caution: Flashing lights indicate icy conditions," along with electric lights, can be interpreted independently or collectively by several neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., an already trained neural network), and the text "Flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1108.

[0215] In at least one embodiment, a CNN for face recognition and vehicle owner recognition can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1100. In at least one embodiment, an always-on sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1104 provide protection against theft and / or carjacking.

[0216] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 1196 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1104 use a CNN to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, a CNN running on a DLA is trained to identify the relative approaching speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, as identified by one or more GNSS sensors 1158. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1162 to execute emergency vehicle safety routines, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0217] In at least one embodiment, the vehicle 1100 may include one or more CPUs 1118 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to the one or more SoCs 1104 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 1118 may include, for example, an X86 processor. The one or more CPUs 1118 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and the one or more SoCs 1104, and / or monitoring the status and health of one or more controllers 1136 and / or an infotainment system on a chip ("infotainment SoC") 1130. In at least one embodiment, the one or more SoCs 1104 include one or more interconnects, and the interconnects may include a Peripheral Component Interconnect Express (PCIe).

[0218] In at least one embodiment, the vehicle 1100 may include one or more GPUs 1120 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to the one or more SoCs 1104 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the one or more GPUs 1120 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on input from sensors of the vehicle 1100 (e.g., sensor data).

[0219] In at least one embodiment, vehicle 1100 may further include a network interface 1124, which may include, but is not limited to, one or more wireless antennas 1126 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1124 may be used to enable wireless connectivity to internet cloud services (e.g., to servers and / or other network devices), to other vehicles, and / or to computing devices (e.g., a passenger's client device). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1100 and the other vehicle, and / or an indirect link may be established (e.g., via a network and the internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1100 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1100). In at least one embodiment, this functionality may be part of the cooperative adaptive cruise control functionality of vehicle 1100.

[0220] In at least one embodiment, the network interface 1124 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 1136 to communicate over a wireless network. In at least one embodiment, the network interface 1124 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by a well-known process and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0221] In at least one embodiment, the vehicle 1100 may further include one or more data stores 1128, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoCs 1104) storage. In at least one embodiment, the one or more data stores 1128 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0222] In at least one embodiment, the vehicle 1100 may further include one or more GNSS sensors 1158 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1158 may be used, including, for example, but not limited to, GPS using a USB connector with an Ethernet to serial interface (e.g., RS-232) bridge.

[0223] In at least one embodiment, the vehicle 1100 may further include one or more RADAR sensors 1160. In at least one embodiment, the one or more RADAR sensors 1160 may be used by the vehicle 1100 for remote vehicle detection, even in darkness and / or in adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASILB. In at least one embodiment, the one or more RADAR sensors 1160 may use a CAN bus and / or bus 1102 (e.g., for transmitting data generated by the one or more RADAR sensors 1160) for control and access to object tracking data, and in some examples, an Ethernet channel may be accessed to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, the one or more RADAR sensors 1160 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the one or more RADAR sensors 1160 are pulse Doppler RADAR sensors.

[0224] In at least one embodiment, one or more RADAR sensors 1160 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved by two or more independent scans (e.g., within a range of 250m). In at least one embodiment, one or more RADAR sensors 1160 can help distinguish between static objects and moving objects and can be used by the ADAS system 1138 for emergency brake assistance and forward collision warning. In at least one embodiment, the one or more sensors 1160 included in the long-range RADAR system may include, but are not limited to, a monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, using six antennas, the central four antennas can create a focused beam pattern designed to record the surrounding environment of the vehicle 1100 at a higher speed with minimal interference from traffic in adjacent lanes. In at least one embodiment, the additional two antennas may extend the field of view, enabling it to quickly detect vehicles entering or leaving the lane of vehicle 1100 .

[0225] In at least one embodiment, as an example, a medium-range RADAR system may include a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1160 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the rear direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 1138 for blind spot detection and / or lane change assistance.

[0226] In at least one embodiment, the vehicle 1100 may further include one or more ultrasonic sensors 1162. In at least one embodiment, one or more ultrasonic sensors 1162, which may be positioned at the front, rear, and / or side of the vehicle 1100, may be used for parking assistance and / or for creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1162 may be used, and different ultrasonic sensors 1162 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1162 may operate at an ASIL B functional safety level.

[0227] In at least one embodiment, the vehicle 1100 can include one or more LIDAR sensors 1164. In at least one embodiment, the one or more LIDAR sensors 1164 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 1164 can operate at a functional safety level of ASIL B. In at least one embodiment, the vehicle 1100 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1164 that can use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0228] In at least one embodiment, one or more LIDAR sensors 1164 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1164 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-obtrusive LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1164 may comprise a small device that can be embedded in the front, rear, side, and / or corner locations of the vehicle 1100. In at least one embodiment, one or more LIDAR sensors 1164 may provide up to 120 degrees of horizontal field of view and 35 degrees of vertical field of view, even for low-reflectivity objects, and have a range of 200 meters. In at least one embodiment, the forward-mounted one or more LIDAR sensors 1164 may be configured for a horizontal field of view between 45 and 135 degrees.

[0229] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate up to approximately 200 meters around vehicle 1100. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 1100 to the object. In at least one embodiment, flash LIDAR can allow for the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 1100. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0230] In at least one embodiment, the vehicle 1100 may also include one or more IMU sensors 1166. In at least one embodiment, the one or more IMU sensors 1166 may be located at the center of the rear axle of the vehicle 1100. In at least one embodiment, the one or more IMU sensors 1166 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, the one or more IMU sensors 1166 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, the one or more IMU sensors 1166 may include, but not limited to, accelerometers, gyroscopes, and magnetometers.

[0231] In at least one embodiment, the one or more IMU sensors 1166 can be implemented as a miniature, high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical systems ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filter algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, the one or more IMU sensors 1166 can enable the vehicle 1100 to estimate its heading by directly observing and correlating velocity changes from GPS to the one or more IMU sensors 1166, without the need for input from a magnetic sensor. In at least one embodiment, the one or more IMU sensors 1166 and the one or more GNSS sensors 1158 can be combined in a single integrated unit.

[0232] In at least one embodiment, the vehicle 1100 can include one or more microphones 1196 positioned within and / or around the vehicle 1100. In at least one embodiment, the one or more microphones 1196 can be used for emergency vehicle detection and identification.

[0233] In at least one embodiment, the vehicle 1100 may further include any number of camera types, including one or more stereo cameras 1168, one or more wide angle cameras 1170, one or more infrared cameras 1172, one or more surround cameras 1174, one or more long range cameras 1198, one or more mid range cameras 1176, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 1100. In at least one embodiment, the type of camera used depends on the vehicle 1100. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1100. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1100 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example but not limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, the present disclosure previously referred to herein may provide a description of the camera types and the camera types used. Figure 11A and Figure 11B Each camera is described in more detail.

[0234] In at least one embodiment, the vehicle 1100 may further include one or more vibration sensors 1142. In at least one embodiment, the one or more vibration sensors 1142 may measure vibrations of a component (e.g., an axle) of the vehicle 1100. For example, in at least one embodiment, changes in vibration may indicate changes in the road surface. In at least one embodiment, when two or more vibration sensors 1142 are used, the difference between the vibrations may be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0235] In at least one embodiment, the vehicle 1100 may include an ADAS system 1138. In at least one embodiment, the ADAS system 1138 may include, in some examples, but is not limited to, an SoC. In at least one embodiment, the ADAS system 1138 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot alert ("BSW") systems, rear cross traffic alert ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0236] In at least one embodiment, the ACC system may utilize one or more RADAR sensors 1160, one or more LIDAR sensors 1164, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1100 and automatically adjusts the speed of the vehicle 1100 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system performs distance keeping and suggests that the vehicle 1100 change lanes when needed. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0237] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from the other vehicles indirectly via a wireless link or through a network connection (e.g., through the Internet) via a network interface 1124 and / or one or more wireless antennas 1126. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, V2V communications provide information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of vehicle 1100 and in the same lane as it), while I2V communications provide information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicle ahead of vehicle 1100, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0238] In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1160, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid brake pulses.

[0239] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can utilize one or more forward-facing cameras and / or one or more RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or collision approach braking.

[0240] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 1100 crosses a lane marking. In at least one embodiment, the LDW system does not activate when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may utilize a forward-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration assembly. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, if the vehicle 1100 begins to leave its lane, the LKA system provides steering input or braking to correct the vehicle 1100.

[0241] In at least one embodiment, the BSW system detects and warns the driver that a vehicle is in the car's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that it is unsafe to merge or change lanes. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0242] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when the vehicle 1100 detects an object outside the range of the rear camera while in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure that the vehicle's brakes are applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0243] In at least one embodiment, conventional ADAS systems can be prone to generating false positive results, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to decide whether a safe condition truly exists and take action accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1100 independently decides whether to follow the results of the primary computer or the secondary computer (e.g., the first or second controller in controller 1136). For example, in at least one embodiment, the ADAS system 1138 can be a backup and / or secondary computer that provides perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant software on hardware components to detect failures in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1138 can be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0244] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU that indicates the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the primary and secondary computers indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0245] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the secondary computer provides a false alarm based, at least in part, on output from the primary computer and output from the secondary computer. In at least one embodiment, the one or more neural networks in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the one or more neural networks in the supervisory MCU can learn when the FCW system is identifying a metal object that is not actually a danger, such as a drain grate or manhole cover, that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override LDW when a cyclist or pedestrian is present and lane departure is actually the safest action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU can include and / or be included as a component of one or more SoCs 1104.

[0246] In at least one embodiment, the ADAS system 1138 may include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially with respect to failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or bug in the software running on the main computer, and non-identical software code running on the auxiliary computer provides consistent overall results, the supervisory MCU may have greater confidence that the overall result is correct and that the vulnerability in the software or hardware on the main computer did not cause a significant error.

[0247] In at least one embodiment, the output of the ADAS system 1138 can be fed into the primary computer's perception block and / or the primary computer's dynamic driving task block. For example, in at least one embodiment, if the ADAS system 1138 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when the object is identified. In at least one embodiment, the secondary computer can have its own neural network that has been trained, as described herein, to reduce the risk of false positives.

[0248] In at least one embodiment, the vehicle 1100 may further include an infotainment SoC 1130 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1130 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1130 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 1100. For example, the infotainment SoC 1130 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connectivity, an onboard computer, an onboard entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a head-up display ("HUD"), an HMI display 1134, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1130 may be further configured to provide information (e.g., visual and / or auditory information) to one or more users of the vehicle 1100, such as information from the ADAS system 1138, autonomous driving information (e.g., planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0249] In at least one embodiment, the infotainment SoC 1130 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1130 can communicate with other devices, systems, and / or components of the vehicle 1100 via the bus 1102. In at least one embodiment, the infotainment SoC 1130 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event that one or more of the main controllers 1136 (e.g., the vehicle's 1100 main computer and / or backup computer) fails. In at least one embodiment, the infotainment SoC 1130 can place the vehicle 1100 in a driver-to-safety parking mode, as described herein.

[0250] In at least one embodiment, the vehicle 1100 may further include an instrument panel 1132 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the instrument panel 1132 may include, but is not limited to, a controller and / or a supercomputer (e.g., a separate controller or a supercomputer). In at least one embodiment, the instrument panel 1132 may include, but is not limited to, a set of instruments in any number and combination, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a gear position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine check lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1130 and the instrument panel 1132. In at least one embodiment, the instrument panel 1132 may be included as part of the infotainment SoC 1130, or vice versa.

[0251] In at least one embodiment, Figure 11C One or more methods, systems or processes are described for using various algorithms, formulas and processes (e.g., in combination with Figure 1 In at least one embodiment, the present invention provides a method for generating a second video of a robotic device performing a task using one or more first videos of the robotic device performing the task in a manner different from that depicted in the one or more first videos, and / or otherwise performing the operations described herein. Figure 11C One or more systems described in are used to implement such as Figure 1-7 One or more systems and / or processes such as those described.

[0252] Figure 11D In accordance with at least one embodiment, one or more cloud-based servers and Figure 11AFIG1 is a diagram of a system for communicating between autonomous vehicles 1100. In at least one embodiment, the system may include, but is not limited to, one or more servers 1178, one or more networks 1190, and any number and type of vehicles, including vehicle 1100. In at least one embodiment, one or more servers 1178 may include, but is not limited to, multiple GPUs 1184(A)-1184(H) (collectively referred to herein as GPUs 1184), PCIe switches 1182(A)-1182(D) (collectively referred to herein as PCIe switches 1182), and / or CPUs 1180(A)-1180(B) (collectively referred to herein as CPUs 1180). In at least one embodiment, GPUs 1184, CPUs 1180, and PCIe switches 1182 may be interconnected using a high-speed interconnect, such as, for example, but not limited to, NVLink interface 1188 and / or PCIe connection 1186 developed by NVIDIA. In at least one embodiment, the GPUs 1184 are connected via NVLink and / or NVSwitch SoCs, and the GPUs 1184 and PCIe switches 1182 are connected via PCIe interconnects. Although eight GPUs 1184, two CPUs 1180, and four PCIe switches 1182 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1178 may include, but is not limited to, any number of GPUs 1184, CPUs 1180, and / or PCIe switches 1182 in any combination. For example, in at least one embodiment, one or more servers 1178 may each include eight, sixteen, thirty-two, and / or more GPUs 1184.

[0253] In at least one embodiment, one or more servers 1178 may receive image data representing an image from a vehicle via one or more networks 1190 that depicts unexpected or altered road conditions, such as recently begun roadwork. In at least one embodiment, one or more servers 1178 may transmit updated neural networks 1192 and / or map information 1194 to the vehicle via one or more networks 1190, including, but not limited to, information regarding traffic and road conditions. In at least one embodiment, updates to map information 1194 may include, but are not limited to, updates to HD map 1122, such as information regarding construction sites, potholes, service roads, flooding, and / or other obstacles. In at least one embodiment, neural networks 1192 and / or map information 1194 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or based at least on training performed at a data center (e.g., using one or more servers 1178 and / or other servers).

[0254] In at least one embodiment, one or more servers 1178 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., sent to the vehicle via one or more networks 1190, and / or the machine learning model can be used by one or more servers 1178 to remotely monitor the vehicle.

[0255] In at least one embodiment, one or more servers 1178 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 1178 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1184, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1178 can include the deep learning infrastructure of a data center using CPU power.

[0256] In at least one embodiment, the deep learning infrastructure of one or more servers 1178 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or associated hardware in the vehicle 1100. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1100, such as an image sequence and / or objects that the vehicle 1100 has located in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 1100, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1100 is malfunctioning, the one or more servers 1178 may send a signal to the vehicle 1100 instructing the vehicle's 1100 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0257] In at least one embodiment, one or more servers 1178 may include one or more GPUs 1184 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time responses. In at least one embodiment, such as in situations where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, one or more hardware structures 815 are used to execute one or more embodiments. Figure 8A and / or Figure 8B Provides details about the hardware structure 815.

[0258] Computer system

[0259] Figure 12 1 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include an execution unit for executing instructions. In at least one embodiment, in accordance with the present disclosure, such as in the embodiments described herein, computer system 1200 may include, but is not limited to, components such as processor 1202 for executing algorithms for processing data using execution units (including logic). In at least one embodiment, computer system 1200 may include a processor such as the Intel Corporation of Santa Clara, California. Processor family, Xeon TM 、 XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1200 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0260] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0261] In at least one embodiment, the computer system 1200 may include, but is not limited to, a processor 1202, which may include, but is not limited to, one or more execution units 1208 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 1200 is a single-processor desktop or server system, but in another embodiment, the computer system 1200 may be a multi-processor system. In at least one embodiment, the processor 1202 may include, but is not limited to, for example, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1202 may be coupled to a processor bus 1210, which may transmit data signals between the processor 1202 and other components in the computer system 1200.

[0262] In at least one embodiment, processor 1202 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1204. In at least one embodiment, processor 1202 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1202. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 1206 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0263] In at least one embodiment, an execution unit 1208, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1202. In at least one embodiment, the processor 1202 may also include a microcode ("ucode") read-only memory ("ROM") that stores microcode for certain macroinstructions. In at least one embodiment, the execution unit 1208 may include logic for processing a packed instruction set 1209. In at least one embodiment, by including the packed instruction set 1209 in the instruction set of a general-purpose processor and the associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the processor 1202. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0264] In at least one embodiment, execution unit 1208 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1200 may include, but is not limited to, memory 1220. In at least one embodiment, memory 1220 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 1220 may store one or more instructions 1219 and / or data 1221 represented by data signals that may be executed by processor 1202.

[0265] In at least one embodiment, the system logic chip can be coupled to the processor bus 1210 and the memory 1220. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1216, and the processor 1202 can communicate with the MCH 1216 via the processor bus 1210. In at least one embodiment, the MCH 1216 can provide a high-bandwidth memory path 1218 to the memory 1220 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1216 can direct data signals between the processor 1202, the memory 1220, and other components in the computer system 1200, and bridge data signals between the processor bus 1210, the memory 1220, and the system I / O interface 1222. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1216 may be coupled to the memory 1220 via a high-bandwidth memory path 1218 , and the graphics / video card 1212 may be coupled to the MCH 1216 via an accelerated graphics port (“AGP”) interconnect 1214 .

[0266] In at least one embodiment, the computer system 1200 can use the system I / O interface 1222 as a proprietary hub interface bus to couple the MCH 1216 to the I / O controller hub ("ICH") 1230. In at least one embodiment, the ICH 1230 can provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus can include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to the memory 1220, the chipset, and the processor 1202. Examples can include, but are not limited to, an audio controller 1229, a firmware hub ("flash BIOS") 1228, a wireless transceiver 1226, a data store 1224, a traditional I / O controller 1223 including a user input and keyboard interface 1225, a serial expansion port 1227 (such as a universal serial bus ("USB") port), and a network controller 1234. In at least one embodiment, the data store 1224 can include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0267] In at least one embodiment, Figure 12 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 12 An exemplary SoC may be shown. In at least one embodiment, Figure 12The devices shown in FIG1200 may be interconnected using a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1200 are interconnected using a Compute Express Link (CXL) interconnect.

[0268] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 can be used in a computer system to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0269] In at least one embodiment, Figure 12 One or more methods, systems or processes are described for using various algorithms, formulas and processes (e.g., in combination with Figure 1 In at least one embodiment, the present invention provides a method for generating a second video of a robotic device performing a task using one or more first videos of the robotic device performing the task in a manner different from that depicted in the one or more first videos, and / or otherwise performing the operations described herein. Figure 12 One or more systems described in are used to implement such as Figure 1-7 One or more systems and / or processes such as those described.

[0270] Figure 13 1 is a block diagram illustrating an electronic device 1300 for utilizing a processor 1310 in accordance with at least one embodiment. In at least one embodiment, the electronic device 1300 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0271] In at least one embodiment, the electronic device 1300 may include, but is not limited to, a processor 1310 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1310 is coupled using a bus or interface, such as an I 2 C bus, System Management Bus ("SMBus"), Low Pin Count (LPC) bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advanced Technology Attachment ("SATA") bus, Universal Serial Bus ("USB") (Revision 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Figure 13 shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 13 An exemplary SoC may be shown. In at least one embodiment, Figure 13 The devices shown in can be interconnected using a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 13 One or more components of the system are interconnected using a Compute Express Link (CXL) interconnect.

[0272] In at least one embodiment, Figure 13 It may include a display 1324, a touch screen 1325, a touchpad 1330, a near field communication unit (“NFC”) 1345, a sensor hub 1340, a thermal sensor 1346, an express chipset (“EC”) 1335, a trusted platform module (“TPM”) 1338, BIOS / firmware / flash memory (“BIOS, FW Flash”) 1322, a DSP 1360, a drive 1320 (such as a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1350, a Bluetooth unit 1352, a wireless wide area network unit (“WWAN”) 1356, a global positioning system (GPS) unit 1355, a camera (“USB 3.0 camera”) 1354 (such as a USB 3.0 camera), and / or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1315 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0273] In at least one embodiment, other components may be communicatively coupled to processor 1310 via the components described herein. In at least one embodiment, an accelerometer 1341, an ambient light sensor (“ALS”) 1342, a compass 1343, and a gyroscope 1344 may be communicatively coupled to sensor hub 1340. In at least one embodiment, a thermal sensor 1339, a fan 1337, a keyboard 1336, and a touchpad 1330 may be communicatively coupled to EC 1335. In at least one embodiment, a speaker 1363, an earpiece 1364, and a microphone (“mic”) 1365 may be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 1362, which in turn may be communicatively coupled to DSP 1360. In at least one embodiment, audio unit 1362 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a SIM card (“SIM”) 1357 may be communicatively coupled to WWAN unit 1356. In at least one embodiment, components such as the WLAN unit 1350 and the Bluetooth unit 1352 and the WWAN unit 1356 may be implemented as a next generation form factor ("NGFF").

[0274] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in electronic device 1300 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0275] In at least one embodiment, Figure 13 One or more methods, systems or processes are described for using various algorithms, formulas and processes (e.g., in combination with Figure 1 In at least one embodiment, the present invention provides a method for generating a second video of a robotic device performing a task using one or more first videos of the robotic device performing the task in a manner different from that depicted in the one or more first videos, and / or otherwise performing the operations described herein. Figure 13 One or more systems described in are used to implement such as Figure 1-7 One or more systems and / or processes such as those described.

[0276] Figure 14 A computer system 1400 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1400 is configured to implement the various processes and methods described throughout this disclosure.

[0277] In at least one embodiment, computer system 1400 includes, but is not limited to, at least one central processing unit ("CPU") 1402 connected to a communication bus 1410 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1400 includes, but is not limited to, main memory 1404 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1404, which may take the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1422 provides an interface to other computing devices and networks for receiving data from and sending data to other systems using computer system 1400.

[0278] In at least one embodiment, computer system 1400 includes, but is not limited to, input device 1408, parallel processing system 1412, and display device 1406, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diode ("LED") displays, plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1408 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein can be located on a single semiconductor platform to form a processing system.

[0279] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding inference and / or training logic 815. In at least one embodiment, logic 815 can be used in computer system 1400 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0280] In at least one embodiment, Figure 14 One or more methods, systems or processes are described for using various algorithms, formulas and processes (e.g., in combination with Figure 1 In at least one embodiment, the present invention provides a method for generating a second video of a robotic device performing a task using one or more first videos of the robotic device performing the task in a manner different from that depicted in the one or more first videos, and / or otherwise performing the operations described herein. Figure 14 One or more systems described in are used to implement such as Figure 1-7 One or more systems and / or processes such as those described.

[0281] Figure 15 A computer system 1500 is shown according to at least one embodiment. In at least one embodiment, computer system 1500 includes, but is not limited to, a computer 1510 and a USB drive 1520. In at least one embodiment, computer 1510 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1510 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0282] In at least one embodiment, the USB disk 1520 includes, but is not limited to, a processing unit 1530, a USB interface 1540, and USB interface logic 1550. In at least one embodiment, the processing unit 1530 may be any instruction execution system, device, or apparatus capable of executing instructions. In at least one embodiment, the processing unit 1530 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1530 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1530 is a tensor processing unit ("TPC") that is optimized to perform machine learning reasoning operations. In at least one embodiment, the processing unit 1530 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

[0283] In at least one embodiment, USB interface 1540 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1540 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1540 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1550 can include any number and type of logic that enables processing unit 1530 to interface with a device (e.g., computer 1510) via USB connector 1540.

[0284] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8BDetails are provided regarding logic 815. In at least one embodiment, logic 815 can be used in computer system 1500 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0285] In at least one embodiment, Figure 15 One or more methods, systems or processes are described for using various algorithms, formulas and processes (e.g., in combination with Figure 1 In at least one embodiment, the present invention provides a method for generating a second video of a robotic device performing a task using one or more first videos of the robotic device performing the task in a manner different from that depicted in the one or more first videos, and / or otherwise performing the operations described herein. Figure 15 One or more systems described in are used to implement such as Figure 1-7 One or more systems and / or processes such as those described.

[0286] Figure 16A An exemplary architecture is shown in which a plurality of GPUs 1610(1)-1610(N) are communicatively coupled to a plurality of multi-core processors 1605(1)-1605(M) via high-speed links 1640(1)-1640(N) (e.g., a bus, a point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1640(1)-1640(N) support 4GB / s, 30GB / s, 80GB / s, or higher communication throughput. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure. In at least one embodiment, as Figure 19A and Figure 19B As disclosed, one or more of the plurality of GPUs 1610(1)-1610(N) include one or more graphics cores (also referred to simply as "cores") 1900. In at least one embodiment, the one or more graphics cores 1900 may be referred to as a streaming multiprocessor ("SM"), a streaming processor ("SP"), a streaming processing unit ("SPU"), a compute unit ("CU"), an execution unit ("EU"), and / or a slice, where a slice in this context may refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or a scheduler).

[0287] Furthermore, in at least one embodiment, two or more GPUs 1610 are interconnected via high-speed links 1629(1)-1629(2), which may be implemented using protocols / links similar to or different from those used for high-speed links 1640(1)-1640(N). Similarly, two or more multi-core processors 1605 may be connected via high-speed link 1628, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links may be used (e.g., via a common interconnect fabric) to accomplish this. Figure 16A All communications between the various system components shown in . In at least one embodiment, one or more of the plurality of GPUs 1610(1)-1610(N) include Figure 19A and 19B Disclosed are one or more graphics cores (which may also be referred to simply as "cores") 1900. In at least one embodiment, one or more graphics cores 1900 may be referred to as a streaming multiprocessor ("SM"), a streaming processor ("SP"), a streaming processing unit ("SPU"), a compute unit ("CU"), an execution unit ("EU"), and / or a slice, where a slice in this context may refer to a portion of processing resources in a processing unit (e.g., a 16-core, a ray tracing unit, a thread director, or a scheduler).

[0288] In at least one embodiment, each multi-core processor 1605 is communicatively coupled to processor memory 1601(1)-1601(M) via memory interconnects 1626(1)-1626(M), respectively, and each GPU 1610(1)-1610(N) is communicatively coupled to GPU memory 1620(1)-1620(N) via GPU memory interconnects 1650(1)-1650(N), respectively. In at least one embodiment, memory interconnects 1626 and 1650 can utilize similar or different memory access technologies. By way of example and not limitation, processor memory 1601(1)-1601(M) and GPU memory 1620 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of the processor memory 1601 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0289] As described herein, although each multi-core processor 1605 and GPU 1610 can be physically coupled to a specific memory 1601, 1620, respectively, and / or a unified memory architecture can be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. For example, processor memories 1601(1)-1601(M) can each include 64GB of system memory address space, and GPU memories 1620(1)-1620(N) can each include 32GB of system memory address space, resulting in a total of 256GB of addressable memory when M=2 and N=4. Other values ​​of N and M are possible.

[0290] Figure 16B Additional details are shown for the interconnection between multi-core processor 1607 and graphics acceleration module 1646 according to an exemplary embodiment. In at least one embodiment, graphics acceleration module 1646 may include one or more GPU chips integrated on a line card that is coupled to processor 1607 via a high-speed link 1640 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, graphics acceleration module 1646 may alternatively be integrated on a package or chip with processor 1607.

[0291] In at least one embodiment, processor 1607 includes multiple cores 1660A-1660D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 1661A-1661D and one or more caches 1662A-1662D. In at least one embodiment, cores 1660A-1660D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, caches 1662A-1662D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1656 may be included in caches 1662A-1662D and shared by groups of cores 1660A-1660D. For example, one embodiment of processor 1607 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1607 and the graphics acceleration module 1646 are connected to the system memory 1614, which may include Figure 16A Processor memory 1601(1)-1601(M) in.

[0292] In at least one embodiment, coherency is maintained for data and instructions stored in the various caches 1662A-1662D, 1656 and system memory 1614 via inter-core communication over a coherency bus 1664. In at least one embodiment, for example, each cache may have cache coherency logic / circuitry associated therewith to communicate over the coherency bus 1664 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented over the coherence bus 1664 to snoop cache accesses.

[0293] In at least one embodiment, proxy circuitry 1625 communicatively couples graphics acceleration module 1646 to coherence bus 1664, thereby allowing graphics acceleration module 1646 to participate in a cache coherence protocol as a peer of cores 1660A-1660D. In particular, in at least one embodiment, interface 1635 provides connectivity to proxy circuitry 1625 via high-speed link 1640, and interface 1637 connects graphics acceleration module 1646 to high-speed link 1640.

[0294] In at least one embodiment, the accelerator integrated circuit 1636 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1631(1)-1631(N) of the graphics acceleration module 1646. In at least one embodiment, the graphics processing engines 1631(1)-1631(N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, the multiple graphics processing engines 1631(1)-1631(N) of the graphics acceleration module 1646 comprise a combination of Figure 19A and Figure 19B The one or more graphics cores 1900 discussed. In at least one embodiment, the graphics processing engines 1631(1)-1631(N) may alternatively include different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1646 may be a GPU having multiple graphics processing engines 1631(1)-1631(N), or the graphics processing engines 1631(1)-1631(N) may be individual GPUs integrated on a common package, circuit card, or chip.

[0295] In at least one embodiment, the accelerator integrated circuit 1636 includes a memory management unit (MMU) 1639 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation), and a memory access protocol for accessing system memory 1614. In at least one embodiment, the MMU 1639 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, a cache 1638 may store commands and data for efficient access by the graphics processing engines 1631(1)-1631(N). In at least one embodiment, a fetch unit 1644 may be used to keep data stored in the cache 1638 and graphics memory 1633(1)-1633(M) consistent with the core caches 1662A-1662D, 1656, and system memory 1614. As previously described, this can be implemented on behalf of cache 1638 and memory 1633(1)-1633(M) via proxy circuit 1625 (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1662A-1662D, 1656 to cache 1638 and receiving updates from cache 1638).

[0296] In at least one embodiment, a set of registers 1645 stores context data for threads executed by graphics processing engines 1631(1)-1631(N), and context management circuitry 1648 manages thread contexts. For example, context management circuitry 1648 can perform save and restore operations to save and restore contexts for various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1648 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​can then be restored upon returning to the context. In at least one embodiment, interrupt management circuitry 1647 receives and processes interrupts received from system devices.

[0297] In at least one embodiment, the MMU 1639 converts virtual / effective addresses from the graphics processing engine 1631 into real / physical addresses in the system memory 1614. In at least one embodiment, the accelerator integrated circuit 1636 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1646 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1646 can be dedicated to a single application executing on the processor 1607, or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1631 (1)-1631 (N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0298] In at least one embodiment, the accelerator integrated circuit 1636 acts as a bridge to the system for the graphics acceleration module 1646 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1636 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1631(1)-1631(N).

[0299] In at least one embodiment, because the hardware resources of graphics processing engines 1631(1)-1631(N) are explicitly mapped into the real address space seen by host processor 1607, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1636 is the physical separation of graphics processing engines 1631(1)-1631(N) so that they appear to the system as independent units.

[0300] In at least one embodiment, one or more graphics memories 1633(1)-1633(M) are coupled to each graphics processing engine 1631(1)-1631(N), respectively, with N=M. In at least one embodiment, graphics memories 1633(1)-1633(M) store instructions and data being processed by each graphics processing engine 1631(1)-1631(N). In at least one embodiment, graphics memories 1633(1)-1633(M) can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0301] In at least one embodiment, to reduce data traffic on high-speed link 1640, a biasing technique may be used to ensure that the data stored in graphics memory 1633(1)-1633(M) is the data most frequently used by graphics processing engines 1631(1)-1631(N), and preferably is not used (at least not frequently) by cores 1660A-1660D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not needed by graphics processing engines 1631(1)-1631(N)) in caches 1662A-1662D, 1656, and system memory 1614.

[0302] Figure 16C Another exemplary embodiment is shown in which an accelerator integrated circuit 1636 is integrated within the processor 1607. In this embodiment, the graphics processing engines 1631(1)-1631(N) communicate directly with the accelerator integrated circuit 1636 via interface 1637 and interface 1635 (again, which can be any form of bus or interface protocol) over a high-speed link 1640. In at least one embodiment, the accelerator integrated circuit 1636 can perform operations related to Figure 16B The operations described above are similar to those described above, but may have higher throughput due to its close proximity to the coherence bus 1664 and caches 1662A-1662D, 1656. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1636 and a programming model controlled by the graphics acceleration module 1646.

[0303] In at least one embodiment, graphics processing engines 1631(1)-1631(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1631(1)-1631(N), thereby providing virtualization within a VM / partition.

[0304] In at least one embodiment, graphics processing engines 1631(1)-1631(N) can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize graphics processing engines 1631(1)-1631(N) to allow each operating system to access them. In at least one embodiment, for a single partition system without a hypervisor, the operating system owns graphics processing engines 1631(1)-1631(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1631(1)-1631(N) to provide access to each process or application.

[0305] In at least one embodiment, the graphics acceleration module 1646 or individual graphics processing engines 1631(1)-1631(N) use a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1614 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1631(1)-1631(N) (i.e., calling system software to add the process element to a linked list of process elements). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the linked list of process elements.

[0306] Figure 16D An exemplary accelerator integrated slice 1690 is shown. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of the accelerator integrated circuit 1636. In at least one embodiment, the application is an effective address space 1682 in system memory 1614, which stores a process element 1683. In at least one embodiment, the process element 1683 is stored in response to a GPU call 1681 from the application 1680 executing on the processor 1607. In at least one embodiment, the process element 1683 contains the process state of the corresponding application 1680. In at least one embodiment, the work descriptor (WD) 1684 contained in the process element 1683 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 1684 is a pointer to a job request queue in the effective address space 1682 of the application.

[0307] In at least one embodiment, the graphics acceleration module 1646 and / or the individual graphics processing engines 1631(1)-1631(N) can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure can be included for setting process state and sending WD 1684 to the graphics acceleration module 1646 to start a job in a virtualized environment.

[0308] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns a graphics acceleration module 1646 or an individual graphics processing engine 1631. In at least one embodiment, when a graphics acceleration module 1646 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when a graphics acceleration module 1646 is assigned, the operating system initializes the accelerator integrated circuit 1636 for the owned process.

[0309] In operation, in at least one embodiment, a WD fetch unit 1691 in the accelerator integrated slice 1690 fetches a next WD 1684, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1646. In at least one embodiment, data from the WD 1684 may be stored in registers 1645 and used by the MMU 1639, interrupt management circuitry 1647, and / or context management circuitry 1648, as shown. For example, one embodiment of the MMU 1639 includes segment / page walk circuitry for accessing segment / page tables 1686 within the OS virtual address space 1685. In at least one embodiment, the interrupt management circuitry 1647 may process interrupt events 1692 received from the graphics acceleration module 1646. In at least one embodiment, when performing graphics operations, effective addresses 1693 generated by the graphics processing engines 1631(1)-1631(N) are converted to real addresses by the MMU 1639.

[0310] In at least one embodiment, registers 1645 are replicated for each graphics processing engine 1631(1)-1631(N) and / or graphics acceleration module 1646, and these registers 1645 can be initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers can be included in an accelerator integration slice 1690. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0311] Table 1 – Registers initialized by the hypervisor

[0312]

[0313]

[0314] Example registers that may be initialized by the operating system are shown in Table 2.

[0315] Table 2 – Registers initialized by the operating system

[0316]

[0317] In at least one embodiment, each WD 1684 is specific to a particular graphics acceleration module 1646 and / or graphics processing engine 1631(1)-1631(N). In at least one embodiment, it contains all the information needed by the graphics processing engine 1631(1)-1631(N) to complete its work, or it may be a pointer to a memory location where an application has set up a command queue for work to be done.

[0318] Figure 16E 16. Additional details of an exemplary embodiment of a sharing model are shown. This embodiment includes a hypervisor real address space 1698 in which a process element list 1699 is stored. In at least one embodiment, the hypervisor real address space 1698 is accessible via a hypervisor 1696 that virtualizes a graphics acceleration module engine for an operating system 1695.

[0319] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1646. In at least one embodiment, there are two programming models where the graphics acceleration module 1646 is shared by multiple processes and partitions, namely, time-sliced ​​sharing and graphics-directed sharing.

[0320] In at least one embodiment, in this model, the hypervisor 1696 owns the graphics acceleration module 1646 and makes its functionality available to all operating systems 1695. In at least one embodiment, for the graphics acceleration module 1646 to support virtualization through the hypervisor 1696, the graphics acceleration module 1646 may adhere to certain requirements, such as (1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1646 must provide a context save and restore mechanism, (2) the graphics acceleration module 1646 guarantees that the application's job requests are completed within a specified amount of time, including any transition errors, or the graphics acceleration module 1646 provides the ability to preempt job processing, and (3) the graphics acceleration module 1646 must ensure fairness between processes when operating in a directed shared programming model.

[0321] In at least one embodiment, the application 1680 is required to make an operating system 1695 system call using a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1646 and can take the form of a graphics acceleration module 1646 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure that describes the work to be performed by the graphics acceleration module 1646.

[0322] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that set the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1636 (not shown) and the graphics acceleration module 1646 does not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1696 may selectively apply the current AMR value before placing the AMR into the process element 1683. In at least one embodiment, the CSRP is one of the registers 1645 that contains the effective address of an area in the application's effective address space 1682 for the graphics acceleration module 1646 to save and restore context state. In at least one embodiment, this pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be fixed system memory.

[0323] Upon receiving the system call, the operating system 1695 can verify that the application 1680 has been registered and granted permission to use the graphics acceleration module 1646. Then, in at least one embodiment, the operating system 1695 calls the hypervisor 1696 using the information shown in Table 3.

[0324] Table 3 – OS to Hypervisor call parameters

[0325]

[0326] In at least one embodiment, upon receiving the hypervisor call, hypervisor 1696 verifies that operating system 1695 has registered and been granted permission to use graphics acceleration module 1646. Then, in at least one embodiment, hypervisor 1696 places process element 1683 into a linked list of process elements of the corresponding type of graphics acceleration module 1646. In at least one embodiment, the process element may include the information shown in Table 4.

[0327] Table 4 – Process element information

[0328]

[0329] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1690 registers 1645 .

[0330] like Figure 16F As shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memory 1601(1)-1601(N) and GPU memory 1620(1)-1620(N). In this implementation, operations executed on GPUs 1610(1)-1610(N) utilize the same virtual / effective memory address space to access processor memory 1601(1)-1601(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1601(1), a second portion is allocated to second processor memory 1601(N), a third portion is allocated to GPU memory 1620(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1601 and GPU memory 1620, thereby allowing any processor or GPU to access any physical memory using a virtual address mapped to that memory.

[0331] In at least one embodiment, bias / coherency management circuitry 1694A-1694E within one or more MMUs 1639A-1639E ensures cache coherency between the caches of one or more host processors (e.g., 1605) and GPU 1610 and implements biasing techniques that indicate the physical memory where certain types of data should be stored. Figure 16F Multiple instances of bias / coherence management circuits 1694A- 1694E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 1605 and / or within an accelerator integrated circuit 1636 .

[0332] One embodiment allows GPU memory 1620 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without the performance drawbacks associated with system-wide cache coherence. In at least one embodiment, the ability to access GPU memory 1620 as system memory without the heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows host processor 1605 software to set operands and access computation results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1620 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in situations with heavy streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1610. In at least one embodiment, the efficiency of operand setup, result access, and GPU computation can play a role in determining the effectiveness of GPU offloading.

[0333] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU additional memory page. In at least one embodiment, the bias table can be implemented in a stolen memory range of one or more GPU memories 1620, with or without a bias cache in GPU 1610 (e.g., for caching frequently / recently used entries in the bias table). Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0334] In at least one embodiment, the bias table entry associated with each access to GPU-attached memory 1620 is accessed before the GPU memory is actually accessed, resulting in the following operations. In at least one embodiment, local requests from GPU 1610 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1620. In at least one embodiment, local requests from the GPU whose pages are found in the host bias are forwarded to processor 1605 (e.g., via the high-speed link described herein). In at least one embodiment, requests from processor 1605 that find the requested page in the host processor bias complete the request similarly to a normal memory read. Alternatively, requests directed to GPU-biased pages can be forwarded to GPU 1610. In at least one embodiment, if the GPU is not currently using the page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in a limited set of cases, a purely hardware-based mechanism.

[0335] In at least one embodiment, a mechanism for changing bias states employs an API call (e.g., OpenCL), which in turn calls a device driver for the GPU, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1605 bias to GPU bias, but not for the reverse migration.

[0336] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1605. In at least one embodiment, to access these pages, processor 1605 may request access from GPU 1610, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between processor 1605 and GPU 1610, it is beneficial to ensure that GPU-biased pages are the pages required by the GPU and not the host processor 1605, and vice versa.

[0337] One or more hardware structures 815 are used to execute one or more embodiments. Figure 8A and / or Figure 8B Details regarding one or more hardware structures 815 are provided.

[0338] Figure 17An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to those shown, other logic and circuits may also be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0339] Figure 17 1700 is a block diagram illustrating an exemplary system on a chip integrated circuit 1700 that can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1700 includes one or more application processors 1705 (e.g., CPUs), at least one graphics processor 1710, and may additionally include an image processor 1715 and / or a video processor 1720, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1700 includes peripheral or bus logic including a USB controller 1725, a UART controller 1730, an SPI / SDIO controller 1735, and an I / O controller. 2 S / I 2 IC controller 1740. In at least one embodiment, integrated circuit 1700 may include a display device 1745 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1750 and a Mobile Industry Processor Interface (MIPI) display interface 1755. In at least one embodiment, storage may be provided by a flash memory subsystem 1760, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1765 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1770.

[0340] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in integrated circuit 1700 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0341] In at least one embodiment, Figure 17 One or more methods, systems or processes are described for using various algorithms, formulas and processes (e.g., in combination with Figure 1In at least one embodiment, the present invention provides a method for generating a second video of a robotic device performing a task using one or more first videos of the robotic device performing the task in a manner different from that depicted in the one or more first videos, and / or otherwise performing the operations described herein. Figure 17 One or more systems described in are used to implement such as Figure 1-7 One or more systems and / or processes such as those described.

[0342] Figures 18A-18B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to those shown, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0343] Figures 18A-18B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 18A An exemplary graphics processor 1810 of a system-on-chip integrated circuit is shown, which may be fabricated using one or more IP cores, in accordance with at least one embodiment. Figure 18B An additional exemplary graphics processor 1840 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 18A The graphics processor 1810 is a low-power graphics processor core. In at least one embodiment, Figure 18B The graphics processor 1840 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1810, 1840 can be Figure 17 A variation of the graphics processor 1710 .

[0344] In at least one embodiment, the graphics processor 1810 includes a vertex processor 1805 and one or more fragment processors 1815A-1815N (e.g., 1815A, 1815B, 1815C, 1815D through 1815N-1 and 1815N). In at least one embodiment, the graphics processor 1810 can execute different shader programs via separate logic, such that the vertex processor 1805 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1815A-1815N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1805 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1815A-1815N use the primitives and vertex data generated by the vertex processor 1805 to generate a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 1815A-1815N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0345] In at least one embodiment, the graphics processor 1810 additionally includes one or more memory management units (MMUs) 1820A-1820B, one or more caches 1825A-1825B, and one or more circuit interconnects 1830A-1830B. In at least one embodiment, the one or more MMUs 1820A-1820B provide virtual to physical address mapping for the graphics processor 1810 (including for the vertex processor 1805 and / or the fragment processors 1815A-1815N), which can reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 1825A-1825B. In at least one embodiment, the one or more MMUs 1820A-1820B can synchronize with other MMUs within the system, including with Figure 17 One or more MMUs associated with one or more application processors 1705, graphics processor 1715, and / or video processor 1720 enable each processor 1705-1720 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1830A-1830B enable graphics processor 1810 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0346] In at least one embodiment, graphics processor 1840 includes: Figure 18B One or more shader cores 1855A-1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F through 1855N-1 and 1855N) are shown, which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1840 includes an inter-core task manager 1845 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1855A-1855N and a tiling unit 1858 to accelerate tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within the scene or to optimize the use of internal caches.

[0347] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in graphics processors 1810 and / or 1840 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0348] In at least one embodiment, Figures 18A-18B One or more methods, systems or processes are described for using various algorithms, formulas and processes (e.g., in combination with Figure 1 In at least one embodiment, the present invention provides a method for generating a second video of a robotic device performing a task using one or more first videos of the robotic device performing the task in a manner different from that depicted in the one or more first videos, and / or otherwise performing the operations described herein. Figures 18A-18B One or more systems described in are used to implement such as Figure 1-7 One or more systems and / or processes such as those described.

[0349] Figures 19A-19B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figures 19A-19B Shown in and about Figures 19A-19B The components described are integrated into a single system, such as a graphics processing unit (GPU), SoC, or other type of processor. In at least one embodiment, Figure 19AShows that can be included in Figure 17 Graphics core 1900 within graphics processor 1710 of FIG. 17 and, in at least one embodiment, may be such as Figure 18B Unified shader cores 1855A-1855N are shown. Figure 19B A highly parallel general-purpose graphics processing unit ("GPGPU," which may be referred to as a "graphics processing unit") 1930 suitable for deployment on a multi-chip module in at least one embodiment is shown. In at least one embodiment, graphics processing unit 1930 is a GPGPU that includes a graphics processor. In at least one embodiment, integrated circuit 1700 includes graphics core 1900, e.g., to form an integrated circuit and / or to form a SoC, wherein such integrated circuit and / or such SoC performs the operations described herein.

[0350] In at least one embodiment, graphics core 1900 includes a shared instruction cache 1902, texture units 1918, and cache / shared memory 1920 (e.g., including L1, L2, L3, last level cache, or other caches), which are common to execution resources within graphics core 1900. In at least one embodiment, graphics core 1900 may include multiple slices 1901A-1901N, or partitions of each core, and the graphics processor may include multiple instances of graphics core 1900. In at least one embodiment, each slice 1901A-1901N refers to graphics core 1900. In at least one embodiment, slices 1901A-1901N have sub-slices, which are portions of slices 1901A-1901N. In at least one embodiment, slices 1901A-1901N may be independent of other slices or dependent on other slices. In at least one embodiment, the slices 1901A-1901N may include support logic including a local instruction cache 1904A-1904N, a thread scheduler (sequencer) 1906A-1906N, a thread dispatcher 1908A-1908N, and a set of registers 1910A-1910N. In at least one embodiment, the slices 1901A-1901N may include a set of additional function units (AFUs 1912A-1912N), floating point units (FPUs 1914A-1914N), integer arithmetic logic units (ALUs 1916A-1916N), address calculation units (ACUs 1913A-1913N), double precision floating point units (DPFPUs 1915A-1915N), and matrix processing units (MPUs 1917A-1917N). In at least one embodiment, the MPUs 1917A-1917N are referred to as a matrix engine.

[0351] In at least one embodiment, each slice 1901A-1901N includes one or more engines for floating-point and integer vector operations and one or more engines for accelerating convolution and matrix operations in artificial intelligence, machine learning, or large data set workloads. In at least one embodiment, one or more slices 1901A-1901N include one or more vector engines for computing vectors (e.g., computing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16-bit floating point (also known as "FP16"), 32-bit floating point (also known as "FP32"), or 64-bit floating point (also known as "FP64"). In at least one embodiment, one or more slices 1901A-1901N include 16 vector engines that are paired with 16 matrix math units to compute matrix / tensor operations, where the vector engines and math units are exposed through matrix extensions. In at least one embodiment, a slice is a designated portion of the processing resources of a processing unit, for example, 16 cores and a ray tracing unit or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units of the processor. In at least one embodiment, graphics core 1900 includes one or more matrix engines for computing matrix operations, such as when computing tensor operations.

[0352] In at least one embodiment, one or more slices 1901A-1901N include one or more ray tracing units for computing ray tracing operations (e.g., 16 ray tracing units per slice 1901A-1901N). In at least one embodiment, the ray tracing units compute ray traversals, triangle intersections, bounding box intersections, or other ray tracing operations.

[0353] In at least one embodiment, one or more slices 1901A-1901N comprise a media slice that encodes, decodes, and / or transcodes data; scales and / or converts the format of data; and / or performs video quality operations on video data.

[0354] In at least one embodiment, one or more slices 1901A-1901N are linked to an L2 cache and memory structure, a link connector, a high bandwidth memory (HBM) (e.g., HBM2e, HDM3) stack, and a media engine. In at least one embodiment, one or more slices 1901A-1901N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 1901A-1901N have one or more L1 caches. In at least one embodiment, one or more slices 1901A-1901N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data (e.g., data corresponding to instructions); one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometry units for performing operations in the geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., a shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by the shape); one or more layered depth buffers (Hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, slices 1901A-1901N include memory structures, such as an L2 cache.

[0355] In at least one embodiment, the FPUs 1914A-1914N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1915A-1915N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1916A-1916N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1917A-1917N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1917A-1917N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 1912A-1912N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0356] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in graphics core 1900 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0357] In at least one embodiment, graphics core 1900 includes an interconnect and link fabric sublayer attached to a switch and GPU-GPU bridge that enables interconnection of multiple graphics processors 1900 (e.g., eight) with load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 1900 without requiring glue to each other. In at least one embodiment, the interconnect includes a standardized interconnect (e.g., PCIe) or some combination thereof.

[0358] In at least one embodiment, graphics core 1900 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, where the individual dies can be connected using an interconnect (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, graphics core 1900 includes compute tiles, memory tiles (e.g., where memory tiles can be exclusively accessed by different tiles or different chipsets (such as Rambo tiles)), substrate tiles, base tiles, HMB tiles, link tiles, and EMIB tiles, where all tiles are packaged together in graphics core 1900 as part of a GPU. In at least one embodiment, graphics core 1900 can include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, a compute tile can have 8 graphics cores 1900, an L1 cache; and a base tile can have a host interface using PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with 8 links, and 8 ports with an embedded switch. In at least one embodiment, the tiles are connected via fine-pitch 36 micron microbumps (e.g., copper pillars) in a face-to-face (F2F) on-chip bonding manner. In at least one embodiment, graphics core 1900 includes a memory structure (which includes memory) and is accessible to multiple tiles. In at least one embodiment, graphics core 1900 stores, accesses, or loads its own hardware context in memory, where the hardware context is a set of data loaded from registers before the process resumes, and where the hardware context can indicate the state of the hardware (e.g., the state of the GPU).

[0359] In at least one embodiment, graphics core 1900 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream to a parallel data stream, or converts a parallel data stream to a serial data stream.

[0360] In at least one embodiment, graphics core 1900 includes a high-speed coherent unified fabric (GPU to GPU), load / store units, bulk data transfer and synchronization semantics, and GPUs connected via an embedded switch, where the GPU-GPU bridge is controlled by a controller.

[0361] In at least one embodiment, graphics core 1900 executes an API that abstracts the hardware of graphics core 1900 and accesses libraries with instructions to perform mathematical operations (e.g., a math kernel library), deep neural network operations (e.g., a deep neural network library), vector operations, collective communications, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0362] In at least one embodiment, Figure 19A One or more methods, systems or processes are described for using various algorithms, formulas and processes (e.g., in combination with Figure 1 In at least one embodiment, the present invention provides a method for generating a second video of a robotic device performing a task using one or more first videos of the robotic device performing the task in a manner different from that depicted in the one or more first videos, and / or otherwise performing the operations described herein. Figure 19A One or more systems described in are used to implement such as Figure 1-7 One or more systems and / or processes such as those described.

[0363] Figure 19BA GPGPU 1930 is shown in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by an array of graphics processing units. In at least one embodiment, GPGPU 1930 can be directly linked to other instances of GPGPU 1930 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 1930 includes a host interface 1932 for connecting to a host processor. In at least one embodiment, host interface 1932 is a PCI Express interface. In at least one embodiment, host interface 1932 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 1930 receives commands from the host processor and uses a global scheduler 1934 (which can be referred to as a thread sequencer and / or asynchronous compute engine) to assign execution threads associated with those commands to a set of compute clusters 1936A-1936H. In at least one embodiment, compute clusters 1936A-1936H share a cache memory 1938. In at least one embodiment, cache memory 1938 may be used as a higher level cache for cache memory within compute clusters 1936A-1936H. In at least one embodiment, compute clusters 1936A-1936H include slices or also referred to as "slices." In at least one embodiment, GPGPU 1930 is part of a SoC, such as part of integrated circuit 1700 ( Figure 17 ).

[0364] In at least one embodiment, GPGPU 1930 includes memory 1944A-1944B coupled to compute clusters 1936A-1936H via a set of memory controllers 1942A-1942B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 1944A-1944B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0365] In at least one embodiment, computing clusters 1936A-1936H each include a set of graphics cores, such as Figure 19AThe graphics core 1900 may include multiple types of integer and floating-point logic units that can perform computational operations across a range of precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 1936A-1936H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0366] In at least one embodiment, multiple instances of GPGPU 1930 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 1936A-1936H for synchronization and data exchange vary between embodiments. In at least one embodiment, multiple instances of GPGPU 1930 communicate via host interface 1932. In at least one embodiment, GPGPU 1930 includes an I / O hub 1939 that couples GPGPU 1930 to a GPU link 1940, which enables direct connections to other instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1930 are located in separate data processing systems and communicate via a network device accessible via host interface 1932. In at least one embodiment, GPU link 1940 may be configured to enable connection to a host processor in addition to or in lieu of host interface 1932 .

[0367] In at least one embodiment, GPGPU 1930 can be configured to train neural networks. In at least one embodiment, GPGPU 1930 can be used within an inference platform. In at least one embodiment, when using GPGPU 1930 for inference, GPGPU 1930 can include fewer compute clusters 1936A-1936H than when using GPGPU 1930 for training a neural network. In at least one embodiment, the memory technology associated with memories 1944A-1944B can differ between the inference and training configurations, with higher-bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of GPGPU 1930 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network.

[0368] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in GPGPU 1930 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0369] In at least one embodiment, Figure 19B One or more methods, systems or processes are described for using various algorithms, formulas and processes (e.g., in combination with Figure 1 In at least one embodiment, the present invention provides a method for generating a second video of a robotic device performing a task using one or more first videos of the robotic device performing the task in a manner different from that depicted in the one or more first videos, and / or otherwise performing the operations described herein. Figure 19B One or more systems described in are used to implement such as Figure 1-7 One or more systems and / or processes such as those described.

[0370] Figure 20 2 is a block diagram illustrating a computing system 2000 according to at least one embodiment. In at least one embodiment, computing system 2000 includes a processing subsystem 2001 having one or more processors 2002 and system memory 2004 communicating via an interconnect path that may include a memory hub 2005. In at least one embodiment, memory hub 2005 may be a separate component within a chipset assembly or may be integrated within one or more processors 2002. In at least one embodiment, memory hub 2005 is coupled to an I / O subsystem 2011 via a communication link 2006. In at least one embodiment, I / O subsystem 2011 includes an I / O hub 2007, which enables computing system 2000 to receive input from one or more input devices 2008. In at least one embodiment, I / O hub 2007 may enable a display controller, which may be included in one or more processors 2002, to provide output to one or more display devices 2010A. In at least one embodiment, the one or more display devices 2010A coupled to the I / O hub 2007 may include local, internal, or embedded display devices.

[0371] In at least one embodiment, the processing subsystem 2001 includes one or more parallel processors 2012 coupled to a memory hub 2005 via a bus or other communication link 2013. In at least one embodiment, the communication link 2013 can use one of any number of standard based communication link technologies or protocols (such as, but not limited to, PCI Express), or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 2012 form a parallel or vector processing system in a computational cluster, which can include a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. In at least one embodiment, some or all of the one or more parallel processors 2012 form a graphics processing subsystem that can output pixels to one of one or more display devices 2010A coupled via an I / O hub 2007. In at least one embodiment, the one or more parallel processors 2012 can also include a display controller and display interface (not shown) for enabling direct connection to one or more display devices 2010B. In at least one embodiment, one or more parallel processors 2012 include one or more cores, such as graphics core 1900 discussed herein.

[0372] In at least one embodiment, a system storage unit 2014 can be connected to the I / O hub 2007 to provide a storage mechanism for the computing system 2000. In at least one embodiment, an I / O switch 2016 can be used to provide an interface mechanism for enabling connections between the I / O hub 2007 and other components, such as a network adapter 2018 and / or a wireless network adapter 2019 that can be integrated into the platform, as well as various other devices that can be added via one or more additional devices 2020. In at least one embodiment, the network adapter 2018 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2019 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0373] In at least one embodiment, the computing system 2000 may include other components not explicitly shown that may also be connected to the I / O hub 2007, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the interconnection may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (such as the NV-Link high-speed interconnect or interconnect protocol). Figure 20The communication paths between the various components in the system.

[0374] In at least one embodiment, one or more parallel processors 2012 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU), e.g., one or more parallel processors 2012 include graphics core 1900. In at least one embodiment, one or more parallel processors 2012 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of computing system 2000 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2012, memory hub 2005, one or more processors 2002, and I / O hub 2007 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 2000 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 2000 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0375] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 can be used in computing system 2000 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0376] In at least one embodiment, Figure 20 One or more methods, systems or processes are described for using various algorithms, formulas and processes (e.g., in combination with Figure 1 In at least one embodiment, the present invention provides a method for generating a second video of a robotic device performing a task using one or more first videos of the robotic device performing the task in a manner different from that depicted in the one or more first videos, and / or otherwise performing the operations described herein. Figure 20 One or more systems described in are used to implement such as Figure 1-7 One or more systems and / or processes such as those described.

[0377] processor

[0378] Figure 21A2100 in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 2100 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 2100 is shown as a processor according to an exemplary embodiment. Figure 20 Variations of one or more parallel processors 2012 are shown. In at least one embodiment, parallel processor 2100 includes one or more graphics cores 1900.

[0379] In at least one embodiment, parallel processor 2100 includes parallel processing unit 2102. In at least one embodiment, parallel processing unit 2102 includes an I / O unit 2104 that enables communication with other devices, including other instances of parallel processing unit 2102. In at least one embodiment, I / O unit 2104 can be directly connected to other devices. In at least one embodiment, I / O unit 2104 connects to other devices using a hub or switch interface (e.g., memory hub 2105). In at least one embodiment, the connection between memory hub 2105 and I / O unit 2104 forms a communication link 2113. In at least one embodiment, I / O unit 2104 is connected to a host interface 2106 and a memory crossbar switch 2116, where host interface 2106 receives commands for performing processing operations and memory crossbar switch 2116 receives commands for performing memory operations.

[0380] In at least one embodiment, when host interface 2106 receives command buffers via I / O unit 2104, host interface 2106 can direct work operations for executing those commands to front end 2108. In at least one embodiment, front end 2108 is coupled with scheduler 2110 (which can be referred to as a sequencer), which is configured to distribute commands or other work items to processing cluster array 2112. In at least one embodiment, scheduler 2110 ensures that processing cluster array 2112 is properly configured and in a valid state before assigning tasks to clusters within processing cluster array 2112. In at least one embodiment, scheduler 2110 is implemented via firmware logic executing on a microcontroller. In at least one embodiment, a microcontroller-implemented scheduler 2110 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing cluster array 2112. In at least one embodiment, host software can identify workloads for scheduling on processing cluster array 2112 via one of multiple graphics processing paths. In at least one embodiment, the workload may then be automatically distributed across the processing cluster array 2112 by scheduler 2110 logic within a microcontroller that includes scheduler 2110 .

[0381] In at least one embodiment, the processing cluster array 2112 may include up to "N" processing clusters (e.g., cluster 2114A, cluster 2114B, through cluster 2114N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, each cluster 2114A-2114N in the processing cluster array 2112 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2110 may use various scheduling and / or work distribution algorithms to distribute work to the clusters 2114A-2114N in the processing cluster array 2112, which may vary depending on the workload generated for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2110 or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2112. In at least one embodiment, different clusters 2114A-2114N in the processing cluster array 2112 may be assigned to process different types of programs or to perform different types of computations.

[0382] In at least one embodiment, processing cluster array 2112 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2112 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 2112 can include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0383] In at least one embodiment, the processing cluster array 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2112 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2112 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing units 2102 may transfer data from system memory via the I / O units 2104 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2122) during processing and then written back to the system memory.

[0384] In at least one embodiment, when parallel processing units 2102 are used to perform graphics processing, scheduler 2110 can be configured to divide the processing workload into tasks of approximately equal size to better facilitate the distribution of graphics processing operations to multiple clusters 2114A-2114N in processing cluster array 2112. In at least one embodiment, portions of processing cluster array 2112 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2114A-2114N can be stored in a buffer to allow the intermediate data to be transferred between clusters 2114A-2114N for further processing.

[0385] In at least one embodiment, the processing cluster array 2112 can receive processing tasks to be executed via the scheduler 2110, which receives commands defining the processing tasks from the front end 2108. In at least one embodiment, the processing tasks can include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2110 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 2108. In at least one embodiment, the front end 2108 can be configured to ensure that the processing cluster array 2112 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0386] In at least one embodiment, each of the one or more instances of parallel processing unit 2102 can be coupled to parallel processor memory 2122. In at least one embodiment, parallel processor memory 2122 can be accessed via memory crossbar 2116, which can receive memory requests from processing cluster array 2112 and I / O unit 2104. In at least one embodiment, memory crossbar 2116 can access parallel processor memory 2122 via memory interface 2118. In at least one embodiment, memory interface 2118 can include multiple partition units (e.g., partition unit 2120A, partition unit 2120B, through partition unit 2120N), each of which can be coupled to a portion of parallel processor memory 2122 (e.g., a memory unit). In at least one embodiment, the number of partition units 2120A-2120N is configured to be equal to the number of memory cells, such that the first partition unit 2120A has a corresponding first memory cell 2124A, the second partition unit 2120B has a corresponding second memory cell 2124B, and the Nth partition unit 2120N has a corresponding Nth memory cell 2124N. In at least one embodiment, the number of partition units 2120A-2120N may not be equal to the number of memory cells.

[0387] In at least one embodiment, memory units 2124A-2124N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2124A-2124N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM), HBM2e, or HDM3. In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 2124A-2124N, allowing partition units 2120A-2120N to write to portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 2122. In at least one embodiment, local instances of parallel processor memory 2122 may be eliminated in favor of a unified memory design that utilizes system memory as well as local cache memory.

[0388] In at least one embodiment, any of the clusters 2114A-2114N in the processing cluster array 2112 can process data to be written to any memory unit 2124A-2124N within the parallel processor memory 2122. In at least one embodiment, the memory crossbar 2116 can be configured to transmit the output of each cluster 2114A-2114N to any partition unit 2120A-2120N or to another cluster 2114A-2114N, which can perform additional processing operations on the output. In at least one embodiment, each cluster 2114A-2114N can communicate with a memory interface 2118 via the memory crossbar 2116 to read from or write to various external memory devices. In at least one embodiment, memory crossbar switch 2116 has connections to memory interface 2118 for communicating with I / O unit 2104, and connections to local instances of parallel processor memory 2122, which enables processing units within different processing clusters 2114A-2114N to communicate with system memory or other memory that is not local to parallel processing unit 2102. In at least one embodiment, memory crossbar switch 2116 can use virtual channels to separate traffic flows between clusters 2114A-2114N and partition units 2120A-2120N.

[0389] In at least one embodiment, multiple instances of parallel processing unit 2102 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2102 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2102 can include a higher precision floating point unit than other instances. In at least one embodiment, a system including one or more instances of parallel processing unit 2102 or parallel processor 2100 can be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0390] Figure 21B is a block diagram of a partition unit 2120 according to at least one embodiment. In at least one embodiment, the partition unit 2120 is Figure 21A 2120N。In at least one embodiment, the partition unit 2120 includes an L2 cache 2121, a frame buffer interface 2125, and an ROP 2126 (raster operation unit). In at least one embodiment, the L2 cache 2121 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 2116 and the ROP 2126. In at least one embodiment, the L2 cache 2121 outputs read misses and urgent write-back requests to the frame buffer interface 2125 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 2125 for processing. In at least one embodiment, the frame buffer interface 2125 communicates with memory units in the parallel processor memory (such as Figure 21A One of the memory units 2124A-2124N (e.g., within parallel processor memory 2122)) is coupled.

[0391] In at least one embodiment, ROP 2126 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2126 then outputs the processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 2126 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2126 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on depth and color data on a per-tile basis.

[0392] In at least one embodiment, ROP 2126 is included within each processing cluster (e.g., Figure 21A In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are routed through memory crossbar 2116. In at least one embodiment, the processed graphics data may be displayed on a display device such as a Figure 20 2010), routed by processor 2002 for further processing, or by Figure 21A One of the processing entities within parallel processor 2100 is routed for further processing.

[0393] Figure 21C is a block diagram of a processing cluster 2114 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Figure 21A In at least one embodiment, processing cluster 2114 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit that is configured to issue instructions to a set of processing engines within each processing cluster.

[0394] In at least one embodiment, the operation of the processing cluster 2114 can be controlled via a pipeline manager 2132 that allocates processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2132 Figure 21AThe scheduler 2110 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2134 and / or the texture unit 2136. In at least one embodiment, the graphics multiprocessor 2134 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing cluster 2114. In at least one embodiment, one or more instances of the graphics multiprocessor 2134 may be included within the processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 may process data, and the data crossbar 2140 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2132 may facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 2140.

[0395] In at least one embodiment, each graphics multiprocessor 2134 within a processing cluster 2114 may include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0396] In at least one embodiment, instructions transmitted to the processing cluster 2114 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 2134. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines can be idle during the processing of a loop within the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 2134, processing can be performed within consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on the graphics multiprocessor 2134.

[0397] In at least one embodiment, the graphics multiprocessor 2134 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2134 can abandon the internal cache and use cache memory within the processing cluster 2114 (e.g., L1 cache 2148). In at least one embodiment, each graphics multiprocessor 2134 can also access a partition unit (e.g., Figure 21A L2 cache within partition units 2120A-2120N) of the graphics multiprocessor 2134 is shared across all processing clusters 2114 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2134 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2102 can be used as global memory. In at least one embodiment, processing cluster 2114 includes multiple instances of graphics multiprocessor 2134, which can share common instructions and data, which can be stored in L1 cache 2148.

[0398] In at least one embodiment, each processing cluster 2114 may include a memory management unit ("MMU") 2145 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2145 may reside in Figure 21A 2148 . In at least one embodiment, the MMU 2145 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2145 may include an address translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 2134 or the L1 cache 2148 or the processing cluster 2114. In at least one embodiment, the physical addresses are processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0399] In at least one embodiment, the processing clusters 2114 can be configured such that each graphics multiprocessor 2134 is coupled to a texture unit 2136 to perform texture mapping operations, which determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2134, and retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 2134 outputs processed tasks to a data crossbar 2140 to provide the processed tasks to another processing cluster 2114 for further processing, or to store the processed tasks in an L2 cache, local parallel processor memory, or in system memory via the memory crossbar 2116. In at least one embodiment, a preROP 2142 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 2134 and direct the data to a ROP unit, which can communicate with a partition unit (e.g., a partition unit) as described herein. Figure 21A In at least one embodiment, the PreROP 2142 unit can perform optimizations for color blending, organizing pixel color data, and performing address translation.

[0400] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in graphics processing cluster 2114 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0401] In at least one embodiment, Figure 21C One or more methods, systems or processes are described for using various algorithms, formulas and processes (e.g., in combination with Figure 1 In at least one embodiment, the present invention provides a method for generating a second video of a robotic device performing a task using one or more first videos of the robotic device performing the task in a manner different from that depicted in the one or more first videos, and / or otherwise performing the operations described herein. Figure 21C One or more systems described in are used to implement such as Figure 1-7 One or more systems and / or processes such as those described.

[0402] Figure 21DA graphics multiprocessor 2134 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2134 is coupled to a pipeline manager 2132 of a processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 has an execution pipeline that includes, but is not limited to, an instruction cache 2152, an instruction unit 2154, an address mapping unit 2156, a register file 2158, one or more general purpose graphics processing unit (GPGPU) cores 2162, and one or more load / store units 2166, wherein the one or more load / store units 2166 can perform load / store operations to load / store instructions corresponding to the execution operations. In at least one embodiment, the GPGPU core 2162 and the load / store unit 2166 are coupled to a cache memory 2172 and a shared memory 2170 via a memory and cache interconnect 2168. In at least one embodiment, the GPGPU core 2162 is part of a SoC (such as a processor). Figure 17 a portion of integrated circuit 1700 in FIG.

[0403] In at least one embodiment, the instruction cache 2152 receives a stream of instructions to be executed from the pipeline manager 2132. In at least one embodiment, the instructions are cached in the instruction cache 2152 and dispatched for execution by the instruction unit 2154. In at least one embodiment, the instruction unit 2154 can dispatch instructions as thread groups (e.g., warps, wavefronts, waves), where each thread in the thread group is assigned to a different execution unit within the GPGPU core 2162. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2156 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 2166.

[0404] In at least one embodiment, register file 2158 provides a set of registers for the functional units of graphics multiprocessor 2134. In at least one embodiment, register file 2158 provides temporary storage for operands for data paths connected to the functional units of graphics multiprocessor 2134 (e.g., GPGPU core 2162, load / store unit 2166). In at least one embodiment, register file 2158 is divided between each functional unit such that a dedicated portion of register file 2158 is allocated to each functional unit. In at least one embodiment, register file 2158 is divided between different warps (which may be referred to as wavefronts and / or waves) being executed by graphics multiprocessor 2134.

[0405] In at least one embodiment, the GPGPU cores 2162 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2134. In at least one embodiment, the architectures of the various GPGPU cores 2162 may be similar or different. In at least one embodiment, a first portion of the GPGPU core 2162 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2134 may additionally include one or more fixed-function or special-function units for performing specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2162 may also include fixed-function or special-function logic.

[0406] In at least one embodiment, the GPGPU core 2162 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2162 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that implement the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0407] In at least one embodiment, the memory and cache interconnect 2168 is an interconnect network that connects each functional unit of the graphics multiprocessor 2134 to the register file 2158 and the shared memory 2170. In at least one embodiment, the memory and cache interconnect 2168 is a crossbar interconnect that allows the load / store unit 2166 to perform load and store operations between the shared memory 2170 and the register file 2158. In at least one embodiment, the register file 2158 can operate at the same frequency as the GPGPU core 2162, resulting in very low latency for data transfers between the GPGPU core 2162 and the register file 2158. In at least one embodiment, the shared memory 2170 can be used to facilitate communication between threads executing on the functional units within the graphics multiprocessor 2134. In at least one embodiment, the cache memory 2172 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 2136. In at least one embodiment, the shared memory 2170 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in ...

Claims

1. A processor, comprising: One or more circuits for using one or more first videos of a robotic apparatus performing a task to generate one or more second videos of the robotic apparatus performing the task in a manner different from that depicted in the one or more first videos.

2. The processor of claim 1 , wherein the one or more circuits are configured to: segmenting the one or more first videos into one or more subtasks, wherein each of the one or more subtasks includes at least a trajectory of the robotic device; generating a new scene including objects different from the objects used by the robotic apparatus to perform the task in the one or more first videos; as well as The one or more second videos are generated including one or more transformed trajectories such that the robotic device performs the task in the new scene in a manner different from that depicted in the one or more first videos.

3. The processor of claim 1 , wherein the one or more circuits are configured to: One or more demonstrations of the robotic apparatus performing in a simulator are recorded using one or more cameras, wherein the one or more demonstrations include tasks different from the tasks depicted in the one or more first videos.

4. The processor of claim 1, wherein the one or more circuits are configured to train one or more neural networks using the one or more first videos and the one or more second videos to infer motion of the robotic device.

5. The processor of claim 1, wherein the one or more circuits are configured to generate the one or more second videos without using a teleoperation operation.

6. The processor of claim 1, wherein the one or more circuits are configured to generate the one or more second videos after a predetermined success simulation threshold is met or exceeded.

7. A method comprising: One or more first videos of a robotic apparatus performing a task are used to generate one or more second videos of the robotic apparatus performing the task in a manner different from that depicted in the one or more first videos.

8. The method according to claim 7, further comprising generating the one or more second videos by: Modifying one or more tracks identified in the one or more first videos based at least in part on adjusting a scene from the one or more first videos, wherein the adjusting the scene comprises: Changing the starting position of the object, replacing the object with a different object, and / or changing the robotic device to a different robotic device.

9. The method according to claim 7, further comprising: The task is performed using a simulator in a manner different from that depicted in the one or more first videos to indicate whether the task performed in the different manner is a successful demonstration.

10. The method of claim 7, wherein the one or more first videos include one or more presentations generated using teleoperation; and Wherein the one or more second videos include one or more demonstrations generated without using remote operation.

11. The method according to claim 7, further comprising: The one or more first videos and the one or more second videos are used to train a policy for controlling the robotic device to grasp one or more objects.

12. The method according to claim 7, further comprising: The starting position of the modified trajectory and the starting position of the robotic device are interpolated.

13. A system comprising: One or more processors for using one or more first videos of a robotic apparatus performing a task to generate one or more second videos of the robotic apparatus performing the task in a manner different from that depicted in the one or more first videos.

14. The system of claim 13, wherein the one or more processors are configured to: A subset of the one or more first videos is used to generate the one or more second videos based at least in part on one or more subtasks of the task performed by the robotic device.

15. The system of claim 13, wherein the one or more second videos include one or more recorded demonstrations generated by a simulator.

16. The system of claim 13, wherein the one or more processors are configured to: segmenting the one or more first videos into a plurality of segments, wherein each segment includes an object and a trajectory of the robotic device grasping the object; and Based at least in part on the trajectory of the robotic apparatus grasping the object from the one or more first videos, a new trajectory of the robotic apparatus grasping a different object is generated.

17. The system of claim 13, wherein the one or more second videos include one or more contexts that are different from one or more contexts of the one or more first videos.

18. The system of claim 13, wherein the robotic device in the one or more second videos includes an arm connected to the robotic device that is different from one or more arms of the robotic device in the one or more first videos.

19. The system of claim 13, wherein the one or more processors are configured to generate the one or more second videos to include one or more objects that are different from one or more objects in the one or more first videos.

20. The system of claim 13, wherein the one or more processors are used to control the robotic device in an autonomous vehicle using one or more neural networks.

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