Test system and test method for optoelectronic heterogeneous integrated chip

Abstract

The embodiment of the present application discloses a test system and a test method for an optoelectronic heterogeneous integrated chip, which relate to the field of semiconductors. The test system for the optoelectronic heterogeneous integrated chip includes: a carrier for carrying the optoelectronic heterogeneous integrated chip to be tested. A first acquisition device is arranged on one side of the carrier, and is used to collect first position information of the conductive bumps in the target area on the first surface. The probe assembly is used to adjust the contact between the probe and the conductive bumps in the target area according to the first position information. The clamping assembly includes an annular chuck, which is used to connect the edge of the optoelectronic heterogeneous integrated chip to be tested. The second acquisition device is arranged on the side of the annular chuck away from the first acquisition device, and is used to collect the second position information of the optical interface of the optical chip according to the position information of the target area. The optical coupling module is arranged on the side of the annular chuck away from the first acquisition device, and is used to obtain the optical signal transmitted by the optical interface according to the second position information and perform a test.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a testing system and a testing method for a photoelectric heterogeneous integrated chip. Background Art

[0002] After the chip is manufactured, it needs to be tested, which generally includes chip function testing, performance testing, and reliability testing. During the chip testing process, the chip or a wafer containing multiple chips (die) is usually placed in the test system. Probes are used to couple with the various contacts on the chip to achieve electrical signal interconnection. By inputting electrical signals into the chip and then detecting the chip's output response, the input and output values ​​are quickly compared and analyzed to achieve the purpose of testing various technical indicators of the chip.

[0003] However, when testing the performance of different types of chips on a heterogeneously integrated optoelectronic chip that integrates an electrical chip and an optical chip, different test processes need to be used to test them separately, which is not conducive to large-scale testing of heterogeneous integrated chips. Summary of the Invention

[0004] In view of this, the embodiments of the present application provide a test system and a test method for an optoelectronic heterogeneous integrated chip, which can expand the application scenarios of the test system, improve test efficiency and reduce test costs.

[0005] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0006] In one aspect, embodiments of the present application provide a test system for an optoelectronic heterogeneous integrated chip, comprising: a carrier, a first acquisition device, a probe assembly, a clamping assembly, a second acquisition device, and an optical coupling module.

[0007] The carrier is used to carry the optoelectronic heterogeneous integrated chip to be tested. The optoelectronic heterogeneous integrated chip includes a wafer-level chip, a plurality of conductive bumps located on the first surface of the two opposite surfaces of the wafer-level chip, and an electrical chip and an optical chip located on the second surface and coupled to the conductive bumps. A first acquisition device is provided on one side of the carrier, and is used to acquire first position information of the conductive bumps in a target area on the first surface. A probe assembly is used to adjust the contact between the probe and the conductive bumps in the target area according to the first position information. The clamping assembly includes an annular chuck, which is used to connect the edge of the optoelectronic heterogeneous integrated chip to be tested. A second acquisition device is provided on a side of the annular chuck away from the first acquisition device, and is used to acquire second position information of the optical interface of the optical chip in the target area according to the position information of the target area. An optical coupling module is provided on a side of the annular chuck away from the first acquisition device, and is used to acquire the optical signal transmitted by the optical interface according to the second position information and perform testing.

[0008] In some examples, the optical coupling module includes: an optical fiber array and a drive motor assembly. The optical fiber array is used to acquire the optical signal transmitted by the optical interface. The drive motor assembly is coupled to the optical fiber array and is used to adjust the relative position between the optical fiber array and the optical interface based on the acquired optical signal power transmitted by the optical interface. The drive motor assembly is used to adjust the movement of the optical fiber array along a first direction, a second direction, and a third direction, where the first direction, the second direction, and the third direction intersect with each other.

[0009] In some examples, the probe assembly includes a probe card and a first position adjustment mechanism connected to the probe card. The first position adjustment mechanism includes a pressure sensor and a first mechanical arm, the first mechanical arm being configured to adjust the distance between the probe card and the optoelectronic heterogeneous integrated chip to be tested based on a pressure value between the probe card and the optoelectronic heterogeneous integrated chip to be tested sensed by the pressure sensor.

[0010] Wherein, at least one probe of the probe card contacts one of the conductive bumps in the target area.

[0011] In some examples, the optoelectronic heterogeneous integrated chip to be tested is divided into a plurality of target regions. The first acquisition device is further configured to re-acquire first position information of the conductive bump within another target region on the first surface. The clamping assembly further includes a second robotic arm connected to the annular chuck, the second robotic arm configured to move the optoelectronic integrated chip to be tested according to the updated target region.

[0012] In some examples, the carrier includes a second position adjustment mechanism and a carrier surface connected to the second position adjustment mechanism, wherein the second position adjustment mechanism is configured to adjust the position of the carrier surface according to the target area. The carrier surface at least covers a portion of the optoelectronic heterogeneous integrated chip corresponding to the target area and exposes the optical interface; the area of ​​the target area is represented by the area of ​​the probe card board of the probe assembly.

[0013] In some examples, the second acquisition device, the optical coupling module, and the supporting platform are located on the same mobile platform. The second position adjustment mechanism is further used to drive the mobile platform to move.

[0014] In some examples, a plurality of vacuum adsorption holes are provided on the surface of the carrier platform; and a distribution density of the plurality of vacuum adsorption holes increases as the area of ​​the surface of the carrier platform decreases.

[0015] In the above-mentioned optoelectronic heterogeneous integrated chip testing system, the first and second surfaces of the optoelectronic heterogeneous integrated chip to be tested are exposed via an annular chuck. The probes couple with the conductive bumps on the first surface to transmit electrical signals to the electrical chip and the optical chip. Furthermore, the optical coupling module can receive the optical signal transmitted by the optical chip on the second surface, and the annular chuck does not block the optical signal emitted by the optical chip on the second surface. In this way, the optical chip and the electrical chip can be tested synchronously using the probe on one side of the optoelectronic heterogeneous integrated chip to be tested and the optical coupling module on the other side. This not only expands the application scenarios for testing different types of integrated chips, but also improves testing efficiency, facilitates large-scale testing, and reduces testing costs. Furthermore, the combined structure and positional relationship of the carrier, first acquisition device, probe assembly, clamping assembly, second acquisition device, and optical coupling module used in the above-mentioned optoelectronic heterogeneous integrated chip testing system facilitates improving the structural compactness of the test system. Furthermore, the position of each functional structure can be controlled and adjusted, making it suitable for testing a variety of heterogeneous integrated chips, thereby increasing the applicability of the test system.

[0016] On the other hand, an embodiment of the present application provides a method for testing an optoelectronic heterogeneous integrated chip. The testing method includes: connecting an annular chuck to the edge of the optoelectronic heterogeneous integrated chip to be tested; determining a target area on the optoelectronic heterogeneous integrated chip to be tested; and providing a plurality of conductive bumps coupled to an optical chip and an electrical chip in the target area. According to the position information of the target area, the carrier table is controlled to contact part of the optoelectronic heterogeneous integrated chip to be tested in the target area, and the optical interface of the optical chip is exposed. The first position information of the conductive bump in the target area is collected, and the probe of the probe assembly is adjusted to contact the conductive bump according to the first position information. An electrical signal is input to the optical chip and the electrical chip through the probe. The electrical chip is tested, and the optical signal transmitted by the optical interface of the optical chip is obtained to test the optical chip.

[0017] In some examples, the testing of the optical chip includes: collecting second position information of the optical interface of the optical chip, and obtaining the optical signal power transmitted by the optical interface, adjusting the relative position of the optical fiber array in the optical coupling module and the optical interface, and testing the optical chip.

[0018] In some examples, the testing method further includes: obtaining a first distance between the probe card of the probe assembly and the optoelectronic heterogeneous integrated chip to be tested, and a pressure value between the probe and the conductive bump, while the probe contacts the conductive bump. Based on the pressure value between the probe and the conductive bump, adjusting the first distance to a second distance that satisfies a preset pressure value between the probe and the conductive bump. The second distance is less than or equal to the first distance. The electrical chip within the target area is tested using the probe.

[0019] The above-mentioned testing method is a method for driving a test system for optoelectronic heterogeneous integrated chips to perform chip testing, and has the same beneficial effects as the test system for optoelectronic heterogeneous integrated chips, which will not be described in detail here.

[0020] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic structural diagram of an optoelectronic heterogeneous integrated chip provided in one embodiment of the present application;

[0022] Figure 2 A schematic diagram of the structure of a test system for an optoelectronic heterogeneous integrated chip provided in one embodiment of the present application;

[0023] Figure 3 Schematic diagram of the structure of the test system for optoelectronic heterogeneous integrated chip provided in one embodiment of the present application Figure 2 ;

[0024] Figure 4 Schematic diagram of the process of testing the optoelectronic heterogeneous integrated chip provided in one embodiment of the present application Figure 1 ;

[0025] Figure 5 Schematic diagram of the process of testing the optoelectronic heterogeneous integrated chip provided in one embodiment of the present application Figure 2 . DETAILED DESCRIPTION

[0026] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0027] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0028] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0029] It should be understood that when an element or layer is referred to as being “on,” “adjacent,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0030] Although the terms first, second, third, etc. can be used to describe various elements, components, areas, layers and / or parts, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer or part from another element, component, area, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, area, layer or part discussed below can be expressed as a second element, component, area, layer or part. When the second element, component, area, layer or part is discussed, it does not mean that the first element, component, area, layer or part necessarily exists in the present application.

[0031] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0032] In order to fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0033] With the vigorous development of artificial intelligence and the digital economy, the demand for high-speed data transmission and fiber-optic network equipment is increasing. Traditional optical modules and on-chip copper interconnects can no longer meet this rapidly growing data transmission demand. Therefore, optoelectronic heterogeneous integration technology has emerged. The high transmission and low latency characteristics of silicon-based optoelectronic heterogeneous integrated chips effectively solve the bandwidth bottleneck and power consumption wall problems faced by traditional copper interconnect technology. High-density optoelectronic heterogeneous integrated chips conform to the needs and challenges of technological development in the continuity of Moore's Law, and have broad prospects and potential in application. In terms of development trend, they show characteristics such as higher integration, higher energy efficiency and lower power consumption. However, they also face challenges such as the complexity of interconnection technology, material and process compatibility, and large-scale testing and screening.

[0034] In large-scale integrated circuit manufacturing, wafer-level testing can determine the quality of process and performance before the chip is cracked, reducing losses in subsequent chip packaging and improving the yield of back-end manufacturing processes. It provides a fast and efficient solution for chip inspection and screening, and is a key factor in promoting the scale and standardization of product development. However, due to the complex functions of silicon-based optoelectronic heterogeneous integrated chips, which involve optical coupling and the integration of multiple chips, it is currently impossible to directly obtain the comprehensive parameter performance of the actual chip through wafer testing, hindering the large-scale industrial application of silicon-based optoelectronic heterogeneous integrated chips.

[0035] Therefore, to achieve efficient testing and batch screening of silicon-based optoelectronic heterogeneous integrated chips, a wafer-level testing device is needed. This device can achieve automated optical coupling and automated probe testing without damaging or warping the chips, ultimately enabling comprehensive parameter measurement and screening at the wafer level. This device, with its compact structure, rational layout, operability, and strong scalability, effectively solves the screening challenges of high-density silicon-based optoelectronic heterogeneous integrated chips and significantly reduces the cost of large-scale deployment of silicon-based heterogeneous integrated chips and optoelectronic fusion chips.

[0036] Based on this, the embodiments of the present application provide a testing system and a testing method for an optoelectronic heterogeneous integrated chip, which can improve the testing efficiency of the optoelectronic heterogeneous integrated chip and reduce the testing cost.

[0037] For example, Figure 1 As shown, the present application provides an optoelectronic heterogeneous integrated chip 100 . The optoelectronic heterogeneous integrated chip 100 includes: a wafer-level chip 110 , a plurality of electrical chips 120 and at least one optical chip 130 .

[0038] It is understandable that the electrical chip 120 is used to implement electrical signal transmission, and the optical chip 130 is used to implement conversion of electrical signals into optical signals.

[0039] The wafer-level chip 110 includes a first semiconductor substrate 111 and a plurality of transfer structures 112 disposed within the first semiconductor substrate 111. The transfer structures 112 extend from one surface of the wafer-level chip 110 to the other surface thereof in a direction perpendicular to the plane of the wafer-level chip 110. For example, the wafer-level chip 110 includes a first surface 1101 and a second surface 1102 that are opposite to each other. The transfer structures 112 form conductive bumps 1121 on portions of the first surface 1101. The portions of the transfer structures 112 that extend to the second surface are coupled to the electrical chip 120 and the optical chip 130.

[0040] A plurality of electrical chips 120 are spaced apart and arranged on the second surface 1102 of the wafer-level chip 110 and coupled to the conductive bumps 1121. The electrical chip 120 includes a second semiconductor substrate ( Figure 1The material of the first semiconductor substrate 111 may be different from the material of the second semiconductor substrate.

[0041] The optical chip 130 and the electrical chip 120 are spaced apart and arranged on the second surface 1102 of the wafer-level chip 110 and coupled to the conductive bumps 1121. The optical chip 130 includes a third semiconductor substrate ( Figure 1 The material of the first semiconductor substrate 111 may be different from the material of the third semiconductor substrate.

[0042] For example, Figure 1 As shown, the optical chip 130 includes at least one optical interface 131 , and the optical interface 131 is capable of transmitting optical signals.

[0043] It should be noted that the optoelectronic heterogeneous integrated chip 100 provided in this application is for the purpose of explaining the testing principle and workflow of the testing system, and does not limit the specific structure of the optoelectronic heterogeneous integrated chip 100 .

[0044] Based on the exemplary optoelectronic heterogeneous integrated chip 100 provided above, the following example of the present application provides a test system that can synchronously test the optical chip 130 and the electrical chip 120 in the same test system.

[0045] In some embodiments, as Figure 2 and Figure 3 As shown, the present application provides a testing system 200 for an optoelectronic heterogeneous integrated chip.

[0046] The test system 200 for optoelectronic heterogeneous integrated chips includes a carrier 210 , a first acquisition device 220 , a probe assembly 230 , a clamping assembly 240 , a second acquisition device 250 and an optical coupling module 260 .

[0047] The carrier 210 is used to carry the optoelectronic heterogeneous integrated chip 100 to be tested. Figure 1 As shown, the optoelectronic heterogeneous integrated chip 100 includes a wafer-level chip 110 , a plurality of conductive bumps 1121 located on a first surface 1101 of two opposite surfaces of the wafer-level chip 110 , and an electrical chip 120 and an optical chip 130 located on a second surface 1102 and coupled to the conductive bumps 1121 .

[0048] The first acquisition device 220 is disposed on one side of the support platform 210 and is configured to acquire first position information of the conductive bumps 1121 within the target area M on the first surface 1101. For example, the first acquisition device 220 may include a microscope and a drive motor. The microscope may include a stereo microscope, a mirror microscope, a telephoto microscope, or a digital microscope. The motor driving the microscope may include at least one of a stepper motor, a servo motor, and a linear motor.

[0049] The probe assembly 230 is used to adjust the probe 231 to contact the conductive bump 1121 in the target area M according to the first position information.

[0050] The clamping assembly 240 includes an annular chuck 241, which is used to connect to the edge of the optoelectronic heterogeneous integrated chip 100 to be tested. For example, the annular chuck 241 is a hollow structure. When connected and fixed to the edge of the optoelectronic heterogeneous integrated chip 100 to be tested, the conductive bumps 1121, the electrical chip 120, and the optical chip 130 on the optoelectronic heterogeneous integrated chip 100 to be tested are exposed.

[0051] The second acquisition device 250 is disposed on a side of the annular chuck 241 away from the first acquisition device 220 and is configured to acquire second position information of the optical interface 131 of the optical chip 130 within the target region M based on the position information of the target region M. For example, the second acquisition device 250 may include a microscope and a drive motor. The microscope may include a stereo microscope, a mirror microscope, a telephoto microscope, or a digital microscope. The motor driving the microscope may include at least one of a stepper motor, a servo motor, and a linear motor.

[0052] The optical coupling module 260 is disposed on a side of the annular chuck 241 away from the first acquisition device 220 , and is configured to acquire the optical signal transmitted by the optical interface 131 according to the second position information and perform a test.

[0053] The first surface 1101 and the second surface 1102 of the optoelectronic heterogeneous integrated chip 100 to be tested are exposed by the annular chuck 241 (see Figure 1 ), probe 2311 (see Figure 2 and Figure 3 ) are coupled to the conductive bumps 1121 on the first surface 1101 to transmit electrical signals to the electrical chip 120 and the optical chip 130; and the optical coupling module 260 is capable of receiving optical signals transmitted by the optical chip 130 on the second surface 1102. In this way, the optical chip 130 and the electrical chip 120 can be tested simultaneously using the probes 2311 on one side of the optoelectronic heterogeneous integrated chip 100 to be tested and the optical coupling module 260 on the other side. This not only expands the application scenarios for testing different types of integrated chips, but also improves testing efficiency, facilitates large-scale testing, and reduces testing costs.

[0054] Moreover, the combined structure and mutual positional relationship of the carrier platform 210, the first acquisition device 220, the probe assembly 230, the clamping assembly 240, the second acquisition device 250 and the optical coupling module 260 used in the above-mentioned optoelectronic heterogeneous integrated chip testing system 200 are conducive to improving the structural compactness of the testing system, and the position of each functional structure is controllably adjustable, which is suitable for the testing process of various heterogeneous integrated chips, thereby improving the applicability of the testing system.

[0055] For example, the material of the annular chuck 241 can be one or more of metal, ceramic or glass.

[0056] In some examples, the annular chuck 241 may be connected to the edge of the optoelectronic heterogeneous integrated chip 100 to be tested by clamping or vacuum adsorption.

[0057] For example, the annular chuck 241 is clamped with the edge of the optoelectronic heterogeneous integrated chip 100 to be tested, and a buffer pad can be provided at the clamping position to improve the tightness of the clamping and reduce the probability of wear on the edge of the optoelectronic heterogeneous integrated chip 100 to be tested by the clamping method.

[0058] Alternatively, the annular chuck 241 is connected to the edge region of the optoelectronic heterogeneous integrated chip 100 to be tested by vacuum adsorption. A plurality of vacuum adsorption holes can be formed on the front surface of the annular structure of the annular chuck 241 (i.e., for adsorbing the surface of the optoelectronic heterogeneous integrated chip 100 to be tested), and a vacuum adsorption gas source interface connected to the vacuum adsorption holes can be formed on the side surface of the annular structure of the annular chuck 241. Furthermore, an air flotation groove for blowing away the optoelectronic heterogeneous integrated chip 100 to be tested can be formed on the back surface of the annular structure of the annular chuck 241, and an air flotation gas source interface connected to the air flotation groove can be formed on the side surface of the annular structure of the annular chuck 241. The number and arrangement of the vacuum adsorption holes can be set according to actual needs.

[0059] In some examples, such as Figure 3 As shown, the optical coupling module 260 includes: an optical fiber array 261 and a driving motor assembly 262 .

[0060] The optical fiber array 261 is used to acquire the optical signal transmitted by the optical interface 131. For example, the optical fiber array 261 includes a plurality of optical fibers arranged in an array, the tips of the optical fibers can be reflective fibers or lens fibers, and the optical fiber materials can be silicon, glass or polymer materials.

[0061] The drive motor assembly 262 is coupled to the optical fiber array 261 and is configured to adjust the relative position of the optical fiber array 261 and the optical interface 131 based on the acquired optical signal power transmitted by the optical interface 131. The drive motor assembly 262 is configured to adjust the movement of the optical fiber array 261 along a first direction X, a second direction Y, and a third direction Z, where the first direction X, the second direction Y, and the third direction Z intersect with each other.

[0062] For example, the drive motor assembly 262 may include a piezoelectric ceramic motor with three-axis displacement and a stepper motor with three-axis rotational displacement. The piezoelectric ceramic motor with three-axis displacement can drive the linear movement of the optical fiber array 261 along the first direction X, the second direction Y, and / or the third direction Z, while the stepper motor with three-axis rotational displacement can adjust the rotation angle of the optical fiber array 261. This allows the ends of the optical fibers of the optical fiber array 261 to be parallel to the slanted waveguides of the optical chip 130, thereby improving optical coupling efficiency and thereby enhancing the sensitivity and accuracy of testing of the optoelectronic heterogeneous integrated chip 100.

[0063] Furthermore, the driving motor assembly 262 may further include a capacitive height probe or a laser rangefinder to precisely control the distance between the tip of the optical fiber array and the optical chip 130 .

[0064] In some examples, such as Figure 3 As shown, the probe assembly 230 includes a probe card 231 and a first position adjustment mechanism 232 connected to the probe card 231 .

[0065] The first position adjustment mechanism 232 includes a pressure sensor and a first robotic arm (not shown in the figure). The first robotic arm is used to adjust the distance between the probe card 231 and the optoelectronic heterogeneous integrated chip 100 to be tested according to the pressure value between the probe card 231 and the optoelectronic heterogeneous integrated chip 100 to be tested sensed by the pressure sensor.

[0066] At least one probe 2311 of the probe card 231 contacts a conductive bump 1121 in the target area M.

[0067] For example, the driving motor of the first robotic arm may include at least one of a stepper motor, a servo motor, and a linear motor. The present application does not impose any specific restrictions on the structure of the first robotic arm, as long as it can drive the position of the probe card 231 to change.

[0068] The probe card 231 includes multiple probes 2311. When the probe card 231 is aligned with a target area on the optoelectronic heterogeneous integrated chip 100 to be tested, at least one probe 2311 is brought into contact with a conductive bump 1121 within the target area M based on the first position information of the multiple conductive bumps 1121 and the arrangement of the probes 2311 (e.g., the number of probes 2311, the spacing between adjacent probes 2311, etc.). This helps improve the electrical signal transmission yield of the optical chip 130 and the electrical chip 120, and enhances the accuracy of the test.

[0069] In some examples, the optoelectronic heterogeneous integrated chip 100 to be tested is divided into a plurality of target regions M. The first acquisition device 220 is further configured to re-acquire first position information of the conductive bump 1121 in another target region M on the first surface 1101 .

[0070] The clamping assembly 240 further includes a second robotic arm (not shown) connected to the annular chuck 241 . The second robotic arm is used to move the optoelectronic heterogeneous integrated chip 100 to be tested according to the updated target area M.

[0071] For example, the optoelectronic heterogeneous integrated chip 100 to be tested can be divided into multiple target areas M. After the optical chip 130 and the electrical chip 120 in one target area M are tested, the first acquisition device 220 can re-determine another target area M. When the first robotic arm drives the probe card 231 away from the surface of the optoelectronic heterogeneous integrated chip 100 to be tested, and the optoelectronic heterogeneous integrated chip 100 to be tested is not fixed on the carrier 210, the second robotic arm of the clamping assembly 240 can move the annular chuck 241 (i.e., the optoelectronic heterogeneous integrated chip 100 to be tested) according to the first position information, and adjust the position of the probe card 231 through the first robotic arm according to the first position information of the conductive bump 1121 in another target area M, so that the probe card 231 contacts the conductive bump 1121 in the updated target area M. The present application does not impose any specific restrictions on the structure of the second robotic arm, and it is sufficient that it can drive the position change of the annular chuck 241.

[0072] In some examples, such as Figure 3 As shown, the carrying platform 210 includes a second position adjustment mechanism 211 and a carrying platform surface 212 connected to the second position adjustment mechanism 211 .

[0073] The second position adjustment mechanism 211 is used to adjust the position of the carrier surface 212 according to the target area M. The carrier surface 212 covers at least the portion of the optoelectronic heterojunction chip 100 corresponding to the target area M and exposes the optical interface 131. The area of ​​the target area M is represented by the area of ​​the probe card board 2310 of the probe assembly 230.

[0074] For example, the second position adjustment mechanism 211 can move the carrier 210 to a position close to the target area M. It can also adjust the distance between the carrier 210 and the optoelectronic heterogeneous integrated chip 100 to provide support and fixation by ensuring that the carrier surface 212 contacts the portion of the optoelectronic heterogeneous integrated chip 100 corresponding to the target area M. Furthermore, in order for the optical coupling module 260 to obtain the optical interface 131 to collect the optical signal, the carrier surface 212 needs to expose the optical interface 131.

[0075] The target region M is represented by the area of ​​the probe card plate 2310 of the probe assembly 230. The combined force of the probes 2311 and the support platform surface 212 can be taken into consideration to reduce the probability of structural warping in other areas (areas outside the target region) of the entire optoelectronic heterogeneous integrated chip 100 to be tested due to a smaller force-bearing area. The support platform surface 212 can be configured to cover at least the portion of the optoelectronic heterogeneous integrated chip 100 corresponding to the target region M, thereby improving structural stability.

[0076] For example, the driving motor of the second position adjustment mechanism 211 may include at least one of a stepper motor drive, a servo motor drive, and a linear motor drive.

[0077] In some examples, such as Figure 2 As shown, the second acquisition device 250, the optical coupling module 260 and the carrier 210 are located on the same mobile platform 270. The second position adjustment mechanism 211 (see Figure 3 ) is also used to drive the mobile platform 270 to move.

[0078] For example, consider a test process in which the second acquisition device 250 is used to determine the second position information of the optical interface 131 in the target area M, the carrier 210 is adjusted to contact the portion of the optoelectronic heterogeneous integrated chip 100 to be tested corresponding to the target area M and expose the optical interface 131, and then the optical coupling module 260 collects the optical signal transmitted by the optical interface 131. Setting the second acquisition device 250, the optical coupling module 260 and the carrier 210 on the same mobile platform 270 is beneficial to simplify the operating steps and improve the test efficiency.

[0079] For example, one or more of an air-floating platform, a marble platform, and a buffer pad can be provided at the bottom of the mobile platform 270 to provide support and shock absorption.

[0080] In some examples, such as Figure 3 As shown, a plurality of vacuum adsorption holes are provided on the carrying platform surface 212 ; the distribution density of the plurality of vacuum adsorption holes increases as the area of ​​the carrying platform surface 212 decreases.

[0081] Thus, when the area of ​​the optoelectronic heterogeneous integrated chip 100 to be tested is larger than the area of ​​the carrier table 212, for example, the area of ​​the optoelectronic heterogeneous integrated chip 100 to be tested may be 8 inches, 10 inches, or 12 inches, and the area of ​​the carrier table 212 may be 1 inch, 2 inches, etc., and not larger than the area of ​​the optoelectronic heterogeneous integrated chip 100 to be tested. By bringing the portion of the optoelectronic heterogeneous integrated chip 100 to be tested, which is pressed by the probe 2311 (i.e., the target area), into contact with the carrier table 212, and taking into account the combined force of the probe 2311 and the carrier table 212, the probability of structural warping of other areas (areas outside the target area) on the entire optoelectronic heterogeneous integrated chip 100 to be tested, which may be caused by a smaller area receiving the force, can be reduced, thereby improving structural stability.

[0082] For example, the shape of the arrangement of the multiple vacuum adsorption holes can be circular, rectangular or other polygonal, and can be set according to actual needs.

[0083] In addition, a semiconductor cooler and / or thermistor may be disposed under the carrier table 212 to adjust the temperature of the optoelectronic heterogeneous integrated chip 100 to be tested, thereby reducing the adverse effects of the number of test operations or the test environment on the accuracy of the test results.

[0084] On the other hand, Figure 4 and Figure 5 As shown, the embodiment of the present application provides a method for testing an optoelectronic heterogeneous integrated chip. The testing method includes: S100 to S400.

[0085] S100: The annular chuck 241 is connected to the edge of the optoelectronic heterogeneous integrated chip 100 to be tested; a target area M is determined on the optoelectronic heterogeneous integrated chip 100 to be tested. The target area M is provided with a plurality of conductive bumps 1121 coupled to the optical chip 130 and the electrical chip 120.

[0086] For example, you can Figure 1 The structure of the optoelectronic heterogeneous integrated chip 100 shown in FIG. 1 can be determined after the optoelectronic heterogeneous integrated chip 100 is placed on the carrier 210. Figure 3 The target area M is shown.

[0087] S200 : According to the position information of the target area M, the carrier table 212 is controlled to contact a portion of the optoelectronic heterogeneous integrated chip 100 to be tested in the target area M, and the optical interface 131 of the optical chip 130 is exposed.

[0088] For example, the controller controls the second position adjustment mechanism to adjust the displacement of the carrier 210 according to the position information of the target area M, and when the carrier 210 is located within the range of the corresponding target area, controls the carrier surface 212 to contact the portion of the optoelectronic heterogeneous integrated chip 100 to be tested in the target area M, and exposes the optical interface 131 of the optical chip 130.

[0089] S300 : collecting first position information of the conductive bump 1121 in the target area M, and adjusting the probe of the probe assembly 230 to contact the conductive bump 1121 according to the first position information.

[0090] For example, Figure 2 As shown, the first acquisition device 220 acquires first position information of the conductive bumps 1121 within the target area M and transmits it to the controller. Based on the first position information, the controller adjusts the displacement of the first robotic arm of the probe assembly 230, driving the probe card 231 to move so that at least one probe 2311 on the probe card 231 contacts one of the conductive bumps 1121.

[0091] S400 : Inputting electrical signals to the optical chip 130 and the electrical chip 120 through the probe 2311 . Testing the electrical chip 120 , and acquiring optical signals transmitted by the optical interface 131 of the optical chip 130 , to test the optical chip 130 .

[0092] For example, when the optoelectronic heterogeneous integrated chip 100 to be tested is stably placed on the carrier table 212 and the probe 2311 is in contact with the conductive bump 1121, an electrical signal is input to the conductive bump 1121 through the probe 2311 and is received by the optical chip 130 and the electrical chip 120 coupled to the conductive bump 1121.

[0093] Then, the signal fed back by the electrical chip 120 can be transmitted through the probe 2311 to test the electrical chip 120 ; and the optical chip 130 converts the received electrical signal into an optical signal and outputs it from the optical interface 131 to test the optical chip 130 .

[0094] During the above-mentioned testing method, the testing operations of the optical chip 130 and the electrical chip 120 can be performed simultaneously, thereby expanding the test application scope of semiconductor structures integrating different types of chips, improving testing efficiency, and helping to reduce testing costs.

[0095] In some examples, such as Figure 5 As shown, the testing method further includes S500.

[0096] S500: After the optoelectronic heterogeneous integrated chip 100 under test contacts the carrier 210, the profile information of the optoelectronic heterogeneous integrated chip 100 under test is collected. The placement angle of the optoelectronic heterogeneous integrated chip 100 under test is adjusted by the clamping assembly 240 to ensure that the optoelectronic heterogeneous integrated chip 100 under test is not tilted. This improves the yield rate and conductivity of the electrical connection between the probe 2311 and the conductive bump 1121.

[0097] In some examples, such as Figure 5 As shown, step S400: testing the optical chip 130 includes S410.

[0098] S410 : collecting second position information of the optical interface 131 of the optical chip 130 and obtaining the optical signal power transmitted by the optical interface 131 , adjusting the relative position of the optical fiber array 261 in the optical coupling module 260 and the optical interface 131 , and testing the optical chip 130 .

[0099] For example, the second acquisition device 250 may include a microscope and a drive motor. The microscope is used to determine the second position information of the optical interface 131 in the target area M. The drive motor (for example, by controlling the displacement of the mobile platform 270) adjusts the position of the optical coupling module 260 near the target area M. Then, the optical coupling module 260 can receive the optical signal transmitted by the optical chip 130 on the second surface 1102, and adjust the relative position of the optical fiber array 261 and the optical interface 131 according to the power of the optical signal. For example, adjust the rotation angle of the optical fiber array 261, and / or the distance between the optical fiber tip and the optical interface 131. In this way, the optical coupling efficiency can be improved and the accuracy of the test of the optical chip 130 can be improved.

[0100] In some examples, such as Figure 5 As shown, the testing method further includes: S420 to S440.

[0101] S420 : When the probe 2311 contacts the conductive bump 1121 , a first distance between the probe card 231 of the probe assembly 230 and the optoelectronic heterogeneous integrated chip 100 to be tested and a pressure value between the probe 2311 and the conductive bump 1121 are obtained.

[0102] For example, the first acquisition device 220 may acquire a first distance between the probe card 231 of the probe assembly 230 and the optoelectronic heterogeneous integrated chip 100 to be tested.

[0103] The probe assembly 230 includes a probe card 231 and a first position adjustment mechanism 232 connected to the probe card 231. The first position adjustment mechanism 232 includes a pressure sensor and a first mechanical arm. The pressure sensor can obtain the pressure value between the probe 2311 and the conductive bump 1121.

[0104] S430: Adjust the first distance to a second distance according to the pressure between the probe 2311 and the conductive bump 1121, where the second distance satisfies a preset pressure between the probe 2311 and the conductive bump 1121. The second distance is less than or equal to the first distance.

[0105] For example, the controller determines whether the current crimping distance between probe 2311 and conductive bump 1121 meets a second distance based on the first distance collected by first acquisition device 220 and the pressure value collected by the pressure sensor. The second distance is a preset distance that ensures probe 2311 does not damage the surface of the optoelectronic heterojunction integrated chip 100 under test and provides good electrical connection with conductive bump 1121. Thus, adjusting the distance between probe card 231 of probe assembly 230 and optoelectronic heterojunction integrated chip 100 under test to the second distance satisfies the chip testing requirements.

[0106] It is understood that when adjusting the distance between the probe card 231 of the probe assembly 230 and the optoelectronic heterogeneous integrated chip 100 to be tested, a larger distance is first maintained to prevent the probes 2311 from directly contacting the surface of the optoelectronic heterogeneous integrated chip 100 to be tested, thereby preventing the probes 2311 from damaging or scratching the surface of the optoelectronic heterogeneous integrated chip 100 to be tested. Then, the distance between the probe card 231 and the optoelectronic heterogeneous integrated chip 100 to be tested is gradually reduced to a second distance.

[0107] S440 : Testing the electronic chip 120 in the target area M through the probe 2311 .

[0108] For example, after the electrical signal is transmitted to the electrical chip 120 through the probe 2311, the electrical signal is processed and fed back inside the electrical chip 120. The controller determines the performance of the electrical chip 120 based on the feedback signal of the electrical chip 120 transmitted by the probe 2311, thereby realizing the test of the electrical chip 120.

[0109] Based on this, Figure 5 As shown, after the above-mentioned steps S420 and S430, electrical signals can be output to the optical chip 130 and the electrical chip 120 through the probe. Then, the time sequence of the test of the optical chip 130 and the test of the electrical chip 120 can be adjusted according to actual needs. The overall testing process is reflected in the synchronous testing of the optical chip 130 and the electrical chip 120.

[0110] It should be noted that the embodiments of the test system for optoelectronic heterogeneous integrated chips provided in this application and the embodiments of the test method are of the same concept; the various technical features in the technical solutions described in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the combination of the various technical features of the test system for optoelectronic heterogeneous integrated chips provided in the embodiments of this application can already solve the technical problems to be solved by this application; therefore, the signal processing device provided in the embodiments of this application is not limited by the test method provided in the embodiments of this application, and any test system for optoelectronic heterogeneous integrated chips that can apply the test method provided in the embodiments of this application is within the scope of protection of this application.

[0111] The above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A test system for optoelectronic heterogeneous integrated chips, characterized in that: include: A carrier platform for carrying an optoelectronic heterogeneous integrated chip to be tested; the optoelectronic heterogeneous integrated chip includes a wafer-level chip, a plurality of conductive bumps located on a first surface of two opposite surfaces of the wafer-level chip, and an electrical chip and an optical chip located on a second surface and coupled to the conductive bumps; A first collecting device, disposed on one side of the carrying platform, for collecting first position information of the conductive bumps in a target area on the first surface; a probe assembly, configured to adjust the probe to contact the conductive bump in the target area according to the first position information; A clamping assembly, comprising an annular chuck, wherein the annular chuck is used to connect to the edge of the optoelectronic heterogeneous integrated chip to be tested; a second acquisition device, disposed on a side of the annular chuck away from the first acquisition device, for acquiring second position information of the optical interface of the optical chip within the target area according to the position information of the target area; An optical coupling module is provided on a side of the annular chuck away from the first acquisition device, and is used to obtain the optical signal transmitted by the optical interface according to the second position information and perform a test.

2. The test system according to claim 1, wherein: The optical coupling module includes: an optical fiber array, for acquiring optical signals transmitted by the optical interface; a drive motor assembly coupled to the optical fiber array and configured to adjust a relative position between the optical fiber array and the optical interface according to the acquired optical signal power transmitted by the optical interface; The driving motor assembly is used to adjust the optical fiber array to move along a first direction, a second direction and a third direction, and the first direction, the second direction and the third direction intersect with each other.

3. The test system according to claim 1, wherein: The probe assembly includes a probe card, and a first position adjustment mechanism connected to the probe card; The first position adjustment mechanism includes a pressure sensor and a first mechanical arm, wherein the first mechanical arm is used to adjust the distance between the probe card and the optoelectronic heterogeneous integrated chip to be tested according to the pressure value between the probe card and the optoelectronic heterogeneous integrated chip to be tested sensed by the pressure sensor; Wherein, at least one probe of the probe card contacts one of the conductive bumps in the target area.

4. The test system according to claim 1, wherein: The optoelectronic heterogeneous integrated chip to be tested is divided into a plurality of target areas; The first acquisition device is further used to re-acquire first position information of the conductive bump in another target area on the first surface; The clamping assembly further includes a second mechanical arm connected to the annular chuck, and the second mechanical arm is used to move the optoelectronic integrated chip to be tested according to the updated target area.

5. The test system according to claim 1, wherein: The carrying platform includes a second position adjustment mechanism and a carrying platform surface connected to the second position adjustment mechanism, wherein the second position adjustment mechanism is used to adjust the position of the carrying platform surface according to the target area; The platform surface at least covers a portion of the optoelectronic heterogeneous integrated chip corresponding to the target area and exposes the optical interface; the area of ​​the target area is represented by the area of ​​the probe card board of the probe assembly.

6. The test system according to claim 5, characterized in that: The second acquisition device, the optical coupling module and the carrying platform are located on the same mobile platform; The second position adjustment mechanism is also used to drive the mobile platform to move.

7. The test system according to claim 5, characterized in that: A plurality of vacuum adsorption holes are provided on the surface of the carrying platform; and the distribution density of the plurality of vacuum adsorption holes increases as the area of ​​the surface of the carrying platform decreases.

8. A method for testing an optoelectronic heterogeneous integrated chip, characterized in that: A test system for an optoelectronic heterogeneous integrated chip according to any one of claims 1 to 7; the test method comprising: The annular chuck is connected to the edge of the optoelectronic heterogeneous integrated chip to be tested; a target area on the optoelectronic heterogeneous integrated chip to be tested is determined; a plurality of conductive bumps coupled to the optical chip and the electrical chip are provided in the target area; Controlling the carrier table to contact a portion of the optoelectronic heterogeneous integrated chip to be tested within the target area according to the position information of the target area, and exposing the optical interface of the optical chip; collecting first position information of the conductive bump in the target area, and adjusting the probe of the probe assembly to contact the conductive bump according to the first position information; Inputting electrical signals to the optical chip and the electrical chip through the probe; The electrical chip is tested, and an optical signal transmitted by the optical interface of the optical chip is obtained to test the optical chip.

9. The testing method according to claim 8, characterized in that: The testing of the optical chip includes: collecting second position information of the optical interface of the optical chip, obtaining the optical signal power transmitted by the optical interface, adjusting the relative position of the optical fiber array in the optical coupling module and the optical interface, and testing the optical chip.

10. The testing method according to claim 8, characterized in that: The test method further comprises: When the probe is in contact with the conductive bump, obtaining a first distance between the probe card of the probe assembly and the optoelectronic heterogeneous integrated chip to be tested, and a pressure value between the probe and the conductive bump; According to the pressure value between the probe and the conductive bump, the first distance is adjusted to a second distance, where the second distance satisfies a preset pressure value between the probe and the conductive bump; wherein the second distance is less than or equal to the first distance; The electrical chip in the target area is tested by the probe.

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