PCIe 3.0 AIC consistency test channel

Abstract

The invention provides a PCIe 3.0 AIC consistency test channel, and relates to the technical field of peripheral equipment high-speed interconnection bus testing. Comprising the steps that a first CEM connector, a first PCB differential transmission line and a PCB golden finger which are connected in sequence are arranged on a first PCB, and the first CEM connector is used for inserting an AIC card to be tested; a second CEM connector, a second PCB differential transmission line, a packaging loss analog circuit and an SMP connector which are connected in sequence are arranged on the second PCB, the PCB golden finger is connected with the second CEM connector, and the packaging loss analog circuit is an analog circuit comprising a first capacitor pair, a third PCB differential transmission line and a second capacitor pair. In this way, the consistency test channel conforming to the PCIe 3.0 standard is determined, and the consistency test of the receiving end of the PCIe 3.0 device is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of peripheral component interconnect express (PCIe) testing, and in particular to a PCIe 3.0 add-in card (AIC) consistency test channel. Background Art

[0002] PCIe is a high-speed serial computer expansion bus, widely used in the communication between AIC cards such as graphics cards, network cards, and accelerator cards and motherboards. The PCIe 3.0 specification supports a maximum single-channel rate of 8 Gigabits per second (8Gbps). In order to maintain the integrity of high-speed communication signals with a maximum single-channel rate of 8Gbps, the PCIe 3.0 specification stipulates that PCIe devices must perform consistency testing. The consistency test mainly includes the transmitter pulse width jitter (TPWJ) test, the transmitter pre-equalization (TP) test, and the receiver link equalization (RLE) test.

[0003] The receiver link equalization test requires the use of equipment or components such as a bit error rate analyzer, a consistency test channel, and a high-speed oscilloscope. The total loss of the consistency test channel must be 17dB@4GHz. The test principle of the consistency test channel is as follows: Figure 1 As shown, Figure 1 The schematic diagram shows the connection block diagram of the link equalization test at the PCIe 3.0AIC receiving end. The bit error rate analyzer sends a specific code pattern signal that meets the specification to the consistency test channel. After passing the consistency test channel, the code pattern will show a certain degree of degradation. The degraded signal is first connected to the oscilloscope for degradation calibration. After the calibration is qualified, the degraded signal is connected to the device under test (including the AIC card). The device under test is powered on, and the bit error analyzer is operated to start the bit error rate test on the device under test. If the test bit error rate is less than 1 bit per 10 12 bits, the consistency test is considered to have passed.

[0004] Currently, consistency testing is implemented by using a transmitter test fixture and an oscilloscope. However, using a transmitter test fixture and an oscilloscope can only implement the electrical consistency test of the transmitter of the PCIe 3.0 device, and cannot implement the consistency test of the receiver of the PCIe 3.0AIC. There is a lack of consistency test channels that comply with the PCIe 3.0 specification to implement the consistency test of the receiver of the PCIe 3.0 device. Summary of the invention

[0005] The purpose of the embodiment of the present invention is to provide a PCIe 3.0AIC consistency test channel to solve the problem of lack of a consistency test channel compliant with the PCIe 3.0 specification to implement consistency testing of the receiving end of a PCIe 3.0 device.

[0006] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0007] The present invention provides a PCIe 3.0AIC consistency test channel, which includes a first PCB, a second PCB, a first CEM connector, a first PCB differential transmission line, a PCB gold finger, a second CEM connector, a second PCB differential transmission line, a package loss simulation circuit and an SMP connector, wherein the package loss simulation circuit is a simulation circuit including a first capacitor pair, a third PCB differential transmission line and a second capacitor pair;

[0008] A first CEM connector, a first PCB differential transmission line and a PCB gold finger are arranged on the first PCB. The first CEM connector, the first PCB differential transmission line and the PCB gold finger are connected in sequence. The first CEM connector is used to insert the AIC card to be tested.

[0009] A second CEM connector, a second PCB differential transmission line, a package loss simulation circuit and an SMP connector are arranged on the second PCB. The second CEM connector, the second PCB differential transmission line, the package loss simulation circuit and the SMP connector are connected in sequence, and the PCB gold finger is connected to the second CEM connector.

[0010] In some embodiments, one end of the first capacitor pair is respectively connected to the SMP connector and one end of the third PCB differential transmission line, and the other end of the first capacitor pair is grounded. One end of the second capacitor pair is respectively connected to the other end of the third PCB differential transmission line and the second PCB differential transmission line, and the other end of the second capacitor pair is grounded. In some embodiments, the first capacitor pair includes two first capacitors, and the capacitance of the two first capacitors is 1 pF. The second capacitor pair includes two second capacitors, and the capacitance of the two second capacitors is 0.3 pF.

[0011] In some embodiments, the first PCB has at least 4 layers.

[0012] In some embodiments, the impedance of the first PCB differential transmission line is 85 ohms, the length of the first PCB differential transmission line is 4 inches, the line width of the first PCB differential transmission line is 6 mils, and the line spacing of the first PCB differential transmission line is 6 mils.

[0013] In some embodiments, the impedance of the second PCB differential transmission line is 85 ohms, the length of the second PCB differential transmission line is 11 inches, the line width of the second PCB differential transmission line is 6 mils, and the line spacing of the second PCB differential transmission line is 6 mils.

[0014] In some embodiments, in the package loss simulation circuit, the length of the third PCB differential transmission line is 1.4 inches, the impedance of the third PCB differential transmission line is 85 ohms, the line width of the third PCB differential transmission line is 6 mils, and the line spacing of the third PCB differential transmission line is 6 mils.

[0015] In some embodiments, both the first CEM connector and the second CEM connector are connectors compliant with the PCIe 3.0 specification.

[0016] In some embodiments, the first PCB differential transmission line, the second PCB differential transmission line, and the third PCB differential transmission line are all microstrip transmission line structures.

[0017] In some embodiments, the SMP connector is connected to a transmit port of a bit error rate analyzer.

[0018] Compared with the prior art, the present invention provides a PCIe 3.0AIC consistency test channel, comprising a first PCB, a second PCB, a first CEM connector, a first PCB differential transmission line, a PCB gold finger, a second CEM connector, a second PCB differential transmission line, a package loss simulation circuit and an SMP connector, wherein the package loss simulation circuit is an analog circuit comprising a first capacitor pair, a third PCB differential transmission line and a second capacitor pair; a first CEM connector, a first PCB differential transmission line and a PCB gold finger are arranged on the first PCB, the first CEM connector, the first PCB differential transmission line and the PCB gold finger are connected in sequence, and the first CEM connector is used to insert an AIC card to be tested; a second CEM connector, a second PCB differential transmission line, a package loss simulation circuit and an SMP connector are arranged on the second PCB, the second CEM connector, the second PCB differential transmission line, the package loss simulation circuit and the SMP connector are connected in sequence, and the PCB gold finger is connected to the second CEM connector. In this way, by setting the first CEM connector for inserting the AIC card to be tested, the first PCB differential transmission line, the PCB gold finger, the second CEM connector, the second PCB differential transmission line, the package loss simulation circuit and the SMP connector which are connected in sequence on two PCBs, a consistency test channel that complies with the PCIe 3.0 specification is determined to implement consistency testing of the receiving end of the PCIe 3.0 device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0020] Figure 1 The figure schematically shows a PCIe 3.0AIC receiver link equalization test connection diagram;

[0021] Figure 2 The structure diagram of the PCIe 3.0AIC consistency test channel is schematically shown;

[0022] Figure 3 A design example diagram of a first PCB is schematically shown;

[0023] Figure 4 A design example diagram of a second PCB is schematically shown;

[0024] Figure 5 An example diagram of a package loss simulation circuit is schematically shown;

[0025] Figure 6 The figure schematically shows the test result of the differential insertion loss of the consistency test channel.

[0026] Description of reference numerals:

[0027] 1. First PCB; 2. Second PCB; 3. First CEM connector; 4. First PCB differential transmission line; 5. PCB gold finger; 6. Second CEM connector; 7. Second PCB differential transmission line; 8. Package loss simulation circuit; 81. First capacitor pair; 82. Third PCB differential transmission line; 83. Second capacitor pair; 9. SMP connector. DETAILED DESCRIPTION

[0028] The following is a further detailed description of the embodiments of the present invention in conjunction with the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to exemplarily illustrate the principles of the present invention, but cannot be used to limit the scope of the present invention. The present invention can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0029] The following is a detailed description of a PCIe 3.0AIC consistency test channel in an embodiment of the present invention.

[0030] See also Figure 2 As shown, Figure 2The structure diagram of the PCIe 3.0AIC consistency test channel is schematically shown. The embodiment of the present invention proposes a PCIe 3.0AIC consistency test channel, which includes a first printed circuit board (PCB) 1, a second PCB 2, a first electromechanical card (CEM) connector, a first PCB differential transmission line 4, a PCB gold finger 5, a second CEM connector 6, a second PCB differential transmission line 7, a package loss simulation circuit 8 and a sub-miniature push-on (SMP) connector. The package loss simulation circuit 8 is a simulation circuit including a first capacitor pair 81, a third PCB differential transmission line 82 and a second capacitor pair 83;

[0031] A first CEM connector 3, a first PCB differential transmission line 4 and a PCB gold finger 5 are arranged on the first PCB 1. The first CEM connector 3, the first PCB differential transmission line 4 and the PCB gold finger 5 are connected in sequence. The first CEM connector 3 is used to insert the AIC card to be tested.

[0032] A second CEM connector 6, a second PCB differential transmission line 7, a package loss simulation circuit 8 and an SMP connector 9 are provided on the second PCB 2. The second CEM connector 6, the second PCB differential transmission line 7, the package loss simulation circuit 8 and the SMP connector 9 are connected in sequence, and the PCB gold finger 5 is connected to the second CEM connector 6.

[0033] Specifically, the package loss simulation circuit 8 is a capacitor-transmission line-capacitor (Capacitor-Transmission Line-Capacitor, CTC) package loss simulation circuit 8 .

[0034] Specifically, the first CEM connector 3 may be a x1-type first CEM connector 3, a x4-type first CEM connector 3, a x8-type first CEM connector 3, and a x16-type first CEM connector 3. Accordingly, the first PCB differential transmission line 4 may be 1 pair of first PCB differential transmission lines 4, 4 pairs of first PCB differential transmission lines 4, 8 pairs of first PCB differential transmission lines 4, and 16 pairs of first PCB differential transmission lines 4. Accordingly, the PCB gold finger 5 may be a x1-type PCB gold finger 5, a x4-type PCB gold finger 5, a x8-type PCB gold finger 5, and a x16-type PCB gold finger 5.

[0035] Accordingly, the second CEM connector 6 may be a x1-type second CEM connector 6, a x4-type second CEM connector 6, a x8-type second CEM connector 6, and a x16-type second CEM connector 6. Accordingly, the second PCB differential transmission line 7 may be 1 pair of second PCB differential transmission lines 7, 4 pairs of second PCB differential transmission lines 7, 8 pairs of second PCB differential transmission lines 7, and 16 pairs of second PCB differential transmission lines 7. Accordingly, the package loss simulation circuit 8 may be 1 package loss simulation circuit 8, 4 package loss simulation circuits 8, 8 package loss simulation circuits 8, and 16 package loss simulation circuits 8. Accordingly, the SMP connector 9 may be 1 pair of SMP connectors 9, 4 pairs of SMP connectors 9, 8 pairs of SMP connectors 9, and 16 pairs of SMP connectors 9.

[0036] The interface model value of the first CEM connector 3, the number of pairs of the first PCB differential transmission line 4, the interface model value of the PCB gold finger 5, the interface model value of the second CEM connector 6, the number of pairs of the second PCB differential transmission line 7, the number of package loss simulation circuits 8 and the number of pairs of the SMP connector 9 are the same.

[0037] Exemplarily, when the selected first CEM connector 3 is a x16-type first CEM connector 3, the first PCB differential transmission line 4 is 16 pairs of first PCB differential transmission lines 4, the PCB gold finger 5 is a x16-type PCB gold finger 5, the second CEM connector 6 is a x16-type second CEM connector 6, the second PCB differential transmission line 7 is 16 pairs of second PCB differential transmission lines 7, the package loss simulation circuit 8 is 16 package loss simulation circuits 8, and the SMP connector 9 is 16 pairs of SMP connectors 9.

[0038] The first PCB differential transmission line 4 and the second PCB differential transmission line 7 are both used to increase the link insertion loss. The PCB gold finger 5 on the first PCB1 is used to insert into the second CEM connector 6 on the second PCB2 to achieve the interconnection of the two PCBs. The second CEM connector 6 is used to accept the insertion of the PCB gold finger 5 on the first PCB1 to achieve the interconnection of the two PCBs. The package loss simulation circuit 8 is a simulation circuit including a first capacitor pair 81, a third PCB differential transmission line 82 and a second capacitor pair 83, wherein the first capacitor pair 81 is used to simulate the chip wafer pin parasitic capacitance, the second capacitor pair 83 is used to simulate the chip package pin parasitic capacitance, the transmission line is used to simulate the chip package transmission line, and the package loss simulation circuit 8 realizes the insertion loss simulation of the chip reference package.

[0039] The PCIe 3.0AIC consistency test channel provided by the present invention can support all existing CEM interface standards such as PCIe x1, PCIe x4, PCIe x8 and PCIe x16.

[0040] Figure 3The design example diagram of the first PCB 1 is schematically shown. The first CEM connector 3 is located on the left side of the first PCB 1. The first CEM connector 3 is a x16-type first CEM connector 3, and the x16-type first CEM connector 3 is a PCIe 3.0 plug-in connector. The two large black dots on the first CEM connector 3 are installation positioning holes. The first PCB differential transmission line 4 is located in the middle of the first PCB 1, and the number of pairs of the first PCB differential transmission line 4 is 16 pairs. The PCB gold finger 5 is a x16-type gold finger. The x16-type first CEM connector 3 has multiple pins, and the multiple pins include the B1 pin to the B80 pin. The x16-type PCB gold finger 5 has multiple pins, and the multiple pins include the B1 pin to the B80 pin.The B14 pin and the B15 pin of the x16 type first CEM connector 3 are both connected to one end of the first pair of first PCB differential transmission lines 4, the B19 pin and the B20 pin of the x16 type first CEM connector 3 are both connected to one end of the second pair of first PCB differential transmission lines 4, the B23 pin and the B24 pin of the x16 type first CEM connector 3 are both connected to one end of the third pair of first PCB differential transmission lines 4, the B27 pin and the B28 pin of the x16 type first CEM connector 3 are both connected to one end of the fourth pair of first PCB differential transmission lines 4, and the The B33 pin and B34 pin of the x16 type first CEM connector 3 are connected to one end of the 5th pair of first PCB differential transmission lines 4, the B37 pin and B38 pin of the x16 type first CEM connector 3 are connected to one end of the 6th pair of first PCB differential transmission lines 4, the B41 pin and B42 pin of the x16 type first CEM connector 3 are connected to one end of the 7th pair of first PCB differential transmission lines 4, the B45 pin and B46 pin of the x16 type first CEM connector 3 are connected to one end of the 8th pair of first PCB differential transmission lines 4, the B50 pin and B51 pin of the x16 type first CEM connector 3 are connected The 9th pair of first PCB differential transmission lines 4 are connected to one end, the B50 pin and the B51 pin of the x16 type first CEM connector 3 are connected to one end of the 9th pair of first PCB differential transmission lines 4, the B54 pin and the B55 pin of the x16 type first CEM connector 3 are connected to one end of the 10th pair of first PCB differential transmission lines 4, the B58 pin and the B59 pin of the x16 type first CEM connector 3 are connected to one end of the 11th pair of first PCB differential transmission lines 4, the B62 pin and the B63 pin of the x16 type first CEM connector 3 are connected to the 12th pair of first PCB differential transmission lines 4. One end of the transmission line 4 is connected, the B66 pin and the B67 pin of the x16 type first CEM connector 3 are both connected to one end of the 13th pair of first PCB differential transmission lines 4, the B70 pin and the B71 pin of the x16 type first CEM connector 3 are both connected to one end of the 14th pair of first PCB differential transmission lines 4, the B74 pin and the B75 pin of the x16 type first CEM connector 3 are both connected to one end of the 15th pair of first PCB differential transmission lines 4, and the B78 pin and the B79 pin of the x16 type first CEM connector 3 are both connected to one end of the 16th pair of first PCB differential transmission lines 4.

[0041] See also Figure 3As shown, the B14 pin and the B15 pin of the x16 type PCB gold finger 5 are connected to the other end of the first pair of first PCB differential transmission lines 4, the B19 pin and the B20 pin of the x16 type PCB gold finger 5 are connected to the other end of the second pair of first PCB differential transmission lines 4, the B23 pin and the B24 pin of the x16 type PCB gold finger 5 are connected to the other end of the third pair of first PCB differential transmission lines 4, and the B27 pin and the B28 pin of the x16 type PCB gold finger 5 are connected to the other end of the fourth pair of first PCB differential transmission lines 4. , the B33 pin and B34 pin of the x16 type PCB gold finger 5 are connected to the other end of the 5th pair of first PCB differential transmission lines 4, the B37 pin and B38 pin of the x16 type PCB gold finger 5 are connected to the other end of the 6th pair of first PCB differential transmission lines 4, the B41 pin and B42 pin of the x16 type PCB gold finger 5 are connected to the other end of the 7th pair of first PCB differential transmission lines 4, the B45 pin and B46 pin of the x16 type PCB gold finger 5 are connected to the other end of the 8th pair of first PCB differential transmission lines 4, The B50 pin and B51 pin of the x6 type PCB gold finger 5 are both connected to the other end of the 9th pair of first PCB differential transmission lines 4, the B54 pin and B55 pin of the x16 type PCB gold finger 5 are both connected to the other end of the 10th pair of first PCB differential transmission lines 4, the B58 pin and B59 pin of the x16 type PCB gold finger 5 are both connected to the other end of the 11th pair of first PCB differential transmission lines 4, the B62 pin and B63 pin of the x16 type PCB gold finger 5 are both connected to the other end of the 12th pair of first PCB differential transmission lines 4, The B66 pin and B67 pin of the x16 type PCB gold finger 5 are both connected to the other end of the 13th pair of first PCB differential transmission lines 4, the B70 pin and B71 pin of the x16 type PCB gold finger 5 are both connected to the other end of the 14th pair of first PCB differential transmission lines 4, the B74 pin and B75 pin of the x16 type PCB gold finger 5 are both connected to the other end of the 15th pair of first PCB differential transmission lines 4, and the B78 pin and B79 pin of the x16 type PCB gold finger 5 are both connected to the other end of the 16th pair of first PCB differential transmission lines 4.

[0042] To ensure that the AIC card can work normally after being inserted into the first CEM connector 3, the other pins in the first CEM connector 3 except for the pin connected to one end of the first PCB differential transmission line 4 can be connected to power supply devices, identification devices, communication devices and transmitting ends.

[0043] In this embodiment, one end of the first capacitor pair 81 is respectively connected to the SMP connector 9 and one end of the third PCB differential transmission line 82, and the other end of the first capacitor pair 81 is grounded. One end of the second capacitor pair 83 is respectively connected to the other end of the third PCB differential transmission line 82 and the second PCB differential transmission line 7, and the other end of the second capacitor pair 83 is grounded.

[0044] Specifically, Figure 4 The design example diagram of the second PCB2 is schematically shown. The second CEM connector 6 is located on the left side of the second PCB2. The second CEM connector 6 is a x16 type second CEM connector 6. The x16 type second CEM connector 6 is a PCIe 3.0 plug-in connector. The two large black dots on the second CEM connector 6 are installation positioning holes. The second PCB differential transmission line 7 is located on the second PCB2 and on the right side of the second CEM connector 6. The number of pairs of the second PCB differential transmission line 7 is 16. The package loss simulation circuit 8 is located on the second PCB2 and on the right side of the second PCB differential transmission line 7. The package loss simulation circuit 8 includes a second capacitor pair 83, a third PCB differential transmission line 82 and a first capacitor pair 81 connected in sequence. The number of package loss simulation circuits 8 is 16, including 16 second capacitor pairs 83, 16 pairs of third PCB differential transmission lines 82 and 16 first capacitor pairs 81. The SMP connector 9 is located on the rightmost side of the second PCB2. The number of pairs of the SMP connector 9 is 16.

[0045] See also Figure 4As shown, the x16 type second CEM connector 6 has a plurality of pins, including pins B1 to B80. Pins B14 and B15 of the x16 type second CEM connector 6 are both connected to one end of the first pair of second PCB differential transmission lines 7, pins B19 and B20 of the x16 type second CEM connector 6 are both connected to one end of the second pair of second PCB differential transmission lines 7, pins B23 and B24 of the x16 type second CEM connector 6 are both connected to one end of the third pair of second PCB differential transmission lines 7, pins B27 and B28 of the x16 type second CEM connector 6 are both connected to one end of the fourth pair of second PCB differential transmission lines 7, and pins B29 and B30 of the x16 type second CEM connector 6 are both connected to one end of the fourth pair of second PCB differential transmission lines 7. The B33 pin and the B34 pin of the x16 second CEM connector 6 are both connected to one end of the fifth pair of second PCB differential transmission lines 7, the B37 pin and the B38 pin of the x16 second CEM connector 6 are both connected to one end of the sixth pair of second PCB differential transmission lines 7, the B41 pin and the B42 pin of the x16 second CEM connector 6 are both connected to one end of the seventh pair of second PCB differential transmission lines 7, the B45 pin and the B46 pin of the x16 second CEM connector 6 are both connected to one end of the eighth pair of second PCB differential transmission lines 7, and the The B50 pin and the B51 pin of the x16 second CEM connector 6 are both connected to one end of the 9th pair of second PCB differential transmission lines 7, the B54 pin and the B55 pin of the x16 second CEM connector 6 are both connected to one end of the 10th pair of second PCB differential transmission lines 7, the B58 pin and the B59 pin of the x16 second CEM connector 6 are both connected to one end of the 11th pair of second PCB differential transmission lines 7, the B62 pin and the B63 pin of the x16 second CEM connector 6 are both connected to one end of the 12th pair of second PCB differential transmission lines 7, and the The B66 pin and B67 pin of the 6-type second CEM connector 6 are both connected to one end of the 13th pair of second PCB differential transmission lines 7, the B70 pin and B71 pin of the x16-type second CEM connector 6 are both connected to one end of the 14th pair of second PCB differential transmission lines 7, the B74 pin and B75 pin of the x16-type second CEM connector 6 are both connected to one end of the 15th pair of second PCB differential transmission lines 7, and the B78 pin and B79 pin of the x16-type second CEM connector 6 are both connected to one end of the 16th pair of second PCB differential transmission lines 7.

[0046] Figure 5 Schematically shows an example diagram of a package loss simulation circuit 8, where the two dots at the other end of the second capacitor pair 83 and the two dots at the other end of the first capacitor pair 81 are vias, see Figure 4 and Figure 5As shown, the other end of the first second capacitor pair 83 is grounded, the other end of the second second capacitor pair 83 is grounded, and so on, until the other end of the 16th second capacitor pair 83 is grounded. One end of the first second capacitor pair 83 is connected to the other end of the first pair of third PCB differential transmission lines 82 and the other end of the first pair of second PCB differential transmission lines 7, respectively, and one end of the second second capacitor pair 83 is connected to the other end of the second pair of third PCB differential transmission lines 82 and the other end of the second pair of second PCB differential transmission lines 7, respectively, and so on, until one end of the 16th second capacitor pair 83 is connected to the other end of the 16th pair of third PCB differential transmission lines 82 and the other end of the 16th pair of second PCB differential transmission lines 7, respectively. The other end of the first first capacitor pair 81 is grounded, the other end of the second first capacitor pair 81 is grounded, and so on, until the other end of the 16th first capacitor pair 81 is grounded. One end of the first first capacitor pair 81 is respectively connected to one end of the first pair of SMP connectors 9 and one end of the first pair of third PCB differential transmission lines 82, one end of the second first capacitor pair 81 is respectively connected to one end of the second pair of SMP connectors 9 and one end of the second pair of third PCB differential transmission lines 82, and so on, until one end of the 16th first capacitor pair 81 is respectively connected to one end of the 16th pair of SMP connectors 9 and one end of the 16th pair of third PCB differential transmission lines 82.

[0047] In this embodiment, the first capacitor pair 81 includes two first capacitors, and the capacitance of the two first capacitors is 1 pF. The second capacitor pair 83 includes two second capacitors, and the capacitance of the two second capacitors is 0.3 pF.

[0048] Exemplarily, the 16 first capacitor pairs 81 each include two first capacitors, and the capacitance of the 32 first capacitors is 1 pF; the 16 second capacitor pairs 83 each include two second capacitors, and the capacitance of the 32 second capacitors is 0.3 pF.

[0049] In this embodiment, the first PCB 1 has at least 4 layers.

[0050] Specifically, the number of layers of the first PCB 1 may be 4 layers, 6 layers, or 8 layers.

[0051] Exemplarily, when the number of layers of the first PCB1 is 4, the first PCB1 is a 4-layer stacked arrangement, wherein the top layer is a signal layer, and the second, third, and fourth layers are all ground (GND) layers, with a thickness of 1.6 mm, and the material is Flame Retardant level 4 (FR-4) material. The other end of the second capacitor pair 83 is connected to the GND of the second, third, and fourth layers through a via to achieve grounding. The other end of the first capacitor pair 81 is connected to the GND of the second, third, and fourth layers through a via to achieve grounding.

[0052] In this embodiment, the impedance of the first PCB differential transmission line 4 is 85 ohms, the length of the first PCB differential transmission line 4 is 4 inches, the line width of the first PCB differential transmission line 4 is 6 mils, and the line spacing of the first PCB differential transmission line 4 is 6 mils.

[0053] Exemplarily, the impedance of each pair of the 16 pairs of first PCB differential transmission lines 4 is 85 ohms, the length of each pair of the first PCB differential transmission lines 4 is 4 inches, the line width of each pair of the first PCB differential transmission lines 4 is 6 mils, and the line spacing of each pair of the first PCB differential transmission lines 4 is 6 mils.

[0054] In this embodiment, the impedance of the second PCB differential transmission line 7 is 85 ohms, the length of the second PCB differential transmission line 7 is 11 inches, the line width of the second PCB differential transmission line 7 is 6 mils, and the line spacing of the second PCB differential transmission line 7 is 6 mils. Since the second PCB differential transmission line 7 is long, serpentine winding is required.

[0055] Exemplarily, the impedance of each pair of second PCB differential transmission lines 7 among the 16 pairs of second PCB differential transmission lines 7 is 85 ohms, the length of each pair of second PCB differential transmission lines 7 is 11 inches, the line width of each pair of second PCB differential transmission lines 7 is 6 mils, and the line spacing of each pair of second PCB differential transmission lines 7 is 6 mils.

[0056] In this embodiment, in the package loss simulation circuit 8, the length of the third PCB differential transmission line 82 is 1.4 inches, the impedance of the third PCB differential transmission line 82 is 85 ohms, the line width of the third PCB differential transmission line 82 is 6 mils, and the line spacing of the third PCB differential transmission line 82 is 6 mils.

[0057] Exemplarily, the length of each pair of third PCB differential transmission lines 82 in the 16 pairs of third PCB differential transmission lines 82 is 1.4 inches, the impedance of each pair of third PCB differential transmission lines 82 is 85 ohms, the line width of each pair of third PCB differential transmission lines 82 is 6 mils, and the line spacing of each pair of third PCB differential transmission lines 82 is 6 mils.

[0058] In this embodiment, both the first CEM connector 3 and the second CEM connector 6 are connectors that comply with the PCIe 3.0 specification.

[0059] Exemplarily, both the x16-type first CEM connector 3 and the x16-type second CEM connector 6 are connectors that comply with the PCIe 3.0 specification.

[0060] In this embodiment, the first PCB differential transmission line 4 , the second PCB differential transmission line 7 and the third PCB differential transmission line 82 are all microstrip transmission line structures.

[0061] Exemplarily, the 16 pairs of first PCB differential transmission lines 4 , the 16 pairs of second PCB differential transmission lines 7 , and the 16 pairs of third PCB differential transmission lines 82 are all microstrip transmission line structures.

[0062] In this embodiment, the SMP connector 9 is connected to the sending port of the bit error rate analyzer.

[0063] Specifically, 16 pairs of SMP connectors 9 are patch-type semi-escapement SMP male connectors that support up to 26.5GHz bandwidth. The other end of the SMP connector 9 is connected to the sending port of the bit error rate analyzer, that is, the SMP interface on the SMP connector 9 is connected to the sending port on the bit error rate analyzer, that is, the Sub Miniature version A (SMA) interface, through an SMA to SMP cable. The transmitting end (SMP interface) of the AIC card to be tested is connected to the receiving end (SMA interface) on the bit error rate analyzer through an SMP to SMA cable. The receiving end of the AIC card to be tested is connected to the first CEM connector 3.

[0064] The SMP connector 9 is used to connect to the transmitting end of the bit error rate analyzer to perform the test.

[0065] Figure 6 The following diagram schematically shows the test results of the differential insertion loss of the consistency test channel. After the PCIe3.0AIC consistency test channel is set up, the insertion loss is tested using a vector network analyzer. Figure 6 As shown, the horizontal axis is frequency, unit is Hz, the vertical axis is differential insertion loss, unit is decibel, and the marking point is located at 4 GHz. It can be seen that the loss at a frequency of 4 GHz is 17.3 dB, which meets the requirements of the PCIe 3.0AIC consistency test channel.

[0066] The working principle of the PCIe 3.0AIC card receiving end link equalization capability test is as follows:

[0067] Step 1: Insert the PCB gold finger 5 on the first PCB1 into the second CEM connector 6 of the second PCB2, insert the AIC card to be tested into the first CEM connector 3 on the first PCB1, connect the sending port of the bit error rate analyzer to the interface of the first pair of SMP connectors 9 of the PCIe 3.0AIC consistency test channel through the SMA to SMP cable, and connect the first pair of sending ports of the AIC card to be tested to the receiving port of the bit error rate analyzer through the SMP to SMA cable, thus completing the setup of the receiving end consistency test environment for the AIC card to be tested. After completing the setup of the consistency test environment, power on the AIC card to be tested.

[0068] Step 2: Since the initial working rate of the PCIe 3.0 device is 2.5 Gbps, the bit error rate analyzer is used to negotiate the rate of the AIC card to be tested and the rate is negotiated to 8 Gbps.

[0069] Step 3: Use the test menu of the bit error rate analyzer to enter the PCIe 3.0 receiver link equalization test item.

[0070] Step 4: Use the test menu of the bit error rate analyzer to negotiate the AIC card to enter the 8 Gbps loopback test mode.

[0071] Step 5: Use the test menu of the bit error rate analyzer to send a consistency test pattern that complies with the PCIe 3.0 specification.

[0072] Step 6: Open the test menu of the bit error rate analyzer, enter the bit error reading interface, and wait for the bit error test number to reach 10. 12 Stop the test after one bit is reached and record the number of bit errors.

[0073] Step 7: Power off the AIC card to be tested, switch the test channel, connect the sending port of the bit error rate analyzer to the second pair of SMP connectors 9 on the PCIe 3.0AIC consistency test channel, connect the corresponding sending end of the AIC card to be tested to the receiving port of the bit error rate analyzer, and then power on the AIC card to be tested, and repeat steps 2 to 6.

[0074] Step 8: After all channels of the AIC card to be tested are tested, organize the data and generate a test report.

[0075] The PCIe 3.0AIC consistency test channel of the embodiment of the present invention includes a first PCB1, a second PCB2, a first CEM connector 3, a first PCB differential transmission line 4, a PCB gold finger 5, a second CEM connector 6, a second PCB differential transmission line 7, a package loss simulation circuit 8 and an SMP connector 9, wherein the package loss simulation circuit 8 is a simulation circuit including a first capacitor pair 81, a third PCB differential transmission line 82 and a second capacitor pair 83; a first CEM connector 3, a first PCB differential transmission line 4 and a PCB gold finger 5 are arranged on the first PCB1, the first CEM connector 3, the first PCB differential transmission line 4 and the PCB gold finger 5 are connected in sequence, and the first CEM connector 3 is used to insert the AIC card to be tested; a second CEM connector 6, a second PCB differential transmission line 7, a package loss simulation circuit 8 and an SMP connector 9 are arranged on the second PCB2, the second CEM connector 6, the second PCB differential transmission line 7, the package loss simulation circuit 8 and the SMP connector 9 are connected in sequence, and the PCB gold finger 5 and the second CEM connector 6 are connected. In this way, by setting the first CEM connector 3 for inserting the AIC card to be tested, the first PCB differential transmission line 4, the PCB gold finger 5, the second CEM connector 6, the second PCB differential transmission line 7, the package loss simulation circuit 8 and the SMP connector 9 which are connected in sequence on two PCBs, a consistency test channel that complies with the PCIe 3.0 specification is determined to achieve consistency testing of the receiving end of the PCIe3.0 device.

[0076] Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present invention. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there is no structural conflict.

[0077] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A PCIe 3.0AIC consistency test channel, characterized in that: The PCIe 3.0AIC consistency test channel includes a first PCB, a second PCB, a first CEM connector, a first PCB differential transmission line, a PCB gold finger, a second CEM connector, a second PCB differential transmission line, a package loss simulation circuit and an SMP connector, wherein the package loss simulation circuit is a simulation circuit including a first capacitor pair, a third PCB differential transmission line and a second capacitor pair; The first CEM connector, the first PCB differential transmission line and the PCB gold finger are arranged on the first PCB, the first CEM connector, the first PCB differential transmission line and the PCB gold finger are connected in sequence, and the first CEM connector is used to insert the AIC card to be tested; The second CEM connector, the second PCB differential transmission line, the package loss simulation circuit and the SMP connector are arranged on the second PCB. The second CEM connector, the second PCB differential transmission line, the package loss simulation circuit and the SMP connector are connected in sequence, and the PCB gold finger is connected to the second CEM connector.

2. The PCIe 3.0AIC consistency test channel according to claim 1, characterized in that: One end of the first capacitor pair is respectively connected to the SMP connector and one end of the third PCB differential transmission line, and the other end of the first capacitor pair is grounded. One end of the second capacitor pair is respectively connected to the other end of the third PCB differential transmission line and the second PCB differential transmission line, and the other end of the second capacitor pair is grounded.

3. The PCIe 3.0AIC consistency test channel according to claim 1, characterized in that: The first capacitor pair includes two first capacitors, each of which has a capacitance of 1 pF. The second capacitor pair includes two second capacitors, each of which has a capacitance of 0.3 pF.

4. The PCIe 3.0AIC consistency test channel according to claim 1, characterized in that: The first PCB has at least 4 layers.

5. The PCIe 3.0AIC consistency test channel according to claim 1, characterized in that: The impedance of the first PCB differential transmission line is 85 ohms, the length of the first PCB differential transmission line is 4 inches, the line width of the first PCB differential transmission line is 6 mils, and the line spacing of the first PCB differential transmission line is 6 mils.

6. The PCIe 3.0AIC consistency test channel according to claim 1, characterized in that: The impedance of the second PCB differential transmission line is 85 ohms, the length of the second PCB differential transmission line is 11 inches, the line width of the second PCB differential transmission line is 6 mils, and the line spacing of the second PCB differential transmission line is 6 mils.

7. The PCIe 3.0AIC consistency test channel according to claim 1, characterized in that: In the package loss simulation circuit, the length of the third PCB differential transmission line is 1.4 inches, the impedance of the third PCB differential transmission line is 85 ohms, the line width of the third PCB differential transmission line is 6 mils, and the line spacing of the third PCB differential transmission line is 6 mils.

8. The PCIe 3.0AIC consistency test channel according to claim 1, characterized in that: Both the first CEM connector and the second CEM connector are connectors that comply with the PCIe 3.0 specification.

9. The PCIe 3.0AIC consistency test channel according to claim 1, characterized in that: The first PCB differential transmission line, the second PCB differential transmission line and the third PCB differential transmission line are all microstrip transmission line structures.

10. The PCIe 3.0AIC consistency test channel according to claim 1, characterized in that: The SMP connector is connected to a transmission port of a bit error rate analyzer.

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