An electronic component testing method, system, intelligent terminal and storage medium

Abstract

The present application relates to an electronic component testing method, system, intelligent terminal and storage medium, and relates to the field of electronic component testing technology. The method includes: in response to detecting a test operation, storing a test instruction in a first storage space, and storing a microinstruction in a second storage space, and there is associated information between the microinstruction and the test instruction; preferentially reading the microinstruction, determining the target test instruction corresponding to the microinstruction and determining the test instruction position corresponding to the target microinstruction after the operation; reading the current test instruction used in this test from the first storage space according to the test instruction position; generating the test instruction operation logic of the electronic component according to the current test instruction and the test instruction position; executing the test instruction according to the test instruction operation logic to complete the test of the electronic component. The present application has the effect of reducing the storage space of the instruction and improving the test speed.

Description

Technical Field

[0001] The present application relates to the technical field of electronic component testing, and in particular to an electronic component testing method, system, intelligent terminal and storage medium. Background Art

[0002] Electronic component testing is a testing process that electronic components must undergo before leaving the factory. The purpose is to ensure that the electronic components meet the design requirements, can work normally and achieve the expected performance. During the testing process, it is necessary to consider various parameters of the components, their working status and their interactions with other components.

[0003] When testing electronic components, related technologies send step instructions to the electronic components. The step instructions include test instructions and microinstructions. Test instructions are control information for the high and low levels of each pin of the electronic components. Microinstructions are some special state instructions, such as jump, loop, etc. While the electronic components are executing the step instructions, the host computer monitors the output level of the pin in real time and determines whether the electronic components are working normally through the output level.

[0004] Regarding the above-mentioned related technologies, the inventor believes that step instructions are composed of test instructions and microinstructions, but the probability of microinstructions appearing is small, so some test instructions that do not require microinstructions will be followed by blank microinstructions, occupying the storage space of step instructions and affecting the test speed. Summary of the invention

[0005] In order to reduce the storage space of instructions and improve the test speed, the present application provides an electronic component testing method, system, intelligent terminal and storage medium.

[0006] In a first aspect, the present application provides an electronic component testing method, which adopts the following technical solution:

[0007] A method for testing electronic components, comprising:

[0008] In response to detecting a test operation, storing a test instruction in a first storage space and storing a microinstruction in a second storage space, wherein the microinstruction has associated information with the test instruction;

[0009] Reading the microinstruction, determining a target test instruction corresponding to the microinstruction and determining a test instruction position corresponding to the target microinstruction after the operation;

[0010] Reading a current test instruction used in this test from the first storage space according to the test instruction position;

[0011] Generate test instruction operation logic for electronic components according to the current test instruction and the test instruction position;

[0012] The test instruction is executed according to the test instruction running logic to complete the test of the electronic component.

[0013] By adopting the above technical solution, the test instructions and microinstructions are stored separately, and there is no need to place microinstructions after the test instructions. This can effectively reduce the storage space of the instructions, improve the reading speed of the test instructions, and improve the test running speed of electronic components.

[0014] Optionally, determining an arrangement position of the target test instruction in an initial arrangement sequence of the test instructions;

[0015] According to the test instruction position and the arrangement position, the initial arrangement order is adjusted to obtain a reading order of the test instructions;

[0016] The current test instructions are read sequentially from the first storage space according to the reading order.

[0017] By adopting the above technical solution, the reading order of the test instructions is determined by the content of the microinstructions, so that the reading order is consistent with the execution order of the test instructions, the reading efficiency of the test instructions can be improved, and the reading and execution of the test instructions can be realized synchronously.

[0018] Optionally, in response to a first update operation, determining a first microinstruction in the second storage space, the first update operation comprising at least one of an add operation, a delete operation, and a modify operation;

[0019] Reading the first microinstruction, obtaining a first test instruction corresponding to the first microinstruction and determining a first test instruction position corresponding to the first microinstruction after the operation;

[0020] Comparing whether an original test instruction position and the first test instruction position are consistent, the original test instruction position being a test instruction position corresponding to the first microinstruction after the operation before receiving the update operation;

[0021] If yes, keep the reading order unchanged;

[0022] If not, the reading order is updated according to the first test instruction position.

[0023] By adopting the above technical solution, only the microinstructions can be updated separately. The updating process will not affect the test instructions, and there is no need to rewrite new test instructions, so the online real-time adjustment of the test instructions can be realized.

[0024] Optionally, reading the first test instruction from the first storage space according to the updated reading order;

[0025] Extracting the priority order of the test instructions;

[0026] Determining whether the updated reading order is mutually exclusive with the priority order;

[0027] If so, identifying candidate test instructions that are mutually exclusive with the updated reading order and the priority order; combining the candidate test instructions and the priority order to generate prompt information;

[0028] If not, continue with the next steps.

[0029] By adopting the above technical solution, it is judged whether the updated microinstructions will affect the normal execution of the test instructions, and it is ensured that the updated microinstructions can correctly instruct the test instructions to work normally.

[0030] Optionally, in the case where the first microinstruction is a microinstruction of the target type, determining whether the reading order before the update and the reading order after the update are both mutually exclusive with the priority order;

[0031] If not, generating a first test instruction execution logic using the read sequence before the update, and generating a second test instruction execution logic using the read sequence after the update;

[0032] Determine the overlap between the first test instruction execution logic and the second test instruction execution logic;

[0033] Using the overlapped portion to test the electronic components;

[0034] When the test reaches the end of the overlapping portion, the first test instruction running logic or the second test instruction running logic is selected for execution according to the test scenario of the electronic component.

[0035] By adopting the above technical solution, two different test instruction running logics are assigned to the test instruction by setting the target type of microinstructions. In the actual test process, different test instruction running logics will be used for testing according to different situations. Moreover, for different test instruction running logics, it is not necessary to store multiple sets of different test instructions, but only one set of test instructions is needed, which can reduce the storage space of the test instructions and ensure the test efficiency of the electronic component test process.

[0036] Optionally, in response to a second update operation, determining a second test instruction in the first storage space, the second update operation comprising at least one of an add operation, a delete operation and a modify operation;

[0037] In the case where the second test instruction is the current test instruction, using the second test instruction to update the test instruction running logic;

[0038] Detecting whether the test instruction running logic passes the feasibility judgment;

[0039] If yes, executing the test instruction according to the test instruction running logic;

[0040] If not, an error reporting instruction in the test instruction execution logic is identified; and an error reporting signal is generated using the error reporting instruction, wherein the error reporting signal is used to indicate the position of the error reporting instruction in the reading sequence.

[0041] By adopting the above technical solution, the test instructions can be updated separately without affecting the microinstructions. In the case of errors in the separate update of the test instructions, an error signal will be generated to prompt relevant personnel to ensure the normal execution of the test of the electronic components.

[0042] Optionally, extracting the error reporting instruction and a second microinstruction corresponding to the error reporting instruction;

[0043] According to the priority order of the second microinstruction and the test instruction, identifying the error cause of the error instruction;

[0044] The second microinstruction is modified according to the error cause.

[0045] By adopting the above technical solution, after the test instruction is updated, the error reporting instruction can be adaptively modified so that the modified error reporting instruction can be normally executed by the electronic component, thereby ensuring the normal test of the electronic component.

[0046] In a second aspect, the present application provides an electronic component testing system, which adopts the following technical solution:

[0047] An electronic component testing system, comprising:

[0048] An acquisition module, used for acquiring a test operation, a test instruction, a microinstruction, a first update operation, an original test instruction position, a priority order, and a second update operation;

[0049] A memory for storing a program of any of the above electronic component testing methods;

[0050] The program in the memory can be loaded and executed by the processor to implement any of the above-mentioned electronic component testing methods.

[0051] By adopting the above technical solution, the test instructions and microinstructions are stored separately, and there is no need to place microinstructions after the test instructions. This can effectively reduce the storage space of the instructions, improve the reading speed of the test instructions, and improve the test running speed of electronic components.

[0052] In a third aspect, the present application provides a smart terminal, which adopts the following technical solution:

[0053] An intelligent terminal comprises a memory and a processor, wherein the memory stores a computer program which can be loaded by the processor and execute any one of the above methods.

[0054] By adopting the above technical solution, the test instructions and microinstructions are stored separately, and there is no need to place microinstructions after the test instructions. This can effectively reduce the storage space of the instructions, improve the reading speed of the test instructions, and improve the test running speed of electronic components.

[0055] In a fourth aspect, the present application provides a computer storage medium capable of storing corresponding programs, which is convenient for reducing the storage space of instructions and improving the test speed, and adopts the following technical solutions:

[0056] A computer-readable storage medium stores a computer program that can be loaded by a processor and execute any of the above-mentioned electronic component testing methods.

[0057] By adopting the above technical solution, the test instructions and microinstructions are stored separately, and there is no need to place microinstructions after the test instructions. This can effectively reduce the storage space of the instructions, improve the reading speed of the test instructions, and improve the test running speed of electronic components.

[0058] In summary, the present application includes at least one of the following beneficial technical effects:

[0059] The test instructions and microinstructions are stored separately, and there is no need to place microinstructions after the test instructions, which can effectively reduce the storage space of the instructions, improve the reading speed of the test instructions, and improve the test running speed of electronic components;

[0060] The reading order of the test instructions is determined by the content of the microinstructions, so that the reading order is consistent with the execution order of the test instructions, which can improve the reading efficiency of the test instructions and can realize the reading and execution of the test instructions synchronously;

[0061] Only the microinstructions can be updated separately. The updating process will not affect the test instructions, and there is no need to rewrite new test instructions, so the test instructions can be adjusted online in real time. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 It is a flow chart of an electronic component testing method provided in an embodiment of the present application.

[0063] Figure 2 It is a flowchart of a method for reading a test instruction provided in an embodiment of the present application.

[0064] Figure 3 It is a flowchart of a microinstruction updating method provided in an embodiment of the present application.

[0065] Figure 4 It is a flowchart of a method for reading a test instruction provided in an embodiment of the present application.

[0066] Figure 5 It is a flowchart of multiple testing methods for electronic components provided in an embodiment of the present application.

[0067] Figure 6 It is a flowchart of a method for updating a test instruction provided in an embodiment of the present application.

[0068] Figure 7 It is a flowchart of a test instruction repair method provided in an embodiment of the present application.

[0069] Figure 8 It is a structural schematic diagram of an electronic component testing system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solutions and advantages of this application more clear, the following Figure 1-8 It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0071] The present application embodiment discloses a flow chart of a method for testing electronic components. Figure 1 , the method comprising:

[0072] Step S101: In response to detecting a test operation, a test instruction is stored in a first storage space, and a microinstruction is stored in a second storage space, wherein there is associated information between the microinstruction and the test instruction.

[0073] The test operation refers to the operation of testing the electronic components. For example, an electrical connection between the electronic components and the host computer is established. The test operation may be that the host computer sends a step instruction to the electronic components, and the step instruction includes a test instruction and a microinstruction. Furthermore, the host computer sends the test instruction and the microinstruction separately.

[0074] In other optional implementations of this embodiment, the test instructions are pre-stored in the first storage space, and the microinstructions are pre-stored in the second storage space. The host computer sends the test instructions to the electronic components, and the electronic components execute subsequent steps after receiving the test instructions.

[0075] The test instructions are the control information of the high and low levels of each pin on the electronic components.

[0076] Microinstructions are special state instructions, such as jump instructions, loop instructions, interrupt instructions, input and output instructions, etc.

[0077] The association information is used to indicate the correspondence between microinstructions and test instructions.

[0078] In some possible implementation modes, the microinstructions carry associated information, and the associated information is used to indicate the instruction sequence of the test instructions corresponding to the microinstructions.

[0079] In some possible implementation modes, both the test instructions and the microinstructions carry association information, and the test instructions and microinstructions corresponding to each other have the same association information.

[0080] In this application, electronic components include chips, integrated circuits, semiconductor devices, electronic instruments, etc.

[0081] Step S102: read the microinstruction, determine the target test instruction corresponding to the microinstruction and determine the test instruction position corresponding to the target microinstruction after the operation.

[0082] The test instruction position refers to the position of the next test instruction of the target test instruction after the operation of the microinstruction.

[0083] Exemplarily, the target test instruction corresponding to the microinstruction is determined by the association information on the microinstruction. It should be noted that not all test instructions have corresponding microinstructions. In actual scenarios, only some test instructions have corresponding microinstructions.

[0084] Step S103: Read the current test instruction used in this test from the first storage space according to the test instruction position.

[0085] The current test instruction refers to the test instruction used in this test. Due to the existence of microinstructions, not all test instructions will be used in the actual test process, but some test instructions may not be used in this test. For example, when the microinstruction is a jump instruction, if the microinstruction runs to the third line of test instructions and then jumps to the fifth line of test instructions to continue running, the fourth line of test instructions will not be tested.

[0086] Step S104: Generate the test instruction running logic of the electronic component according to the current test instruction and the test instruction position.

[0087] The test instruction operation logic is used to represent the actual execution logic of electronic components during the test process.

[0088] Exemplarily, the test instruction execution logic starts from the first line of test instructions and executes in sequence to the third line of test instructions, then jumps to the fifth line of test instructions, and then loops and executes the fifth line of test instructions for 3 seconds.

[0089] Step S105: Execute the test instruction according to the test instruction running logic to complete the test of the electronic components.

[0090] In another optional implementation manner of the present application, reading the current test instruction and executing the test instruction are performed synchronously.

[0091] By adopting the above technical solution, the test instructions and microinstructions are stored separately, and there is no need to place microinstructions after the test instructions. This can effectively reduce the storage space of the instructions, improve the reading speed of the test instructions, and improve the test running speed of electronic components.

[0092] In the following embodiments, when reading the test instructions, the test instructions can be read in a certain order, which is conducive to the simultaneous reading and execution of the test instructions. The embodiment of the present application discloses a flow chart of a method for reading a test instruction. Figure 2 , the method comprising:

[0093] Step S201: Determine the arrangement position of the target test instruction in the initial arrangement sequence of the test instructions.

[0094] The initial arrangement sequence refers to the preset arrangement sequence of the test instructions in the initial state.

[0095] The arrangement position refers to the position of the target test instruction among all test instructions.

[0096] Exemplarily, the arrangement position of the target test instruction is determined by the association information. For example, it is determined that the target test instruction is the test instruction in the third row.

[0097] Step S202: adjusting the initial arrangement sequence according to the test instruction position and the arrangement position to obtain the reading sequence of the test instructions.

[0098] The arrangement positions correspond one-to-one to the test instruction positions.

[0099] Exemplarily, the arrangement position is determined in the initial arrangement sequence, and the next position of the arrangement position is updated to the test instruction position; after the above-mentioned update process is completed, the test instruction after the test instruction position is determined from the initial arrangement sequence and used as the reading order.

[0100] For example, if the test instruction position corresponds to the 2nd line of test instructions, and its corresponding test instruction position corresponds to the 4th line of test instructions, then in the reading order, the next test instruction of the 2nd line of test instructions is the 4th line of test instructions, not the 3rd line of test instructions, and at the same time, the reading order after the 4th line of test instructions is determined according to the arrangement order after the 4th line of test instructions in the initial arrangement order. That is, the reading order is the 1st line of test instructions, the 2nd line of test instructions, the 4th line of test instructions, and the 5th line of test instructions.

[0101] Step S203: read the current test instructions from the first storage space in sequence according to the reading order.

[0102] Furthermore, after the current test instruction is read, the current test instruction can be directly executed, thereby realizing synchronous operation of reading and executing the test instruction.

[0103] In some other embodiments, the execution time of the test instruction executed by the electronic component is recorded. When testing the same type of electronic components, the reading time of the current test instruction can be set according to the execution time, so that the reading time of each current test instruction is consistent with the execution time of the previous current test instruction, thereby realizing the synchronous operation of reading and executing the current test instruction.

[0104] In summary, the reading order of the test instructions is determined by the content of the microinstructions, so that the reading order is consistent with the execution order of the test instructions, the reading efficiency of the test instructions can be improved, and the reading and execution of the test instructions can be realized synchronously.

[0105] In the following embodiments, because the test instructions and microinstructions are stored separately, the present application can update the microinstructions separately. Therefore, the present application embodiment discloses a flow chart of a method for updating microinstructions. Figure 3 , the method comprising:

[0106] Step S301: In response to a first update operation, determining a first microinstruction in a second storage space, the first update operation including at least one of an add operation, a delete operation, and a modify operation.

[0107] The first microinstruction refers to the microinstruction in the second storage space that is subjected to the first update operation.

[0108] Exemplarily, the first update operation is that the host computer sends a first microinstruction to the electronic component, and the electronic component searches the second storage space for a position corresponding to the first microinstruction according to the updated microinstruction.

[0109] In some other embodiments, a second microinstruction is determined in a second storage space, and a first update operation is performed on the second microinstruction.

[0110] Step S302: read the first microinstruction, obtain the first test instruction corresponding to the first microinstruction and determine the first test instruction position corresponding to the first microinstruction after the operation.

[0111] The first test instruction position refers to the position of the next test instruction of the first test instruction after the operation of the first microinstruction.

[0112] Step S303: comparing the original test instruction position and the first test instruction position to see if they are consistent, the original test instruction position being the test instruction position corresponding to the first microinstruction after the operation before receiving the update operation.

[0113] If the original test instruction position is consistent with the first test instruction position, step S304 is executed;

[0114] If the original test instruction position is inconsistent with the first test instruction position, step S305 is executed.

[0115] Step S304: If yes, keep the reading order unchanged.

[0116] If the original test instruction position is consistent with the first test instruction position, it means that the update of the first microinstruction will not affect the reading order of the test instructions, so the reading order remains unchanged.

[0117] Step S305: If not, then update the reading order according to the first test instruction position.

[0118] The reading sequence is updated according to the first test instruction position, so that in the updated reading sequence, the next test instruction of the first test instruction corresponds to the first test instruction position.

[0119] In summary, only the microinstructions can be updated separately, the updating process will not affect the test instructions, and there is no need to rewrite new test instructions, so the online real-time adjustment of the test instructions can be realized.

[0120] In the following embodiments, after the microinstructions are updated, it is also necessary to consider whether the updated reading order will affect the normal operation of the test instructions. Therefore, the embodiment of the present application discloses a flow chart of a method for reading a test instruction. Figure 4 , the method comprising:

[0121] Step S401: Read a first test instruction from a first storage space according to an updated reading order.

[0122] Exemplarily, if the original test instruction position is consistent with the first test instruction position, the reading order does not change, and the first test instruction is read from the first storage space in the original reading order. If the original test instruction position is consistent with the first test instruction position, the reading order changes, and the first test instruction is read from the first storage space using the updated reading order.

[0123] Step S402: extracting the priority order of the test instructions.

[0124] The priority order is used to indicate the intended execution order of the test instructions.

[0125] For example, when testing electronic components, some test instructions have execution order requirements. For example, the 2nd line of test instructions need to be executed before the 4th line of test instructions are executed. For another example, the 2nd line of test instructions need to be executed before the 5th line of test instructions.

[0126] In some embodiments, the priority order is preset, or the priority order is generated according to the test records of the electronic components.

[0127] Step S403: Determine whether the updated reading order is mutually exclusive with the priority order.

[0128] If the updated reading order and the priority order are mutually exclusive, then execute steps S404 to S405;

[0129] If the updated reading order and the priority order are not mutually exclusive, step S406 is executed.

[0130] Step S404: If yes, identify the candidate test instructions that are mutually exclusive with the updated reading order and the priority order.

[0131] If the updated reading order and the priority order are mutually exclusive, it means that if the electronic component generates and executes the test instruction operation logic according to the updated reading order, problems will occur in the electronic component during the test process, which may further cause failure of the electronic component.

[0132] Candidate test instructions refer to test instructions whose updated reading order and priority order are mutually exclusive. For example, if the priority order requires that the second line of test instructions must be executed before the third line of test instructions are executed, then the updated reading order is the first line of test instructions, the third line of test instructions, and the fourth line of test instructions. At this time, the priority order and the updated reading order are mutually exclusive, and the candidate test instructions that cause the two to be mutually exclusive are the second line of test instructions and the third line of test instructions.

[0133] Step S405: Combine candidate test instructions and priority order to generate prompt information.

[0134] An information template is selected according to the type of candidate test instructions, and spaces are reserved in the information template for filling in candidate test instructions and priority sequences. The candidate test instructions and priority sequences are filled in the aforementioned spaces to obtain prompt information.

[0135] In some other embodiments, repair suggestions are generated based on the candidate test instructions and the priority order.

[0136] Step S406: If not, continue to execute subsequent steps.

[0137] If the updated reading order and the priority order are not mutually exclusive, the test instruction operation logic for generating the electronic component can continue to be executed according to the current test instruction and the test instruction position.

[0138] In summary, it is determined whether the updated microinstructions will affect the normal execution of the test instructions to ensure that the updated microinstructions can correctly instruct the test instructions to work normally.

[0139] In the following embodiments, since the test instructions and microinstructions are stored separately, different microinstructions can be matched for the same test instruction, so that the test instruction operation logic executed by the electronic component is different, thereby achieving different test purposes. The embodiment of the present application discloses a flow chart of multiple test methods for electronic components. Figure 5 , the method comprising:

[0140] Step S501 : when the first microinstruction is a microinstruction of the target type, determine whether the reading order before updating and the reading order after updating are mutually exclusive with the priority order.

[0141] If the reading order before updating and the reading order after updating are not mutually exclusive with the priority order, step S502 to step S505 are executed.

[0142] If either the read order before update or the read order after update is mutually exclusive with the priority order, refer to Figure 4 Steps S404 to S405 in the illustrated embodiment.

[0143] The target type is the preset microinstruction type.

[0144] The reading order before updating refers to the reading order of the test instructions before the first updating operation, and the reading order after updating refers to the reading order of the test instructions after the second updating operation.

[0145] Step S502: If not, the first test instruction execution logic is generated using the read sequence before the update, and the second test instruction execution logic is generated using the read sequence after the update.

[0146] When the reading order before the update and the reading order after the update are not mutually exclusive with the priority order, it means that the test instruction operation logic obtained by the reading order before the update and the reading order after the update can operate normally. Therefore, the first test instruction operation logic is generated using the reading order before the update, and the second test instruction operation logic is generated using the reading order after the update.

[0147] Step S503: Determine the overlapped portion of the first test instruction execution logic and the second test instruction execution logic.

[0148] The overlapping portion refers to the portion in which the electronic components execute the same test instruction in the first test instruction running logic and the second test instruction running logic.

[0149] Step S504: Use the overlapped portion to test the electronic components.

[0150] Furthermore, if the overlapping portion is located at the start of the first test instruction running logic and the second test instruction running logic, the electronic component is made to run the overlapping portion first.

[0151] If the overlapping portion is not located at the beginning of the first test instruction execution logic and the second test instruction execution logic, the process directly jumps to step S505.

[0152] Step S505: When the test reaches the end of the overlapping portion, the first test instruction running logic or the second test instruction running logic is selected for execution according to the test scenario of the electronic component.

[0153] The test scenario is related to at least one of the type of the electronic component, the function of the electronic component, the test purpose, and the state of the electronic component.

[0154] In some other implementation scenarios, the test instruction operation logic used in this test can also be determined at the beginning of the test according to the test scenario of the electronic components. Exemplarily, the type of electronic components is read, and different types correspond to different test instruction operation logics, and the test instruction operation logic to be used in the test of the electronic components is determined according to the aforementioned types.

[0155] In summary, by setting the target type of microinstructions, two different test instruction running logics are assigned to the test instructions. In the actual test process, different test instruction running logics will be used for testing according to different situations. Moreover, for different test instruction running logics, there is no need to store multiple sets of different test instructions, only one set of test instructions is needed, which can reduce the storage space of the test instructions and ensure the test efficiency of the electronic component test process.

[0156] In the following embodiments, in addition to being able to modify microinstructions individually, the technical solution provided by the present application can also be used to modify test instructions individually. Therefore, the present application embodiment discloses a flow chart of a method for updating test instructions. Figure 6 , the method comprising:

[0157] Step S601: In response to a second update operation, determining a second test instruction in a first storage space, the second update operation including at least one of an add operation, a delete operation and a modify operation.

[0158] The second microinstruction refers to a test instruction in the first storage space that is subjected to a second update operation.

[0159] Exemplarily, the second update operation is that the host computer sends a second test instruction to the electronic component. The electronic component searches for a position corresponding to the second test instruction in the first storage space according to the updated test instruction. For example, the host computer sends a second test instruction to the electronic component, and the second test instruction also carries the position of the second test instruction. The electronic component can search for a position corresponding to the second test instruction in the first storage through the aforementioned position, and use the second test instruction to replace the original test instruction.

[0160] In some other embodiments, a second microinstruction is determined in a second storage space, and a first update operation is performed on the second microinstruction.

[0161] Step S602: when the second test instruction is the current test instruction, use the second test instruction to update the test instruction execution logic.

[0162] In the case where the second test instruction is not the current test instruction, the update behavior of the second test instruction will not affect the test of the electronic component this time, so there is no need to use the second test instruction to update the test instruction running logic.

[0163] Step S603: Detect whether the test instruction execution logic passes the feasibility judgment.

[0164] If the detection test instruction operation logic passes the feasibility judgment, step S604 is executed;

[0165] If the detection test instruction running logic does not pass the feasibility judgment, step S605 to step S606 are executed.

[0166] Feasibility judgment is used to determine whether the test instruction operation logic can run normally on electronic components.

[0167] Optionally, the feasibility judgment includes at least one of grammatical correctness detection, instruction dependency identification, input data validity detection, and execution result prediction.

[0168] Optionally, obtain an error log, which is used to record error information of electronic components during the test process. Identify whether there is a potential error logic consistent with the error log in the test instruction operation logic. If so, it means that the test instruction operation logic has not passed the feasibility judgment. If not, it means that the test instruction operation logic has passed the feasibility judgment.

[0169] Step S604: If yes, execute the test instruction according to the test instruction running logic.

[0170] If it is detected that the test instruction running logic passes the feasibility judgment, it means that after the test instruction is updated, the corresponding test instruction running logic can still be executed and used normally by the electronic components, so the test instruction is executed according to the test instruction running logic.

[0171] Step S605: If not, identify the error reporting instruction in the test instruction execution logic.

[0172] If it is detected that the test instruction running logic fails the feasibility judgment, it means that after the test instruction is updated, the corresponding test instruction running logic cannot be normally executed by the electronic component. Therefore, this step requires identifying the error instruction in the test instruction running logic.

[0173] Exemplarily, the error reporting instruction is obtained according to the judgment result of the feasibility judgment. For example, when the feasibility judgment includes grammatical correctness detection, the test instruction with grammatical errors is determined as the error reporting instruction. For another example, when the feasibility judgment includes instruction dependency identification, the test instruction that does not meet the instruction dependency is determined as the error reporting instruction.

[0174] Exemplarily, error information consistent with the error log in the test instruction running logic is determined, and the test instruction corresponding to the error information is determined as the error instruction.

[0175] Step S606: Generate an error signal using the error reporting instruction, where the error reporting signal is used to indicate the position of the error reporting instruction in the reading sequence.

[0176] Exemplarily, a space for filling in an error reporting instruction is reserved in the signal template. The error reporting instruction is filled in the aforementioned space to obtain an error reporting signal.

[0177] In summary, the test instructions can be updated individually without affecting the microinstructions. In the event of an error in the individual update of the test instructions, an error signal will be generated to alert relevant personnel to ensure that the test of the electronic components is performed normally.

[0178] In the following embodiments, after the error signal is generated, the cause of the error can be identified, and the second microinstruction corresponding to the error instruction can be adjusted so that the test instruction running logic can run normally. The present application embodiment discloses a flow chart of a method for repairing a test instruction. Figure 7 , the method comprising:

[0179] Step S701: extracting an error reporting instruction and a second microinstruction corresponding to the error reporting instruction.

[0180] If the error reporting instruction does not have a corresponding second microinstruction, the process of this embodiment ends and the subsequent steps are not executed.

[0181] Step S702: Identify the error cause of the error instruction according to the priority order of the second microinstruction and the test instruction.

[0182] Exemplarily, the error cause includes that the error instruction depends on the correct execution of the second microinstruction, but the second microinstruction is not executed correctly, or the error instruction conflicts with the second microinstruction, or the second microinstruction needs to wait for response information from an external device or system, but the response information fails to arrive in time.

[0183] Step S703: modify the second microinstruction according to the error cause.

[0184] Exemplarily, the second microinstruction is modified to eliminate the conflict between the error reporting instruction and the second microinstruction.

[0185] Exemplarily, the second microinstruction is updated so that the second microinstruction can be executed normally. If the updated second microinstruction still cannot be executed normally, a prompt message is generated and sent.

[0186] Exemplarily, the second microinstruction is executed separately, and response information corresponding to the second microinstruction is obtained, and the response information is stored in a register.

[0187] In summary, after the test instruction is updated, the error reporting instruction can be adaptively modified so that the modified error reporting instruction can be normally executed by the electronic component, thereby ensuring normal testing of the electronic component.

[0188] Based on the same inventive concept, the present application embodiment provides an electronic component testing system, please refer to Figure 8 ,include:

[0189] An acquisition module 801 is used to acquire a test operation, a test instruction, a microinstruction, a first update operation, an original test instruction position, a priority order, and a second update operation;

[0190] A memory 802, used to store a program of any of the above electronic component testing methods;

[0191] Processor 803, the program in the memory can be loaded and executed by the processor to implement any of the above-mentioned electronic component testing methods.

[0192] By adopting the above technical solution, the test instructions and microinstructions are stored separately, and there is no need to place microinstructions after the test instructions. This can effectively reduce the storage space of the instructions, improve the reading speed of the test instructions, and improve the test running speed of electronic components.

[0193] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device and unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0194] An embodiment of the present application provides a computer-readable storage medium storing a computer program that can be loaded by a processor and execute an electronic component testing method.

[0195] Computer storage media include, for example, various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or optical disks.

[0196] Based on the same inventive concept, an embodiment of the present application provides an intelligent terminal, including a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and execute an electronic component testing method.

[0197] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device and unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0198] The above are all preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. Any feature disclosed in this specification (including the abstract and drawings), unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes. That is, unless otherwise stated, each feature is only an example of a series of equivalent or similar features.

Claims

1. A method for testing electronic components, characterized in that: include: In response to detecting a test operation, a test instruction is stored in a first storage space, and a microinstruction is stored in a second storage space, wherein the microinstruction has associated information with the test instruction, the test instruction is control information of the high and low levels of each pin on the electronic component, and the microinstruction is a special state instruction of the electronic component; Read the microinstruction, determine the target test instruction corresponding to the microinstruction and determine the test instruction position corresponding to the target test instruction after the operation, wherein the test instruction position refers to the position of the next test instruction of the target test instruction after the operation of the microinstruction; Reading a current test instruction used in this test from the first storage space according to the test instruction position; Generate test instruction operation logic for electronic components according to the current test instruction and the test instruction position; The test instruction is executed according to the test instruction running logic to complete the test of the electronic component.

2. The electronic component testing method according to claim 1, characterized in that: The step of reading the current test instruction used in the current test from the first storage space according to the test instruction position includes: Determining an arrangement position of the target test instruction in an initial arrangement sequence of the test instructions; According to the test instruction position and the arrangement position, the initial arrangement order is adjusted to obtain a reading order of the test instructions; The current test instructions are read sequentially from the first storage space according to the reading order.

3. The electronic component testing method according to claim 2, characterized in that: The method further comprises: In response to a first update operation, determining a first microinstruction in the second storage space, the first update operation comprising at least one of an add operation, a delete operation, and a modify operation; Reading the first microinstruction, obtaining a first test instruction corresponding to the first microinstruction and determining a first test instruction position corresponding to the first microinstruction after the operation; Comparing whether an original test instruction position and the first test instruction position are consistent, the original test instruction position being a test instruction position corresponding to the first microinstruction after the operation before receiving the update operation; If yes, keep the reading order unchanged; If not, the reading order is updated according to the first test instruction position.

4. The electronic component testing method according to claim 3, characterized in that: The method further comprises: Reading the first test instruction from the first storage space according to the updated reading order; Extracting the priority order of the test instructions; Determining whether the updated reading order is mutually exclusive with the priority order; If so, identifying candidate test instructions that are mutually exclusive with the updated reading order and the priority order; combining the candidate test instructions and the priority order to generate prompt information; If not, continue with the next steps.

5. The electronic component testing method according to claim 3, characterized in that: The method further comprises: In the case where the first microinstruction is a microinstruction of the target type, determining whether the reading order before the update and the reading order after the update are both mutually exclusive with the priority order; If not, generating a first test instruction execution logic using the read sequence before the update, and generating a second test instruction execution logic using the read sequence after the update; Determine the overlap between the first test instruction execution logic and the second test instruction execution logic; Using the overlapped portion to test the electronic components; When the test reaches the end of the overlapping portion, the first test instruction running logic or the second test instruction running logic is selected for execution according to the test scenario of the electronic component.

6. The electronic component testing method according to claim 2, characterized in that: The method further comprises: In response to a second update operation, determining a second test instruction in the first storage space, wherein the second update operation includes at least one of an add operation, a delete operation, and a modify operation; In the case where the second test instruction is the current test instruction, using the second test instruction to update the test instruction running logic; Detecting whether the test instruction running logic passes the feasibility judgment; If yes, executing the test instruction according to the test instruction running logic; If not, an error reporting instruction in the test instruction execution logic is identified; and an error reporting signal is generated using the error reporting instruction, wherein the error reporting signal is used to indicate the position of the error reporting instruction in the reading sequence.

7. The electronic component testing method according to claim 6, characterized in that: The method further comprises: Extracting the error reporting instruction and a second microinstruction corresponding to the error reporting instruction; According to the priority order of the second microinstruction and the test instruction, identifying the error cause of the error instruction; The second microinstruction is modified according to the error cause.

8. An electronic component testing system, characterized in that: include: An acquisition module, used for acquiring a test operation, a test instruction, a microinstruction, a first update operation, an original test instruction position, a priority order, and a second update operation; A memory for storing a program of the electronic component testing method according to any one of claims 1 to 7; The program in the memory can be loaded and executed by the processor to implement the electronic component testing method according to any one of claims 1 to 7.

9. An intelligent terminal, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program which can be loaded by the processor and executes any one of the methods of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: A computer program is stored which can be loaded by a processor and execute the method according to any one of claims 1 to 7.

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