Host system, memory system, electronic device, operation method, and storage medium

Abstract

The embodiment of the invention provides a host system, a memory system, electronic equipment, an operation method and a storage medium. The host system comprises a host controller, the host controller is coupled with a memory system, the memory system comprises a memory device, the memory device comprises a plurality of memory blocks, the plurality of memory blocks comprise a first memory area and a second memory area, the storage bit number of each storage unit in the second storage area is smaller than that of each storage unit in the first storage area; the memory device includes a plurality of regions; the host controller is configured to send a first instruction, wherein the first instruction indicates that data of a hot area in the plurality of areas is stored in the second storage area; the hot area is determined according to the access information of the computer program and the data access condition of the computer program.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a host system, a memory system, an electronic device and an operating method, and a storage medium. Background Art

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become a mainstream product in the storage market due to its high storage density, controllable production cost, suitable editing and erasing speed and retention characteristics. Summary of the invention

[0003] Based on this, the embodiments of the present disclosure propose a host system, a memory system, an electronic device, an operation method, and a storage medium. Among them, the host system provided by the embodiments of the present disclosure includes: a host controller, the host controller is coupled to the memory system, the memory system includes a memory device, the memory device includes multiple storage blocks, the multiple storage blocks include a first storage area and a second storage area, the number of storage bits of each storage unit in the second storage area is less than the number of storage bits of each storage unit in the first storage area; the memory device includes multiple areas; the host controller is configured to: send a first instruction, the first instruction indicates that the data of the hot area among the multiple areas is stored in the second storage area; the hot area is determined according to the access information of the computer program and the data access situation of the computer program.

[0004] In one embodiment, the host controller is configured to: determine the hot area from the multiple areas; wherein, according to different access information of the computer program, the corresponding data access threshold for determining the hot area is different.

[0005] In one embodiment, the host controller is configured to: when the access information of the computer program corresponding to the corresponding area is commonly used information, and the number of data accesses corresponding to the corresponding area within a preset time period is greater than a first threshold, determine the corresponding area as a hot area; when the access information of the computer program corresponding to the corresponding area is not commonly used information, and the number of data accesses corresponding to the corresponding area within a preset time period is greater than a second threshold, determine the corresponding area as a hot area; the first threshold is less than the second threshold.

[0006] In one embodiment, the host controller is configured to: send a second instruction before sending the first instruction, wherein the second instruction instructs to write data into the memory device.

[0007] The present disclosure also provides a memory system coupled to a host system, comprising: a memory device comprising a plurality of storage blocks, the plurality of storage blocks comprising a first storage area and a second storage area, the number of storage bits of each storage unit in the second storage area being smaller than the number of storage bits of each storage unit in the first storage area; the memory device comprising a plurality of regions; a memory controller coupled to the memory device and configured to: receive a first instruction; send a command set to the memory device in response to the first instruction; the command set instructs to store data of a hot region among the plurality of regions in the second storage area; the hot region is determined based on access information of a computer program and data access conditions of the computer program.

[0008] In one embodiment, the command set includes a third instruction and a fourth instruction; the third instruction instructs reading data of a hot area among the multiple areas; and the fourth instruction instructs storing the read data of the hot area in the second storage area.

[0009] In one embodiment, the memory controller is configured to: receive a second instruction before receiving the first instruction; send a fifth instruction to the memory device in response to the second instruction; the fifth instruction instructs to write data to the second storage area; wherein, when the remaining capacity of the second storage area is less than a preset capacity, the data is moved from the second storage area to the first storage area.

[0010] In one embodiment, the memory controller is also configured to: in response to the first instruction, determine whether the data of the hot area is in the first storage area or the second storage area; if the data of the hot area is in the first storage area, send a command set to the memory device; the command set instructs to move the data of the hot area from the first storage area to the second storage area; if the data of the hot area is in the second storage area, send a sixth instruction to the memory device; the sixth instruction instructs to retain the data of the hot area in the second storage area.

[0011] In one embodiment, if the data in the hot area is in the first storage area, the memory controller is further configured to: determine the storage capacity of the hot area and the remaining capacity of the second storage area; when the storage capacity of the hot area is less than the remaining capacity of the second storage area, and the remaining capacity of the second storage area is greater than a preset capacity, move all the data in the hot area from the first storage area to the second storage area; when the storage capacity of the hot area is greater than the remaining capacity of the second storage area, or when the remaining capacity of the second storage area is less than the preset capacity, move part of the data in the hot area from the first storage area to the second storage area, or do not move the data in the hot area.

[0012] In one embodiment, if the data in the hot area is in the first storage area, the memory controller is configured to: send a command set to the memory device in response to the first instruction; the command set indicates that when the memory system is in an idle state, the data in the hot area among the multiple areas is moved from the first storage area to the second storage area.

[0013] In one embodiment, the memory system includes a universal flash memory device, the memory device including a NAND type memory.

[0014] An embodiment of the present disclosure also provides an electronic device, comprising: a host system and a memory system coupled to the host system, wherein: the memory system comprises a memory device and a memory controller coupled to the memory device; the memory device comprises a plurality of storage blocks, the plurality of storage blocks comprises a first storage area and a second storage area, the number of storage bits of each storage unit in the second storage area is less than the number of storage bits of each storage unit in the first storage area; the memory device comprises a plurality of areas; the host system is configured to: send a first instruction; the memory controller is configured to: receive a first instruction; and in response to the first instruction, send a command set to the memory device; the command set indicates that data of a hot area among the plurality of areas is stored in the second storage area; the hot area is determined based on access information of a computer program and data access conditions of the computer program.

[0015] In one embodiment, the host system is configured to: send a second instruction before sending the first instruction; the memory controller is configured to: receive the second instruction, and send a fifth instruction to the memory device in response to the second instruction; the fifth instruction instructs to write data to the second storage area; when the remaining capacity of the second storage area is less than a preset capacity, move the data from the second storage area to the first storage area.

[0016] An embodiment of the present disclosure also provides an operating method of an electronic device, the operating method comprising: a host system of the electronic device sends a first instruction; a memory system of the electronic device receives the first instruction; and in response to the first instruction, storing data of a hot area among multiple areas of a memory device in a second storage area of ​​the memory device; the hot area is determined based on access information of a computer program and data access conditions of the computer program; the memory system comprises the memory device and a memory controller coupled to the memory device; the memory device comprises a plurality of storage blocks, the plurality of storage blocks comprises a first storage area and a second storage area, the number of storage bits of each storage unit in the second storage area is less than the number of storage bits of each storage unit in the first storage area; the memory device comprises a plurality of areas.

[0017] In one embodiment, the method also includes: the host system of the electronic device sends a second instruction before sending the first instruction; the memory system of the electronic device receives the second instruction, and writes data to the second storage area in response to the second instruction; wherein, when the remaining capacity of the second storage area is less than a preset capacity, the data is moved from the second storage area to the first storage area.

[0018] The embodiments of the present disclosure further provide a storage medium having executable instructions stored thereon. When the executable instructions are executed by an electronic device, the steps of the method for operating the electronic device described in the above embodiments of the present disclosure can be implemented.

[0019] In the embodiments of the present disclosure, a host system, a memory system, an electronic device, an operation method, and a storage medium are proposed. The host system includes: a host controller, the host controller is coupled to the memory system, the memory system includes a memory device, the memory device includes a plurality of storage blocks, the plurality of storage blocks include a first storage area and a second storage area, the number of storage bits of each storage unit in the second storage area is less than the number of storage bits of each storage unit in the first storage area; the memory device includes a plurality of areas; the host controller is configured to: send a first instruction, the first instruction indicates that the data of the hot area in the plurality of areas is stored in the second storage area; the hot area is determined according to the access information of the computer program and the data access situation of the computer program. In the embodiments of the present disclosure, the storage unit of the second storage area of ​​the memory device has the characteristics of fast reading and writing speed; the host controller improves the reading speed of the data in the hot area by sending a first instruction to the memory system to instruct the data of the hot area of ​​the memory device to be stored in the second storage area; further, by moving the data of the hot area in the memory device, the access performance of the memory device can be improved when the data in the hot area is frequently accessed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0021] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0022] Figure 2b A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0023] Figure 3a A schematic diagram of the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0024] Figure 3b A schematic diagram of an exemplary memory including a peripheral circuit according to an embodiment of the present disclosure;

[0025] Figure 4 A cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present disclosure;

[0026] Figure 5 A schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present disclosure;

[0027] Figure 6 A schematic diagram of the structure of an electronic device provided in one embodiment of the present disclosure;

[0028] Figure 7 A schematic diagram of a command interaction situation in an electronic device provided by an embodiment of the present disclosure;

[0029] Figure 8 A schematic diagram of the composition structure of another electronic device is provided for one embodiment of the present disclosure;

[0030] Fig. 9 A schematic diagram of a step flow of an operating method of an electronic device provided by an embodiment of the present disclosure;

[0031] Fig.10 A schematic diagram of the composition structure of a storage medium provided in one embodiment of the present disclosure.

[0032] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0033] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0034] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0035] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0036] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0037] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0040] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, a three-dimensional NAND memory is taken as an example for description.

[0041] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1 As shown in , the system 100 may include a host system 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host system 108 may be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host system 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0042] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host system 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host system 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0043] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host system 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0044] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2a In one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host system 108 in FIG. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0045] Figure 3a A schematic diagram of the structure of a storage cell array of a three-dimensional NAND memory is given as an example. Figure 3a As shown, the memory cell array of the three-dimensional NAND memory is composed of several parallel and staggered rows of memory cell rows parallel to the gate isolation structure, every two rows of memory cell rows are separated by the gate isolation structure and the upper selection gate isolation structure, and each memory cell row includes a plurality of memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure, the first gate isolation structure divides the memory cell array into a plurality of memory blocks (Blocks), the plurality of second gate isolation structures may divide the memory blocks into a plurality of finger storage areas (Fingers), and the upper selection gate isolation structure disposed in the middle of each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. Figure 3a A storage block shown in FIG. 1 includes 6 storage slices. In actual applications, the number of storage slices in a storage block is not limited thereto.

[0046] In some embodiments, each memory block may be coupled to a plurality of word lines, and a plurality of memory cells coupled to each individually controlled word line constitute a page. For example, Figure 3a All memory cells in each memory slice are coupled to form a page.

[0047] It should be noted that Figure 3a The number of memory cell rows between the gate isolation structure and the upper selection gate isolation structure given in the disclosure is only an exemplary demonstration and is not used to limit the number of memory cell rows contained in a finger storage area of ​​the three-dimensional NAND memory in the present disclosure. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0048] Figure 3b 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be Figure 1300 is an example of a memory device 104 in FIG. The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is taken as an example of a three-dimensional NAND-type memory cell array, wherein the memory cell 306 is a NAND-type memory cell, and the memory cell 306 is provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons captured in the region of the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0049] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible storage states and can therefore store one bit of data. For example, the first storage state "0" may correspond to a first voltage range, and the second storage state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-bit memory cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a two-bit memory cell, Double-Level Cell), three bits per cell (also referred to as a three-bit memory cell (TLC, Trinary-Level Cell)), four bits per cell (also referred to as a four-bit memory cell (QLC, Quad-Level Cell)), five bits per cell (also referred to as a five-bit memory cell (PLC, Penta-level cell)), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLCs can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0050] like Figure 3bAs shown in , each memory string 308 may include a lower selection transistor 310 (also known as a source selection transistor BSG, which includes a source selection gate) at its source terminal and an upper selection transistor 312 (also known as a drain selection transistor TSG, which includes a drain selection gate) at its drain terminal. The source selection transistor BSG310 and the drain selection transistor TSG312 can be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each storage string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having TSG312) or a deselection voltage (e.g., 0 V) ​​to a corresponding TSG312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having BSG310) or a deselection voltage (e.g., 0 V) ​​to a corresponding BSG310 via one or more BSG lines 315.

[0051] like Figure 3b As shown in , the memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and the unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by the read and program operations. In some embodiments, in combination with the previous Figure 3a, multiple memory cells are isolated by an upper selection gate isolation structure and a gate isolation structure, and multiple memory cells between the upper selection gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, and each memory cell row is parallel to the gate isolation structure and the upper selection gate isolation structure. Among them, the memory cells in the memory slice sharing the same word line form a physical page 320, and each physical page 320 can be mapped to at least one logical page according to the storage mode of the corresponding memory cell 306 (for example, SLC or MLC as mentioned above), and the logical page can constitute the basic data unit of the programming operation and the reading operation.

[0052] refer to Figure 3a , Figure 3b Each memory cell 306 of the plurality of memory cells is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding selection transistor (eg, drain selection transistor (TSG) 312).

[0053] Figure 4 FIG. 3 is a cross-sectional schematic diagram of an exemplary memory cell array 301 including a memory string 308 using NAND as an example according to some aspects of the present disclosure. Figure 4 As shown, the NAND memory cell array 301 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a channel structure that vertically penetrates the gate layers 411 and the insulating layers 412, wherein the channel structure is coupled with each gate layer to form a memory cell, and the channel structure is coupled with a plurality of gate layers in the stacked structure 410 to form a memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412.

[0054] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0055] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0056] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0057] Return to reference Figure 3b , the peripheral circuit 302 may be coupled to the memory cell array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0058] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store the program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306, and amplify the small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512, and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0059] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512 and select / deselect the memory block 304 of the memory cell array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the (one or more) selected word lines 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.

[0060] The control logic 512 may be coupled to each of the other parts in the peripheral circuits described above, and is configured to control the operation of each of the other parts in the peripheral circuits. The register 514 may be coupled to the control logic 512, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512, and act as a control buffer to buffer control commands received from a host system (not shown) and relay them to the control logic 512, and to buffer status information received from the control logic 512 and relay them to the host system. The interface 516 may also be coupled to the column decoder / bit line driver 506 via the data bus 518, and act as a data I / O interface and a data buffer to buffer data and relay them to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0061] As mentioned above, in NAND type memory, a single-bit storage cell (SLC) has fast read and write speed, high reliability, and long service life, but small storage capacity, and a multi-bit storage cell (MLC, TLC, QLC, PLC) has large storage capacity and low cost, but slow read and write speed; in other words, when a single-bit storage cell (SLC) and a multi-bit storage cell (MLC, TLC, QLC, PLC) perform read operations respectively, there is a large gap in read performance between the two, that is, there is a large gap in read access performance of the memory system to the two; among them, when the memory system reads data in a single-bit storage cell, the reading speed is fast, the reading time is short, and the data access performance is high; comparatively, when the memory system reads data in a multi-bit storage cell, the reading speed is slow, the reading time is long, the data access performance is low, and the user experience is poor.

[0062] Based on one or more of the above problems, the embodiments of the present disclosure provide a host system, a memory system, an electronic device and an operation method thereof, and a storage medium. The host system includes: a host controller, the host controller is coupled to the memory system, the memory system includes a memory device, the memory device includes a plurality of storage blocks, the plurality of storage blocks include a first storage area and a second storage area, the number of storage bits of each storage unit in the second storage area is less than the number of storage bits of each storage unit in the first storage area; the memory device includes a plurality of areas; the host controller is configured to: send a first instruction, the first instruction indicates that the data of the hot area among the plurality of areas is stored in the second storage area; the hot area is determined according to the access information of the computer program and the data access situation of the computer program.

[0063] refer to Figure 6 , Figure 6 A schematic diagram of the structure of an electronic device is shown. Figure 6 As shown, the electronic device 600 includes a host system 601 and a memory system 602; the memory system 602 is connected to the host system 601, and the host system 601 can be an electronic device such as a personal computer or a mobile terminal. The host system 601 can include a host controller 605. In other embodiments, the host system can also include a host storage area ( Figure 6 ); the memory system 602 includes: a memory controller 603 and a memory device 604, the memory controller 603 is used to control the memory device 604 to perform operations such as reading, writing, and erasing, and the memory controller 603 and the memory device 604 can be coupled in any suitable manner. The memory controller 603 may include a control unit 606 for overall control of the memory system 602, and the control unit 606 is, for example, a central processing unit (CPU), a microprocessor (MPU), etc.

[0064] The memory device 604 may include a plurality of memory blocks 607, and the plurality of memory blocks 607 may include a first memory area 608 and a second memory area 609; here, the first memory area and the second memory area may be located in the same memory block, or may be located in two different memory blocks respectively; Figure 6 608 and the second storage area 609 are located in the same storage block 607. The first storage area and the second storage area may each include a plurality of storage cells, each of which is used to store data; wherein the number of storage bits of each storage cell in the second storage area is less than the number of storage bits of each storage cell in the first storage area, that is, the storage capacity of each storage cell in the second storage area is less than the storage capacity of each storage cell in the first storage area, in other words, the read and write speed of each storage cell in the second storage area is greater than the read and write speed of each storage cell in the first storage area. Exemplarily, the storage cells in the first storage area are all multi-bit storage cells (MLC, TLC, QLC, PLC), and the storage cells in the second storage area are all single-bit storage cells (SLC).

[0065] In the disclosed embodiment, according to the user's data access situation, the memory device can also be divided into multiple areas, and the multiple areas can include hot areas and non-hot areas; each area in the multiple areas includes multiple storage units. It should be noted that the size of each area in the multiple areas can be selected and set according to actual conditions; for example, a region can include one or more storage blocks, or a storage block includes multiple areas. Here, the size of each area is not limited; but it should be understood that a part of the multiple areas corresponds to the first storage area, and another part corresponds to the second storage area.

[0066] In order to facilitate understanding of the correspondence between the multiple regions and the first storage area and the second storage area, Figure 66 shows that one of the multiple regions (such as the hot region 610) is located in the first storage area 608. It should be understood that the hot region 610 can be located in the first storage area or in the second storage area, and the non-hot region ( Figure 6 (not shown) can be located in the first storage area or in the second storage area; in other embodiments, the hot area can also be partially located in the first storage area and the other part in the second storage area; in other words, the correspondence between the hot area, the non-hot area and the first storage area and the second storage area can be selected and set according to actual conditions, and is not limited here. The following is a detailed description of the hot area being located in the first storage area as an example, which will not be repeated here.

[0067] In some embodiments, multiple areas of the memory device can be divided into hot areas and non-hot areas according to the access information of the computer program and the data access situation of the computer program. In other words, before storing the data in the hot area in the second storage area, the host controller 605 is further configured to: determine the hot area from the multiple areas.

[0068] As mentioned above, the hot area is determined based on the access information of the computer program and the data access situation of the computer program. Here, the access information of the computer program can be divided into commonly used information and uncommon information. For example, the area corresponding to the commonly used information is a hot area, and the area corresponding to the uncommon information is a non-hot area. The data access situation of the computer program can be divided according to whether the number of data accesses in the corresponding area within a preset time reaches a threshold. For example, if the number of data accesses corresponding to the corresponding area within the preset time has reached a certain threshold, the corresponding area is divided into a hot area; if the number of data accesses corresponding to the corresponding area within the preset time does not reach a certain threshold, the corresponding area is divided into a non-hot area. In some embodiments, the hot area can be determined only for the access information of the computer program, or only for the data access situation of the computer program, or according to the combination of the two situations. It should be noted that when the hot area is determined by the combination of the two situations, when the user reads the data in the hot area, the data in the hot area can be obtained more flexibly and accurately, which improves the user's operating experience.

[0069] The following describes in detail how to determine a hot area based on access information of a computer program and data access status of the computer program in conjunction with an embodiment.

[0070] In the embodiment of the present disclosure, according to different access information of computer programs, the corresponding data access thresholds for determining the hot areas are different. Specifically, when the access information of the computer program corresponding to the corresponding area is common information, and the number of data accesses corresponding to the corresponding area within a preset time period is greater than a first threshold, the corresponding area is determined as a hot area; when the access information of the computer program corresponding to the corresponding area is not common information, and the number of data accesses corresponding to the corresponding area within a preset time period is greater than a second threshold, the corresponding area is determined as a hot area; the first threshold is less than the second threshold.

[0071] In other words, when the access information of the computer program corresponding to the corresponding area is commonly used information, and the number of data accesses corresponding to the corresponding area within a preset time period is less than a first threshold, the corresponding area is a non-hot area; when the access information of the computer program corresponding to the corresponding area is not frequently used information, and the number of data accesses corresponding to the corresponding area within a preset time period is less than a second threshold, the corresponding area is a non-hot area.

[0072] Exemplarily, when the access information of a computer program is commonly used information, such as WeChat, the number of data accesses to the corresponding area corresponding to the computer program within a unit time (e.g., minute min) is 1000 times, that is, the first threshold is 1000 times / min; that is, when the access information of the computer program is commonly used information, among the multiple areas corresponding to the data of the computer program, when the number of data accesses to the corresponding area within a unit time is greater than 1000 times / min, the corresponding area is a hot area; when the number of data accesses to the corresponding area within a unit time is less than 1000 times / min, the corresponding area is a non-hot area.

[0073] Exemplarily, when the access information of a computer program is not frequently used information, the number of data accesses to a corresponding area corresponding to the computer program within a unit time (e.g., minute min) is 2000 times, that is, the second threshold is 2000 times / min; wherein, when the access information of a computer program is not frequently used information, among the multiple areas corresponding to the data of the computer program, when the number of data accesses to a corresponding area within a unit time is greater than 2000 times / min, the corresponding area is a hot area; when the number of data accesses to a corresponding area within a unit time is less than 2000 times / min, the corresponding area is a non-hot area.

[0074] It should be noted that a computer program can be a native program or software module in an operating system; it can be a native application (APP, Application), that is, a program that needs to be installed in the operating system to run, such as WeChat APP; it can also be a small program that can be embedded in any APP, that is, a program that can be run only by downloading it to a browser environment. In short, the above-mentioned computer program can be any form of application, module or plug-in.

[0075] It should be explained that the data of a computer program may include data interacted through the computer program. It should be understood that the computer program itself is usually stored in a memory device in the form of data; therefore, in other embodiments, the data of a computer program may also include the data of the computer program itself. In the embodiments of the present disclosure, the data to be moved is the data interacted through the computer program; the data of the computer program itself is not moved for the time being.

[0076] After determining the hot area, the host controller is configured to: send a first instruction to the memory controller, where the first instruction instructs to store data of the hot area among the multiple areas in the second storage area.

[0077] It should be noted that the prerequisite for storing the data of the hot area in the second storage area is that the data of the hot area is stored in the first storage area. In other words, before moving the data of the hot area, it is also necessary to determine whether the data of the hot area is stored in the first storage area. In the embodiment of the present disclosure, the host controller and the memory system (memory controller) can both make a judgment on whether the data of the hot area is stored in the first storage area. Exemplarily, the host controller makes a judgment; wherein, after determining the hot area, the host controller is also configured to: determine whether the data of the hot area is stored in the first storage area; after determining that the data of the hot area is stored in the first storage area, send a first instruction to the memory controller. Exemplarily, the memory controller makes a judgment; wherein, after determining the hot area, the host controller directly sends a first instruction to the memory controller; the memory controller responds to the first instruction, and determines whether the data of the hot area is stored in the first storage area, and executes the first instruction after determining that the data of the hot area is stored in the first storage area. In the following embodiments, the memory system makes a judgment to determine whether the data of the hot area is stored in the first storage area as an example for explanation, but it should be understood that the following content about the subject of making a judgment is only used to illustrate the present disclosure, and is not used to limit the scope of the present disclosure.

[0078] Based on this, after determining the hot area, the host controller directly sends a first instruction to the memory controller. Here, the first instruction is not only used to instruct the data in the hot area to be moved, but also used to characterize which area among multiple areas is the hot area. It should be understood that the data in the hot area is the user's frequently used data. If the data in the hot area is stored in the first storage area, the user's frequently used data is moved to the second storage area, which can increase the reading speed of the data in the hot area, thereby reducing the data reading time in the hot area, improving the reading performance of the data in the hot area, and thus improving the user's reading experience.

[0079] In some embodiments, the host controller is configured to: before sending the first instruction, send a second instruction instructing to write data into the memory device.

[0080] In other words, before executing the above-mentioned move operation, it is necessary to ensure that data has been written into the first storage area before the data in the first storage area can be moved; based on this, the host controller is also configured to send a second instruction to the memory system, instructing the memory system to write data into the first storage area in the memory device.

[0081] Based on the above-mentioned host system, a memory system is also provided in an embodiment of the present disclosure, wherein the memory system is coupled to the host system, and the memory system includes a memory device, and a memory controller coupled to the memory device, wherein the memory controller is configured to: receive a first instruction; in response to the first instruction, send a command set to the memory device; the command set instructs to store data of a hot area among the multiple areas in the second storage area; the hot area is determined based on access information of a computer program and data access status of the computer program.

[0082] Exemplary, reference Figure 6 After the host controller 605 sends the first instruction to the memory system 602, the memory controller 603 in the memory system 602 is used to receive the first instruction. In response to the first instruction, the memory controller 603 sends a command set to the memory device 604, and the memory device moves data according to the received command set. As mentioned above, after receiving the first instruction, the memory controller in the memory system needs to determine the location of the data in the hot area.

[0083] In some embodiments, the memory controller is further configured to: in response to the first instruction, determine whether the data of the hot area is in the first storage area or the second storage area; if the data of the hot area is in the first storage area, send a command set to the memory device; the command set instructs to move the data of the hot area from the first storage area to the second storage area; if the data of the hot area is in the second storage area, send a sixth instruction to the memory device; the sixth instruction instructs to retain the data of the hot area in the second storage area.

[0084] The memory controller receives the first instruction, determines which area of ​​the multiple areas of the memory device is a hot area according to the instruction of the first instruction, and determines whether the data of the hot area is stored in the first storage area according to the attribute information corresponding to the hot area (such as the L2P table). When the data of the hot area is in the first storage area, the memory controller sends a command set to the memory device, instructing the memory device to move the hot area data in the first storage area to the second storage area.

[0085] It should be noted that, in the process of moving the hot area data in the first storage area, the memory device needs multiple instructions to complete, for example, it is necessary to read the data in the hot area, move the data, update the L2P table, etc., so as to achieve a complete data movement operation. Based on this, the command set issued by the memory controller includes a third instruction and a fourth instruction; the third instruction instructs to read the data of the hot area among the multiple areas; the fourth instruction instructs to store the read data of the hot area in the second storage area. In some specific embodiments, the memory controller is also used to send an update instruction to the memory device after the fourth instruction, and the update instruction is used to instruct to update the L2P table corresponding to the hot area data in the memory device. In other specific embodiments, the memory controller is also used to send a marking instruction to the memory device after the fourth instruction, and the marking instruction is used to instruct to mark the data in the hot area of ​​the memory device as invalid.

[0086] In some embodiments, the command set indicates that when the memory system is in an idle state, data in a hot area among the multiple areas is moved from the first storage area to the second storage area.

[0087] In some embodiments, when the data in the hot area is in the first storage area, in order to ensure that the memory device can perform the data movement operation on the hot area, the memory controller needs to determine whether the remaining capacity of the second storage area in the memory device can store all the data in the hot area before issuing the command set.

[0088] In some specific embodiments, if the data of the hot area is in the first storage area, the memory controller is further configured to: determine the storage capacity of the hot area and the remaining capacity of the second storage area; when the storage capacity of the hot area is less than the remaining capacity of the second storage area, and the remaining capacity of the second storage area is greater than a preset capacity, move all the data of the hot area from the first storage area to the second storage area; when the storage capacity of the hot area is greater than the remaining capacity of the second storage area, or when the remaining capacity of the second storage area is less than the preset capacity, move part of the data of the hot area from the first storage area to the second storage area, or do not move the data of the hot area.

[0089] Among them, when the remaining capacity of the second storage area is greater than the storage capacity of the hot area, it indicates that the second storage area can store all the data in the hot area. However, it should be noted that when the remaining capacity of the second storage area is greater than the preset capacity, all the data in the hot area can be moved to the second storage area; when the remaining capacity of the second storage area is less than the preset capacity, part of the data in the hot area can be moved to the second storage area, or the data in the hot area is not moved. Here, the preset capacity is 0-10% of the capacity of the second storage area.

[0090] When the remaining capacity of the second storage area is less than the storage capacity of the hot area, it indicates that the second storage area can only store part of the data in the hot area. In this case, based on the specific difference between the remaining capacity of the second storage area and the storage capacity of the hot area, part of the data in the hot area can be moved to the second storage area, or the data in the hot area need not be moved.

[0091] In addition, when the data in the hot area is in the second storage area, the memory controller sends a sixth instruction to the memory device; the sixth instruction instructs to keep the data in the hot area in the second storage area, that is, not to move the data in the hot area.

[0092] In the disclosed embodiment, the storage unit of the second storage area of ​​the memory device has the characteristics of fast reading and writing speed; the host controller sends a first instruction to the memory system to instruct the data of the hot area of ​​the memory device to be stored in the second storage area, so as to improve the reading speed of the data in the hot area; further, by moving the data in the hot area of ​​the memory device, the access performance of the memory device can be improved when the data in the hot area is frequently accessed.

[0093] It should be understood that before the data in the first storage area is moved, in order to ensure that the data has been written into the first storage area, the memory controller is configured to: receive a second instruction before receiving the first instruction; send a fifth instruction to the memory device in response to the second instruction; the fifth instruction instructs to write the data into the second storage area; wherein, in the process of writing the data into the second storage area, when the remaining capacity of the second storage area is less than the preset capacity, the data is moved from the second storage area to the first storage area. The preset capacity can be set according to actual conditions. Here, the speed of writing data into the second storage area is greater than the speed of writing data into the first storage area. In other words, the memory controller responds to the second instruction, first writes the data into the second storage area, and then moves the data in the second storage area to the first storage area, which can increase the data writing speed.

[0094] In some other embodiments, the memory controller may be further configured to: send a seventh instruction to the memory device in response to the second instruction; the seventh instruction instructs to write data directly into the first storage area.

[0095] Based on the above host system and memory system, the present disclosure also provides an electronic device, referring to Figure 7 , Figure 7 A schematic diagram of a command interaction situation in an electronic device provided by an embodiment of the present disclosure; Figure 7 As shown, the electronic device includes: a host system and a memory system coupled to the host system, wherein: the memory system includes a memory device and a memory controller coupled to the memory device; the memory device includes a plurality of storage blocks, the plurality of storage blocks include a first storage area and a second storage area, the number of storage bits of each storage unit in the second storage area is less than the number of storage bits of each storage unit in the first storage area; the memory device includes a plurality of areas; the host system is configured to: send a first instruction; the memory controller is configured to: receive a first instruction; and in response to the first instruction, send a command set to the memory device; the command set indicates that data of a hot area among the plurality of areas is stored in the second storage area; the hot area is determined based on access information of a computer program and data access conditions of the computer program.

[0096] In some embodiments, the host system is configured to: send a second instruction before sending the first instruction;

[0097] The memory controller is configured to: receive a second instruction, and in response to the second instruction, send a fifth instruction to the memory device; the fifth instruction instructs to write data into the second storage area; when the remaining capacity of the second storage area is less than a preset capacity, move the data from the second storage area to the first storage area.

[0098] In some specific embodiments, reference Figure 8 , Figure 8 A schematic diagram of the composition structure of another electronic device is provided for an embodiment of the present disclosure; wherein, the host controller includes an application layer (Application), a block storage layer (Block layer) and a driver layer; wherein, the application layer can be configured as a program that communicates with a memory system to use the functions of the memory system. The block storage layer is used to adapt the communication protocol between the host system and the memory system; the block storage layer also includes a recommendation module (Recommend module), which is used to analyze the data reading situation recommended by the memory system, the attribute information of the computer program, etc., and determine which area of ​​the multiple areas of the memory device is a hot area according to the analysis results. The application layer can send an input-output request (IOR) to the driver layer for input / output (I / O) operations on the memory device. IOR can refer to a data read request, a data storage (or write) request and / or a data discard request, but is not limited thereto. The host controller can also send a command converted by the driver layer, such as a first instruction. The memory controller also includes firmware, which is used to monitor the data reading status of each area of ​​the multiple areas of the memory device, and feed back the access information of the computer program corresponding to each area and the data access status of the computer program to the recommendation module of the host system. The recommendation module sets the first threshold and the second threshold according to the feedback, and determines which area of ​​the multiple areas of the memory device is a hot area. After determining the hot area, the host system sends a first instruction to the memory system.

[0099] The present disclosure also provides an operating method of an electronic device, referring to Figure 7 and Fig. 9 , Fig. 9 A schematic diagram of a step flow of an operating method of an electronic device provided in an embodiment of the present disclosure, wherein the operating method comprises the following steps:

[0100] Step S901: the host system of the electronic device sends a first instruction.

[0101] Step S902: The memory system of the electronic device receives a first instruction; and in response to the first instruction, stores data of a hot area among multiple areas of the memory device in a second storage area of ​​the memory device; the hot area is determined based on access information of a computer program and data access status of the computer program; the memory system includes a memory device and a memory controller coupled to the memory device; the memory device includes multiple storage blocks, the multiple storage blocks include a first storage area and a second storage area, the number of storage bits of each storage unit in the second storage area is less than the number of storage bits of each storage unit in the first storage area; the memory device includes multiple areas.

[0102] In some embodiments, the method also includes: the host system of the electronic device sends a second instruction before sending the first instruction; the memory system of the electronic device receives the second instruction, and writes data to the second storage area in response to the second instruction; wherein, when the remaining capacity of the second storage area is less than a preset capacity, the data is moved from the second storage area to the first storage area.

[0103] In some embodiments, the memory system includes a universal flash storage device (UFS) or a solid state drive; the memory device includes a NAND type memory.

[0104] The embodiment of the present disclosure also provides a storage medium on which executable instructions are stored.

[0105] In some specific embodiments, the storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface storage, an optical disk, or a compact disc read-only memory (CD-ROM); it can also be various devices including one or any combination of the above-mentioned memory devices.

[0106] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0107] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0108] As an example, the executable instructions may be deployed to be executed on one electronic device, or on multiple electronic devices located at one site, or on multiple electronic devices distributed at multiple sites and interconnected by a communication network.

[0109] In some specific embodiments, reference Fig.10 , Fig.10 A schematic diagram of the composition structure of a storage medium provided in an embodiment of the present disclosure; wherein the storage medium includes a first storage medium corresponding to a host system, a second storage medium corresponding to a memory system, and a third storage medium corresponding to an electronic device; when the executable instruction is executed by the host system, the first storage medium can be used to implement the steps of the operating method of the host system described in the above embodiment of the present disclosure; when the executable instruction is executed by the memory system, the second storage medium can be used to implement the steps of the operating method of the memory system described in the above embodiment of the present disclosure; when the executable instruction is executed by the electronic device, the third storage medium can be used to implement the steps of the operating method of the electronic device described in the above embodiment of the present disclosure.

[0110] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0111] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0112] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A host system, characterized in that: include: A host controller coupled to a memory system, wherein the memory system comprises a memory device, wherein the memory device comprises a plurality of memory blocks, wherein the plurality of memory blocks comprises a first memory area and a second memory area, wherein the number of storage bits of each memory cell in the second memory area is less than the number of storage bits of each memory cell in the first memory area; and the memory device comprises a plurality of regions; The host controller is configured to: A first instruction is sent, wherein the first instruction instructs to store data of a hot area among the multiple areas in the second storage area; the hot area is determined according to access information of a computer program and data access status of the computer program.

2. The host system according to claim 1, characterized in that: The host controller is configured to: determine the hot area from the multiple areas; According to different access information of the computer program, the corresponding data access threshold for determining the hot area is different.

3. The host system according to claim 1, characterized in that: The host controller is configured to: When the access information of the computer program corresponding to the corresponding area is common information, and the number of data accesses corresponding to the corresponding area within a preset time period is greater than a first threshold, the corresponding area is determined as a hot area; When the access information of the computer program corresponding to the corresponding area is not very common information, and the number of data accesses corresponding to the corresponding area within a preset time period is greater than a second threshold, the corresponding area is determined as a hot area; the first threshold is less than the second threshold.

4. The host system according to claim 1, characterized in that: The host controller is configured to: Before sending the first instruction, a second instruction is sent, the second instruction instructing to write data into the memory device.

5. A memory system, characterized in that: coupled to a host system, comprising: a memory device including a plurality of memory blocks, the plurality of memory blocks including a first memory area and a second memory area, the number of storage bits of each memory cell in the second memory area being less than the number of storage bits of each memory cell in the first memory area; the memory device comprising a plurality of regions; A memory controller is coupled to the memory device and is configured to: receiving a first instruction; In response to the first instruction, a command set is sent to the memory device; the command set instructs to store data of a hot area among the multiple areas in the second storage area; the hot area is determined based on access information of a computer program and data access conditions of the computer program.

6. The memory system according to claim 5, characterized in that: The command set includes a third instruction and a fourth instruction; the third instruction instructs to read data of a hot area among the multiple areas; and the fourth instruction instructs to store the read data of the hot area in the second storage area.

7. The memory system according to claim 6, characterized in that: The memory controller is configured to: Before receiving the first instruction, receiving a second instruction; In response to the second instruction, sending a fifth instruction to the memory device; the fifth instruction instructs writing data into the second storage area; When the remaining capacity of the second storage area is less than a preset capacity, the data is moved from the second storage area to the first storage area.

8. The memory system according to claim 7, characterized in that: The memory controller is further configured to: In response to the first instruction, determining whether the data of the hot area is in the first storage area or the second storage area; If the data of the hot area is in the first storage area, sending a command set to the memory device; The command set instructs to move the data of the hot area from the first storage area to the second storage area; if the data of the hot area is in the second storage area, sending a sixth instruction to the memory device; The sixth instruction instructs to keep the data of the hot area in the second storage area.

9. The memory system according to claim 8, characterized in that: If the data of the hot area is in the first storage area, the memory controller is further configured to: Determining the storage capacity of the hot area and the remaining capacity of the second storage area; When the storage capacity of the hot area is less than the remaining capacity of the second storage area, and the remaining capacity of the second storage area is greater than a preset capacity, all data of the hot area is moved from the first storage area to the second storage area; When the storage capacity of the hot area is greater than the remaining capacity of the second storage area, or when the remaining capacity of the second storage area is less than the preset capacity, part of the data in the hot area is moved from the first storage area to the second storage area, or the data in the hot area is not moved.

10. The memory system according to claim 5, characterized in that: If the data of the hot area is in the first storage area, the memory controller is configured to: In response to the first instruction, a command set is sent to the memory device; the command set indicates that when the memory system is in an idle state, data in a hot area among the multiple areas is moved from the first storage area to the second storage area.

11. The memory system according to claim 7, wherein: The memory system includes a universal flash memory device, the memory device including a NAND type memory.

12. An electronic device, characterized in that: include: A host system and a memory system coupled to the host system, wherein: The memory system comprises a memory device and a memory controller coupled to the memory device; the memory device comprises a plurality of memory blocks, the plurality of memory blocks comprises a first memory area and a second memory area, the number of storage bits of each memory cell in the second memory area is less than the number of storage bits of each memory cell in the first memory area; the memory device comprises a plurality of regions; The host system is configured to: send a first instruction; The memory controller is configured to: receive a first instruction; and in response to the first instruction, send a command set to the memory device; the command set instructs to store data of a hot area among the multiple areas in the second storage area; the hot area is determined based on access information of a computer program and data access conditions of the computer program.

13. The electronic device according to claim 12, characterized in that: The host system is configured to: send a second instruction before sending the first instruction; The memory controller is configured to: receive a second instruction, and in response to the second instruction, send a fifth instruction to the memory device; the fifth instruction instructs to write data into the second storage area; When the remaining capacity of the second storage area is less than a preset capacity, the data is moved from the second storage area to the first storage area.

14. A method for operating an electronic device, characterized in that: The operation method comprises: The host system of the electronic device sends a first instruction; The memory system of the electronic device receives a first instruction; and in response to the first instruction, stores data of a hot area among multiple areas of a memory device in a second storage area of ​​the memory device; the hot area is determined according to access information of a computer program and data access conditions of the computer program; The memory system includes the memory device and a memory controller coupled to the memory device; the memory device includes multiple storage blocks, the multiple storage blocks include a first storage area and a second storage area, the number of storage bits of each storage unit in the second storage area is less than the number of storage bits of each storage unit in the first storage area; the memory device includes multiple areas.

15. The operating method according to claim 14, characterized in that: The method further comprises: The host system of the electronic device sends a second instruction before sending the first instruction; The memory system of the electronic device receives a second instruction, and in response to the second instruction, writes data into the second storage area; wherein, when the remaining capacity of the second storage area is less than a preset capacity, the data is moved from the second storage area to the first storage area.

16. A storage medium, characterized in that: The storage medium stores executable instructions, and when the executable instructions are executed by the electronic device, the steps of the electronic device operating method described in any one of claims 14-15 can be implemented.

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