Dynamic selection of cores for processing responses

Abstract

The application is directed to dynamic selection of cores for processing responses. The memory subsystem may receive a read command from a host system to retrieve data. The memory subsystem may include a first core and a second core. The first core may process the read command based on receiving the read command. The first core may identify the second core to process a read response associated with the read command. The first core may issue an internal command to retrieve the data from a memory device of the memory subsystem. The internal command may include an indication of the second core selected to process the read response.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application. The parent application is an invention patent application with application date of March 11, 2021, application number 202110266070.1, and invention name “Dynamic selection of core for processing response”.

[0003] Cross Reference

[0004] This patent application claims priority to U.S. patent application No. 16 / 822,916, filed on March 18, 2020 by Ish et al., entitled “DYNAMIC SELECTION OF CORES FOR PROCESSING RESPONSES,” which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety.

[0005] The technical field relates to dynamic selection of a core for processing a response. Background Art

[0006] A memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, a host system may utilize a memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0007] A method is described. The method may include receiving a read command from a host system to retrieve data from a memory subsystem; processing the read command using a first core of the memory subsystem based at least in part on receiving the read command; identifying, by the first core, a second core of the memory subsystem to process a read response associated with the read command; and issuing, by the first core, an internal command to retrieve the data from a memory device of the memory subsystem, the internal command including an indication of the second core selected to process the read response.

[0008] A system is described. The system may include a plurality of memory components; and a processing device operatively coupled to the plurality of memory components to: receive a read command from a host system to retrieve data from a memory subsystem; process the read command using a first core of the memory subsystem based at least in part on receiving the read command; identify, by the first core, a second core of the memory subsystem to process a read response associated with the read command; and issue, by the first core, an internal command to retrieve the data from a memory device of the memory subsystem, the internal command including an indication of the second core selected to process the read response.

[0009] A non-transitory computer-readable medium storing code for wireless communication is described. The code may include instructions executable by a processor to: receive a read command from a host system to retrieve data from a memory subsystem; process the read command using a first core of the memory subsystem based at least in part on receiving the read command; identify, by the first core, a second core of the memory subsystem to process a read response associated with the read command; and issue, by the first core, an internal command to retrieve the data from a memory device of the memory subsystem, the internal command including an indication of the second core selected to process the read response. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0011] Figure 1 An example of a computing system including a memory subsystem according to some examples of the present disclosure is described.

[0012] Figure 2 is a flow chart of an example method for dynamic selection of a core for processing responses according to some examples of the present disclosure.

[0013] Figure 3 is a block diagram of an example system for dynamic selection of a core for processing a response according to some examples of the present disclosure.

[0014] Figure 4 is a block diagram of an example memory subsystem for dynamic selection of a core for processing a response according to some examples of the present disclosure.

[0015] Figure 5 is a block diagram of an example computer system in which examples of the present disclosure may operate. DETAILED DESCRIPTION

[0016] Aspects of the present disclosure are directed to dynamic selection of a core for processing a response. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0017] Some memory subsystems may include multiple cores that perform various operations and functions of the memory system. Using multiple cores may increase the speed at which operations are performed by allowing a form of parallel processing. Different cores may be assigned to different types of operations. For example, a memory system or memory subsystem may include a first core for processing read operations, a second core for processing write operations, a third core for processing control operations, and a fourth core for processing error detection and / or correction operations. At various times, all cores may not be utilized equally, and processing resources may remain idle at some cores while other cores have a backlog of operations to be executed.

[0018] Aspects of the present disclosure address the above and other deficiencies by dynamically selecting a memory subsystem in which a processing core handles a second portion of an access operation. For example, a first core may process a read operation (e.g., a first portion) received from a host system, and a second core different from the first core may be selected to process a response (e.g., a second portion) outgoing to the host system associated with the read operation. In some memory subsystems, the same core that processes a received read command is also assigned to process the response and transmit the response to the read command. In the techniques described herein, a second core different from the first core may be selected to process the read response. For example, a read core may process an incoming read command and may assign a write core to process the read response, thereby freeing up the processing resources of the read core to handle more read operations received from the host system. In such techniques, portions of the same access operation may be performed by different cores, portions of the access operation may be dynamically assigned to cores, and indicators indicating dynamically assigned cores may be exchanged.

[0019] Such techniques can utilize processing resources that would otherwise remain idle when using traditional techniques to perform operations. Such techniques can also improve the latency of performing some operations and improve the power consumption associated with performing some operations (e.g., reduce power consumption).

[0020] First, in the reference Figure 1 Features of the present disclosure are described in the context of the described computing environment. Figure 2-4Features of the present disclosure are described in the context of the described flowcharts and block diagrams. Figure 5 These and other features of the present disclosure are further illustrated by and described with reference to the described computer system involving dynamic selection of a core for processing a response.

[0021] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more non-volatile memory devices (such as memory device 130), one or more volatile memory devices (such as memory device 140), or a combination thereof.

[0022] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile DIMMs (NVDIMMs).

[0023] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), a device supporting the Internet of Things (IoT), an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device (e.g., a processor).

[0024] Computing system 100 can include a host system 105 coupled with one or more memory subsystems 110. In some examples, host system 105 is coupled with memory subsystems 110 of different types. Figure 1 An example of a host system 105 coupled to a memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0025] The host system 105 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 105 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0026] The host system 105 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a USB interface, a Fibre Channel, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transmit data between the host system 105 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 105 through a PCIe interface, the host system 105 may further utilize a Non-Volatile Memory Express (NVMe) interface to access components (e.g., one or more memory devices 130). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 105 . Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 105 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0027] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM) such as dynamic RAM (DRAM) and synchronous DRAM (SDRAM).

[0028] Some examples of non-volatile memory devices (e.g., memory device 130) include "NAND" type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memories can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0029] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, for example, a single-level cell (SLC) may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of such memory cell arrays. In some embodiments, a particular memory device may include an SLC portion of a memory cell, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0030] Although nonvolatile memory components such as NAND-type flash memory (e.g., 2D NAND, 3D NAND) and 3D cross-point nonvolatile memory cell arrays are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0031] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can include a processor chipset that includes one or more cores. The memory subsystem controller 115 can be a microcontroller, a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or other suitable processor.

[0032] The memory subsystem controller 115 may include a processor 120 (e.g., a processing device) configured to execute instructions stored in a local memory 125. In the illustrated example, the local memory 125 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 105.

[0033] In some examples, local memory 125 may include memory registers that store memory pointers, fetched data, etc. Local memory 125 may also include ROM for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem).

[0034] In general, the memory subsystem controller 115 may receive commands or operations from the host system 105 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), name space) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may additionally include host interface circuitry to communicate with the host system 105 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 105.

[0035] The memory subsystem 110 may also include additional circuits or components not illustrated. In some examples, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and address circuits (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0036] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] The memory subsystem 110 includes a core manager 150 that can handle communications between the memory subsystem 110 and the host system 105. Some memory subsystems 110 may include more than one processing core that performs operations. For example, the memory subsystem 110 may include a first processing core that performs a read operation and a second processing core that performs a write operation. In some embodiments, read operations may be performed more commonly than write operations. In such embodiments, some cores may be used more than other cores. To reduce latency due to the use of the same processing core to perform a large number of operations, the core manager 150 may be configured to dynamically select cores that perform different parts of an operation. For example, the core manager 150 may be configured to select a core to process a response as part of a read operation that is different from the core used to process the reception of a read command from the host system 105.

[0038] In some examples, the memory subsystem controller 115 includes at least a portion of a core manager 150. For example, the memory subsystem controller 115 may include a processor 120 (e.g., a processing device) configured to execute instructions stored in a local memory 125 for performing the operations described herein. In some examples, the core manager 150 is part of the host system 105, an application, or an operating system.

[0039] The core manager 150 may, in response to receiving a read command, dynamically select a core to process a read response that is different from the core to process the read command. By allowing the core manager 150 to dynamically select a core to use for portions of an access operation, the core manager 150 may reduce latency for performing portions of a read operation. In some cases, a read operation may be performed by more than one core. Additional details regarding the operation of the core manager 150 are described below.

[0040] Figure 2 is a flow chart of an example method 200 for dynamic selection of a core for processing a response according to some examples of the present disclosure. The method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some examples, the method 200 is performed by Figure 1 The core manager 150 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, the illustrated examples should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various examples. Therefore, not all processes are required in each example. Other process flows are also possible.

[0041] At operation 205, the memory subsystem may receive an access command from the host system. Such an access command may be a read command, a write command, or an erase command, which may read, erase, write, and / or rewrite data to a specific memory cell in a memory device of the memory subsystem. In some cases, the access command may cause the memory subsystem to retrieve data from the memory device for use by the host system. In some examples, each read command includes an instruction to read one or more of the blocks of data at a corresponding source address of the memory subsystem.

[0042] At operation 210, the memory subsystem may process an access command using a first core of the memory subsystem. The first core may be associated with a front end portion of the firmware such that the first core is used to perform functions associated with a front end manager of the firmware. The front end manager of the firmware may be configured to interface with a host system. In some instances, the first core may be a read core, or an instance of a processing core used to process read operations. The first core of the front end of the memory subsystem may receive a read command to retrieve data from the host system. In some instances, the read command may correspond to accessing the first core of the front end manager within the memory subsystem.

[0043] At operation 215, the first core of the memory subsystem may identify or select a second core of the memory subsystem to process the read response. The second core may be associated with a front-end portion of the firmware so that the first core is used to perform functions associated with the front-end manager of the firmware. In some instances, the second core may be a write core, or an instance of a processing core used to process write operations. In some instances, the second core identified to process the read response may be different from the first core. In other instances, the second core identified to process the read response may be the same as the first core. In other cases, the first core and the second core may be instances of one or more cores working together. Additionally or alternatively, the first core that processes the received read command may query one core or multiple cores. Once one or more cores are queried, the first core may delegate part of the read operation to one or more cores for execution. The core selected to process the second portion of the access command may be dynamically selected.

[0044] At operation 220, the first core of the memory subsystem may issue an internal command to retrieve data. In some examples, the internal command may include an indication of a second core identified as processing a read response. The backend manager may receive the internal command, causing the requested data to be retrieved from the memory device, and may issue a second internal command that the requested data is ready to be sent to the host system. The second internal command may be sent to the second core identified in the internal command, or the second internal command may include an indication of the second core identified as processing a read response. The second core may process the requested data and / or the second internal command to generate a read response. The second core may transmit a read response based on the generation.

[0045] Figure 3 An example of a system 300 for dynamically selecting a core for processing responses according to examples disclosed herein is illustrated. The system 300 may include a host system 305 in communication with a memory subsystem 310. The host system 305 may be a reference Figure 1 The host system 105 is described as an example. The memory subsystem 310 may be referenced Figure 1 An example of memory subsystem 110 is depicted. Components of memory subsystem 310 may receive and transmit communications associated with read operations.

[0046] The read operation may be split into one or more parts and each part may be performed by a different processing core. For example, a first part of the read operation may involve processing a read command by a front-end manager, a second part of the read operation may involve retrieving data from a memory device by a back-end manager and / or memory device component, and a third part may involve processing a read response by the front-end manager and transmitting the read response to the host system 305. Portions of the read operation may be performed by one or more processing cores associated with each manager and / or device. Information processed by one or more processing cores associated with the front-end manager may be directed to one or more processing cores associated with the back-end manager through one or more processing cores associated with the flash translation manager. Reference Figure 4 Describes additional details about the processing core of each manager.

[0047] The system 300 may include a host system 305 in communication with a memory subsystem 310. The memory subsystem 310 may include a first core 315-a, a second core 315-b, and a memory device 320. The first core 315-a and the second core 315-b of the memory subsystem 310 may be examples of processing cores associated with a front-end manager of the memory subsystem 310. The memory subsystem 310 may include firmware, and include a front-end manager (e.g., a front-end layer), a translation manager (e.g., a flash translation layer), and a back-end manager, each of which is associated with a processing core.

[0048] The host system 305 may issue an access command 325 (eg, a read command, a write command, or other type of command) to retrieve data from the memory subsystem 310 . The memory subsystem 310 may receive the access command 325 to retrieve data from the memory device 320 on behalf of the host system 305 .

[0049] Once the memory subsystem 310 receives the access command 325, the first core 315-a may process the access command 325 at operation 330. When processing the access command 325, the first core 315 may identify the type of access command 325 received from the host system 305 or identify one or more parameters of the access command 325.

[0050] At operation 335, the first core 315-a may select a processing core to handle at least a portion of the access operation (e.g., a read operation). For example, the first core 315-a may select a processing core to process and / or transmit a response 360 ​​(e.g., a read response) to the access operation. Figure 4 Described in more detail, the memory subsystem 310 may have any number of cores 315. The first core 315-a may represent a processing core for processing a received access command (e.g., a read command). The second core 315-b may represent a processing core for processing a response to an access command (e.g., a read response).

[0051] By selecting a processing core to handle a portion of an access operation, processing resources may be used or allocated more efficiently. For example, the first core 315-a may be an instance of a read core that is configured to perform the function of a read operation, and the second core 315-b may be an instance of a write core that is configured to perform the function of a write operation. After receiving a read command (e.g., access command 325), the write core (e.g., second core 315-b) may be relatively idle (or underutilized for a duration) compared to the read core (e.g., first core 315-a). To reduce bottlenecks at the read core, portions of the read operation may be offloaded to other cores, such as the write core.

[0052] After selecting the second core 315-b to process the response to the access command 325, the first core 315-a may issue a first internal command 340 to the memory device 320 (through the backend manager) to retrieve the data requested by the access command 325. The first internal command 340 may include information about the selected second core 315-b. For example, the first internal command 340 may include an indicator identifying which processing core has been selected as the second core 315-b to process the response 360. In some embodiments, the first core 315-a may select a different core to process the response 360, in which case the second core 315-b represents a core different from the first core 315-a. In some embodiments, the first core 315-a may select itself to process the response 360, in which case the second core 315-b represents the same core as the first core 315-a.

[0053] In some examples, as part of selecting a processing core to process response 360, first core 315-a may query one or more cores to determine utilization of the one or more cores. The other cores may respond to the query with utilization information related to usage of each core over a duration. First core 315-a may use the utilization information to select which core to serve as second core 315-b and process response 360.

[0054] Upon receiving the first internal command 340, the memory device 320 may retrieve the requested data from one or more memory units included in the memory device 320. For example, at operation 345, the memory device 320 may retrieve the data to be sent as part of the response 360. The memory device 320 may perform an operation in response to receiving the internal command. In some cases, the memory device 320 may identify the second core 315-b selected to process the response 360. The memory device 320 may issue the second internal command 350 to the dynamically selected core (e.g., the second core 315-b) based on completing the internal operation initiated by the first internal command 340. In some cases, the second internal command 350 may include the data retrieved from the memory device 320. In some cases, the second internal command 350 may include an indicator of the dynamically selected core (e.g., the second core 315-b).

[0055] At operation 355, the second core 315-b of the memory subsystem 310 may process the response 360 ​​based on receiving the second internal command 350. The second core 315-b may identify data included in the second internal command 350, which may include control information or data retrieved from the memory unit, and may generate the response 360 ​​for transmission to the host system 305. For example, when the access command 325 is a read command, the second core 315-b may generate a read response using data retrieved from the memory device 320. The second core 315-b may transmit the response 360 ​​to the host system 305. The second internal command 350 may be sent directly to the second core 315-b selected for processing the response 360. The second internal command 350 may be sent to a queue with an indication of the second core 315-b selected for processing the response 360. The processing core may query the queue, and the assigned processing core may be configured to perform the operations included in the queue.

[0056] Figure 4 An example of a memory subsystem 400 for dynamic selection of a core for processing responses according to examples disclosed herein is illustrated. The memory subsystem may include firmware 405. Firmware 405 may include a front-end manager 410 (sometimes referred to as a front-end layer), a translation manager 415 (sometimes referred to as a flash translation layer or FTL), and a back-end manager 420 (sometimes referred to as a back-end layer). As described herein, a core may be an example of a processor (e.g., processor 120), one or more portions of a processor, a processing device (e.g., processing device 505), one or more portions of a processing device, or a combination thereof. A core may be any circuit, processor hardware, or device configured to execute one or more instructions to perform one or more operations.

[0057] The front-end manager 410 may be configured as an interface between a host system and a memory subsystem. For example, the front-end manager 410 may be configured to receive, process and / or interpret commands and other communications received from and transmitted to the host system. One or more cores 425 may be used to perform the functions of the front-end manager 410. For example, a first core 425-a, a second core 425-b, and an Nth core 425-N may be used to implement the functions of the front-end manager 410. In some embodiments, these cores 425 may be dedicated to performing the functions of the front-end manager 410. In some embodiments, one or more of these cores 425 may be used to perform the functions of the front-end manager 410, the translation manager 415, or the back-end manager 420, or a combination thereof. N may represent any positive integer number of cores.

[0058] The backend manager 420 may be configured as an interface between the memory subsystem and the memory device of the memory subsystem. For example, the backend manager 420 may be configured to receive, process and / or interpret data and other communications received from and transmitted to the memory device. One or more cores 435 may be used to perform the functions of the backend manager 420. For example, the first core 435-a, the second core 435-b, and the Nth core 435-n may be used to implement the functions of the backend manager 420. In some embodiments, these cores 435 may be dedicated to performing the functions of the backend manager 420. In some embodiments, one or more of these cores 435 may be used to perform the functions of the frontend manager 410, the translation manager 415, or the backend manager 420, or a combination thereof. N may represent any positive integer number of cores.

[0059] The translation manager 415 may be configured as an interface between the front-end manager 410 and the back-end manager 420. In some embodiments, the command and signaling scheme used by the host system may be different from the command and signaling scheme used by the memory device. In order to facilitate communication between the host system and the memory device storing data on behalf of the host system, the translation manager 415 may translate or otherwise convert host system information into memory device information and vice versa. One or more cores 430 may be used to perform the functions of the translation manager 415. For example, the first core 430-a, the second core 430-b, and the Nth core 430-N may be used to implement the functions of the translation manager 415. In some embodiments, these cores 430 may be dedicated to performing the functions of the translation manager 415. In some embodiments, one or more of these cores 430 may be used to perform the functions of the translation manager 415, the translation manager 415, or the back-end manager 420, or a combination thereof. N may represent any positive integer number of cores.

[0060] refer to Figure 3The first core 315-a and the second core 315-b described may be examples of cores 425 of the front-end manager 410. In such examples, the first core 315-a that processes the access command may be any one of the N-th cores 425-N, and the second core that processes the response may be any one of the N-th cores 425-N. In some cases, the first core 425-a of the front-end manager 410 may perform a first portion of the read operation (e.g., processing the received access command). The second portion of the read operation, retrieving data or otherwise performing the access operation, may be performed by one or more cores 430 of the translation manager 415, one or more cores 435 of the back-end manager 420, a memory device, or a combination thereof. For example, the one or more cores 430 and the one or more cores 435 may be used to execute commands based on an internal command issued by the core 425. The second core 425-b of the front-end manager 410 may perform a third portion of the read operation (e.g., processing the response).

[0061] Figure 5 An example machine of a computer system 500 supporting a sequential folding scoreboard according to examples disclosed herein is illustrated. The computer system 500 may include a set of instructions for causing the machine to perform any one or more of the techniques described herein. In some examples, the computer system 500 may correspond to a computer system that includes, is coupled to, or uses a memory subsystem (e.g., reference Figure 1 The memory subsystem 110 described above may be used to perform operations of the controller (e.g., to execute an operating system to execute a corresponding operation corresponding to the reference Figure 1 The operation of the core manager 150 described herein) is described by a host system (e.g., referring to Figure 1 In some examples, the machine may be connected (e.g., using a network) to other machines in a local area network (LAN), an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0062] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" shall also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0063] The example computer system 500 may include a processing device 505, a main memory 510 (e.g., ROM, flash memory, DRAM such as SDRAM or Rambus DRAM (RDRAM), etc.), a static memory 515 (e.g., flash memory, static RAM (SRAM), etc.), and a data storage system 525, which communicate with each other via a bus 545.

[0064] Processing device 505 represents one or more general processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 505 can also be one or more special-purpose processing devices, such as ASIC, FPGA, DSP, network processor, etc. Processing device 505 is configured to execute instructions 535 for performing the operations and steps discussed herein. Computer system 500 may additionally include a network interface device 520 to communicate on a network 540.

[0065] The data storage system 525 may include a machine-readable storage medium 530 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 535 or software embodying any one or more of the methods or functions described herein. The instructions 535 may also reside, completely or at least partially, within the main memory 510 and / or within the processing device 505 during execution by the computer system 500, the main memory 510 and the processing device 505 also constituting machine-readable storage media. The machine-readable storage medium 530, the data storage system 525, and / or the main memory 510 may correspond to a memory subsystem.

[0066] In one example, instructions 535 include instructions for implementing instructions corresponding to core manager 550 (eg, reference Figure 1 The machine-readable storage medium 530 is a storage medium that stores instructions for the functionality of the core manager 150 described herein. Although the machine-readable storage medium 530 is shown as a single medium, the term "machine-readable storage medium" may include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" may also include any medium that is capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" may include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0067] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to others skilled in the art. In this article, an algorithm is generally conceived as a self-consistent sequence of steps that produce a desired result. An operation is one that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven to be convenient at times, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0068] It should be borne in mind, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0069] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions and each coupled to a computer system bus.

[0070] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with the programs according to the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. The structures of various such systems will be presented as set forth in the description below. In addition, the present disclosure is described without reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0071] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some examples, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as ROM, RAM, magnetic disk storage media, optical storage media, flash memory components, etc.

[0072] In the foregoing description, examples of the present disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications and variations may be made thereto without departing from the broader spirit and scope of the examples of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A device comprising: A front-end manager coupled to the host system, the front-end manager being configured to: receiving one or more commands from the host system for accessing a memory subsystem; and processing the received one or more commands; a backend manager coupled to a memory device of the memory subsystem, the backend manager being configured to: performing access operations associated with the memory device based at least in part on the front end manager processing the one or more commands received; and receiving a communication from the memory device based at least in part on performing the access operation; and A translation manager is coupled to the front-end manager and the back-end manager and is configured to facilitate communication between the front-end manager and the back-end manager.

2. The apparatus of claim 1 , wherein the translation manager is implemented by one or more cores that facilitate communication between the front-end manager and the back-end manager by converting between a first command and signaling scheme of the front-end manager and a second command and signaling scheme of the back-end manager.

3. The apparatus of claim 1, wherein the front-end manager is implemented by a first core, the first core being used to process the one or more commands. 4 . The apparatus of claim 3 , wherein the translation manager is implemented by a third core, the third core to identify the first core based at least in part on querying a plurality of cores of the front-end manager.

5. The apparatus of claim 1, wherein the backend manager is implemented by a second core, the second core being used to perform the access operations and to process communications received from the memory device.

6. The apparatus of claim 5, wherein the translation manager is implemented by a third core, the third core to identify the second core based at least in part on querying a plurality of cores of the backend manager.

7. The apparatus of claim 1, wherein: The one or more commands include at least one read command; The front end manager is implemented by one or more cores for executing a first portion of a read operation associated with the at least one read command; and The backend manager is implemented by one or more cores for performing a second portion of the read operation.

8. The apparatus of claim 1, wherein: The one or more commands include at least one write command; The front end manager is implemented by one or more cores for performing a first portion of a write operation associated with the at least one write command; and The backend manager is implemented by one or more cores for performing a second portion of the write operation.

9. The apparatus of claim 1, wherein: The one or more commands include at least one erase command; The front end manager is implemented by one or more cores for performing a first portion of an erase operation associated with the at least one erase command; and The backend manager is implemented by one or more cores for performing a second portion of the erase operation.

10. A method comprising: receiving one or more commands from a host system for accessing a memory subsystem; Processing the one or more commands received using the front-end manager; executing, using a backend manager, access operations associated with a memory device of the memory subsystem based at least in part on the one or more commands received; receiving, at the backend manager, a communication from the memory device based at least in part on performing the access operation; as well as A translation manager is used to facilitate communication between the front-end manager and the back-end manager.

11. The method of claim 10, wherein facilitating communication comprises: Converting between a first command and signaling scheme of the front-end manager and a second command and signaling scheme of the back-end manager, wherein the first command and signaling scheme is different from the second command and signaling scheme.

12. The method according to claim 10, wherein: Processing the one or more received commands includes processing the one or more received commands using a first core of the front end manager.

13. The method according to claim 12, further comprising: The first core of the front end manager is identified using a third core of the translation manager based at least in part on querying a plurality of cores of the front end manager.

14. The method according to claim 10, further comprising: A second core using the backend manager performs the access operation and receives communications from the memory device.

15. The method according to claim 14, further comprising: The third core of the backend manager is identified using the third core of the translation manager based at least in part on querying a plurality of cores of the backend manager.

16. The method of claim 10, wherein the one or more commands include at least one read command, and the method further comprises: executing, using one or more cores of the front-end manager, a first portion of a read operation associated with the at least one read command; and A second portion of the read operation is performed using one or more cores of the backend manager.

17. The method of claim 10, wherein the one or more commands include at least one write command, and the method further comprises: executing a first portion of a write operation associated with the at least one write command using one or more cores of the front-end manager; and A second portion of the write operation is performed using one or more cores of the backend manager.

18. The method of claim 10, wherein the one or more commands include at least one erase command, and the method further comprises: executing, using one or more cores of the front-end manager, a first portion of an erase operation associated with the at least one erase command; and A second portion of the erase operation is performed using one or more cores of the backend manager.

19. An apparatus comprising: A front-end manager that couples with the host system to: receiving a write command from the host system to store data in the memory subsystem; and Processing the received write command; A backend manager coupled to a memory device of the memory subsystem to: performing access operations associated with the memory device based at least in part on the front-end manager processing the received write command; and transferring data to the memory device based at least in part on performing the access operation; and A translation manager is coupled to the front-end manager and the back-end manager and is configured to facilitate communication between the front-end manager and the back-end manager.

20. The apparatus of claim 19, wherein the translation manager is implemented by one or more cores that facilitate communication between the front-end manager and the back-end manager by converting between a first command and signaling scheme of the front-end manager and a second command and signaling scheme of the back-end manager.

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