SOC upgrading method and system based on multi-core heterogeneity, terminal and medium

Abstract

The invention provides an SOC upgrading method and system based on multi-core heterogeneity, a terminal and a medium, and belongs to the field of chips. The method is applied to the upgrading system based on the multi-core heterogeneous SOC, the upgrading system comprises the multi-core heterogeneous SOC, the multi-core heterogeneous SOC comprises a first processor and a second processor, and the method comprises the steps that the upgrading system obtains a first upgrading package of the first processor and sends the first upgrading package to the second processor; the upgrading system performs upgrading processing on the first processor by using the second processor and the first upgrading package to obtain a first upgrading state of the first processor; when the second processor determines that the first upgrading state is upgrading exception, the second processor determines a first exception repair strategy required when the first processor performs exception repair according to the upgrading exception; and the second processor performs exception handling on the first processor according to the first exception repair strategy to ensure normal operation of the first processor. The problems that in the upgrading process, occupied storage resources are high, and upgrading abnormity cannot be accurately processed are solved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to an upgrade method, system, terminal and medium based on a multi-core heterogeneous SOC. Background Art

[0002] In the application scenario of low-power IPC (IP CAMERA, network camera), low-power IPC is usually composed of an audio and video encoding system and a network keep-alive system. During the OTA (Over the air, air download technology) process, the low-power IPC needs to partition the system to be upgraded for double backup or save it in multiple memories to ensure the safety of the upgrade. This upgrade method requires double the storage space, thus causing a waste of storage space, thereby reducing the upgrade efficiency. In addition, when a freeze or other abnormality occurs during the upgrade process, the system that uses a watchdog or heartbeat to keep alive to reset the freeze cannot fundamentally solve the freeze problem, and may even cause the system to restart repeatedly. Therefore, there is an urgent need for an upgrade method to solve the problem of low upgrade efficiency and inability to accurately handle upgrade anomalies in related technologies. Summary of the invention

[0003] The main purpose of the embodiments of the present invention is to provide an upgrade method, system, terminal and medium based on a multi-core heterogeneous SOC, aiming to solve the problem that the upgrade method adopted in the related art needs to occupy double the storage space, thereby causing a waste of storage space, and also to solve the problem that the exception cannot be accurately handled when a freeze or other exceptions occur during the upgrade process.

[0004] In a first aspect, an embodiment of the present invention provides an upgrade method based on a multi-core heterogeneous SOC, which is applied to an upgrade system based on a multi-core heterogeneous SOC, wherein the upgrade system includes the multi-core heterogeneous SOC, wherein the multi-core heterogeneous SOC includes at least a first processor and a second processor, including:

[0005] The upgrade system obtains a first upgrade package corresponding to the first processor, and sends the first upgrade package to the second processor;

[0006] The upgrade system uses the second processor and the first upgrade package to upgrade the first processor to obtain a first upgrade state corresponding to the first processor;

[0007] When the second processor determines that the first upgrade state is an upgrade exception, the second processor determines, according to the upgrade exception, a first exception repair strategy required for the first processor to perform exception repair;

[0008] The second processor performs exception processing on the first processor according to the first exception repair strategy to ensure normal operation of the first processor.

[0009] In a second aspect, an embodiment of the present invention provides an upgrade system based on a multi-core heterogeneous SOC, wherein the upgrade system includes the multi-core heterogeneous SOC, wherein the multi-core heterogeneous SOC includes at least a first processor and a second processor, and the upgrade system performs the following steps:

[0010] The upgrade system obtains a first upgrade package corresponding to the first processor, and sends the first upgrade package to the second processor;

[0011] The upgrade system uses the second processor and the first upgrade package to upgrade the first processor to obtain a first upgrade state corresponding to the first processor;

[0012] When the second processor determines that the first upgrade state is an upgrade exception, the second processor determines, according to the upgrade exception, a first exception repair strategy required for the first processor to perform exception repair;

[0013] The second processor performs exception processing on the first processor according to the first exception repair strategy to ensure normal operation of the first processor.

[0014] In a third aspect, an embodiment of the present application provides a terminal, comprising at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions executable by the at least one control processor, and the instructions are executed by the at least one control processor so that the at least one control processor can execute the upgrade method based on multi-core heterogeneous SOC as described in the first aspect above.

[0015] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the upgrade method based on multi-core heterogeneous SOC as described in the first aspect above.

[0016] The embodiment of the present invention provides an upgrade method and system based on a multi-core heterogeneous SOC (System on chip), the method is applied to an upgrade system based on a multi-core heterogeneous SOC, the upgrade system includes a multi-core heterogeneous SOC, wherein the multi-core heterogeneous SOC includes at least a first processor and a second processor, the method includes: the upgrade system obtains a first upgrade package corresponding to the first processor, and sends the first upgrade package to the second processor; then the upgrade system uses the second processor and the first upgrade package to perform upgrade processing on the first processor, so as to obtain a first upgrade state corresponding to the first processor; then when the second processor determines that the first upgrade state is an upgrade exception, the second processor determines a first exception repair strategy required for the first processor to perform exception repair according to the upgrade exception; thereby the second processor performs exception processing on the first processor according to the first exception repair strategy to ensure the normal operation of the first processor. In the present application, when upgrading a multi-core heterogeneous SOC, the upgrade processing of the first processor and the second processor is separated, and the second processor is used to upgrade the first processor and the first processor is used to upgrade the second processor, so that there is no need to occupy double the storage space when upgrading the processor, thereby solving the problem of high storage resource occupation during the upgrade process. In addition, the upgraded processor can be monitored during the upgrade process or after the upgrade is completed, so as to obtain the first exception repair strategy required for the first processor to repair the exception and the second exception repair strategy required for the second processor to repair the exception in time according to the upgrade exception, thereby also solving the problem of not being able to accurately handle the exception when a freeze or other exception occurs during the upgrade process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A schematic diagram of a flow chart of an upgrade method based on a multi-core heterogeneous SOC provided in an embodiment of the present invention;

[0019] Figure 2 A schematic diagram of the structure of an upgrade system based on a multi-core heterogeneous SOC provided by an embodiment of the present invention;

[0020] Figure 3 A schematic diagram of a scenario for implementing the upgrade method based on multi-core heterogeneous SOC provided in this embodiment;

[0021] Figure 4 A schematic diagram of the structure of a terminal provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0024] It should be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0025] The embodiment of the present invention provides an upgrade method, system, terminal and medium based on a multi-core heterogeneous SOC. The upgrade method based on a multi-core heterogeneous SOC can be applied to an upgrade system based on a multi-core heterogeneous SOC, wherein the upgrade system includes a multi-core heterogeneous SOC, wherein the multi-core heterogeneous SOC includes at least a first processor and a second processor.

[0026] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0027] Please refer to Figure 1 , Figure 1 A flowchart of an upgrade method for a multi-core heterogeneous SOC provided in an embodiment of the present invention.

[0028] like Figure 1 As shown, the upgrade method based on multi-core heterogeneous SOC includes steps S101 to S104.

[0029] Step S101: The upgrade system obtains a first upgrade package corresponding to the first processor, and sends the first upgrade package to the second processor.

[0030] Exemplarily, the SOC includes at least two heterogeneous processors, each of which runs its own business logic. To ensure that the SOC can be upgraded bidirectionally and safely, that is, when any heterogeneous processor in the SOC is upgraded abnormally or damaged, the mutual rescue mechanism can be activated and the normal operation can be restored. Therefore, when upgrading the processors in the upgrade system based on multi-core heterogeneous SOC, the present application adopts a mutual upgrade method to solve the problem that the upgrade method adopted in the related art needs to occupy double the storage space, thereby causing a waste of storage space and reducing the upgrade efficiency. At the same time, it also solves the problem that the exception cannot be accurately handled when a freeze or other exception occurs during the upgrade process.

[0031] Exemplarily, the upgrade system upgrades the first processor, and then the application uses the second processor in the upgrade system to upgrade the first processor. First, the upgrade system accesses the official website or support page of the manufacturer corresponding to the first processor, searches for the latest upgrade package corresponding to the processor model of the first processor currently in use, and then downloads the first upgrade package required for the first processor upgrade, and ensures that the downloaded first upgrade package is compatible with the processor model of the first processor and the upgrade system architecture. Thus, the upgrade system copies the downloaded first upgrade package file to the storage location corresponding to the second processor.

[0032] In some embodiments, the upgrade system based on multi-core heterogeneous SOC also includes: a micro control unit and a wireless network chip, the upgrade system obtains a first upgrade package corresponding to the first processor, and sends the first upgrade package to the second processor, including: the upgrade system uses the micro control unit and the wireless network chip to build a network, determines a first communication connection between the first processor and the micro control unit and a second communication connection between the second processor and the micro control unit; the micro control unit obtains the first upgrade package corresponding to the first processor from an external terminal; the micro control unit uses the second communication connection to send the first upgrade package to the second processor.

[0033] For example, Figure 2 As shown, the upgrade system 100 includes a first processor 101, a second processor 102, a micro control unit 103 and a wireless network chip 104. The upgrade system uses the micro control unit and the wireless network chip to build a network and is responsible for all network actions. In addition, by using the micro control unit and the wireless network chip to establish a network, wireless communication with external devices can be achieved, so that data transmission and control can be conveniently performed.

[0034] Exemplarily, the microcontroller unit may perform data communication with the SOC via a data protocol, and then determine a first communication connection between the first processor and the microcontroller unit according to the digital protocol and determine a second communication connection between the second processor and the microcontroller unit according to the digital protocol.

[0035] Optionally, the data protocol can be an SPI (serial peripheral interface) / SDIO (secure digital input and output) protocol, or other protocols. This application does not make specific restrictions, and users can set it according to actual needs.

[0036] Exemplarily, the micro control unit obtains a first upgrade package corresponding to the first processor from an external terminal according to the result of network establishment by the wireless network chip; after obtaining the first upgrade package, the micro control unit sends the first upgrade package to the second processor using a second communication connection.

[0037] Specifically, the microcontroller obtains the first upgrade package corresponding to the first processor from the external terminal, and the microcontroller acts as an intermediary to transmit data between the external terminal and the second processor, thereby conveniently obtaining the upgrade package required by the first processor, thereby avoiding directly exposing the processor or network to the outside, and improving the security of the system. In addition, the microcontroller of the present application transmits the obtained first upgrade package to the second processor through the second communication connection, providing support for the subsequent completion of the upgrade of the first processor.

[0038] Step S102: The upgrade system uses the second processor and the first upgrade package to upgrade the first processor to obtain a first upgrade state corresponding to the first processor.

[0039] Exemplarily, when the upgrade system uses the second processor to upgrade the first processor, the second processor runs the upgrade program corresponding to the first upgrade package to upgrade the operating system corresponding to the first processor.

[0040] Exemplarily, the Bootloader guides the first processor and the second processor to start up in sequence. When the first processor needs to perform a system upgrade, the second processor enters the upgrade state, obtains the first upgrade package corresponding to the first processor from the microcontroller unit, operates the storage interface to update the system image of the first processor, and resets the system after the update is completed. After the reset, the first processor and the second processor start normally, and the first processor and the second processor confirm that the system is normal through the heartbeat packet. Among them, the Bootloader is a small program that runs before the operating system kernel runs. It starts to execute when the system is powered on, initializes the hardware equipment, prepares the software environment, and finally calls the operating system kernel.

[0041] Exemplarily, when an abnormality such as power failure occurs during the process of the upgrade system using the second processor and the first upgrade package to upgrade the first processor, after the system is powered on again, the system abnormality emergency method will be triggered, and at this time, the first upgrade state of the first processor is determined to be an upgrade abnormality. Alternatively, after the upgrade system uses the second processor and the first upgrade package to upgrade the first processor, it is found that the first processor and the second processor cannot communicate normally, then the first upgrade state corresponding to the first processor is determined to be an upgrade abnormality. If no abnormality occurs during the process of the upgrade system using the second processor and the first upgrade package to upgrade the first processor and after the upgrade is completed, it can be determined that the first upgrade state corresponding to the first processor is a normal upgrade.

[0042] Optionally, the exceptions in the process of upgrading the first processor in the present application may include power failure exceptions, connection exceptions, etc. The present application does not make specific restrictions, and users can choose according to actual needs.

[0043] In some embodiments, obtaining the first upgrade status corresponding to the first processor includes: the second system corresponding to the second processor sends a keep-alive heartbeat packet to the first system corresponding to the first processor; when the first system does not receive the keep-alive heartbeat packet or the first system does not respond to the keep-alive heartbeat packet, it is determined that the first upgrade status corresponding to the first processor is the upgrade exception; when the first system receives the keep-alive heartbeat packet and the first system responds to the keep-alive heartbeat packet, it is determined that the first upgrade status corresponding to the first processor is the upgrade normal.

[0044] Exemplarily, a communication channel is established between the first system of the first processor and the second system of the second processor so that the second system can periodically send keep-alive heartbeat packets to the first system, wherein the communication channel can be implemented through network communication, serial port communication, etc.

[0045] Exemplarily, the frequency and content format of the keep-alive heartbeat packet are determined so that the second system can send the keep-alive heartbeat packet to the first system at the set frequency. Then the first system continuously monitors whether the keep-alive heartbeat packet is received. If it is not received or the first system receives the keep-alive heartbeat packet but does not respond to the keep-alive heartbeat packet, it is considered that the upgrade is abnormal. Therefore, when the first system does not receive the keep-alive heartbeat packet or receives the keep-alive heartbeat packet but does not respond to the keep-alive heartbeat packet, the first upgrade state corresponding to the first processor is set to upgrade abnormality.

[0046] Exemplarily, when the first system receives the keep-alive heartbeat packet and responds to it, the first upgrade state corresponding to the first processor is set to upgrade normally.

[0047] Specifically, by sending the keep-alive heartbeat packet regularly, the communication status between the first processor and the second processor can be monitored in real time to ensure system stability and reliability. In addition, by determining the sending and receiving status of the keep-alive heartbeat packet to determine the upgrade status, unexpected situations during the upgrade process can be effectively avoided, and the reliability and security of the upgrade process can be improved.

[0048] Step S103: When the second processor determines that the first upgrade state is an upgrade exception, the second processor determines, according to the upgrade exception, a first exception repair strategy required for the first processor to perform exception repair.

[0049] Exemplarily, when the second processor determines that the first upgrade state is an upgrade exception, the second processor may need to check logs, error codes or other relevant information to analyze the cause of the upgrade exception to understand the root cause of the upgrade exception. Then, according to the abnormal situation, the second processor needs to formulate a corresponding abnormality repair strategy. For example, the first abnormality repair strategy includes but is not limited to resending the upgrade package, executing a specific repair program, restarting the processor, and other operations.

[0050] In some embodiments, the second processor determines a first exception repair strategy required for the first processor to repair the exception based on the upgrade exception, including: the second processor obtains a first frequency of the first system not receiving the keep-alive heartbeat packet or a second frequency of the first system not replying to the keep-alive heartbeat packet; the second processor determines an exception occurrence frequency corresponding to the upgrade exception based on the first frequency or the second frequency; the second processor determines the first exception repair strategy required for the first processor to repair the exception based on the exception occurrence frequency.

[0051] Exemplarily, the second processor needs to count the frequency of the first system not receiving the keep-alive heartbeat packet to obtain the first frequency, or count the frequency of the first system not replying to the keep-alive heartbeat packet to obtain the second frequency, and then the second processor divides the frequency according to the first frequency or the second frequency to obtain the abnormal occurrence frequency corresponding to the upgrade abnormality of the first processor. For example, the abnormal occurrence frequency corresponding to the upgrade abnormality can be determined as low frequency, medium frequency, high frequency, etc. according to the first frequency or the second frequency.

[0052] Exemplarily, based on the frequency of exception occurrence, the second processor can establish a mapping relationship between the frequency of exception occurrence and the exception repair strategy. For example, a simple repair strategy can be adopted for low-frequency exceptions, while a more complex repair strategy may be required for high-frequency exceptions. Then, a strategy search is performed in the mapping relationship according to the frequency of exception occurrence, so that the second processor obtains the first exception repair strategy for the first processor to perform exception processing. The first exception repair strategy includes but is not limited to operations such as resending a keep-alive heartbeat packet, reconnecting the first processor, and executing a specific exception repair program.

[0053] Specifically, the second processor determines the exception repair strategy of the first processor according to the frequency of the exception occurrence, so that appropriate measures can be taken to solve the problem and improve the stability of the system according to the severity and frequency of the exception occurrence.

[0054] In some embodiments, the second processor determines the first exception repair strategy required for the first processor to repair the exception based on the exception occurrence frequency, including: when the exception occurrence frequency is greater than or equal to a first preset frequency, the first exception repair strategy is that the second processor restarts and resets the first system corresponding to the first processor and the second system corresponding to the second processor; when the exception occurrence frequency is less than the first preset frequency, and the exception occurrence frequency is greater than or equal to the second preset frequency, the first exception repair strategy is that the second processor re-upgrades or rolls back the first processor.

[0055] Exemplarily, the frequency of abnormal occurrence is the frequency obtained by the second processor by summing the first frequency of the first system not receiving the keep-alive heartbeat packet and the second frequency of the first system not replying to the keep-alive heartbeat packet, or it can be the maximum value between the first frequency of the first system not receiving the keep-alive heartbeat packet and the second frequency of the first system not replying to the keep-alive heartbeat packet.

[0056] Exemplarily, after obtaining the exception occurrence frequency corresponding to the first processor, when the exception occurrence frequency is greater than or equal to the first preset frequency, the first exception repair strategy is that the second processor restarts and resets the first system corresponding to the first processor and the second system corresponding to the second processor; when the exception occurrence frequency is less than the first preset frequency, and the exception occurrence frequency is greater than or equal to the second preset frequency, the first exception repair strategy is that the second processor re-upgrades or rolls back the version of the first processor.

[0057] For example, the first system of the first processor and the second system of the second processor send a keep-alive heartbeat packet through heterogeneous communication. When an exception occurs in any of the first system of the first processor or the second system of the second processor, the system on the other processor cannot receive the keep-alive heartbeat packet or does not respond to the keep-alive heartbeat packet, and then enters the abnormal emergency mode. The emergency mode can restart and reset the entire system, or re-upgrade or roll back the version of the system on the other processor. Taking the first upgrade state corresponding to the first processor as an upgrade exception as an example, the upgrade exception is not limited to OTA (over the air, air download technology) upgrade power failure, system version exception, the first processor cannot receive the keep-alive heartbeat packet sent by the second processor, and then according to the frequency of abnormal occurrence of the problem, when the abnormal occurrence frequency is greater than or equal to the first preset frequency, the first abnormal repair strategy is that the second processor restarts and resets the first system corresponding to the first processor and the second system corresponding to the second processor; when the abnormal occurrence frequency is less than the first preset frequency, and the abnormal occurrence frequency is greater than or equal to the second preset frequency, the first abnormal repair strategy is that the second processor re-upgrades or rolls back the version of the first processor.

[0058] Optionally, the first preset frequency is greater than the second preset frequency. The first preset frequency and the second preset frequency can be set according to actual needs, and this application does not make specific restrictions.

[0059] Specifically, according to the magnitude of the frequency of the abnormality, an appropriate abnormality repair strategy is determined. This helps to achieve adaptive abnormality handling, and different repair measures are taken according to the specific situation, so as to solve the abnormal problem more effectively. In addition, when the frequency of abnormality is high, performing a restart and reset operation on the first system and the second system helps to clean up the system state and restore it to normal. This can improve the stability of the system and avoid more serious problems caused by being in an abnormal state for a long time. When the frequency of abnormality is between the first preset frequency and the second preset frequency, a re-upgrade or version rollback operation is performed. This helps the system to take corresponding measures to repair the problem when the abnormality frequency is low but there are still problems, and improve the system's tolerance for abnormalities. Finally, by automatically determining the abnormality frequency and executing the corresponding abnormality repair strategy, the cost of manual intervention can be reduced. The system can take actions on its own to a certain extent, reducing dependence on personnel and operating costs.

[0060] In some embodiments, when the exception occurrence frequency is less than the first preset frequency, and the exception occurrence frequency is greater than or equal to the second preset frequency, the first exception repair strategy is that the second processor re-upgrades or rolls back the first processor, including: the second processor resets and restarts the first system corresponding to the first processor; after the first system is reset and restarted, the second processor re-upgrades the first processor according to the first upgrade package, if the first system is still upgraded abnormally, the second processor re-obtains the first upgrade package from the microcontroller unit, and upgrades the first system according to the re-obtained first upgrade package; when the first processor is upgraded according to the re-obtained first upgrade package, if the upgrade is still abnormal, the second processor obtains the third upgrade package corresponding to the first processor, and rolls back the version of the first system according to the third upgrade package.

[0061] Exemplarily, when the frequency of exception occurrence is less than a first preset frequency, and the frequency of exception occurrence is greater than or equal to a second preset frequency, the first exception repair strategy can be further subdivided into when the frequency of exception occurrence is less than the first preset frequency, and the frequency of exception occurrence is greater than or equal to the second preset frequency, the second processor first resets and restarts the first system corresponding to the first processor, and then after the first system is reset and restarted, the second processor re-upgrades the first processor according to the first upgrade package, and continues to monitor the upgrade process and upgrade results of the first processor. If the first system corresponding to the first processor is still upgraded abnormally, the second processor re-obtains the first upgrade package from the microcontroller unit, and then re-upgrades the first system according to the re-obtained first upgrade package.

[0062] Exemplarily, when the first processor is upgraded according to the first upgrade package that has been retrieved, and the upgrade is still abnormal, the second processor obtains the third upgrade package corresponding to the first processor, and performs version rollback on the first system according to the third upgrade package. The third upgrade package is the upgrade package of the current version corresponding to the first processor when the first upgrade package corresponding to the first processor is upgraded, that is, the upgrade package of the current version corresponding to the first processor before the version upgrade.

[0063] For example, if the first system of the first processor still has an upgrade exception, the second processor applies to the microcontroller unit MCU corresponding to the upgraded system to obtain the upgrade package corresponding to the first system of the first processor, and operates the storage to re-update the partition data of the first processor; if the first system corresponding to the first processor continues to have an upgrade exception, the second processor applies to the microcontroller unit MCU to obtain the old version upgrade package (that is, the third upgrade package) corresponding to the first system of the first processor for version rollback.

[0064] Specifically, after the first system is reset and restarted, the second processor upgrades the first processor according to the first upgrade package, which is conducive to automatically trying to use the original upgrade package to fix the problem, simplifying the repair process and improving processing efficiency. If the first system still has an upgrade exception, the second processor can re-acquire the upgrade package and try to upgrade the first system with a new upgrade package, which increases intelligent processing and tries different repair methods to solve the problem. When the first system is still abnormal after upgrading according to the re-acquired first upgrade package, the second processor obtains the third upgrade package and rolls back the version of the first system, which provides a backup plan for dealing with upgrade exceptions and ensures that the system can return to a stable state. In addition, by trying multiple automated processing processes, the system can handle upgrade exceptions more effectively, increase the success rate of upgrades, and reduce the system unavailability time caused by exceptions. In general, the above steps help to improve the system's self-repair ability and the success rate of the upgrade process, reduce system stability problems caused by upgrade exceptions, and ensure the reliability and stability of the system during the upgrade process.

[0065] Step S104: The second processor performs exception processing on the first processor according to the first exception repair strategy to ensure normal operation of the first processor.

[0066] Exemplarily, after the second processor determines the first exception repair strategy according to the upgrade exception corresponding to the first processor, the second processor performs exception processing on the first processor according to the first exception repair strategy, thereby ensuring the normal operation of the first processor.

[0067] In some implementations, the micro control unit records and manages abnormal parameters corresponding to the upgrade abnormality.

[0068] Exemplarily, the microcontroller unit communicates data with the SOC via the SPI / SDIO protocol. The microcontroller unit has a built-in ROM that can record and manage abnormal parameters corresponding to the upgrade abnormality. For example, the abnormal parameters can include system upgrade status, system abnormality times, system version, etc.

[0069] Optionally, the abnormal parameters include but are not limited to system upgrade status, number of system abnormalities, system version, etc., which can be set according to needs, and this application does not make specific restrictions.

[0070] Specifically, the microcontroller unit records and manages the abnormal parameters corresponding to the upgrade abnormality, which facilitates subsequent developers to find problems in the upgrade version corresponding to the upgrade abnormality, quickly resolve the upgrade abnormality in the upgrade package, and provide good support for improving the upgrade efficiency in the future.

[0071] In some implementations, the first processor and the second processor in the multi-core heterogeneous SOC use the same interface and can operate the microcontroller unit independently; the first processor and the second processor share peripheral resources.

[0072] Exemplarily, the first processor and the second processor in the multi-core heterogeneous SOC use the same interface and can operate the microcontroller unit independently, and the first processor and the second processor share peripheral resources.

[0073] For example, in a multi-core heterogeneous SOC system, it is ensured that the first processor and the second processor use the same interface to communicate with the microcontroller unit, so that a unified communication interface can be implemented, facilitating data exchange and sharing between the two processors.

[0074] Exemplarily, it is ensured that the first processor and the second processor can independently operate the microcontroller unit, that is, can independently send instructions to the microcontroller unit and obtain responses. This ensures that the processors do not interfere with each other in accessing the microcontroller unit, thereby improving the parallelism and efficiency of the processors.

[0075] Exemplarily, it is ensured that the first processor and the second processor can share peripheral resources. This can avoid unnecessary hardware redundancy and improve the resource utilization of the system. For example, some peripheral resources can be allocated to the first processor for use, while other peripheral resources can be allocated to the second processor for use, so as to meet the diverse needs of the system.

[0076] For example, by sharing the interface and operating the microcontroller independently, the first processor and the second processor can perform tasks in parallel, making full use of system resources, thereby improving the overall performance of the system. By sharing peripheral resources and allocating and utilizing them according to actual needs, the hardware cost of the system can be reduced. At the same time, using the same interface and operating the microcontroller independently can also simplify system design and development and reduce development costs.

[0077] In some embodiments, the method also includes: the upgrade system obtains a second upgrade package corresponding to the second processor, and sends the second upgrade package to the first processor; the upgrade system uses the first processor and the second upgrade package to perform upgrade processing on the second processor to obtain a second upgrade state corresponding to the second processor; when the first processor determines that the second upgrade state is the upgrade exception, the first processor determines a second exception repair strategy required for the second processor to repair the exception based on the upgrade exception; the first processor performs exception processing on the second processor according to the second exception repair strategy to ensure the normal operation of the second processor.

[0078] Exemplarily, the upgrade system uses the second processor and the first upgrade package to upgrade the first processor. After obtaining that the first upgrade status corresponding to the first processor is normal, the upgrade system accesses the official website or support page of the manufacturer corresponding to the second processor, searches for the latest upgrade package corresponding to the processor model of the second processor currently in use, and then downloads the second upgrade package required for the second processor upgrade, and ensures that the downloaded second upgrade package is compatible with the processor model of the second processor and the upgrade system architecture. Thus, the upgrade system copies the downloaded second upgrade package file to the storage location corresponding to the first processor.

[0079] Exemplarily, when an abnormality such as power failure occurs during the process of the upgrade system using the first processor and the second upgrade package to upgrade the second processor, after the system is powered on again, the system abnormality emergency method will be triggered, and at this time, the second upgrade state of the second processor is determined to be an upgrade abnormality. Alternatively, after the upgrade system uses the first processor and the second upgrade package to upgrade the second processor, it is found that the first processor and the second processor cannot communicate normally, then the second upgrade state corresponding to the second processor is determined to be an upgrade abnormality. If no abnormality occurs during the process of the upgrade system using the first processor and the second upgrade package to upgrade the second processor and after the upgrade is completed, it can be determined that the second upgrade state corresponding to the second processor is a normal upgrade.

[0080] Exemplarily, when the first processor determines that the second upgrade state corresponding to the second processor is an upgrade exception, the first processor may need to check logs, error codes or other relevant information to analyze the cause of the upgrade exception to understand the root cause of the upgrade exception. Then, according to the abnormal situation, the first processor needs to formulate a corresponding abnormality repair strategy. For example, the second abnormality repair strategy includes but is not limited to resending the upgrade package, executing a specific repair program, restarting the processor, and other operations.

[0081] Optionally, the method for the first processor to determine the second exception repair strategy corresponding to the second processor is the same as the method for the second processor to determine the first exception repair strategy corresponding to the first processor. Please refer to the above for details, which will not be repeated here.

[0082] Exemplarily, after the first processor determines the second exception repair strategy according to the upgrade exception corresponding to the second processor, the first processor performs exception processing on the second processor according to the second exception repair strategy, thereby ensuring the normal operation of the second processor.

[0083] Please refer to Figure 3 , Figure 3 A schematic diagram of a scenario for implementing the upgrade method based on multi-core heterogeneous SOC provided in this embodiment, as shown in FIG. Figure 3As shown, this upgrade system consists of a dual-core heterogeneous SOC, a microcontroller unit and a wireless network chip (wifi chip). The microcontroller unit and the wifi chip complete the network configuration and are responsible for all network actions. The microcontroller unit communicates data with the SOC through the spi / sdio protocol. The built-in ROM of the microcontroller unit can record the system upgrade status, the number of system abnormalities, the system version, etc. The operating systems running on the two CPUs (the first processor and the second processor) under the dual-core heterogeneous SOC can use the same peripherals. Therefore, the first processor and the second processor can use the same interface to operate the flash and the microcontroller unit separately and share peripheral resources. The first processor and the second processor run their own independent operating systems, and the first processor and the second processor send and respond to the keep-alive heartbeat packets to confirm the system status of the other processor. When the first processor and the second processor in the dual-core heterogeneous SOC need to upgrade the system, the Bootloader guides the first processor and the second processor to start up successively. When the first processor needs to upgrade the system, the second processor enters the upgrade state, obtains the first upgrade package of the first processor from the microcontroller unit, operates the storage interface to update the system image of the first processor, and resets the system after the update is completed. After the reset, the first processor and the second processor start normally, and the heartbeat packet confirms that the system is normal. Similarly, when the second processor needs a system upgrade, the first processor obtains the second upgrade package of the second processor from the microcontroller unit, and operates the storage interface to update the system image of the second processor. In this process, abnormalities such as power failure occur. After the system is powered on again, the system abnormality repair strategy will be triggered, and mutual upgrades or version rollbacks will also be performed. For example, the systems on the first processor and the second processor send a keep-alive heartbeat packet through heterogeneous communication. When an abnormality occurs in either the first processor or the second processor, the system on the other processor cannot receive the heartbeat packet or the heartbeat packet response, and will enter the abnormal emergency mode. The emergency mode can restart and reset the entire system, or re-upgrade or roll back the system on the other processor. Taking the abnormality of the first processor as an example, the abnormality is not limited to power failure during OTA upgrade and abnormal system version. The second processor cannot receive the heartbeat packet sent by the first processor. According to the frequency of the problem, the system is reset and restarted first; if the first processor system is still abnormal, apply to the microcontroller unit to obtain the first upgrade package of the first system on the first processor, and operate the storage to re-update the partition data of the first processor; if the first system on the first processor continues to be abnormal, apply to the microcontroller unit to obtain the old version upgrade package corresponding to the first processor for version rollback.

[0084] In the present application, the SOC end includes two heterogeneous processors: a first processor and a second processor, and the two processors run their own business logic. During the upgrade process, the first processor runs the upgrade program to upgrade the operating system of the second processor. After the system restarts normally, the second processor upgrades the operating system of the first processor. When only one of the processors' operating system needs to be upgraded, the other processor also performs the upgrade. This solves the problem that the upgrade method used in the related art needs to occupy double the storage space, thus causing a waste of storage space and reducing the upgrade efficiency. In addition, the first processor and the second processor confirm the system status of the two processors by sending a heartbeat packet-response. When one of the systems is abnormal, the other system can start the emergency module. The system abnormality includes but is not limited to the interruption of the upgrade process and the system crash caused by the defect of the upgrade version. The emergency program can choose to restart the device, continue to upgrade the version, or roll back the device version according to the system status to handle the system abnormality. In the first aid module, the normal processor accesses the microcontroller unit through SPI or SDIO. The microcontroller unit downloads the upgrade package from the remote server through WiFi, and sends the upgrade package to the SOC end through the SDIO or SPI interface, operates the flash memory, and re-completes the first aid of the abnormal processor. Therefore, this application also solves the problem of not being able to accurately handle the exception when a freeze or other exceptions occur during the upgrade process.

[0085] like Figure 2 As shown, the embodiment of the present application further provides an upgrade system 100 based on a multi-core heterogeneous SOC, wherein the upgrade system 100 includes the multi-core heterogeneous SOC, wherein the multi-core heterogeneous SOC includes at least a first processor 101 and a second processor 102, and the upgrade system 100 performs the following steps:

[0086] The upgrade system obtains a first upgrade package corresponding to the first processor, and sends the first upgrade package to the second processor;

[0087] The upgrade system uses the second processor and the first upgrade package to upgrade the first processor to obtain a first upgrade state corresponding to the first processor;

[0088] When the second processor determines that the first upgrade state is an upgrade exception, the second processor determines, according to the upgrade exception, a first exception repair strategy required for the first processor to perform exception repair;

[0089] The second processor performs exception processing on the first processor according to the first exception repair strategy to ensure normal operation of the first processor.

[0090] In some implementations, the multi-core heterogeneous SOC-based upgrade system 100 further includes: a microcontroller unit 103 and a wireless network chip 104. The upgrade system 100 obtains a first upgrade package corresponding to the first processor, and in the process of sending the first upgrade package to the second processor, executes:

[0091] The upgrade system uses the micro control unit and the wireless network chip to build a network, and determines a first communication connection between the first processor and the micro control unit and a second communication connection between the second processor and the micro control unit;

[0092] The micro control unit obtains the first upgrade package corresponding to the first processor from an external terminal;

[0093] The micro control unit sends the first upgrade package to the second processor using the second communication connection.

[0094] In some implementations, during the process of obtaining the first upgrade state corresponding to the first processor, the upgrade system 100 executes:

[0095] The second system corresponding to the second processor sends a keep-alive heartbeat packet to the first system corresponding to the first processor;

[0096] When the first system does not receive the keep-alive heartbeat packet or the first system does not respond to the keep-alive heartbeat packet, determining that the first upgrade state corresponding to the first processor is the upgrade exception;

[0097] When the first system receives the keep-alive heartbeat packet and responds to the keep-alive heartbeat packet, it is determined that the first upgrade state corresponding to the first processor is normal upgrade.

[0098] In some implementations, during the process of determining, according to the upgrade exception, a first exception repair strategy required by the first processor for performing exception repair, the second processor 102 executes:

[0099] The second processor obtains a first frequency of the first system failing to receive the keep-alive heartbeat packet or a second frequency of the first system failing to reply to the keep-alive heartbeat packet;

[0100] The second processor determines, according to the first frequency or the second frequency, an exception occurrence frequency corresponding to the upgrade exception;

[0101] The second processor determines, according to the frequency of occurrence of the exception, the first exception repair strategy required by the first processor when performing exception repair.

[0102] In some implementations, the second processor 102, in determining the first exception repair strategy required by the first processor to repair the exception according to the exception occurrence frequency, executes:

[0103] When the frequency of occurrence of the exception is greater than or equal to a first preset frequency, the first exception repair strategy is that the second processor restarts and resets the first system corresponding to the first processor and the second system corresponding to the second processor;

[0104] When the exception occurrence frequency is less than the first preset frequency and the exception occurrence frequency is greater than or equal to the second preset frequency, the first exception repair strategy is that the second processor re-upgrades or rolls back the version of the first processor.

[0105] In some implementations, when the exception occurrence frequency is less than the first preset frequency and the exception occurrence frequency is greater than or equal to the second preset frequency, the first exception repair strategy is that during the re-upgrade or version rollback of the first processor by the second processor, the following is executed:

[0106] The second processor resets and restarts the first system corresponding to the first processor;

[0107] After the first system is reset and restarted, the second processor re-upgrades the first processor according to the first upgrade package. If the first system is still upgraded abnormally, the second processor re-obtains the first upgrade package from the micro control unit and upgrades the first system according to the re-obtained first upgrade package.

[0108] When the first processor is upgraded according to the first upgrade package that has been retrieved and the upgrade is still abnormal, the second processor obtains a third upgrade package corresponding to the first processor and performs a version rollback on the first system according to the third upgrade package.

[0109] In some implementations, the micro control unit 103 records and manages the abnormal parameters corresponding to the upgrade abnormality.

[0110] In some implementations, the first processor and the second processor in the multi-core heterogeneous SOC use the same interface and can operate the microcontroller unit independently; the first processor and the second processor share peripheral resources.

[0111] In some implementations, the upgrade system 100 further performs:

[0112] The upgrade system obtains a second upgrade package corresponding to the second processor, and sends the second upgrade package to the first processor;

[0113] The upgrade system uses the first processor and the second upgrade package to upgrade the second processor to obtain a second upgrade state corresponding to the second processor;

[0114] When the first processor determines that the second upgrade state is the upgrade exception, the first processor determines, according to the upgrade exception, a second exception repair strategy required for the second processor to perform exception repair;

[0115] The first processor performs exception processing on the second processor according to the second exception repair strategy to ensure normal operation of the second processor.

[0116] It should be noted that, technical personnel in the relevant field can clearly understand that, for the convenience and conciseness of description, the specific working process of the upgrade system based on multi-core heterogeneous SOC described above can refer to the corresponding process in the aforementioned upgrade method embodiment based on multi-core heterogeneous SOC, and will not be repeated here.

[0117] like Figure 4 As shown, Figure 4 The structure block diagram of a terminal 1500 provided according to an embodiment of the present application is shown. The components of the terminal 1500 include but are not limited to a memory 1510 and a processor 1520. The processor 1520 is connected to the memory 1510 via a bus 1530, and the database 1550 is used to store data.

[0118] The terminal 1500 also includes an access device 1540 that enables the terminal 1500 to communicate via one or more networks 1560. Examples of these networks include a public switched telephone network (PSTN), a local area network (LAN), a wide area network (WAN), a personal area network (PAN), or a combination of communication networks such as the Internet. The access device 1540 may include one or more of any type of network interface (e.g., a network interface card (NIC)) of wired or wireless, such as an IEEE 802.11 wireless local area network (WLAN) wireless interface, a global interconnection for microwave access (Wi□MAX) interface, an Ethernet interface, a universal serial bus (USB) interface, a cellular network interface, a Bluetooth interface, a near field communication (NFC) interface, and the like.

[0119] In one embodiment of the present application, the above components of the terminal 1500 and Figure 4 Other components not shown in the figure may also be connected to each other, for example, via a bus. It should be understood that Figure 4The electronic device structure block diagram shown is only for the purpose of illustration, and is not intended to limit the scope of the present application. Those skilled in the art may add or replace other components as needed.

[0120] Terminal 1500 may be any type of stationary or mobile electronic device, including a mobile computer or mobile electronic device (e.g., a tablet computer, a personal digital assistant, a laptop computer, a notebook computer, a netbook, etc.), a mobile phone (e.g., a smart phone), a wearable electronic device (e.g., a smart watch, smart glasses, etc.), or other types of mobile devices, or a stationary electronic device such as a desktop computer or a PC. Terminal 1500 may also be a mobile or stationary server.

[0121] The processor 1520 is used to execute computer executable instructions of the object processing method.

[0122] The above is a schematic scheme of a computing device of this embodiment. It should be noted that the technical scheme of the computing device and the technical scheme of the object processing method described above are of the same concept, and the details not described in detail in the technical scheme of the computing device can be referred to the description of the technical scheme of the object processing method described above.

[0123] An embodiment of the present application further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the above-mentioned method for adjusting the image angle is implemented.

[0124] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0125] It will be appreciated by those skilled in the art that all or some of the steps and systems in the disclosed method above may be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media generally include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0126] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above implementation mode. Technical personnel familiar with the field can also make various equivalent modifications or substitutions under the shared conditions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. An upgrade method based on multi-core heterogeneous SOC, characterized in that: Applied to an upgrade system based on a multi-core heterogeneous SOC, the upgrade system includes the multi-core heterogeneous SOC, wherein the multi-core heterogeneous SOC includes at least a first processor and a second processor, the method includes: The upgrade system obtains a first upgrade package corresponding to the first processor, and sends the first upgrade package to the second processor; The upgrade system uses the second processor and the first upgrade package to upgrade the first processor to obtain a first upgrade state corresponding to the first processor; When the second processor determines that the first upgrade state is an upgrade exception, the second processor determines, according to the upgrade exception, a first exception repair strategy required for the first processor to perform exception repair; The second processor performs exception processing on the first processor according to the first exception repair strategy to ensure normal operation of the first processor.

2. The method according to claim 1, characterized in that The upgrade system based on multi-core heterogeneous SOC further includes: a micro control unit and a wireless network chip. The upgrade system obtains a first upgrade package corresponding to the first processor and sends the first upgrade package to the second processor, including: The upgrade system uses the micro control unit and the wireless network chip to build a network, and determines a first communication connection between the first processor and the micro control unit and a second communication connection between the second processor and the micro control unit; The micro control unit obtains the first upgrade package corresponding to the first processor from an external terminal; The micro control unit sends the first upgrade package to the second processor using the second communication connection.

3. The method according to claim 1, characterized in that The obtaining a first upgrade state corresponding to the first processor includes: The second system corresponding to the second processor sends a keep-alive heartbeat packet to the first system corresponding to the first processor; When the first system does not receive the keep-alive heartbeat packet or the first system does not respond to the keep-alive heartbeat packet, determining that the first upgrade state corresponding to the first processor is the upgrade exception; When the first system receives the keep-alive heartbeat packet and responds to the keep-alive heartbeat packet, it is determined that the first upgrade state corresponding to the first processor is normal upgrade.

4. The method according to claim 3, characterized in that The second processor determines, according to the upgrade exception, a first exception repair strategy required by the first processor for performing exception repair, including: The second processor obtains a first frequency of the first system failing to receive the keep-alive heartbeat packet or a second frequency of the first system failing to reply to the keep-alive heartbeat packet; The second processor determines, according to the first frequency or the second frequency, an exception occurrence frequency corresponding to the upgrade exception; The second processor determines, according to the frequency of occurrence of the exception, the first exception repair strategy required by the first processor when performing exception repair.

5. The method according to claim 4, characterized in that The second processor determines, according to the frequency of the exception, the first exception repair strategy required by the first processor for performing exception repair, including: When the frequency of occurrence of the exception is greater than or equal to a first preset frequency, the first exception repair strategy is that the second processor restarts and resets the first system corresponding to the first processor and the second system corresponding to the second processor; When the exception occurrence frequency is less than the first preset frequency and the exception occurrence frequency is greater than or equal to the second preset frequency, the first exception repair strategy is that the second processor re-upgrades or rolls back the version of the first processor.

6. The method according to claim 5, characterized in that When the exception occurrence frequency is less than the first preset frequency, and the exception occurrence frequency is greater than or equal to the second preset frequency, the first exception repair strategy is that the second processor re-upgrades or rolls back the first processor, including: The second processor resets and restarts the first system corresponding to the first processor; After the first system is reset and restarted, the second processor re-upgrades the first processor according to the first upgrade package. If the first system is still upgraded abnormally, the second processor re-obtains the first upgrade package from the micro control unit and upgrades the first system according to the re-obtained first upgrade package. When the first processor is upgraded according to the first upgrade package that has been retrieved and the upgrade is still abnormal, the second processor obtains a third upgrade package corresponding to the first processor and performs a version rollback on the first system according to the third upgrade package.

7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: The upgrade system obtains a second upgrade package corresponding to the second processor, and sends the second upgrade package to the first processor; The upgrade system uses the first processor and the second upgrade package to upgrade the second processor to obtain a second upgrade state corresponding to the second processor; When the first processor determines that the second upgrade state is the upgrade exception, the first processor determines, according to the upgrade exception, a second exception repair strategy required for the second processor to perform exception repair; The first processor performs exception processing on the second processor according to the second exception repair strategy to ensure normal operation of the second processor.

8. An upgrade system based on multi-core heterogeneous SOC, characterized in that: The upgrade system includes the multi-core heterogeneous SOC, wherein the multi-core heterogeneous SOC includes at least a first processor and a second processor, and the upgrade system performs the following steps: The upgrade system obtains a first upgrade package corresponding to the first processor, and sends the first upgrade package to the second processor; The upgrade system uses the second processor and the first upgrade package to upgrade the first processor to obtain a first upgrade state corresponding to the first processor; When the second processor determines that the first upgrade state is an upgrade exception, the second processor determines, according to the upgrade exception, a first exception repair strategy required for the first processor to perform exception repair; The second processor performs exception processing on the first processor according to the first exception repair strategy to ensure normal operation of the first processor.

9. A terminal, characterized in that: It includes at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions that can be executed by the at least one control processor, and the instructions are executed by the at least one control processor so that the at least one control processor can execute the upgrade method based on multi-core heterogeneous SOC as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the upgrade method based on a multi-core heterogeneous SOC as described in any one of claims 1 to 7.

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