Memory device and control method for controlling memory device

Abstract

The present disclosure provides a memory device and a control method for the memory device. The memory device includes a memory array and a control logic circuit. The memory array includes memory cell rows. The control logic circuit comprises a counter and a reset circuit. The counter counts the number of accesses performed on the memory cell rows to generate a count value corresponding to the memory cell row accessed among the memory cell rows, and sets the count value to a random value when the count value is equal to a predetermined value and when the accesses are performed. The reset circuit resets the count value to a predetermined value in response to a refresh command. When the count value reaches a threshold value, the control logic circuit arranges a memory cell row near the accessed memory cell row into a mitigation operation.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a control method for controlling the memory device, and more particularly, to a memory device and a control method for mitigating row-hammer attacks. Background Art

[0002] Generally, a memory device performs a mitigation operation on a memory cell row in a memory array to prevent a row hammering event. When the number of accesses to a memory cell row reaches a threshold, the memory device performs a mitigation operation to refresh memory cell rows near a memory cell row that is frequently accessed within a short period of time.

[0003] However, an external attacker (e.g., a hacker or a malicious program) obtains a mitigation operation based on a threshold value and a count value corresponding to the number of accesses. Therefore, based on the threshold value and the count value, the external attacker may focus on writing to a specific row of memory cells, or cause a large number of accesses to reach the threshold value in a very short period. The above-mentioned row hammering attack may make the memory device busy, thereby reducing the performance of the memory device or disturbing a specific memory cell. Therefore, how to mitigate the row hammering attack is one of the research and development focuses of technicians in the field. Summary of the invention

[0004] The present disclosure provides a memory device and a control method of the memory device for mitigating row hammer attacks on the memory device.

[0005] The memory device includes a storage array and a control logic circuit. The storage array includes a plurality of storage cell rows. The control logic circuit is coupled to the storage array. The control logic circuit performs access to the storage array. The control logic circuit includes a counter, a reset circuit and a comparator. The counter counts the number of accesses performed on the plurality of storage cell rows to generate a count value corresponding to the accessed storage cell row among the plurality of storage cell rows, and sets the count value to a random value when the count value is equal to a predetermined value and when the access is performed. The reset circuit resets the count value to a predetermined value in response to a refresh command. The comparator compares a threshold with the count value. When the count value corresponding to the accessed storage cell row reaches the threshold, the control logic circuit arranges the storage cell rows near the accessed storage cell row into a mitigation operation.

[0006] A control method for controlling a memory device includes: providing a count value corresponding to an accessed memory cell row among a plurality of memory cell rows of a memory array of the memory device; resetting the count value to a predetermined value in response to a refresh command; setting the count value to a random value when the count value is equal to the predetermined value and when access is performed; comparing the count value with a threshold; and when the count value corresponding to the accessed memory cell row reaches the threshold, arranging memory cell rows near the accessed memory cell row into a mitigation operation.

[0007] Based on the above, the count value is reset to a predetermined value in response to a refresh command. When the count value is equal to the predetermined value and when access is performed, the count value is set to a random value. When access is performed after the reset, the count value is set to a random value. Therefore, an external attacker (e.g., a hacker or a malicious program) cannot obtain the count value having a random value. An external attacker cannot obtain the mitigation operation of the row hammering disclosed herein. Therefore, the memory device mitigates the row hammering attack.

[0008] In order to make the above contents easier to understand, several embodiments accompanied by drawings are described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure includes accompanying drawings to provide a further understanding of the present disclosure, and the accompanying drawings are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0010] Figure 1 A schematic diagram showing a control circuit and an image sensor according to an embodiment of the present disclosure;

[0011] Figure 2A and Figure 2B A schematic diagram showing count values ​​according to an embodiment of the present disclosure;

[0012] Figure 3 A schematic diagram showing a memory array according to an embodiment of the present disclosure;

[0013] Figure 4 A flow chart of a control method according to an embodiment of the present disclosure is shown.

[0014] Description of Reference Numerals

[0015] 100: Memory device

[0016] 110, 210: Storage array

[0017] 120: Control logic circuit

[0018] 121: Counter

[0019] 1211: Random value generator

[0020] 122: Reset circuit

[0021] 123: Comparator

[0022] B0~B14:bit value

[0023] CMC1_1, CMC1_2, CMC1_n, CMC2_1, CMC2_2, CMC2_n, CMCq_1, CMCq_2, CMCq_n: Count value unit

[0024] CV, CV1~CVn: count value

[0025] MC1, MC2, MCn: data unit

[0026] MR_1, MR_2~MR_(m-2), MR_(m-1), MR_m, MR_(m+1), MR_(m+2), MR_n: storage unit row

[0027] PV: Predetermined value

[0028] RFCMD: Refresh Command

[0029] RV: Random Value

[0030] S100: Control Methods

[0031] S110~S170: Steps

[0032] TV:Threshold DETAILED DESCRIPTION

[0033] The present disclosure may be understood by referring to the following detailed description in conjunction with the drawings described below. It should be noted that, for the sake of clarity of illustration and ease of understanding by the reader, the various drawings of the present disclosure illustrate a portion of an electronic device, and some elements in the various drawings may not be drawn to scale. In addition, the number and size of each device shown in the drawings are merely illustrative and are not intended to limit the scope of the present disclosure.

[0034] Certain terms are used throughout the description and the appended claims to refer to specific components. As will be understood by those skilled in the art, electronic device manufacturers may use different names to refer to components. This document is not intended to distinguish between components that have different names but the same function. In the following description and in the claims, the terms "include", "comprise" and "have" are used in an open-ended manner and should therefore be interpreted to mean "including but not limited to...". Therefore, when the terms "include", "comprises" and / or "have" are used in the description of the present disclosure, it will indicate the presence of corresponding features, regions, steps, operations and / or components, but is not limited to the presence of one or more corresponding features, regions, steps, operations and / or components.

[0035] It should be understood that when an element is said to be “coupled to”, “connected to” or “conducted to” another element, the element may be directly connected to the other element and a direct electrical connection may be established, or an intermediate element may exist between the element and the other element for relaying the electrical connection (indirect electrical connection). In contrast, when an element is said to be “directly coupled to”, “directly conducted to” or “directly connected to” another element, there are no intermediate elements.

[0036] Figure 1 FIG. 1 is a schematic diagram showing a control circuit according to a first embodiment of the present disclosure. Figure 1 In this embodiment, the memory device 100 includes a memory array 110 and a control logic circuit 120. The memory array 110 may be a dynamic random access memory (DRAM) memory array, but the present disclosure is not limited thereto. The memory array 110 includes memory cell rows MR_1 to MR_n. The control logic circuit 120 is coupled to the memory array. The control logic circuit 120 performs access to the memory array 110. In this embodiment, the access includes at least a write operation or a read operation. In addition, the control logic circuit 120 sets a count value corresponding to the accessed memory cell row.

[0037] In the present embodiment, the control logic circuit 120 includes a counter 121, a reset circuit 122, and a comparator 123. The counter 121 counts the number of accesses performed on the memory cell rows MR_1 to MR_n to generate count values ​​CV1 to CVn corresponding to the memory cell rows MR_1 to MR_n. For example, the count value CV1 corresponds to the memory cell row MR_1. The count value CV2 corresponds to the memory cell row MR_2, and so on. For example, when an access is performed on the memory cell row MR_1, the counter 121 increments the count value CV1 by a positive integer (e.g., "1").

[0038] The reset circuit 122 resets the count value to a predetermined value PV in response to a refresh command RFCMD. When the refresh command RFCMD is received, the control logic circuit 120 refreshes (e.g., rewrites or precharges) the data in at least one of the memory cell rows MR_1 to MR_n. For example, when the refresh command RFCMD for the memory cell row MR_1 is received, the control logic circuit 120 refreshes the data in the memory cell row MR_1. The reset circuit 122 resets the count value CV1 to a predetermined value PV in response to the refresh command RFCMD for the memory cell row MR_1. Therefore, when the refresh command RFCMD for the memory cell row MR_1 is received, the count value CV1 has a predetermined value PV. In other words, when the refresh command RFCMD for the memory cell row MR_1 is received, the count value CV1 is equal to the predetermined value PV.

[0039] In this embodiment, when access is performed, the counter 121 determines the count value corresponding to the accessed memory cell row. When the count value is equal to the predetermined value PV, the counter 121 sets the count value to the random value RV. On the other hand, when the count value is not equal to the predetermined value PV, the counter 121 sets the count value to the random value RV when performing access.

[0040] The count value of the accessed memory cell row is not set during access.

[0041] For example, when access is performed on the memory cell row MR_m ("m" is less than or equal to "n"), the counter 121 determines the count value CVm corresponding to the memory cell row MR_m (i.e., the accessed memory cell row). When the count value CVm is equal to the predetermined value PV, the counter 121 sets the count value CVm to the random value RV. On the other hand, when the count value CVm is not equal to the predetermined value PV, when access is performed on the memory cell row MR_m, the counter 121 does not set the count value CVm.

[0042] In the present embodiment, the comparator 123 compares the threshold TV with the count value. When the count value corresponding to the accessed memory cell row reaches the threshold TV, the control logic circuit 120 arranges the memory cell row near the accessed memory cell row to the row hammer mitigation operation. On the other hand, when the count value is less than the threshold TV, the counter 121 increments the count value of the accessed memory cell row when performing access.

[0043] For example, when the count value CVm reaches the threshold value TV, the control logic circuit 120 arranges the memory cell rows MR_(m-1) and MR_(m+1) adjacent to the memory cell row MR_m into the mitigation operation. On the other hand, when the count value CVm does not reach the threshold value TV, the counter 121 increments the count value CVm when the memory cell row MR_m is accessed.

[0044] In some embodiments, when the count value CVm reaches the threshold TV, the control logic circuit 120 arranges the memory cell rows MR_(m-2), MR_(m-1), MR_(m+1), and MR_(m+2) into a mitigation operation.

[0045] In some embodiments, when the count value CVm reaches the threshold TV, the control logic circuit 120 arranges the memory cell rows MR_(m-1), MR_m, and MR_(m+1) into a mitigation operation.

[0046] It should be noted that the reset circuit 122 resets the count value (e.g., count value CVm) to a predetermined value PV in response to the refresh command RFCMD. When the count value is equal to the predetermined value PV and when access is performed, the counter 121 sets the count value corresponding to the accessed memory cell row (e.g., memory cell row MR_m) to a random value RV. When access is performed after the reset, the count value is set to the random value RV. Therefore, an external attacker (e.g., a hacker or a malicious program) cannot obtain the count value having the random value RV. An external attacker cannot obtain the row hammer mitigation operation of the present disclosure. Therefore, the memory device mitigates the row hammer attack.

[0047] In this embodiment, the counter 121 includes a random value generator 1211. The random value generator 1211 generates a random value RV. For example, the random value generator 1211 uses a linear feedback shift register (LFSR) to generate the random value RV. For example, the random value generator 1211 includes a Fibonacci-type LFSR or a Galois-type LFSR.

[0048] For example, the random value generator 1211 generates a random value RV for each access. For example, when any one of the count values ​​CV1 to CVn is equal to the predetermined value PV, the random value generator 1211 generates the random value RV.

[0049] In this embodiment, each count value CV1 to CVn is stored in a corresponding row. For example, the count value CV1 is stored in the memory cell row MR_1, the count value CV2 is stored in the memory cell row MR_2, and so on.

[0050] Figure 2A and Figure 2B A schematic diagram showing the count value according to an embodiment of the present disclosure. Figure 1 , Figure 2A and Figure 2B In this embodiment, the count value CV includes bit values ​​B0 to B14, but the present disclosure is not limited thereto. The reset circuit 122 resets the bit values ​​B0 to B14 to the same logic value in response to the refresh command RFCMD. For example, Figure 2A As shown, the reset circuit 122 resets the bit values ​​B0 to B14 to logic values ​​"0" in response to the refresh command RFCMD. Figure 2B As shown, the reset circuit 122 resets the bit values ​​B0 to B14 to logic values ​​"1" in response to the refresh command RFCMD.

[0051] Figure 3 A schematic diagram of a storage array according to an embodiment of the present disclosure is shown. Figure 1 and Figure 3 In this embodiment, the memory array 210 includes memory cell rows MR_1 to MR_n. The memory cell row MR_1 includes a data cell MC1 and count value cells CMC1_1 to CMCq_1. The memory cell row MR_2 includes a data cell MC2 and count value cells CMC1_2 to CMCq_2. The memory cell row MR_n includes a data cell MCn and count value cells CMC1_n to CMCq_n. The data cell MC1 is used to store data. The count value cells CMC1_1 to CMCq_1 store count values ​​CV1. The data cell MC2 is used to store data. The count value cells CMC1_2 to CMCq_2 store count values ​​CV2. The data cell MCn is used to store data. The count value cells CMC1_n to CMCq_n store count values ​​CVn.

[0052] In the present embodiment, each of the memory cell rows MR_1 to MR_n corresponds to a different word line. For example, when the memory cell row MR_1 is asserted by the word line signal on the first word line, the count value CV1 can be read or written. For example, the count value CV1 can be read or written by the input / output circuit, sense amplifier, and voltage equalization circuit described in U.S. Application No. 18 / 350,753.

[0053] Furthermore, the count value cells CMC1_1 to CMC1_n are formed as a first memory cell column. The count value cells CMC2_1 to CMC2_n are formed as a second memory cell column. The count value cells CMCq_1 to CMCq_n are formed as a third memory cell column.

[0054] Taking the memory cell row MR_1 as an example, the count value units CMC1_1 to CMCq_1 are not adjacent to each other, but the present disclosure is not limited thereto. In some embodiments, the count value units CMC1_1 to CMCq_1 are continuously located in the memory cell row MR_1. In some embodiments, the count value units CMC1_1 to CMCq_1 are continuously located at the ends of the memory cell row MR_1. When receiving the refresh command RFCMD, the reset circuit 122 rewrites the count value CV1 having the predetermined value PV to the count value units CMC1_1 to CMCq_1.

[0055] When access is performed, the counter 121 reads the count value CV1 from the count value units CMC1_1 to CMCq_1 , and when the count value CV1 is equal to the predetermined value PV, rewrites the count value CV1 having the random value RV to the count value units CMC1_1 to CMCq_1 .

[0056] In the present embodiment, the count value units CMC1_1 to CMCq_1 may be formed as count value registers for the memory cell row MR_1. The count value units CMC1_2 to CMCq_2 may be formed as count value registers for the memory cell row MR_2. The count value units CMC1_n to CMCq_n may be formed as count value registers for the memory cell row MR_n.

[0057] Figure 4 A flow chart of a control method according to an embodiment of the present disclosure is shown. Figure 1 and Figure 4In the present embodiment, the control method S100 is applicable to the memory device 100. The control method S100 includes steps S110 to S170. In step S110, the counter 121 provides a count value corresponding to the accessed memory cell row. In step S120, the reset circuit 122 resets the count value to a predetermined value PV in response to the refresh command RFCMD. When the control logic circuit 120 receives the refresh command RFCMD, the reset circuit 122 resets the count value. When the control logic circuit 120 does not receive the refresh command RFCMD, the reset circuit 122 does not reset the count value.

[0058] In step S130, when access is performed, the counter 121 determines the count value. When the count value is equal to the predetermined value PV, this means that the accessed memory cell row has been refreshed before the access. Therefore, in step S140, the counter 121 sets the count value to the random value RV. Then, in step S150, the comparator 123 compares the threshold TV with the count value.

[0059] On the other hand, when the count value is not equal to the predetermined value PV, this means that the accessed memory cell row has not been refreshed before access. Therefore, the counter 121 does not set the count value to the random value RV. Then, in step S150, the comparator 123 compares the threshold TV with the count value.

[0060] In step S150, when the count value reaches the threshold TV, the control logic circuit 120 arranges at least the memory cell rows near the accessed memory cell row to the row hammer mitigation operation in step S160. Then, the control logic circuit 120 executes step S120.

[0061] On the other hand, when the count value is less than the threshold value TV, in step S170, the counter 121 increments the count value. Then, the control logic circuit 120 executes step S120.

[0062] Taking the memory cell row MR_m as an example, a count value CVm is provided in step S110. In step S120, when the control logic circuit 120 receives the refresh command RFCMD, the reset circuit 122 resets the count value CVm. When the control logic circuit 120 does not receive the refresh command RFCMD, the reset circuit 122 does not reset the count value CVm.

[0063] In step S130, when access is performed, the counter 121 determines the count value CVm. When the count value CVm is equal to the predetermined value PV, the counter 121 sets the count value CVm to the random value RV in step S140. On the other hand, when the count value CVm is not equal to the predetermined value PV, the counter 121 does not set the count value to the random value RV.

[0064] In step S150, when the count value CVm reaches the threshold TV, the control logic circuit 120 arranges at least the memory cell rows MR_(m-1) and MR_(m+1) to the row hammer mitigation operation in step S160. Then, the control logic circuit 120 executes step S120.

[0065] In some embodiments, when the count value CVm reaches the threshold value TV, the control logic circuit 120 arranges the memory cell rows MR_(m-2), MR_(m-1), MR_(m+1), and MR_(m+2) into a mitigation operation. In some embodiments, when the count value CVm reaches the threshold value TV, the control logic circuit 120 arranges the memory cell rows MR_(m-1), MR_m, and MR_(m+1) into a mitigation operation.

[0066] On the other hand, when the count value CVm does not reach the threshold value TV, in step S170, the counter 121 increments the count value CVm. Then, the control logic circuit 120 executes step S120.

[0067] In summary, the count value is reset to a predetermined value in response to a refresh command. When the count value is equal to the predetermined value and when access is performed, the count value is set to a random value. When access is performed after the reset, the count value is set to a random value. Therefore, an external attacker cannot obtain a count value having a random value. An external attacker cannot obtain the mitigation operation of the row hammering disclosed herein. Therefore, the memory device mitigates the row hammering attack.

[0068] It will be apparent to those skilled in the art that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In summary, the present disclosure is intended to cover various modifications and variations as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A memory device, comprising: A storage array including a plurality of storage cell rows; as well as A control logic circuit is coupled to the memory array and configured to access the memory array, wherein the control logic circuit comprises: a counter configured to count the number of times the access is performed on the plurality of memory cell rows to generate a count value corresponding to an accessed memory cell row among the plurality of memory cell rows, and to set the count value to a random value when the count value is equal to a predetermined value and when the access is performed; a reset circuit configured to reset the count value to the predetermined value in response to a refresh command; and a comparator configured to compare a threshold value with the count value, When the count value corresponding to the accessed memory cell row reaches the threshold, the control logic circuit arranges memory cell rows adjacent to the accessed memory cell row to a mitigation operation.

2. The memory device according to claim 1, wherein when the count value corresponding to the accessed memory cell row reaches the threshold value, the control logic circuit arranges the accessed memory cell row and the memory cell rows adjacent to the accessed memory cell row into the mitigation operation.

3. The memory device according to claim 1, wherein the counter increments the count value of the accessed memory cell row when the accessed memory cell row is accessed and when the count value is less than the threshold value.

4. The memory device of claim 1 , wherein the counter comprises: The random value generator is configured to generate the random value.

5. The memory device of claim 1 , wherein the accessed memory cell row comprises: a plurality of data units configured to store data; as well as A plurality of count value units are configured to store the count values. 6 . The memory device according to claim 5 , wherein when the refresh command is received, the reset circuit rewrites the count value having the predetermined value to the plurality of count value units.

7. The memory device according to claim 5, wherein when the access is performed, the counter reads the count value from the plurality of count value units, and rewrites the count value having the random value into the plurality of count value units when the count value is equal to the predetermined value.

8. The memory device of claim 1, wherein: The count value includes a plurality of bit values, and The reset circuit resets the plurality of bit values ​​to a same logic value in response to the refresh command.

9. A control method for controlling a memory device, comprising: providing a count value corresponding to an accessed memory cell row among a plurality of memory cell rows of a memory array of the memory device; resetting the count value to a predetermined value in response to a refresh command; When the count value is equal to the predetermined value and when the access is performed, setting the count value to a random value; comparing the count value with a threshold; as well as When the count value corresponding to the accessed memory cell row reaches the threshold value, memory cell rows adjacent to the accessed memory cell row are arranged into a mitigation operation.

10. The control method according to claim 9, wherein arranging the memory cell row near the accessed memory cell row into the mitigation operation when the count value corresponding to the accessed memory cell row reaches the threshold comprises: When the count value corresponding to the accessed memory cell row reaches the threshold value, the accessed memory cell row and the memory cell rows adjacent to the accessed memory cell row are arranged into the mitigation operation.

11. The control method according to claim 9, further comprising: When the accessed memory cell row is accessed and when the count value is less than the threshold value, the count value of the accessed memory cell row is incremented.

12. The control method according to claim 9, wherein the accessed memory cell row comprises a plurality of data cells and a plurality of count value cells, wherein the plurality of data cells store data, wherein the count value cell is configured to store the count value, wherein when the count value is equal to the predetermined value and when the access is performed, setting the count value to the random value comprises: reading the count values ​​from the plurality of count value units; When the count value is equal to the predetermined value, setting the count value to the random value; generating the count value having the random value; as well as The count value having the random value is rewritten to the plurality of count value units.

13. The control method according to claim 9, wherein the count value comprises a plurality of bit values, wherein resetting the count value to the predetermined value in response to the refresh command comprises: The plurality of bit values ​​are reset to a same logic value in response to the refresh command.

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