Interface circuit and system for neural signal reception

Abstract

The invention provides an interface circuit and system for neural signal reception. The interface circuit for neural signal reception comprises a first clock domain, a second clock domain and a memory. Wherein the first clock domain is used for receiving neural signals collected by multiple channels, the first clock domain adopts a lower sampling frequency to collect the corresponding neural signals, and the lower sampling frequency reduces the power consumption of the interface circuit, so that the situation that the collected neural signals are inaccurate due to temperature rise when the interface circuit collects the signals is avoided; furthermore, the second clock domain is used for integrating the signals of the first clock domain to obtain the neural signal transmitted at a high speed, so that the first clock domain and the second clock domain are combined, low-power-consumption and high-speed sampling of the neural signal is realized, and the accuracy of the neural signal is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of information processing technology, and in particular to an interface circuit and system for receiving neural signals. Background Art

[0002] Neural signal acquisition and simultaneous recording of electrical activity of neurons in multiple brain regions help us understand brain function. Decoding neural potentials can reveal the relationship between coordinated activity of a collection of neurons and behavior. Accurate decoding of neural activity depends on neural signals with high spatiotemporal resolution, and invasive collectors are a common way to obtain signals.

[0003] However, the body is very sensitive to the heat generated by the invasive implant of the invasive collector, and the heat of the invasive collector is related to the power consumption of the invasive collector. The greater the power consumption, the more heat is generated. In order to achieve low power consumption, the neural signal acquisition equipment in the related art reduces the number of acquisition channels or reduces the sampling frequency, which cannot meet the requirements of high spatiotemporal resolution. Summary of the invention

[0004] The present disclosure provides an interface circuit and system for receiving neural signals.

[0005] The first aspect of the present disclosure provides an interface circuit for receiving neural signals, wherein the interface circuit comprises a first clock domain, a second clock domain and a memory, the first clock domain is connected to the second clock domain, the second clock domain is connected to the memory, the sampling frequency of the first clock domain is less than the sampling frequency of the second clock domain,

[0006] The first clock domain is used to obtain neural signals of the subject through acquisition electrodes;

[0007] The second clock domain is used to obtain the neural signal of the first clock domain and store the neural signal in the memory.

[0008] In an embodiment of the present disclosure, the interface circuit also includes a signal processing unit, the output of which is connected to the input of the first clock domain and the second clock domain respectively, for generating a clock signal of a preset target frequency so as to synchronize the sampling frequency of the first clock domain and the second clock.

[0009] In an embodiment of the present disclosure, the interface circuit also includes a synchronization register, the output of the first clock domain is the input of the synchronization register, the output of the synchronization register is the input of the second clock domain, and the synchronization register is used to merge the parallel multi-channel neural signals output by the first clock domain into a serial neural signal.

[0010] In the disclosed embodiment, the interface circuit further includes acquisition electrodes for acquiring neural signals of the subject.

[0011] In the embodiment of the present disclosure, the interface circuit further includes a filter and an analog-to-digital converter, the filter is between the sampling electrode and the first clock domain, and the analog-to-digital converter is connected to the first clock domain after the filter.

[0012] The filter is used to filter the neural signal acquired by the sampling electrode and transmit it to the filter;

[0013] The analog-to-digital converter is used to convert the received signal and transmit the obtained digital signal to the first clock domain.

[0014] In the embodiment of the present disclosure, the interface circuit further includes a wireless transmission unit connected to the memory, for sending the neural signals in the memory to the analysis platform.

[0015] In an embodiment of the present disclosure, the interface circuit further includes a power supply, which is used to supply power to each unit in the interface circuit and regulate the power supply of each power supply.

[0016] The embodiment of the second aspect of the present disclosure provides a system for receiving and analyzing neural signals, comprising the interface circuit and analysis device for receiving neural signals as described in the first aspect above, wherein the analysis device comprises a wireless transmission unit, a signal analysis unit, and a display unit.

[0017] The wireless transmission unit is used to receive the neural signal sent by the interface circuit via the wireless transmission unit;

[0018] The signal analysis unit is used to analyze the neural signal;

[0019] The display unit is used to display the analysis results.

[0020] The technical solution provided in the embodiments of the present disclosure has at least the following technical effects or advantages:

[0021] The interface circuit for receiving neural signals includes a first clock domain, a second clock domain, and a memory. The first clock domain is used to receive neural signals collected by multiple channels. The first clock domain uses a lower sampling frequency to collect the corresponding neural signals. The lower sampling frequency reduces the power consumption of the interface circuit, thereby avoiding the temperature rise of the interface circuit when collecting signals, resulting in inaccurate collected neural signals; further, the second clock domain is used to integrate the signals of the first clock domain to obtain high-speed transmitted neural signals. Therefore, the combination of the first clock domain and the second clock domain realizes low-power and high-speed sampling of neural signals, thereby improving the accuracy of neural signals.

[0022] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will become apparent from the following description or be learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] By reading the detailed description of the preferred embodiment below, various other advantages and benefits will become clear to those of ordinary skill in the art. The accompanying drawings are only used for the purpose of illustrating the preferred embodiment and are not considered to be limitations of the present disclosure. In addition, the same reference symbols are used to represent the same components throughout the accompanying drawings.

[0024] In the attached picture:

[0025] Figure 1 A schematic diagram of an interface circuit for receiving neural signals provided by an embodiment of the present disclosure is shown;

[0026] Figure 2 A schematic diagram showing data collection of an interface circuit for receiving neural signals provided by an embodiment of the present disclosure is shown;

[0027] Figure 3 A schematic diagram of a neural signal receiving and analyzing system provided by an embodiment of the present disclosure is shown;

[0028] Figure 4 A schematic diagram of a neural signal receiving and analyzing system provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0029] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0030] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in the present disclosure should have the common meanings understood by those skilled in the art to which the present disclosure belongs.

[0031] High-density neural signal acquisition plays an important role in neuroscience research. Simultaneously recording the electrical activity of neurons in multiple brain regions helps to gain a deeper understanding of brain function. Decoding neural potentials reveals the relationship between the coordinated activity of neuronal ensembles and behavior. With the increase in the number of channels, high-density recording technology enables researchers to explore the spatiotemporal dynamics and connection patterns of neural networks, thereby advancing the understanding of sensory, motor and cognitive processes.

[0032] High resolution and density of neural signals allow decoding of complex brain-computer interface tasks. For example, restoring dexterous user movements, such as high-degree-of-freedom hand movements, or fine motor skills, such as handwriting or language ability requires recordings from hundreds of electrodes. Such large-scale recordings provide key data for understanding the self-organization and dysfunction of neural networks, supporting the development of clinical applications. High anatomical spatial coverage and high temporal resolution are key features for obtaining precise cap structures and analyzing complex neural activities.

[0033] Organisms are sensitive to the heat generated by the invasive implants of the collector, which increases the high demand for compact, low-power chips. The Neural Tree SoC proposes ultra-low sampling power and chip area, and the high number of channels enables it to achieve finger movement classification. However, it only provides 2 thousand samples per second (sps), and the lack of high-bandwidth action potential recording capability limits its application in complex tasks such as motion decoding. Aika's 512-channel collector has a sampling rate of 30ksps and is capable of detecting action potentials and field potentials. In theory, it can achieve fine neural decoding, but its power consumption of 125 milliwatts limits its application in brain implants. The related technology also includes a neural signal processor with an integrated on-chip neural network accelerator that supports direct on-chip decoding, but its application scenarios are limited by the limited 16 channels. In addition, wired connections increase the risk of infection and limit the freedom of the subject being measured, while wireless data transmission can enhance the flexibility of the device and reduce the overall interface size.

[0034] In view of this, the embodiments of the present disclosure propose an interface circuit for receiving neural signals, such as Figure 1 As shown, it includes a first clock domain 101, a second clock domain 102 and a memory 103, the first clock domain 101 is connected to the second clock domain 102, the second clock domain 102 is connected to the memory 103, the sampling frequency of the first clock domain 101 is less than the sampling frequency of the second clock domain 102, the first clock domain 101 is used to obtain the neural signal of the object under test through the acquisition electrode; the second clock domain 102 is used to obtain the neural signal of the first clock domain 101 and store the neural signal in the memory 103.

[0035] The first clock domain 101 is combined with the second clock to achieve multi-channel low-power and high-rate neural signal sampling. In the embodiment of the present disclosure, 128 channels of neural signal sampling are achieved.

[0036] The interface circuit further includes a signal processing unit, the output of which is connected to the input of the first clock domain 101 and the second clock domain 102 respectively, for generating a clock signal of a preset target frequency so as to synchronize the sampling frequency of the first clock domain 101 and the second clock. The signal processing unit may be a voltage controlled oscillator, and the input reference noise may be 0.66 μVrms in the range of 0.5-60 Hz.

[0037] It also includes a synchronization register, wherein the output of the first clock domain 101 is the input of the synchronization register, and the output of the synchronization register is the input of the second clock domain 102. The synchronization register is used to merge the parallel multi-channel neural signals output by the first clock domain 101 into a serial neural signal.

[0038] The interface circuit also includes a collection electrode for collecting neural signals of the object being tested. It can collect 128 points at the same time, support 16-bit resolution and a maximum collection rate of 32ksps, power consumption of 3.43mW and an area of ​​6.27mm 2 ,Compared with previously reported techniques, the lowest normalized energy consumption of 0.84μW / ch / ksps is achieved.

[0039] The interface circuit also includes a filter and an analog-to-digital converter, wherein the filter is between the sampling electrode and the first clock domain 101, and the analog-to-digital converter is connected to the first clock domain 101 after the filter, and the filter is used to filter the neural signal acquired by the sampling electrode and transmit it to the filter; the analog-to-digital converter is used to convert the received signal and transmit the obtained digital signal to the first clock domain 101. The filter can be an integrated on-chip CIC filter, which can eliminate out-of-band noise, reduce the impact on neural signals, and improve the accuracy of the collected signals. The interface circuit in the embodiment of the present disclosure is implanted in the cerebral cortex of the subject to be measured, and its electrocorticogram (ECoG) signal can be measured.

[0040] The interface circuit also includes a wireless transmission unit connected to the memory 103, which is used to send the neural signals in the memory 103 to the analysis platform. The wireless transmission unit can be a WIFI module connected to the recorder circuit through a QSPI interface, thereby realizing wireless control and data transmission. The interface circuit also includes a power supply, which is used to supply power to each unit in the interface circuit and adjust the power supply of each power supply. It is connected to the neural acquisition site through electrodes. The collected neural signals are quantized into 16-bit digital signals by VCO. The collected signals are temporarily stored in the on-chip FIFO by the data control unit. The Wi-Fi module reads the signal from the FIFO through the QSPI serial interface and wirelessly transmits the data to the host for further processing.

[0041] The first clock domain 101 is a slow sampling clock domain, and the second clock domain 102 is a high-speed data transmission clock domain. On the rising edge of the sampling clock of each slow sampling clock domain, 16-bit data from 128 channels is collected. Depending on the configuration, the data can be filtered through the CIC filter or output directly. The synchronization register facilitates the synchronization of data from the slow clock domain to the high-speed clock domain. In the high-speed clock domain, the data control unit updates the synchronization register and scans the data from all 128 channels in turn. This process converts the parallel data obtained from the 128 channels into serial data. The serial data is then written to the FIFO. As shown in the figure, Figure 2 As shown, to ensure that data from different sampling cycles are correctly identified, a frame identifier is written to the FIFO before the data from channel 1 on each rising edge of the sampling clock. This allows the system to clearly describe the starting point of each channel data. The frame identifier is increased by 1 after each complete cycle of 128 channels. The frame identifier is also used as a frame counter to detect any packet loss during off-chip data decoding.

[0042] A sine wave signal can be used as the input for 128 channels, and a logic analyzer can be used to read the QSPI output to verify the accuracy of the data stream. At 32ksps, the power consumption is 3.43mW. In this verification, the power consumption per channel per thousand samples per second (power / ch / ksps) is used as a normalized metric to evaluate the power efficiency of different neural interface features. This normalization allows a fair comparison of systems with different numbers of channels and sampling rates. Table 1 compares the acquisition chips in the embodiments of the present disclosure with those in the related art.

[0043]

[0044] The embodiments of the present disclosure provide a system for receiving and analyzing neural signals, such as Figure 3 As shown, it includes an interface circuit 301 for receiving neural signals and an analysis device 302, wherein the analysis device 302 includes a wireless transmission unit 3021, a signal processing unit 3022 and a display unit 3023.

[0045] The wireless transmission unit 3021 is used to receive the neural signal sent by the interface circuit through the wireless transmission unit; the signal analysis unit 3022 is used to analyze the neural signal; and the display unit 3023 is used to display the analysis result.

[0046] like Figure 4As shown, it is a schematic diagram of a specific example of the above-mentioned neural signal receiving and analyzing system. The voltage-controlled oscillator VCO is a signal processing unit; the digital quantizer Digital Quantizer is used to convert a continuous analog signal into a discrete digital signal; the multiplexer MUX is used to select one of multiple input signals and transmit it to a single output electronic device or circuit; the filter CIC is used to filter out the noise of the received neural signal; the synchronizer Synchronizer is used to ensure that the frequency of data transmission between the first clock domain and the second clock domain is the same; then the collected neural signal is processed by the data control unit Data Control Unit and stored in the memory Ping-Pong FIFO. Finally, the wireless transmission unit WIFI Module reads the neural signal stored in the memory through QSPI and sends it to the analysis device. The analysis device can analyze, process and display the neural signal.

[0047] It should be noted that:

[0048] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present disclosure can be practiced without these specific details. In some instances, well-known structures and technologies are not shown in detail so as not to obscure the understanding of this description.

[0049] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of the exemplary embodiments of the present disclosure, the various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. However, the disclosed method should not be interpreted as reflecting the following schematic diagram: the claimed disclosure requires more features than the features explicitly recited in each claim. More specifically, as reflected in the claims below, the inventive aspects lie in less than all the features of the single embodiment disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present disclosure.

[0050] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of this disclosure and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.

[0051] The above is only a preferred specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An interface circuit for receiving neural signals, characterized in that: The interface circuit includes a first clock domain, a second clock domain and a memory, the first clock domain is connected to the second clock domain, the second clock domain is connected to the memory, and the sampling frequency of the first clock domain is lower than the sampling frequency of the second clock domain. The first clock domain is used to obtain neural signals of the subject through acquisition electrodes; The second clock domain is used to obtain the neural signal of the first clock domain and store the neural signal in the memory.

2. The interface circuit according to claim 1, characterized in that: The interface circuit also includes a signal processing unit, the output of which is connected to the input of the first clock domain and the second clock domain respectively, for generating a clock signal of a preset target frequency so as to synchronize the sampling frequencies of the first clock domain and the second clock.

3. The interface circuit according to claim 1, characterized in that: The interface circuit also includes a synchronization register, the output of the first clock domain is the input of the synchronization register, the output of the synchronization register is the input of the second clock domain, and the synchronization register is used to merge the parallel multi-channel neural signals output by the first clock domain into a serial neural signal.

4. The interface circuit according to claim 1, characterized in that: The interface circuit also includes a collection electrode for collecting neural signals of the object being measured.

5. The interface circuit according to claim 4, characterized in that: The interface circuit further comprises a filter and an analog-to-digital converter, wherein the filter is between the sampling electrode and the first clock domain, and the analog-to-digital converter is connected to the first clock domain after the filter. The filter is used to filter the neural signal acquired by the sampling electrode and transmit it to the filter; The analog-to-digital converter is used to convert the received signal and transmit the obtained digital signal to the first clock domain.

6. The interface circuit according to claim 1, characterized in that: The interface circuit also includes a wireless transmission unit connected to the memory, and is used to send the neural signals in the memory to the analysis platform.

7. The interface circuit according to claim 1, characterized in that: The interface circuit also includes a power supply, which is used to supply power to each unit in the interface circuit and adjust the power supply of each power supply.

8. A system for receiving and analyzing neural signals, comprising an interface circuit for receiving neural signals and an analysis device as claimed in any one of claims 1 to 7, wherein the analysis device comprises a wireless transmission unit, a signal processing unit and a display unit. The wireless transmission unit is used to receive the neural signal sent by the interface circuit via the wireless transmission unit; The signal analysis unit is used to analyze the neural signal; The display unit is used to display the analysis results.

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