High-speed communication method, system and device between dual-core processors and storable medium

Abstract

The invention discloses a high-speed communication method, system and device between dual-core processors and a storable medium, and the method comprises the steps: distributing a shared region in a memory, and building a communication channel; the processors divide a piece of memory managed by each processor into memory blocks with fixed sizes, and pointers of the memory blocks form a memory pool; memory block pointers are obtained from the memory pool, and the pointers are managed by adopting an annular buffer area structure; the data writing end obtains a memory block pointer pointed by the writing pointer from the annular buffer managed by the data reading end, and writes the data into the pointed memory block; the data reading end obtains and uses the memory block pointer according to the read pointer; obtaining a new memory block pointer from the memory pool to replace the read memory block pointer; and the data reading end returns the used memory block pointer to the memory pool again. According to the method, the memory block pointer is used as a communication medium to avoid direct data copying, the data transmission efficiency is improved, the delay is reduced, and the method is suitable for high-real-time application scenes.

Description

Technical Field

[0001] The present invention belongs to the technical field of dual-core communication, and in particular relates to a high-speed communication method, system, computer equipment and storable medium between dual-core processors. Background Art

[0002] With the rapid development of computer communication technology, the demand for data transmission between processors is increasing. Especially in multi-core processor systems, the communication efficiency between processors directly affects the overall performance and real-time performance of the system. However, the existing inter-processor communication method mainly relies on the use of buffers for data copy transmission, which shows obvious shortcomings when processing large amounts of data or in scenarios with high real-time requirements.

[0003] Frequent data copying operations greatly reduce communication efficiency and introduce additional delays. As the amount of data increases, the communication overhead of the system increases significantly, affecting the overall processing speed.

[0004] Therefore, the prior art still has problems to be solved in terms of high-speed and low-latency communication between processors. A new communication method between processors is needed to solve this problem. Summary of the invention

[0005] The main purpose of the present invention is to overcome the shortcomings and deficiencies of the prior art and to provide a high-speed communication method, system, computer device and storable medium between dual-core processors.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions: In a first aspect, the present invention provides a high-speed communication method between dual-core processors, which is applied to dual-core processors, where the dual-core processors are respectively connected to memories, and the high-speed communication method comprises the following steps: S1. Allocate a shared area in memory and establish a communication channel; S2, the dual-core processors divide a piece of memory managed by each into memory blocks of fixed size, and organize the memory block pointers into a memory pool; S3, obtain the memory block pointer from the memory pool, and manage the memory block pointer using a ring buffer structure; S4, the data writing end obtains the memory block pointer pointed to by the write pointer from the ring buffer managed by the data reading end, and writes the data into the memory block pointed to by the memory block pointer; S5, the data reading end obtains and uses the memory block pointer according to the read pointer; S6, the data reading end obtains a new memory block pointer from the memory pool to replace the read memory block pointer; S7. The data reader returns the memory block pointer to the memory pool after use.

[0007] Furthermore, the step S1 is specifically as follows: A region is allocated in the memory as a shared region for dual-core processors. The size of the shared region is determined according to actual needs, and the region allows two processors to access it simultaneously. The shared region is divided into four parts, including the channel information region, the ring buffer structure region, the memory block region, and the idle region. The channel information region stores the channel name, the processor 0 ring buffer base address, the processor 1 ring buffer base address, the number of buffer units N, the memory block size, the processor 0 memory block region base address, and the processor 1 memory block region base address. This region is used to provide channel information to the processor and ensure the consistency of the channel information obtained by the two processors; the ring buffer structure region is used to store the ring buffers managed by the two processors; the memory block region is used for the processors to split to form a memory pool; the idle region represents the remaining memory that is not used, and the memory of the idle region can be allocated according to actual needs.

[0008] Furthermore, in step S2, each processor divides the portion of the memory block area that it manages, and the specific steps are as follows: S2.1. The two processors obtain the memory block size from the channel information area, and divide the memory blocks from the parts of the memory block area that they manage respectively according to the predetermined memory pool size. S2.2, each processor creates a queue for storing pointers, and stores each pointer pointing to a memory block in the pointer queue to form a memory pool. Establishing a memory pool can facilitate the processor to manage memory blocks, and the memory pool allows the processor to obtain a memory block pointer.

[0009] Furthermore, in step S3, a memory block pointer is obtained from the memory pool, and the pointer is managed using a ring buffer structure. The specific steps are as follows: The processor obtains the corresponding ring buffer base address and the number of buffer units N from the channel information area. Starting from the ring buffer base address, a ring buffer structure is created. The ring buffer structure contains a buffer header and N buffer units. The buffer header contains information such as the buffer write pointer, read pointer, and number of buffer units. The buffer header allows two processors to access it simultaneously. The data reading end only allows the read pointer to be modified, and the data writing end only allows the write pointer to be modified. The buffer unit contains a memory block pointer and the length of the stored data. The processor extracts N memory block pointers from the memory pool to fill an equal amount of buffer units to initialize the ring buffer. The memory block pointer in the buffer unit is the communication medium between the two processors. The read and write pointers enable the processor to find the memory block pointer in the corresponding buffer unit.

[0010] Furthermore, the specific steps of step S4 are as follows: S4.1. The data writing end obtains the ring buffer base address of the data reading end from the channel information area, and finds the buffer header through the ring buffer base address to obtain the write pointer.

[0011] S4.2. The data writing end obtains the memory block pointer according to the buffer unit pointed to by the write pointer, copies the data to be written into the memory block, and sets the length of the stored data in the buffer unit to the data length. The length of the data to be written should be less than or equal to the memory block size to avoid memory out-of-bounds problems; S4.3. After the writing operation is completed, the write pointer moves backward by one position. If it reaches the end of the ring buffer, it points to the start position of the ring buffer again.

[0012] Furthermore, the specific steps of step S5 are as follows: S5.1, the data reading end obtains its own ring buffer base address from the channel information area, and finds the buffer header through the ring buffer base address to obtain the read pointer; S5.2, the data reading end retrieves the memory block pointer and the length of the stored data according to the buffer unit pointed to by the read pointer. After retrieving the memory block pointer, the data reading end can read the corresponding data at the memory block according to the length of the stored data.

[0013] Furthermore, the specific steps of step S6 are as follows: S6.1. After the data reader retrieves the memory block pointer, it obtains a new memory block pointer from the local memory pool to replace the original pointer. This is done to prevent the retrieved memory block pointer from being rewritten by the data writer, thereby allowing the data reader to arbitrarily control the retrieved memory block pointer; S6.2, after the replacement operation is completed, the read pointer moves backward one position, and if it reaches the end of the ring buffer, it points to the start position of the ring buffer again.

[0014] Furthermore, the step S7 is specifically: After the data reader uses the memory block pointer retrieved in step S5.2 at any location, it must put the memory block pointer back into the memory pool so that the memory block pointer can be allocated and used again in subsequent operations, thereby ensuring that the pointers in the memory pool are effectively managed and recycled.

[0015] In a second aspect, the present invention provides a high-speed communication system between dual-core processors, which is used to execute the high-speed communication method between dual-core processors. The high-speed communication system includes: A communication channel establishment module is used to allocate a shared area in the memory and establish a communication channel; The memory segmentation module is used by the dual-core processors to segment a piece of memory managed by each processor into memory blocks of fixed size, and to form a memory pool with pointers to the memory blocks; A memory block pointer management module is used to obtain a memory block pointer from a memory pool and manage the memory block pointer using a ring buffer structure; A data writing module is used for the data writing end to obtain the memory block pointer pointed to by the write pointer from the ring buffer managed by the data reading end, and write the data into the memory block pointed to by the memory block pointer; A first data reading module, used for the data reading end to obtain and use the memory block pointer according to the read pointer; A second data reading module, used for the data reading end to obtain a new memory block pointer from the memory pool to replace the read memory block pointer; The third data reading module is used for the data reading end to return the pointer of the used memory block to the memory pool.

[0016] In a third aspect, the present invention provides a computer device, comprising a processor and a memory for storing a program executable by the processor, wherein when the processor executes the program stored in the memory, the high-speed communication method between dual-core processors described above is implemented.

[0017] In a fourth aspect, the present invention provides a storage medium storing a program, which, when executed by a processor, implements the above-mentioned high-speed communication method between dual-core processors.

[0018] Compared with the prior art, the present invention has the following advantages and beneficial effects: 1. The present invention adopts the design of shared memory and ring buffer, and uses memory block pointer as communication medium. On the one hand, the memory block pointer as communication medium enables the processor to manage memory more flexibly. On the other hand, this method effectively reduces frequent data copy operations, significantly improves data transmission efficiency and reduces communication delay.

[0019] 2. The present invention has good scalability. By simply modifying the channel configuration in the channel information area, the present invention can be easily expanded to adapt to different communication scenarios. Users can flexibly adjust according to the actual application scenario, ensuring the scalability of the system.

[0020] 3. The present invention supports the instantiation of multiple channels. By adding new channel information in the channel information area, the parallel construction and management of multiple communication channels can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 is a flowchart of the steps of a high-speed communication method between dual-core processors disclosed in Embodiment 1 of the present invention; Figure 2 This is a high-speed channel workflow diagram of a high-speed communication method between dual-core processors disclosed in Embodiment 1 of the present invention; Figure 3 It is a memory space allocation diagram of a high-speed communication method between dual-core processors disclosed in Embodiment 1 of the present invention; Figure 4 It is a structural block diagram of a dual-core dual-system data communication case in Embodiment 1 of the present invention; Figure 5 is a schematic diagram of the channel information area in Example 2 of the present invention; Figure 6 is a structural block diagram of a high-speed communication system between dual-core processors in Embodiment 4 of the present invention; Figure 7 It is a structural block diagram of the computer device in Example 5 of the present invention. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0024] Reference to "embodiments" in this application means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments.

[0025] Example 1 refer to Figure 4This embodiment provides a high-speed communication system between dual-core processors, which has a memory and two processors. The two processors run different systems, namely the Linux system and the bare core. In the Linux system, the application is responsible for sending data to the high-speed channel and receiving data from the high-speed channel, and the kernel driver is responsible for maintaining the high-speed channel. The bare core program inside the bare core is responsible for maintaining the high-speed channel and also for sending and receiving data. The specific steps are as follows: S1. Allocate a shared area in memory and establish a communication channel; S2, the dual-core processors divide a piece of memory managed by each into memory blocks of fixed size, and organize the memory block pointers into a memory pool; S3, obtain the memory block pointer from the memory pool and manage the pointer using a ring buffer structure; S4, the data writing end obtains the memory block pointer pointed to by the write pointer from the ring buffer managed by the data reading end, and writes the data into the memory block pointed to by the pointer; S5, the data reading end obtains and uses the memory block pointer according to the read pointer; S6, the data reading end obtains a new memory block pointer from the memory pool to replace the read memory block pointer; S7. The data reader returns the memory block pointer to the memory pool after use.

[0026] In this embodiment, step S1 specifically includes: dividing an area in the memory as a shared area for the two processors. Figure 3 As shown. The size of the shared area is determined according to actual needs, and the area allows two processors to access it simultaneously. The shared area is divided into four parts, including the channel information area, the ring buffer structure area, the memory block area, and the idle area. The channel information area stores the channel name, the processor 0 ring buffer base address, the processor 1 ring buffer base address, the number of buffer units N, the memory block size, the processor 0 memory block area base address, and the processor 1 memory block area base address; the ring buffer structure area is used to store the ring buffers managed by the two processors; the memory block area is used for processor segmentation to form a memory pool; the idle area represents unused remaining memory, and the memory in the idle area can be allocated according to actual needs. The channel information area is as follows Figure 5 shown.

[0027] like Figure 3The figure shows a memory space allocation diagram of a dual-core high-speed communication method, in which the entire memory space is divided into three parts. They are processor 0 running memory, processor 1 running memory, and shared memory. The shared memory includes channel information, processor 0 ring buffer structure, processor 1 ring buffer structure, processor 0 memory block area, processor 1 memory block area, and idle area. In this embodiment, processor 0 runs the Linux system, and processor 1 does not run the operating system and is a bare core processor.

[0028] In this embodiment, in step S2, each processor divides the portion of the memory block area that it manages, and the specific steps are as follows: S2.1, the processor obtains the memory block size from the channel information area, and divides the memory block area into memory blocks according to the predetermined memory pool size; In the kernel driver of the Linux processor, according to the pre-defined memory area address, find Figure 3 The channel information area shown in the figure reads the memory block size B. Then find the base address of the processor 0 memory block area, which is the base address of the memory block area managed by the Linux system processor, and cut the processor 0 memory block area into P memory blocks of size B of the memory pool size from the base address, where the memory pool size is set in the program initialization. Similarly, in the bare core program of the bare core processor, the memory block size is obtained according to the pre-defined memory area address, and then the processor 1 memory block area is divided according to the memory pool size.

[0029] S2.2. After segmentation, each pointer to the memory block is stored in a pointer queue to form a memory pool.

[0030] In the kernel driver of the Linux processor, a queue q is created to store pointers. The queue is empty at initialization. After the memory pool area is divided, the memory block pointers corresponding to the P memory blocks are placed in the queue. Similarly, the bare core processor also needs to create a queue q to store pointers and place the memory block pointers corresponding to the memory blocks in the queue.

[0031] In this embodiment, step S3 obtains a memory block pointer from the memory pool and manages the pointer using a ring buffer structure, as follows: In the kernel driver of the Linux processor, the base address of the processor 0 ring buffer and the number of buffer units N are obtained from the channel information area. Starting from the base address of the processor 0 ring buffer, a ring buffer structure is created. The ring buffer structure includes a buffer header and N buffer units. The buffer header includes information such as a buffer write pointer, a read pointer, and the number of buffer units. The buffer unit includes a memory block pointer and the length of the stored data. The processor extracts N memory block pointers from the memory pool to fill an equal number of buffer units to initialize the ring buffer.

[0032] In the bare core program of the bare core processor, the processor 1 ring buffer base address and the number of buffer units N are obtained from the channel information area. Similar to the above operation, a ring buffer structure is created starting from the processor ring buffer base address.

[0033] In this embodiment, the specific steps of step S4 are as follows: S4.1. The data writing end obtains the ring buffer base address of the data reading end from the channel information area, and finds the buffer header through the ring buffer base address to obtain the write pointer.

[0034] refer to Figure 2 In this example, the bare core processor, namely processor 1, is the data writing end. In the bare core program, the bare core processor first finds the base address of the processor 0 ring buffer managed by the Linux processor through the channel information area, and then finds the buffer header under the base address to obtain the write pointer.

[0035] S4.2, the data writing end obtains the memory block pointer according to the buffer unit pointed to by the write pointer, copies the data to be written into the memory block, and sets the storage data length in the buffer unit to the data length; The bare core processor obtains the memory block pointer p from the buffer unit pointed to by the write pointer 2 , which is the memory block where data can be written. Copy the data to be written to the memory block pointer p 2 The memory block pointed to by the buffer unit stores the data length l 2 Set to the length of the data to be written. The length must not exceed the memory block size B, otherwise a memory out-of-bounds problem will occur.

[0036] S4.3. After the writing operation is completed, the write pointer moves backward by one position. If it reaches the end of the ring buffer, it points to the start position of the ring buffer again.

[0037] After the write operation is completed, the bare core processor needs to modify the write pointer information of the buffer table header and move its position to point to the next buffer unit. If the buffer unit currently pointed to is the last one, it will be moved to point to the first buffer unit.

[0038] In this embodiment, the specific steps of step S5 are as follows: S5.1, the data reading end obtains its own ring buffer base address from the channel information area, and finds the buffer header through the ring buffer base address to obtain the read pointer; refer to Figure 2 In this example, the Linux processor, namely processor 0, is the data reading end. In the kernel driver, the Linux processor first finds the base address of the processor 0 ring buffer through the channel information area, and then finds the buffer header under the base address to obtain the read pointer.

[0039] S5.2, the data reading end retrieves the memory block pointer and the length of the stored data according to the buffer unit pointed to by the read pointer. The data reading end can read the corresponding data at the memory block according to the length of the stored data.

[0040] In the kernel driver, the Linux processor takes out the memory block pointer p from the buffer unit pointed to by the read pointer. 1 , and storage data length l 1 . When taking out the memory block pointer p 1 And the data length l 1 After that, according to the storage data length l 1 At the memory block pointer p 1 The data is handed over to the application in the Linux processor at the memory block pointed to.

[0041] In this embodiment, the specific steps of step S6 are as follows: S6.1, after the data reader retrieves the memory block pointer, it needs to obtain a new memory block pointer from the local memory pool of the data reader to replace the above memory block pointer; refer to Figure 2 , the Linux processor is processor 0, take out the memory block pointer p 1 After that, it is necessary to obtain a new memory block pointer p from the pointer queue q described in S2.2, which is the processor 0 memory pool new , and put the memory block pointer p back into 1 The buffer unit.

[0042] S6.2. After the replacement operation is completed, the pointer moves backward one position. If it reaches the end of the ring buffer, it points to the starting position of the ring buffer again.

[0043] After the replacement operation is completed, the Linux processor modifies the read pointer information of the buffer header and moves it to point to the next buffer unit. If the buffer unit currently pointed to is the last one, it is moved to point to the first buffer unit.

[0044] In this embodiment, step S7 is that the data reading end returns the pointer of the used memory block to the memory pool, which is specifically: When the Linux processor sets the memory block pointer p in the kernel driver 1 After the data stored in the memory is handed over to the application, the memory block pointer p 1 Put it back into the pointer queue q, which is the processor 0 memory pool.

[0045] Example 2 refer to Figure 4 This embodiment provides a set of experimental data, which is based on the high-speed communication method disclosed in Example 1. The experimental content is: A test program is run on the Linux processor. Its function is to generate test data. The data size is randomly generated between 50 and 1600 bytes, which is in line with the size of Ethernet data packets. The test data is sent to the bare core through the high-speed channel maintained by the kernel driver. The data sent by the bare core through the high-speed channel is obtained through the kernel driver. The sent data is compared with the received data to see if they are the same. The time difference between sending data and receiving data is measured. The above steps are repeated 50,000 times, and the time differences are summed and averaged.

[0046] The bare core program of the bare core processor is set as a test program, whose functions include receiving data from the Linux processor through the high-speed channel; and sending the data received from the high-speed channel to the Linux processor through the high-speed channel.

[0047] The high-speed communication method between dual-core processors includes the following steps: S1. Allocate a shared area in memory and establish a communication channel; S2, the dual-core processors divide a piece of memory managed by each into memory blocks of fixed size, and organize the memory block pointers into a memory pool; S3, obtain the memory block pointer from the memory pool and manage the pointer using a ring buffer structure; S4, the data writing end obtains the memory block pointer pointed to by the write pointer from the ring buffer managed by the data reading end, and writes the data into the memory block pointed to by the pointer; S5, the data reading end obtains and uses the memory block pointer according to the read pointer; S6, the data reading end obtains a new memory block pointer from the memory pool to replace the read memory block pointer; S7. The data reader returns the memory block pointer to the memory pool after use.

[0048] The contents of the above method embodiments are all applicable to this embodiment. In this embodiment, after the above test, it is obtained that after 50,000 data loopback tests, the high-speed communication method is used, and the average time is 27us. In the same system, compared with the traditional dual-core processor communication method, the average time of the traditional method is 40us, so the high-speed communication method can effectively improve the communication efficiency.

[0049] Example 3 This embodiment provides a high-speed communication method between dual-core processors. The high-speed communication method is applied to Figure 4 In the dual-core processor shown, the dual-core processor includes two high-speed channels, which are marked as high-speed channel 0 and high-speed channel 1. In this embodiment, by creating two high-speed channels, the dual-core processor is allowed to transmit data in parallel through two different high-speed channels.

[0050] The high-speed communication method between dual-core processors includes the following steps: S1. Allocate a shared area in memory and establish a communication channel; S2, the dual-core processors divide a piece of memory managed by each into memory blocks of fixed size, and organize the memory block pointers into a memory pool; S3, obtain the memory block pointer from the memory pool and manage the pointer using a ring buffer structure; S4, the data writing end obtains the memory block pointer pointed to by the write pointer from the ring buffer managed by the data reading end, and writes the data into the memory block pointed to by the pointer; S5, the data reading end obtains and uses the memory block pointer according to the read pointer; S6, the data reading end obtains a new memory block pointer from the memory pool to replace the read memory block pointer; S7. The data reader returns the memory block pointer to the memory pool after use.

[0051] In this embodiment, the difference between step S1 and embodiment 1 is as follows: refer to Figure 5In the channel information area, the information of high-speed channel 0 is first stored, including the channel name "HSCH0", the processor 0 ring buffer base address 0x11100000, the processor 1 ring buffer base address 0x11103E90, the number of buffer units 1600, the memory block size 2000, the processor 0 memory block area base address 0x1150FA80, and the processor 1 memory block area base address 0x11CB3390. Then the information of high-speed channel 1 is stored, including the channel name "HSCH1", the processor 0 ring buffer base address 0x11107D20, the processor 1 ring buffer base address 0x1110BBB0, the number of buffer units 2000, the memory block size 1600, the processor 0 memory block area base address 0x12456CA0, and the processor 1 memory block area base address 0x12BFA5B0.

[0052] Example 4 Reference Figure 6 This embodiment provides a high-speed communication system between dual-core processors, the high-speed communication system includes a communication channel establishment module 501, a memory segmentation module 502, a memory block pointer management module 503, a data writing module 504, a first data reading module 505, a second data reading module 506 and a third data reading module 507 connected in sequence, wherein: The communication channel establishing module 501 is used to allocate a shared area in the memory and establish a communication channel; A memory segmentation module 502 is used for the dual-core processors to segment a memory managed by each of the two processors into memory blocks of fixed sizes, and to form a memory pool with pointers to the memory blocks; A memory block pointer management module 503 is used to obtain a memory block pointer from a memory pool and manage the memory block pointer using a ring buffer structure; The data writing module 504 is used for the data writing end to obtain the memory block pointer pointed to by the write pointer from the ring buffer managed by the data reading end, and write the data into the memory block pointed to by the memory block pointer; A first data reading module 505, used for the data reading end to obtain and use the memory block pointer according to the read pointer; A second data reading module 506, configured for the data reading end to obtain a new memory block pointer from the memory pool to replace the read memory block pointer; The third data reading module 507 is used for the data reading end to return the used memory block pointer to the memory pool.

[0053] The contents of the above method embodiments are all applicable to the present system embodiments, and the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments.

[0054] Example 5 This embodiment provides a computer device, which may be a computer, such as Figure 7 As shown, a processor 602, a memory, an input device 603, a display 604 and a network interface 605 connected via a system bus 601 are provided. The processor is used to provide computing and control capabilities. The memory includes a non-volatile storage medium 606 and an internal memory 607. The non-volatile storage medium 606 stores an operating system, a computer program and a database. The internal memory 607 provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. When the processor 602 executes the computer program stored in the memory, a high-speed communication method between dual-core processors proposed in the above-mentioned embodiment 1 is implemented. The high-speed communication method between dual-core processors includes the following steps: S1. Allocate a shared area in memory and establish a communication channel; S2, the dual-core processors divide a piece of memory managed by each into memory blocks of fixed size, and organize the memory block pointers into a memory pool; S3, obtain the memory block pointer from the memory pool and manage the pointer using a ring buffer structure; S4, the data writing end obtains the memory block pointer pointed to by the write pointer from the ring buffer managed by the data reading end, and writes the data into the memory block pointed to by the pointer; S5, the data reading end obtains and uses the memory block pointer according to the read pointer; S6, the data reading end obtains a new memory block pointer from the memory pool to replace the read memory block pointer; S7. The data reader returns the memory block pointer to the memory pool after use.

[0055] Example 6 This embodiment provides a storage medium, which is a computer-readable storage medium, storing a computer program. When the computer program is executed by a processor, a high-speed communication method between dual-core processors proposed in the above embodiment 1 is implemented. The high-speed communication method between dual-core processors includes the following steps: S1. Allocate a shared area in memory and establish a communication channel; S2, the dual-core processors divide a piece of memory managed by each into memory blocks of fixed size, and organize the memory block pointers into a memory pool; S3, obtain the memory block pointer from the memory pool and manage the pointer using a ring buffer structure; S4, the data writing end obtains the memory block pointer pointed to by the write pointer from the ring buffer managed by the data reading end, and writes the data into the memory block pointed to by the pointer; S5, the data reading end obtains and uses the memory block pointer according to the read pointer; S6, the data reading end obtains a new memory block pointer from the memory pool to replace the read memory block pointer; S7. The data reader returns the memory block pointer to the memory pool after use.

[0056] The storage medium described in this embodiment can be a magnetic disk, an optical disk, a computer memory, a random access memory (RAM), a U disk, a mobile hard disk, or other media.

[0057] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

[0058] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A high-speed communication method between dual-core processors, applied to dual-core processors, the dual-core processors are respectively connected to memories, characterized in that: The high-speed communication method comprises the following steps: S1. Allocate a shared area in memory and establish a communication channel; S2, the dual-core processors divide a piece of memory managed by each into memory blocks of fixed size, and organize the memory block pointers into a memory pool; S3, obtain the memory block pointer from the memory pool, and manage the memory block pointer using a ring buffer structure; S4, the data writing end obtains the memory block pointer pointed to by the write pointer from the ring buffer managed by the data reading end, and writes the data into the memory block pointed to by the memory block pointer; S5, the data reading end obtains and uses the memory block pointer according to the read pointer; S6, the data reading end obtains a new memory block pointer from the memory pool to replace the read memory block pointer; S7. The data reader returns the pointer of the used memory block to the memory pool.

2. The high-speed communication method according to claim 1, characterized in that: The shared area is divided into four parts, including a channel information area, a ring buffer structure area, a memory block area and an idle area. The channel information area stores the channel name, the processor 0 ring buffer base address, the processor 1 ring buffer base address, the buffer unit number N, the memory block size, the processor 0 memory block area base address, and the processor 1 memory block area base address; the ring buffer structure area is used to store the ring buffers managed by the two processors; the memory block area is used for the processors to split to form a memory pool; the idle area represents the remaining memory that is not used, and the memory of the idle area can be allocated according to actual needs.

3. The high-speed communication method according to claim 1, characterized in that: The process of step S2 is as follows: S2.1, the processor obtains the memory block size from the channel information area, and divides the memory blocks from the memory block area according to the pre-set memory pool size; S2.

2. After segmentation, each pointer to the memory block is stored in a pointer queue to form a memory pool.

4. The high-speed communication method according to claim 1, characterized in that: The ring buffer structure includes a buffer header and N buffer units. The buffer header includes information such as a buffer write pointer, a read pointer, and the number of buffer units. The buffer unit includes a memory block pointer and a storage data length. The processor extracts an equal amount of memory block pointers from the memory pool to fill the buffer units according to the number of buffer units N to initialize the ring buffer.

5. The high-speed communication method according to claim 4, characterized in that: The process of step S4 is as follows: S4.1, the data writing end obtains the ring buffer base address of the data reading end from the channel information area, and finds the buffer header through the ring buffer base address to obtain the write pointer; S4.2, the data writing end obtains the memory block pointer according to the buffer unit pointed to by the write pointer, copies the data to be written into the memory block, and sets the storage data length in the buffer unit to the data length; S4.

3. After the writing operation is completed, the write pointer moves backward by one position. If it reaches the end of the ring buffer, it points to the start position of the ring buffer again.

6. The high-speed communication method according to claim 5, characterized in that: The process of step S5 is as follows: S5.1, the data reading end obtains the local ring buffer base address from the channel information area, and finds the buffer header through the ring buffer base address to obtain the read pointer; S5.

2. The data reader retrieves the memory block pointer and the length of the stored data according to the buffer unit pointed to by the read pointer, and reads the corresponding data at the memory block according to the length of the stored data.

7. The high-speed communication method according to claim 1, characterized in that: The process of step S6 is as follows: S6.1, after taking out the memory block pointer, the data reading end obtains a new memory block pointer from the local memory pool of the data reading end to replace the above memory block pointer; S6.2, after the replacement operation is completed, the read pointer moves backward one position, and if it reaches the end of the ring buffer, it points to the start position of the ring buffer again.

8. A high-speed communication system between dual-core processors, used to execute the high-speed communication method according to any one of claims 1 to 7, characterized in that: The high-speed communication system comprises: A communication channel establishment module is used to allocate a shared area in the memory and establish a communication channel; The memory segmentation module is used by the dual-core processors to segment a piece of memory managed by each processor into memory blocks of fixed size, and to form a memory pool with pointers to the memory blocks; A memory block pointer management module is used to obtain a memory block pointer from a memory pool and manage the memory block pointer using a ring buffer structure; A data writing module is used for the data writing end to obtain the memory block pointer pointed to by the write pointer from the ring buffer managed by the data reading end, and write the data into the memory block pointed to by the memory block pointer; A first data reading module, used for the data reading end to obtain and use the memory block pointer according to the read pointer; A second data reading module, used for the data reading end to obtain a new memory block pointer from the memory pool to replace the read memory block pointer; The third data reading module is used for the data reading end to return the pointer of the used memory block to the memory pool.

9. A computer device comprising a processor and a memory for storing a program executable by the processor, characterized in that: When the processor executes the program stored in the memory, the high-speed communication method described in any one of claims 1 to 7 is implemented.

10. A storage medium storing a program, characterized in that: When the program is executed by a processor, the high-speed communication method according to any one of claims 1 to 7 is implemented.

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