Machine learning model training method and host system
By using a rewriteable nonvolatile memory module in the host system to store transient and backtracking data during the training process of deep learning model, the time wasted problem caused by the increase in the size of the data set during the training process is solved, and a more efficient and reliable training process is achieved.
Patent Information
- Application Number
- CN202411594109.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-08
- Publication Date
- 2025-02-28
AI Technical Summary
When training deep learning models, the time required for each period increases significantly as the dataset size increases, resulting in a lot of time and computing resources being wasted when the system is interrupted and the period is re-executed.
Rewriteable nonvolatile memory modules are used to store transient data and backtracking data generated during machine learning model training. When the system exception causes iteration interruption, data is read from the storage module, the iteration phase is determined based on the backtracking data, and the phase is re-executeed based on the transient data.
It effectively reduces the wasted time and resources caused by system interruption during training, especially in the training of large data sets, and improves training efficiency and reliability.
Smart Images
Figure CN119538994A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a method for training a machine learning model using a rewritable non-volatile memory module and a host system. Background Art
[0002] With the rapid development of artificial intelligence technology, deep learning models are increasingly being used, especially in the fields of natural language processing, image recognition, and speech recognition. However, training these complex models requires a large amount of data, which makes the training process very time-consuming. Generally speaking, the training process of a deep learning model is divided into multiple epochs, each of which represents a complete traversal of the training data set. During the training process, in order to reduce the impact of unexpected interruptions on the training progress, a checkpoint is usually set after each epoch. If the system is interrupted or fails, the model can be restored from the last checkpoint and the current epoch can be re-executed to avoid starting training from scratch.
[0003] However, as the size of the dataset increases, the time required for each epoch also increases significantly. Even with a record point mechanism, tracing back to the record point and re-executing the epoch after a system interruption will still waste a lot of time and computing resources. This problem is particularly prominent in the training of large datasets, especially when the model must be iterated multiple times to achieve the desired accuracy, the efficiency loss is more obvious. Summary of the invention
[0004] The present invention proposes a training method for a machine learning model, which is applicable to a host system, and the host system includes a rewritable non-volatile memory module. The training method includes: executing a training program for the machine learning model, wherein in an iteration of a period of the training program, the transient data and the backtracking data generated by the iteration are stored in the rewritable non-volatile memory module; if an abnormality occurs in the host system and the iteration is interrupted, the transient data and the backtracking data are read from the rewritable non-volatile memory module, the stage of the iteration is determined according to the backtracking data, and this stage is executed according to the transient data.
[0005] In one embodiment of the present invention, the above iteration includes forward propagation, backward propagation, and update phases. The step of storing the transient data and backtracking data generated by the iteration in the rewritable non-volatile memory module includes: when the forward propagation is completed, obtaining the output of a neuron in the machine learning model, setting the transient data to include the output of the neuron, setting the backtracking data to indicate that the forward propagation has been completed, and writing the output of the neuron and the backtracking data to the rewritable non-volatile memory module.
[0006] In one embodiment of the present invention, the steps of determining the iteration stage according to the backtracking data and executing the stage according to the transient data include: setting the stage to backpropagation according to the backtracking data; and reading the output and multiple weights of the neuron from the rewritable non-volatile memory module, and re-executing the backpropagation according to the input and weights of the activation function.
[0007] In one embodiment of the present invention, the step of storing the iteratively generated transient data and backtrace data in a rewritable non-volatile memory module includes: when the back propagation is completed, setting the transient data to include a gradient, setting the backtrace data to indicate that the back propagation has been completed, and writing the gradient and backtrace data to the rewritable non-volatile memory module.
[0008] In one embodiment of the present invention, the step of determining the iterative stage according to the backtracking data and executing the stage according to the transient data includes: setting the stage as the update stage according to the backtracking data; and reading the gradient and a plurality of weights from the rewritable non-volatile memory module, and re-executing the update stage according to the gradient and the weight.
[0009] In one embodiment of the present invention, the above-mentioned machine learning model includes multiple layers, and the step of storing the iteratively generated transient data and backtracking data in the rewritable non-volatile memory module also includes: after updating the first layer in the update phase, setting the transient data to also include multiple updated weights of the first layer, setting the backtracking data to indicate that the first layer has been updated, and writing the updated weights and backtracking data to the rewritable non-volatile memory module.
[0010] In one embodiment of the present invention, the steps of determining the stage of iteration according to the backtracking data and executing the stage according to the transient data include: setting the above-mentioned stage to the second layer according to the backtracking data, wherein the second layer is different from the first layer; and reading the gradient and multiple weights of the second layer from the rewritable non-volatile memory module, and updating the weight of the second layer according to the gradient.
[0011] In one embodiment of the present invention, the step of storing the iteratively generated transient data and back-tracing data in a rewritable non-volatile memory module includes: when the update phase is completed, setting the transient data to include a plurality of updated weights and updated optimization parameters, setting the back-tracing data to indicate that the back propagation has been completed, and writing the updated weights, updated optimization parameters and back-tracing data to the rewritable non-volatile memory module.
[0012] In one embodiment of the present invention, the above-mentioned training method also includes: if the forward propagation of the subsequent iteration is interrupted, reading the updated weights and the updated optimization parameters from the rewritable non-volatile memory module; and re-executing the subsequent iteration according to the updated weights and the updated optimization parameters, wherein the subsequent iteration is executed after the iteration.
[0013] From another perspective, an embodiment of the present invention provides a host system, comprising a rewritable non-volatile memory module and a processor. The processor is electrically connected to the rewritable non-volatile memory module to perform multiple steps: executing a training program of a machine learning model, wherein in an iteration of a period of the training program, the transient data and the backtracking data generated by the iteration are stored in the rewritable non-volatile memory module; and if an abnormality occurs in the host system and the iteration is interrupted, the transient data and the backtracking data are read from the rewritable non-volatile memory module, a stage of the iteration is determined according to the backtracking data, and the stage is executed according to the transient data.
[0014] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 is a schematic diagram of a host system and an input / output (I / O) device according to an exemplary embodiment of the present invention;
[0016] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;
[0017] Figure 3 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;
[0018] Figure 4 is a schematic diagram showing a training procedure according to an embodiment;
[0019] Figure 5A is a schematic diagram of storing transient data in one iteration according to an embodiment;
[0020] Figure 5B is a schematic diagram showing traceback data according to an embodiment;
[0021] Figure 6 is a schematic diagram of backtracking when reverse propagation is interrupted according to an embodiment;
[0022] Figure 7 is a schematic diagram showing backtracking one layer in an update phase according to an embodiment;
[0023] Figure 8 is a flowchart illustrating a method for training a machine learning model according to one embodiment. DETAILED DESCRIPTION
[0024] Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The referenced element symbols in the following description will be regarded as the same or similar elements when the same element symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementation methods of the present invention. More specifically, these embodiments are only examples of the systems and methods in the claims of the present invention.
[0025] The terms “first”, “second”, etc. used herein do not particularly refer to an order or sequence, but are only used to distinguish elements or operations described with the same technical term.
[0026] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used together with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.
[0027] Figure 1 is a schematic diagram of a host system and input / output (I / O) devices according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.
[0028] Please refer to Figure 1 and Figure 2 , the host system 11 is a computer system, and this computer system can be a desktop computer, a server, a distributed system, a laptop computer, etc., but the present invention is not limited thereto. The host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be coupled to a system bus 110. The processor 111 may be a graphic processing unit (GPU), a tensor processing unit (TPU), a neural processing unit (NPR), a central processing unit, etc. In some embodiments, a memory is also provided in the processor 111.
[0029] In an exemplary embodiment, the processor 111 may be coupled to the memory storage device 10 via a data transmission interface 114. For example, the processor 111 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be coupled to the I / O device 12 via the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110. In other embodiments, the processor 111 may also be electrically connected to the memory storage device 10 via a dedicated data transmission interface 114 instead of the system bus 110.
[0030] In an exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be coupled to the memory storage device 10 via a wired or wireless manner.
[0031] In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, or a solid state drive (SSD) 203. In some embodiments, the memory storage device 10 may be disposed outside the host system 11 as a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a low-power Bluetooth memory storage device (e.g., iBeacon) or other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be coupled to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.
[0032] Figure 3 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 3 The memory storage device 10 includes a connection interface unit 31, a memory control circuit unit 32 and a rewritable non-volatile memory module 33.
[0033] The connection interface unit 31 is used to couple to the processor 111. The memory storage device 10 can communicate with the processor 111 via the connection interface unit 31. In an exemplary embodiment, the connection interface unit 31 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 31 may also comply with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 31 and the memory control circuit unit 32 may be packaged in one chip, or the connection interface unit 31 may be disposed outside a chip including the memory control circuit unit 32 .
[0034] The memory control circuit unit 32 is coupled to the connection interface unit 31 and the rewritable non-volatile memory module 33. The memory control circuit unit 32 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 33 according to the instructions of the processor 111.
[0035] The rewritable non-volatile memory module 33 is used to store data written by the processor 111. The rewritable non-volatile memory module 33 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one storage cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one storage cell), other flash memory modules or other memory modules with the same characteristics.
[0036] Each memory cell in the rewritable non-volatile memory module 33 stores one or more bits by changing the voltage (hereinafter also referred to as the critical voltage). Specifically, there is a charge capture layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge capture layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the critical voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the critical voltage changes, each memory cell in the rewritable non-volatile memory module 33 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in this memory cell.
[0037] In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 33 may constitute a plurality of physical programming units, and these physical programming units may constitute a plurality of physical erasing units. Specifically, the memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line may be classified into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming unit is greater than the write speed of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.
[0038] In some embodiments, the rewritable non-volatile memory module 33 uses a lower physical programming unit or a single-level storage unit to store the data written by the processor 111. The processor 111 executes a training method for a machine learning model, and the rewritable non-volatile memory module 33 serves as a cache for the processor 111. The transient data generated by the training program of the machine learning model will be stored in the rewritable non-volatile memory module 33. In addition, the rewritable non-volatile memory module 33 will also store backtracking data to indicate which stage the training program has been executed to. When a power outage or other abnormality causes the training program to be interrupted, the training program can be re-executed based on these backtracking data and transient data. In an embodiment using a lower physical programming unit or a single-level storage unit, the drive write (Drive Writes Per Day, DWPD) of the rewritable non-volatile memory module 33 is relatively large, so frequent writing can be allowed, and more backtracking points can be set in the training program to avoid losing a large amount of computing resources when the training program is interrupted.
[0039] Figure 44 is a schematic diagram showing a training procedure according to an embodiment. The machine learning model to be trained here is a neural network 400. The training of the neural network includes forward propagation 410, backward propagation 420, and an update phase. The completion of these three phases is called an iteration. Multiple training samples can be trained in one iteration, and these training samples are called a batch. The training of all samples is called an epoch. Assuming that a batch contains 50 samples and there are 70,000 samples in total, it takes 1,400 iterations to complete an epoch.
[0040] The neural network 400 includes multiple layers 431-433, each layer includes multiple neurons (e.g., neurons 441-443), each neuron includes multiple inputs and at least one output, and each input corresponds to a weight. When performing forward propagation 410, the inputs are multiplied and then added according to these weights, which can be expressed as the following mathematical formula 1.
[0041] [Mathematical formula 1]
[0042]
[0043] where w i,j represents the i-th weight in the j-th neuron, x i represents the i-th input, b j represents the bias of the jth neuron. The value z calculated by equation 1 is j It will then pass through an activation function to obtain the output of this neuron, which is also called the activation value, as shown in the following mathematical formula 2.
[0044] [Mathematical formula 2]
[0045] a j =f(z i )
[0046] where a j is the output of the activation function (also the output of the neuron). f() is the activation function, which can be any nonlinear function. One or more outputs are calculated in the output layer 433 of the neural network 400, and the loss L can be calculated through a loss function and the true label (ground truth). During back propagation, the gradient of the loss relative to the weight is calculated, and the update of each weight can be used in the following mathematical formula 3.
[0047] [Mathematical formula 3]
[0048]
[0049] Where γ is the learning rate. It is called the gradient. Based on the chain rule of calculus, the gradient It can be broken down into multiple gradients, such as the gradient of the loss relative to the output of the neuron, etc., which will not be described here for simplicity. When performing back propagation 420, the gradient of the last layer must be calculated first, then the gradient of the second-to-last layer, and then the gradient of the first layer. After calculating the gradients of all layers, the update stage will be performed according to Mathematical Formula 3.
[0050] In an iteration of a certain period in the training program, the transient data and backtracking data generated in this iteration are stored in the rewritable non-volatile memory module 33. As mentioned above, an iteration includes three stages, namely, forward propagation, back propagation, and update stage, and each stage generates different transient data. Figure 5A is a schematic diagram showing the storage of transient data in one iteration according to an embodiment. Figure 5A In the forward propagation 410, the processor 111 reads the weights of the neural network from the rewritable non-volatile memory module 33. The output of the neuron can be calculated based on these weights and the input of the model. After the forward propagation is completed, the output of the neural network and the output of all neurons in all layers can be written into the rewritable non-volatile memory module 33. In other words, the transient data at this time includes the output of the neural network and the output of the neuron. In some embodiments, the transient data may also include the input of each layer. On the other hand, the processor 111 also sets the backtracking data to indicate that the forward propagation 410 has been completed, and then writes the backtracking data into the rewritable non-volatile memory module 33. In some embodiments, the backtracking data also includes the memory address of the transient data.
[0051] When performing back propagation 420, the weights of the neural network are read from the rewritable non-volatile memory module 33, and then the gradients of each weight are calculated based on these weights, the output of the neural network, and the output of the neurons in each layer. After back propagation 420 is completed, the gradient corresponding to each weight can be is written into the rewritable non-volatile memory module 33. In other words, the transient data at this time includes the gradient In addition, the back-tracing data may also be set to indicate that the back-propagation 420 has been completed. In some embodiments, the back-tracing data also includes the memory address of the gradient.
[0052] When the update stage 510 is performed, weights, gradients, and optimization parameters are read from the rewritable non-volatile memory module 33. The optimization parameters include, for example, the above-mentioned learning rate, momentum, etc., but the present invention is not limited thereto. According to the above-mentioned mathematical formula 3, the weights can be updated to generate corresponding updated weights, and the optimization parameters of other parts can also be updated (for example, updating momentum) to generate updated optimized parameters. After the update stage 510 is executed, the updated weights and the updated optimized parameters can be written to the rewritable non-volatile memory module 33. In other words, the transient data at this stage includes the updated weights and the updated optimized parameters. In addition, the backtracking data can also be set to indicate that the back propagation 420 has been executed. In some embodiments, the backtracking data can also include the memory address of the updated weights and the updated optimized parameters.
[0053] Figure 5B is a schematic diagram showing backtracking data according to an embodiment. Figure 5B In this embodiment, the traceback data includes a mapping table 520, and the mapping table 520 includes fields 521 to 524. Field 521 records the memory address of the transient data of the previous iteration. Field 522 records the memory address of the transient data of the current iteration. Field 523 records the number of the current iteration. And field 524 records the current stage. If a system power outage occurs, the iteration executed before the power outage can be known from field 523 of the mapping table 520, and the stage executed before the power outage (forward propagation, reverse propagation, or update stage) can be known according to field 524. And according to fields 521 and 522, the required transient data can be obtained from the rewritable non-volatile memory module 33.
[0054] Through the above-mentioned approach, at each stage of the iteration, the corresponding transient data and backtracking data are written to the rewritable non-volatile memory module 33. If an abnormality occurs in the host system 11 and a certain iteration is interrupted, the transient data and backtracking data can be read from the rewritable non-volatile memory module 33, and a stage in the iteration can be determined based on the backtracking data, and this stage can be re-executed based on the transient data.
[0055] Specifically, Figure 6 FIG. 1 is a schematic diagram showing a backtracking diagram of an interrupted reverse propagation according to an embodiment. Figure 5A and Figure 6 ,exist Figure 66 shows two iterations 610 and 620 of the training procedure. Iteration 620 is performed after iteration 610, so iteration 620 is also called a subsequent iteration. Iteration 610 includes forward propagation 611, back propagation 612, and update phase 613. Iteration 620 includes forward propagation 621, back propagation 622, and update phase 623.
[0056] Please refer to interrupt 631. If an abnormality occurs in the host system 11 when executing the reverse propagation 612, causing the reverse propagation 612 to be interrupted, the back-trace data can be read from the rewritable non-volatile memory module 33, and then the transient data stored when the forward propagation 611 is completed can be read. According to this back-trace data, it can be known that the forward propagation 611 has been completed but the reverse propagation 612 has not been completed, so the stage that must be re-executed is the reverse propagation 612. Next, the output of the neurons in the transient data and the input of each layer can be obtained. In addition, the weights of the neural network can be read from the rewritable non-volatile memory module 33. The reverse propagation 612 can be re-executed based on the output of these neurons, the input of each layer and the weights.
[0057] Please refer to the interrupt 632. If an exception occurs in the host system 11 during the execution of the update phase 613, causing the update phase 613 to be interrupted, the back-trace data can be read from the rewritable non-volatile memory module 33, and then the transient data stored when the back propagation 612 is completed can be read. According to the back-trace data, it can be known that the back propagation 612 has been completed but the update phase 613 has not been completed, so the phase that must be re-executed is the update phase 613. Next, the gradients in the transient data and the weights of the neural network can be obtained, and the update phase 613 can be re-executed based on these gradients and weights.
[0058] Referring to interrupt 633, if the forward propagation 621 of iteration 620 is interrupted, the back-trace data can be read from the rewritable non-volatile memory module 33, and then the transient data stored when the update stage 613 is completed can be read. According to the back-trace data, it can be known that the update stage 613 has been completed but the forward propagation 621 has not been completed, so the stage that must be re-executed is the forward propagation 621. Next, the updated weights and updated optimized parameters in the transient data can be obtained, and the forward propagation 621 of the subsequent iteration 620 can be re-executed based on these updated weights and updated optimized parameters.
[0059] During the update phase, the weights in each layer are updated independently of each other, that is, the update of one layer does not depend on the update of another layer. Therefore, in some embodiments, when the update phase is interrupted, execution can be started from the layers that have not been completed, without executing the layers that have been updated. Figure 7FIG. 1 is a schematic diagram showing backtracking one layer in the update phase according to an embodiment. Figure 7 The update phase 613 includes updates of the first layer 701, the second layer 702, the third layer 703, etc. After the first layer 701 has been updated, the transient data may be set to include multiple updated weights of the first layer 701, and these updated weights may be written to the rewritable non-volatile memory module 33. In addition, the traceback data may be set to indicate that the first layer has been updated.
[0060] Please refer to interrupt 710. If the update stage 613 is interrupted due to a system abnormality when updating the second layer 702, the backtracking data can be read from the rewritable non-volatile memory module 33, and then the corresponding transient data can be read. According to the backtracking data, it can be known that the first layer 701 has been updated, so it is the update of the second layer 702 that must be re-executed. Next, the gradient can be read from the transient data, and the weight of the second layer can also be read from the rewritable non-volatile memory module 33. The weight of the second layer 702 can be updated according to the gradient. In this way, the layer that has been updated does not need to be re-executed.
[0061] In some embodiments, the forward propagation 611 and the backward propagation 612 are also traced back with the layer as the minimum granularity. When each layer is calculated in the forward propagation 611, the input of the layer, the output of the neuron and other data can be added to the transient data, and the transient data can be written to the rewritable non-volatile memory module 33. When each layer is calculated in the backward propagation 612, the gradient and other data of each layer can also be added to the transient data, and the transient data can be written to the rewritable non-volatile memory module 33.
[0062] Figure 8 is a flow chart showing a method for training a machine learning model according to an embodiment. Figure 8 In step 801, a training program of a machine learning model is executed, wherein in an iteration of a period of the training program, the transient data and the backtracking data generated by this iteration are stored in a rewritable non-volatile memory module. If there is no abnormality in the system that causes the training program to be interrupted, then return to step 801 to continue the next iteration. If an abnormality occurs in the host system that causes the iteration to be interrupted, step 802 is executed to read the transient data and the backtracking data from the rewritable non-volatile memory module, determine a stage of the iteration according to the backtracking data, and execute this stage according to the transient data. Figure 8 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figure 8 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 8 The method can be used in conjunction with the above embodiment or can be used alone. In other words, Figure 8 Other steps may also be added between the steps.
[0063] In the above-mentioned host system and training method, the transient data generated in the iteration will be written into the rewritable non-volatile memory module, so that when the training program is interrupted, the granularity of each stage in the iteration is used for backtracking. In some embodiments, the granularity of the layer can also be used for backtracking. In this way, the waste of computing resources can be avoided.
[0064] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.
[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for training a machine learning model, characterized in that: Applicable to a host system, the host system including a rewritable non-volatile memory module, the training method comprising: executing a training procedure for the machine learning model, wherein at an iteration of a period of the training procedure, transient data and backtracking data generated by the iteration are stored in the rewritable non-volatile memory module; as well as If an exception occurs in the host system and the iteration is interrupted, the transient data and the backtrace data are read from the rewritable non-volatile memory module, the stage of the iteration is determined according to the backtrace data, and the stage is executed according to the transient data.
2. The training method according to claim 1, characterized in that The iteration includes forward propagation, backward propagation, and update phases, wherein the step of storing the transient data and the backtracking data generated by the iteration in the rewritable non-volatile memory module includes: When the forward propagation is completed, the output of the neuron in the machine learning model is obtained, the transient data is set to include the output of the neuron, the backtracking data is set to indicate that the forward propagation has been completed, and the output of the neuron and the backtracking data are written to the rewritable non-volatile memory module.
3. The training method according to claim 2, characterized in that The steps of determining the phase of the iteration according to the backtracking data and executing the phase according to the transient data include: Setting the stage to the backpropagation according to the backtracking data; and The output and a plurality of weights of the neuron are read from the rewritable non-volatile memory module, and the back propagation is re-executed according to the output and the plurality of weights of the neuron.
4. The training method according to claim 1, characterized in that The iteration includes forward propagation, backward propagation, and update phases, and the step of storing the transient data and the backtracking data generated by the iteration in the rewritable non-volatile memory module includes: When the back propagation is completed, the transient data is set to include a gradient, the backtracking data is set to indicate that the back propagation has been completed, and the gradient and the backtracking data are written into the rewritable non-volatile memory module.
5. The training method according to claim 4, characterized in that The steps of determining the phase of the iteration according to the backtracking data and executing the phase according to the transient data include: Setting the phase as the update phase according to the backtracking data; and The gradient and the weights are read from the rewritable non-volatile memory module, and the update phase is re-executed according to the gradient and the weights.
6. The training method according to claim 4, characterized in that The machine learning model includes multiple layers, and the step of storing the transient data and the backtracking data generated by the iteration in the rewritable non-volatile memory module further includes: After updating the first layer of the multiple layers in the update phase, the transient data is set to also include multiple updated weights of the first layer, the backtracking data is set to indicate that the first layer has been updated, and the multiple updated weights and the backtracking data are written to the rewritable non-volatile memory module.
7. The training method according to claim 6, characterized in that The steps of determining the phase of the iteration according to the backtracking data and executing the phase according to the transient data include: setting the stage to a second layer of the plurality of layers according to the traceback data, wherein the second layer is different from the first layer; and The gradient and a plurality of weights of the second layer are read from the rewritable non-volatile memory module, and the plurality of weights of the second layer are updated according to the gradient.
8. The training method according to claim 1, characterized in that The iteration includes forward propagation, backward propagation, and update phases, and the step of storing the transient data and the backtracking data generated by the iteration in the rewritable non-volatile memory module includes: When the update phase is completed, the transient data is set to include multiple updated weights and updated optimization parameters, the backtracking data is set to indicate that the back propagation has been completed, and the multiple updated weights, the updated optimization parameters and the backtracking data are written to the rewritable non-volatile memory module.
9. The training method according to claim 8, characterized in that Also includes: If the forward propagation of the subsequent iteration is interrupted, reading the updated weights and the updated optimization parameters from the rewritable non-volatile memory module; as well as The subsequent iteration is re-performed based on the plurality of updated weights and the updated optimization parameters, wherein the subsequent iteration is performed after the iteration.
10. A host system, characterized in that: Include: a rewritable non-volatile memory module; and A processor is electrically connected to the rewritable non-volatile memory module and is configured to perform a plurality of steps: executing a training procedure for a machine learning model, wherein at an iteration of a period of the training procedure, transient data and backtracking data generated by the iteration are stored in the rewritable non-volatile memory module; as well as If an exception occurs in the host system and the iteration is interrupted, the transient data and the backtrace data are read from the rewritable non-volatile memory module, the stage of the iteration is determined according to the backtrace data, and the stage is executed according to the transient data.
11. The host system according to claim 10, wherein: The iteration includes forward propagation, backward propagation, and update phases, wherein the step of storing the transient data and the backtracking data generated by the iteration in the rewritable non-volatile memory module includes: When the forward propagation is completed, the output of the neuron in the machine learning model is obtained, the transient data is set to include the output of the neuron, the backtracking data is set to indicate that the forward propagation has been completed, and the output of the neuron and the backtracking data are written to the rewritable non-volatile memory module.
12. The host system according to claim 11, wherein: The steps of determining the phase of the iteration according to the backtracking data and executing the phase according to the transient data include: Setting the stage to the backpropagation according to the backtracking data; and The output and a plurality of weights of the neuron are read from the rewritable non-volatile memory module, and the back propagation is re-executed according to the output and the plurality of weights of the neuron.
13. The host system according to claim 10, wherein: The iteration includes forward propagation, backward propagation, and update phases, and the step of storing the transient data and the backtracking data generated by the iteration in the rewritable non-volatile memory module includes: When the back propagation is completed, the transient data is set to include a gradient, the backtracking data is set to indicate that the back propagation has been completed, and the gradient and the backtracking data are written into the rewritable non-volatile memory module.
14. The host system according to claim 13, wherein: The steps of determining the phase of the iteration according to the backtracking data and executing the phase according to the transient data include: Setting the phase as the update phase according to the backtracking data; and The gradient and the weights are read from the rewritable non-volatile memory module, and the update phase is re-executed according to the gradient and the weights.
15. The host system according to claim 13, wherein: The machine learning model includes multiple layers, and the step of storing the transient data and the backtracking data generated by the iteration in the rewritable non-volatile memory module further includes: After updating the first layer of the multiple layers in the update phase, the transient data is set to also include multiple updated weights of the first layer, the backtracking data is set to indicate that the first layer has been updated, and the multiple updated weights and the backtracking data are written to the rewritable non-volatile memory module.
16. The host system according to claim 15, wherein: The steps of determining the phase of the iteration according to the backtracking data and executing the phase according to the transient data include: setting the stage to a second layer of the plurality of layers according to the traceback data, wherein the second layer is different from the first layer; and The gradient and a plurality of weights of the second layer are read from the rewritable non-volatile memory module, and the plurality of weights of the second layer are updated according to the gradient.
17. The host system according to claim 10, wherein: The iteration includes forward propagation, backward propagation, and update phases, and the step of storing the transient data and the backtracking data generated by the iteration in the rewritable non-volatile memory module includes: When the update phase is completed, the transient data is set to include multiple updated weights and updated optimization parameters, the backtracking data is set to indicate that the back propagation has been completed, and the multiple updated weights, the updated optimization parameters and the backtracking data are written to the rewritable non-volatile memory module.
18. The host system according to claim 17, wherein: The multiple steps also include: If the forward propagation of the subsequent iteration is interrupted, reading the updated weights and the updated optimization parameters from the rewritable non-volatile memory module; and The subsequent iteration is re-performed based on the plurality of updated weights and the updated optimization parameters, wherein the subsequent iteration is performed after the iteration.