Gate driving circuit, driving method of display panel and display panel

Abstract

The embodiment of the invention provides a gate driving circuit, a driving method of a display panel and the display panel, the gate driving circuit comprises a plurality of cascaded gate driving sub-circuits, each gate driving sub-circuit correspondingly controls a row of sub-pixels, and each gate driving sub-circuit comprises a pull-up module, a pull-down module and an output control module. The pull-up module controls the potential of a first node according to a first level transmission signal and a clock signal; the pull-down module controls the potential of the first node according to a preset low potential and a second level transmission signal; and the output control module outputs a corresponding driving signal to the corresponding sub-pixel through the output port according to the control signal, a preset low potential and the potential of the first node. Through the setting, the problems of high power consumption and poor cruising ability of the intelligent equipment with the high-refresh-rate display panel are at least solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit, a driving method for a display panel, and a display panel. Background Art

[0002] At present, screens with high refresh rates have become standard for mid- to high-end smart devices, but high resolution and high refresh rates also bring high power consumption, resulting in high power consumption and poor battery life for smart devices with high refresh rate display panels. Summary of the invention

[0003] The embodiments of the present application provide a gate driving circuit, a display panel driving method and a display panel, so as to at least solve the problem that a smart device with a high refresh rate display panel has high power consumption and poor battery life.

[0004] On the one hand, an embodiment of the present application provides a gate driving circuit, comprising a plurality of cascaded gate driving sub-circuits, each of which controls a row of sub-pixels, and the Nth-level gate driving sub-circuit comprises: a pull-up module, which is connected to a first-level transmission signal and a clock signal and connected to a first node, and the pull-up module is configured to control the potential of the first node according to the first-level transmission signal and the clock signal; wherein the first-level transmission signal is a scanning signal output by the NKth-level gate driving sub-circuit, N>K>0; a pull-down module, which is connected to a preset low potential and a second-level transmission signal and connected to the first node, and the pull-down module is configured to control the potential of the first node according to the preset low potential and the second-level transmission signal; wherein the second-level transmission signal is a scanning signal output by the N+Mth-level gate driving sub-circuit, M>0; and an output control module, which is connected to a control signal and the preset low potential and connected to the first node and an output port, and the output control module is configured to output a driving signal to the sub-pixel corresponding to the gate driving sub-circuit through the output port according to the control signal, the preset low potential and the potential of the first node.

[0005] In some embodiments, the output control module is also configured to control the output port to output a preset low potential to the pixel row corresponding to the gate drive subcircuit when the control signal is a preset high potential, and to control the output port to output the potential of the first node to the pixel row corresponding to the gate drive subcircuit when the control signal is a preset low potential.

[0006] In some embodiments, the output control module includes: a first transistor, including a control electrode connected to the first node, a first electrode connected to the first node, and a second electrode connected to the second node; a second transistor, including a control electrode connected to the second node, a first electrode connected to the first node, and a second electrode connected to the output port; a third transistor, including a control electrode connected to the control signal, a first electrode connected to the second node, and a second electrode connected to the preset low potential; and a fourth transistor, including a control electrode connected to the control signal, a first electrode connected to the output port, and a second electrode connected to the preset low potential.

[0007] In some embodiments, within a first time t1, the gate driving sub-circuits of the kth to mth levels are all connected to the first type of control signal, and the gate driving sub-circuits of the m+1th to nth levels are all connected to the first type of control signal; within a second time t2, the gate driving sub-circuits of the kth to mth levels are all connected to the first type of control signal, and the gate driving sub-circuits of the m+1th to nth levels are all connected to the second type of control signal; wherein, n>m>k, t1>0, t2>0, one of the first type of control signal and the second type of control signal is a preset high potential, and the other is a preset low potential.

[0008] In some embodiments, within a first time t1, the gate driving sub-circuits from level n+1 to level x are all connected to the control signal of the first type; within a second time t2, the gate driving sub-circuits from level n+1 to level x are all connected to the control signal of the first type; wherein x>n.

[0009] In some embodiments, within the third time t3, the gate driving sub-circuits of levels k to m are all connected to the control signal of the first type, the gate driving sub-circuits of levels m+1 to n are all connected to the control signal of the second type, and the gate driving sub-circuits of levels n+1 to x are all connected to the control signal of the second type; wherein, t3>0.

[0010] On the other hand, an embodiment of the present application also provides a method for driving a display panel, wherein the display panel includes a plurality of cascaded gate driving sub-circuits, each of the gate driving sub-circuit corresponding to controlling a row of sub-pixels, and the method for driving the display panel includes: the gate driving sub-circuit generates a potential of a first node based on a first-level transmission signal, a second-level transmission signal, a clock signal and a preset low potential; and outputs a driving signal to the pixel row corresponding to the gate driving sub-circuit based on the potential of the first node and the control signal.

[0011] In some embodiments, generating a drive signal based on the potential of the first node and a control signal and outputting it to the pixel row corresponding to the gate drive subcircuit includes: when the control signal is a preset high potential, outputting a preset low potential to the pixel row corresponding to the gate drive subcircuit.

[0012] In some embodiments, generating a drive signal based on the potential of the first node and a control signal and outputting it to the pixel row corresponding to the gate drive subcircuit includes: when the control signal is a preset low potential, outputting the potential of the first node to the pixel row corresponding to the gate drive subcircuit.

[0013] In some embodiments, outputting a drive signal to a pixel row corresponding to the gate drive subcircuit according to the potential of the first node and the control signal includes: within a first time t1, inputting the first type of control signal to the kth to mth gate drive subcircuits, and inputting the first type of control signal to the m+1th to nth gate drive subcircuits, so as to output the first type of drive signal to the kth to nth pixel rows; within a second time t2, inputting the first type of control signal to the kth to mth gate drive subcircuits, so as to output the first type of drive signal to the kth to mth pixel rows; inputting the second type of control signal to the m+1th to nth gate drive subcircuits, so as to output the second type of drive signal to the m+1th to nth pixel rows; wherein, n>m>k, t1>0, t2>0, and one of the first type of control signal and the second type of control signal is a preset high potential, and the other is a preset low potential.

[0014] In some embodiments, within a first time t1, the first type of control signal is input to the gate driving sub-circuit of the n+1th to xth levels to output the first type of driving signal to the n+1th to xth pixel rows; within a second time t2, the first type of control signal is input to the gate driving sub-circuit of the n+1th to xth levels to output the first type of driving signal to the n+1th to xth pixel rows; wherein, x>n.

[0015] In some embodiments, within the third time t3, the first type of control signal is input to the kth to mth level gate driver subcircuits to output the first type of drive signal to the kth to mth pixel rows; the second type of control signal is input to the m+1th to nth level gate driver subcircuits to output the second type of drive signal to the m+1th to nth pixel rows; and the second type of control signal is input to the n+1th to xth level gate driver subcircuits to output the second type of drive signal to the n+1th to xth pixel rows; wherein, t3>0.

[0016] On the other hand, another embodiment of the present application further provides a display panel, comprising the gate driving circuit described in any of the above embodiments.

[0017] The beneficial effects provided by the embodiments of the present application include at least:

[0018] The embodiment of the present application provides a gate driving circuit, a driving method of a display panel and a display panel, wherein the gate driving circuit includes a plurality of cascaded gate driving subcircuits, each gate driving subcircuit corresponding to a row of sub-pixels, and each gate driving subcircuit includes a pull-up module, a pull-down module and an output control module. The pull-up module controls the potential of the first node according to the first-level transmission signal and the clock signal; the pull-down module controls the potential of the first node according to the preset low potential and the second-level transmission signal; the output control module outputs the corresponding driving signal to the corresponding pixel row through the output port according to the control signal, the preset low potential and the potential of the first node. Through the above setting, the output control module can selectively output a valid gate control signal or an invalid gate control signal for a row of pixels, thereby controlling different display areas of the same display panel to have different refresh rates, and by outputting an invalid gate control signal for a display row that does not require a high refresh rate, the refresh rate of the corresponding display row can be reduced, at least solving the problem that the smart device with a high refresh rate display panel has high power consumption and poor battery life, thereby effectively reducing the power consumption of the display panel and extending the battery life of the smart device.

[0019] Other beneficial effects of the embodiments of the present application will be further described in the following specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the structure of a gate driving circuit provided in some embodiments of the present application;

[0021] Figure 2 A schematic diagram of the structure of a gate driving sub-circuit provided in some embodiments of the present application;

[0022] Figure 3 A schematic diagram of the structure of another gate driving sub-circuit provided in some embodiments of the present application;

[0023] Figure 4 A schematic diagram of the structure of another gate driving sub-circuit provided in some embodiments of the present application;

[0024] Figure 5 is a schematic diagram of partitions of a display panel provided in some embodiments of the present application;

[0025] Figure 6 is a timing diagram of a control signal provided in some embodiments of the present application;

[0026] Figure 7 is a schematic diagram of partitioning of another display panel provided in some embodiments of the present application;

[0027] Figure 8 is a timing diagram of another control signal provided in some embodiments of the present application;

[0028] Fig. 9 is a timing diagram of another control signal provided in some embodiments of the present application;

[0029] Fig.10 A flowchart of a method for driving a display panel provided in some embodiments of the present application;

[0030] Fig.11 It is a schematic diagram of the structure of a display panel provided in some embodiments of the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The described technical solutions are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0032] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0033] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0034] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0035] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. As another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of the embodiments of the present application.

[0036] The various embodiments provided in this application are similar, and features in different embodiments may be combined with each other.

[0037] The use of "configured to" in the embodiments of the present application is meant to be open and inclusive language, which does not exclude devices adapted for or configured to perform additional tasks or steps.

[0038] The order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0039] In order to solve the problem of high power consumption and poor battery life of smart devices with high refresh rate display panels, an embodiment of the present application provides a gate drive circuit, including multiple cascaded gate drive sub-circuits. For the sake of simple description, the following signal ports and corresponding received or transmitted signals are described using the same symbols, for example, the clock signal terminal and the clock signal are both represented by CK, the first node and the first node potential are both represented by G(N), and the output port and the output drive signal are both represented by G(N)-AA.

[0040] Figure 1 Schematic diagram of a gate drive circuit provided in some embodiments of the present application. Figure 1As shown, an embodiment of the present application provides a gate drive circuit GM, the gate drive circuit GM includes a plurality of cascaded gate drive sub-circuits GA and a frequency division control line CL for transmitting a control signal Ctr to the plurality of gate drive sub-circuits GA, the plurality of gate drive sub-circuits GA are electrically connected to a plurality of clock lines CKL1 to CKL8, and the plurality of gate drive sub-circuits GA are configured to output a scan signal Nscan to a corresponding pixel row as a gate drive signal, and at the same time output to an input terminal STV of a corresponding gate drive sub-circuit as an input signal or output to a pull-down signal control terminal PD of a corresponding gate drive sub-circuit as a pull-down control signal. For example Figure 1 As shown, the scan signal Nscan 1 output by the first-stage gate driving sub-circuit is the input signal of the fifth-stage gate driving sub-circuit GA, and the scan signal Nscan 5 output by the fifth-stage gate driving sub-circuit GA is the pull-down control signal of the first-stage gate driving sub-circuit. Figure 1 The input signal of the Nth gate driving sub-circuit shown in FIG. 1 is the scanning signal output by the N-4th gate driving sub-circuit. Therefore, the input signals of the first 4 gate driving sub-circuits are the frame start signal stv.

[0041] It should be noted that Figure 1 The frequency division control line CL shown in the figure is connected to multiple gate drive sub-circuits GA respectively, which is an exemplary display. In practical applications, since the potentials of the control signals Ctr connected to different gate drive sub-circuits are different, each level of gate drive sub-circuit can be connected to an independent frequency division control line CL to obtain an independent control signal Ctr, thereby controlling the refresh frequency of each row of pixels. It is also possible to set the partitions of the display screen according to different refresh frequencies. For example, rows 1 to 100 share the same frequency division control line CL1, rows 101 to 1100 share the same frequency division control line CL2, and rows 1101 to 1200 share the same frequency division control line CL3. Each level of gate drive sub-circuit is connected to an independent frequency division control line CL, which can more flexibly control the refresh frequency of each pixel row. The partitions share a frequency division control line CL, which can effectively save the area of ​​the non-display area of ​​the panel.

[0042] Figure 2 Schematic diagram of a gate drive subcircuit provided in some embodiments of the present application. Figure 2 As shown, the gate driving sub-circuit GA of the Nth stage is taken as an example for exemplary description. The gate driving sub-circuit GA includes a pull-up module 1211 , a pull-down module 1212 and an output control module 1213 .

[0043] The pull-up module 1211 is connected to the first-level transmission signal G (NK) and the CK clock signal, and is connected to the first node G (N). The pull-up module 1211 is configured to control the potential of the first node according to the first-level transmission signal G (NK) and the preset high potential CK; wherein the first-level transmission signal G (NK) comes from the NKth level gate drive sub-circuit, and N>K>0.

[0044] The pull-down module 1212 is connected to a preset low potential VSS and a second-level transmission signal G(N+M), and is connected to the first node G(N). The pull-down module 1212 is configured to control the potential of the first node G(N) according to the preset low potential VSS and the second-level transmission signal G(N+M); wherein the second-level transmission signal G(N+M) comes from the N+Mth-level gate driving sub-circuit, and M>0.

[0045] The output control module 1213 receives the control signal Ctr and the preset low potential VSS, and connects the first node G(N) and the output port G(N)-AA. The output control module 1213 is configured to output the corresponding driving signal to the corresponding sub-pixel through the output port G(N)-AA according to the control signal Ctr, the preset low potential VSS and the potential G(N) of the first node.

[0046] Through the above settings, the output control module 1213 can selectively output a valid gate control signal or an invalid gate control signal for a certain row or several rows of sub-pixels, thereby controlling different display areas of the same display panel to have different refresh rates, at least solving the problem of high power consumption and poor battery life of smart devices with high refresh rate display panels. Specifically, when the control signal Ctr is high, the output port G(N)-AA outputs a preset low potential VSS to the pixel row corresponding to the gate drive subcircuit, and when the control signal Ctr is low, the output port G(N)-AA outputs the potential G(N) of the first node to the pixel row corresponding to the gate drive subcircuit, thereby controlling different display areas of the same display panel to have different refresh rates. By outputting an invalid gate control signal for display rows that do not require a high refresh rate, the refresh rate of the corresponding display row can be reduced, thereby effectively reducing the power consumption of the display panel and extending the battery life of the smart device.

[0047] It should be noted that the realization of each unit and control switch in the gate drive circuit can be a single transistor, a combination of multiple transistors, a capacitor, or a combination of a transistor and a capacitor. The transistors used in all embodiments of the present application can be thin film transistors (TFT), field effect transistors (MOS), or other devices with the same characteristics, and the embodiments of the present application are not limited to this.

[0048] Exemplarily, the transistor may be a TFT. The TFT may be manufactured using an a-Si process, an oxide semiconductor process, a low temperature polysilicon (LTPS) process, or a high temperature polysilicon (HTPS) process. The embodiments of the present application are not limited thereto.

[0049] The embodiments of the present application do not limit the type of transistor. The transistor may be an N-type transistor, or a P-type transistor, or an enhancement-type transistor, or a depletion-type transistor. In the embodiments of the present application, the present application is exemplarily described by taking all transistors as N-type transistors as an example. The N-type transistor is turned on by a high-level voltage signal and turned off by a low-level voltage signal; that is, the operating voltage of the N-type transistor is a high-level voltage, and the turn-off voltage is a low-level voltage.

[0050] In the embodiments of the present application, the gate of the transistor is the control electrode. At the same time, in order to distinguish the two electrodes of the transistor other than the gate, one of the electrodes is directly described as the first electrode and the other electrode is the second electrode. At this time, the first electrode of the transistor can be one of the source and the drain of the transistor, and the second electrode can be the other of the source and the drain of the transistor. Since the source and the drain of the transistor can be symmetrical in structure, the source and the drain can be indistinguishable in structure.

[0051] The capacitor in the embodiment of the present application can be a capacitor device made separately through a process, for example, a capacitor device is realized by making a special capacitor electrode, and each capacitor electrode (first plate and second plate) of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc. The capacitor can also be a parasitic capacitor between transistors, or realized by the transistor itself and other devices and circuits, or by using the parasitic capacitor between the circuits of the circuit itself.

[0052] Each of the above transistors may also include at least one switch connected in parallel with each of the transistors. The embodiments of the present application are merely examples of the pixel driving circuit and the gate driving circuit, and other structures with the same functions as the pixel driving circuit and the gate driving circuit are not described one by one, but should all fall within the protection scope of the present application.

[0053] The “first node”, “second node”, etc. in the embodiments of the present application do not represent actual existing components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0054] Figure 3 FIG. 1 is a schematic diagram of the structure of another gate driving subcircuit provided in some embodiments of the present application. Figure 3 As shown, in some embodiments, the output control module 1213 is also configured to control the output port G(N)-AA to output a preset low potential to the pixel row corresponding to the gate driver subcircuit GA when the control signal Ctr is a preset high potential, and, when the control signal Ctr is a preset low potential, control the output port G(N)-AA to output the potential G(N) of the first node to the pixel row corresponding to the gate driver subcircuit GA.

[0055] Continue to refer to Figure 3 As shown, in some embodiments, the output control module 1213 includes: a first transistor T1, including a control electrode connected to the first node G(N), a first electrode connected to the first node G(N), and a second electrode connected to the second node A; a second transistor T2, including a control electrode connected to the second node A, a first electrode connected to the first node G(N), and a second electrode connected to the output port G(N); a third transistor T3, including a control electrode connected to the control signal Ctr, a first electrode connected to the second node A, and a second electrode connected to a preset low potential VSS; and a fourth transistor T4, including a control electrode connected to the control signal Ctr, a first electrode connected to the output port G(N)-AA, and a second electrode connected to the preset low potential VSS.

[0056] The gate drive subcircuit provided in the embodiment of the present application is equivalent to determining whether to output a valid G(N) signal through the output control module 1213 before the gate control signal G(N) is output to the sub-pixel corresponding to the AA area. The control signal Ctr is connected to the gate drive subcircuit GA through the frequency division signal line CL. The frequency division control line CL can be connected to the timing controller TCON or the system on chip SIC. By setting the control signal Ctr of a certain row or several rows, it is possible to control whether the gate control signal input to the sub-pixel corresponding to the AA area is a valid G(N) signal.

[0057] Continue to refer to Figure 3 As shown, when the Ctr signal input into the gate driving subcircuit of a row of sub-pixels is at a low level, the third transistor T3 and the fourth transistor T4 are turned off, and the low potential VSS cannot be transmitted to the output port G(N)-AA through the third transistor T3 or the fourth transistor T4, and the potential G(N) of the first node can be transmitted to the output port G(N)-AA, that is, the G(N)-AA signal received by the corresponding sub-pixel is consistent with the potential G(N) of the first node, and the sub-pixel executes the refresh of the data signal.

[0058] When the Ctr signal input into the gate driving subcircuit of a row of sub-pixels is at a high level, the third transistor T3 and the fourth transistor T4 are turned on, and the low potential VSS can be transmitted to the output port G(N)-AA through the third transistor T3 or the fourth transistor T4. The potential G(N) of the first node cannot be normally transmitted to the output port G(N)-AA, that is, the G(N)-AA signal received by the corresponding sub-pixel is a continuous low level, and the sub-pixel does not refresh the data signal.

[0059] It should be noted that the pull-up module and the pull-down module can be implemented by a conventional GOA (Gate-driver on array) circuit, such as 7T2C, 9T2C or 13T2C, etc., which can be selected according to actual needs, and the embodiments of the present application do not limit this.

[0060] Figure 4 FIG. 1 is a schematic diagram of the structure of another gate driving subcircuit provided in some embodiments of the present application. Figure 4 As shown, the gate driving sub-circuit GA of the Nth stage includes a pull-up module 1211, a pull-down module 1212, an output control module 1213, an inverting module 1214, a pull-down maintaining module 1215, and two reset transistors T6 and T15.

[0061] The pull-up module 1211 includes a fifth transistor T5 and a sixteenth transistor T16, wherein the control electrode of the fifth transistor T5 is connected to the first electrode and the first-stage transmission signal G(N-4), and the second electrode is connected to the third node Q(N); the control electrode of the sixteenth transistor T16 is connected to the third node Q(N), the first electrode is connected to the clock signal CKN, and the second electrode is connected to the first node G(N). The pull-up module 1211 is used to turn on the sixteenth transistor T16 when the potential of the second node Q(N) is high, and output the high potential to the first node G(N) when the clock signal CKN is high.

[0062] The pull-down module 1212 includes a thirteenth transistor T13 and a fourteenth transistor T14, wherein the control electrode of the thirteenth transistor T13 is connected to the second-stage transmission signal G(N+6), the first electrode is connected to the third node Q(N), and the second electrode is connected to the preset low potential VSS; the control electrode of the fourteenth transistor T14 is connected to the third-stage transmission signal G(N+4), the first electrode is connected to the first node G(N), and the second electrode is connected to the preset low potential VSS. The thirteenth transistor T13 is used to pull down the potential of the third node Q(N), and the fourteenth transistor T14 is used to pull down the potential of the first node G(N).

[0063] The inversion module 1214 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10. The control electrode of the seventh transistor T7 is connected to its first electrode and a preset high potential VGH, and the second electrode is connected to the first electrode of the eighth transistor T8; the control electrode of the eighth transistor T8 is connected to the third node Q(N), the first electrode is connected to the second electrode of the seventh transistor T7, and the second electrode is connected to the preset low potential VSS; the control electrode of the ninth transistor T9 is connected to the first electrode of the eighth transistor T8, the first electrode is connected to the first electrode of the seventh transistor T7, and the second electrode is connected to the fourth node P(N); the control electrode of the tenth transistor T10 is connected to the third node Q(N), the first electrode is connected to the fourth node P(N), and the second electrode is connected to the preset low potential VSS. The inversion module 1214 is used to invert the potentials of the fourth node P(N) and the third node Q(N).

[0064] The pull-down maintenance module 1215 includes an eleventh transistor T11 and a twelfth transistor T12, wherein the control electrode of the eleventh transistor T11 is connected to the fourth node P(N), the first electrode is connected to the third node Q(N), and the second electrode is connected to the preset low potential VSS; the control electrode of the twelfth transistor T12 is connected to the fourth node P(N), the first electrode is connected to one end of the bootstrap capacitor C, and the second electrode is connected to the preset low potential VSS. The pull-down maintenance module 1215 is used to maintain the third node Q(N) and voltage stability. The two ends of the bootstrap capacitor C are respectively connected to the third node Q(N) and the first node G(N), and are used to couple the voltage between the third node Q(N) and the first node G(N).

[0065] The sixth transistor T6 and the fifteenth transistor T15 are reset transistors, and the potentials of the third node Q(N) and the first node G(N) can be reset by one key by accessing a reset signal.

[0066] In some embodiments, within a first time t1, the gate driving sub-circuits of the kth to mth levels are all connected to the first type of control signal, and the gate driving sub-circuits of the m+1th to nth levels are all connected to the first type of control signal; within a second time t2, the gate driving sub-circuits of the kth to mth levels are all connected to the first type of control signal, and the gate driving sub-circuits of the m+1th to nth levels are all connected to the second type of control signal; wherein, n>m>k, t1>0, t2>0, one of the first type of control signal and the second type of control signal is a preset high potential, and the other is a preset low potential.

[0067] Figure 5 is a schematic diagram of partitions of a display panel provided in some embodiments of the present application, Figure 6 is a timing diagram of a control signal provided in some embodiments of the present application. Figure 5 and Figure 6As shown, the display area (AA) of the display panel can be divided into two display partitions with different refresh frequencies, for example, the 1st to 100th row of sub-pixels are a dynamic display area with a refresh frequency of 120HZ, and the 101st to 1200th row of sub-pixels are a static display area with a refresh frequency of 60HZ. The 1st to 100th level gate drive sub-circuit is connected to the first control signal Ctr 1, and the 101st to 1200th level gate drive sub-circuit is connected to the second control signal Ctr2. During the first time t1, the first control signal Ctr 1 is at a low level, the gate driver sub-circuit of rows 1 to 100 outputs a valid G(N)-AA, the second control signal Ctr 2 is at a low level, the gate driver sub-circuit of rows 101 to 1200 outputs a valid G(N)-AA; during the second time t2, the first control signal Ctr 1 is at a low level, the gate driver sub-circuit of rows 1 to 100 outputs a valid G(N)-AA, the second control signal Ctr 2 is at a high level, the gate driver sub-circuit of rows 101 to 1200 outputs a preset low potential, and data refresh is not performed.

[0068] In some embodiments, the 1st to 100th rows of sub-pixels can also be used as a static display area with a refresh frequency of 30 Hz, and the 101st to 1200th rows of sub-pixels can be used as a dynamic display area with a refresh frequency of 100 Hz. The specific partitions and corresponding refresh frequencies can be set according to the actual application scenario, and the embodiments of the present application are not limited to this.

[0069] In some embodiments, within a first time t1, the n+1th to xth gate driver sub-circuits are all connected to a first type of control signal; within a second time t2, the n+1th to xth gate driver sub-circuits are all connected to a first type of control signal; wherein x>n.

[0070] Figure 7 is a schematic diagram of partitioning of another display panel provided in some embodiments of the present application, Figure 8 is a timing diagram of another control signal provided in some embodiments of the present application. Figure 7 and Figure 8As shown, the display area (AA) of the display panel can be divided into three display partitions with different refresh frequencies, for example, the 1st to 100th row of sub-pixels is a dynamic display area with a refresh frequency of 120HZ, the 101st to 1100th row of sub-pixels is a static display area with a refresh frequency of 60HZ, and the 1101st to 1200th row of sub-pixels is a dynamic display area with a refresh frequency of 120HZ. The 1st to 100th level gate driving sub-circuit is connected to the first control signal Ctr 1, the 101st to 1100th level gate driving sub-circuit is connected to the second control signal Ctr 2, and the 1101st to 1200th level gate driving sub-circuit is connected to the third control signal Ctr 3. During the first time t1, the first control signal Ctr 1 is at a low level, and the gate driving sub-circuits of the 1st to 100th levels output valid G(N)-AA, the second control signal Ctr 2 is at a low level, and the gate driving sub-circuits of the 101st to 1100th levels output valid G(N)-AA, and the third control signal Ctr 3 is at a low level, and the gate driving sub-circuits of the 1101st to 1200th levels output valid G(N)-AA; during the second time t2, the first control signal Ctr 1 is at a low level, and the gate driving sub-circuits of the 1st to 100th levels output valid G(N)-AA, the second control signal Ctr 2 is at a high level, and the gate driving sub-circuits of the 101st to 1200th levels output a preset low potential, and data refresh is not performed, and the third control signal Ctr 1 is at a low level, and the gate driving sub-circuits of the 1st to 100th levels output valid G(N)-AA.

[0071] Figure 8 In the timing sequence shown, the refresh frequency of the sub-pixels in the 1st to 100th rows is the same as the refresh frequency of the 1101st to 1200th rows. The timing control of the specific control signal can be Figure 8 On the contrary, for example, the sub-pixels in rows 1 to 100 are the static display area with a refresh frequency of 60 Hz, the sub-pixels in rows 101 to 1100 are the dynamic display area with a refresh frequency of 120 Hz, and the sub-pixels in rows 1101 to 1200 are the static display area with a refresh frequency of 60 Hz. The corresponding first control signal Ctr 1 is low level in the first time t1 and high level in the second time t2, the second control signal Ctr 2 is low level in both the first time t1 and the second time t2, and the third control signal Ctr3 is low level in the first time t1 and high level in the second time t2.

[0072] In some embodiments, within the third time t3, the kth to mth level gate driver sub-circuits are all connected to the first type of control signal, the m+1th to nth level gate driver sub-circuits are all connected to the second type of control signal, and the n+1th to xth level gate driver sub-circuits are all connected to the second type of control signal; wherein, t3>0.

[0073] Fig. 9is a timing diagram of another control signal provided in some embodiments of the present application. Fig. 9 As shown, the display panel can be divided into three partitions, and the refresh frequencies of the three partitions are different. The first to 100th level gate driving subcircuits are connected to the first control signal Ctr 1, the 101st to 1100th level gate driving subcircuits are connected to the second control signal Ctr 2, and the 1101st to 1200th level gate driving subcircuits are connected to the third control signal Ctr 3. In the first time t1, the second time t2 and the third time t3, the first control signal Ctr 1 is low level, and the 1st to 100th level gate driving subcircuits always output valid G(N)-AA. The second control signal Ctr 2 is low level in the first time t1, the 101st to 1100th level gate driving subcircuits output valid G(N)-AA, and is high level in the second time t2 and the third time t3, the 101st to 1200th level gate driving subcircuits output a preset low potential, and do not perform data refresh. The third control signal Ctr 3 is at a low level during the first time t1, and the gate driver sub-circuit of the 1101st to 1200th levels outputs a valid G(N)-AA; it is at a high level during the second time t2, and the gate driver sub-circuit of the 1101st to 1200th levels outputs a preset low potential and does not perform data refresh; it is at a low level during the third time t3, and the gate driver sub-circuit of the 1101st to 1200th levels outputs a valid G(N)-AA.

[0074] Fig.10 Flow chart of a method for driving a display panel provided in some embodiments of the present application. Fig.10 As shown, another embodiment of the present application further provides a method for driving a display panel, which is implemented by the gate driving circuit in any of the above embodiments, and the contents that have been described will not be repeated here.

[0075] The above driving method includes:

[0076] Step S1001, the gate driving sub-circuit generates a potential of a first node according to a first-level transmission signal, a second-level transmission signal, a clock signal and a preset low potential;

[0077] Step S1002 , outputting a driving signal to the pixel row corresponding to the gate driving sub-circuit according to the potential of the first node and the control signal.

[0078] In some embodiments, the above step S1002 can be implemented by the following steps:

[0079] S11, when the control signal is a preset high potential, outputting a preset low potential to the pixel row corresponding to the gate driving sub-circuit.

[0080] In some embodiments, the above step S1002 can be implemented by the following steps:

[0081] S21, when the control signal is a preset low potential, outputting the potential of the first node to the pixel row corresponding to the gate driving sub-circuit.

[0082] In some embodiments, the above step S1002 can be implemented by the following steps:

[0083] In the first time t1, a first type of control signal is input to the kth to mth gate driving sub-circuits, and a first type of control signal is input to the m+1th to nth gate driving sub-circuits, so as to output the first type of driving signal to the kth to nth pixel rows;

[0084] In the second time t2, the control signal of the first type is input to the kth to mth gate driving sub-circuits to output the driving signal of the first type to the kth to mth pixel rows; the control signal of the second type is input to the m+1th to nth gate driving sub-circuits to output the driving signal of the second type to the m+1th to nth pixel rows;

[0085] Among them, n>m>k, t1>0, t2>0, one of the first type of control signal and the second type of control signal is a preset high potential, and the other is a preset low potential.

[0086] In some embodiments, within a first time t1, the first type of control signal is input to the n+1th to xth level gate driver sub-circuit to output the first type of drive signal to the n+1th to xth pixel rows; within a second time t2, the first type of control signal is input to the n+1th to xth level gate driver sub-circuit to output the first type of drive signal to the n+1th to xth pixel rows; wherein x>n.

[0087] In some embodiments, within the third time t3, the first type of control signal is input to the kth to mth level gate driver subcircuits to output the first type of drive signal to the kth to mth pixel rows; the second type of control signal is input to the m+1th to nth level gate driver subcircuits to output the second type of drive signal to the m+1th to nth pixel rows; and the second type of control signal is input to the n+1th to xth level gate driver subcircuits to output the second type of drive signal to the n+1th to xth pixel rows; wherein, t3>0.

[0088] Through the above method, according to the potential of the first node and the control signal, a drive signal is output to the pixel row corresponding to the gate drive subcircuit, which can effectively control whether the signal output by each level of the gate drive subcircuit is a valid scanning signal, realize partition control of the display panel, and reduce the refresh rate of some display areas, which at least solves the problem of high power consumption and poor battery life of smart devices with high refresh rate display panels, thereby controlling different display areas of the same display panel to have different refresh rates. For display rows that do not require a high refresh rate, the refresh rate of the corresponding display row can be reduced by outputting an invalid gate control signal, thereby effectively reducing the power consumption of the display panel and extending the battery life of the smart device.

[0089] Fig.11 is a schematic diagram of the structure of a display panel provided in some embodiments of the present application. Fig.11 As shown, another embodiment of the present application further provides a display panel 100, comprising the gate driving circuit GM described in any of the above embodiments. The display panel 100 comprises an effective display area AA and a non-display area NA located around AA, the gate driving circuit GM is arranged in the non-display area NA, and the gate driving circuit GM receives a clock signal and a control signal from a timing controller TCON.

[0090] Another embodiment of the present application further provides a non-transitory computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the steps of the above-mentioned display panel driving method are implemented. The non-transitory computer-readable storage medium has all the beneficial effects of the above-mentioned display panel driving method, and the present application will not repeat them here.

[0091] The computer-readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or component, or any combination thereof, which is not specifically limited in the present application. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0092] In some embodiments of the present application, computer-readable storage media may be any tangible media that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0093] Computer program code for performing the operations of some embodiments of the present application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network (including a local area network (LAN) or a wide area network (WAN)), or it can be connected to an external computer (for example, using an Internet service provider to connect through the Internet).

[0094] In the embodiments of the present application, specific examples are used to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

[0095] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A gate drive circuit, characterized in that: It includes a plurality of cascaded gate driving sub-circuits, each of which controls a row of sub-pixels, and the gate driving sub-circuit of the Nth level includes: A pull-up module is connected to the first-level transmission signal and the clock signal and is connected to the first node, and the pull-up module is configured to control the potential of the first node according to the first-level transmission signal and the clock signal; wherein the first-level transmission signal is a scanning signal output by the gate driving sub-circuit of the NKth level, N>K>0; a pull-down module, connected to a preset low potential and a second-level transmission signal, and connected to the first node, the pull-down module being configured to control the potential of the first node according to the preset low potential and the second-level transmission signal; wherein the second-level transmission signal is a scanning signal output by the gate driving sub-circuit of the N+Mth level, M>0; and An output control module receives a control signal and the preset low potential, and connects the first node and an output port. The output control module is configured to output a drive signal to a pixel row corresponding to the gate drive subcircuit through the output port according to the control signal, the preset low potential and the potential of the first node.

2. The gate driving circuit according to claim 1, characterized in that: The output control module is also configured as: When the control signal is a preset high potential, the output port is controlled to output a preset low potential to the pixel row corresponding to the gate drive subcircuit, and, when the control signal is a preset low potential, the output port is controlled to output the potential of the first node to the pixel row corresponding to the gate drive subcircuit.

3. The gate driving circuit according to claim 2, characterized in that: The output control module comprises: A first transistor including a control electrode connected to the first node, a first electrode connected to the first node, and a second electrode connected to a second node; a second transistor including a control electrode connected to the second node, a first electrode connected to the first node, and a second electrode connected to the output port; A third transistor includes a control electrode connected to the control signal, a first electrode connected to the second node, and a second electrode connected to the preset low potential; and The fourth transistor includes a control electrode connected to the control signal, a first electrode connected to the output port, and a second electrode connected to the preset low potential.

4. The gate driving circuit according to claim 2, characterized in that: In the first time t1, the gate driving sub-circuits of the kth to mth levels are all connected to the control signal of the first type, and the gate driving sub-circuits of the m+1th to nth levels are all connected to the control signal of the first type; In the second time t2, the gate driving sub-circuits of the kth to mth stages are all connected to the control signal of the first type, and the gate driving sub-circuits of the m+1th to nth stages are all connected to the control signal of the second type; Among them, n>m>k, t1>0, t2>0, one of the first type of control signal and the second type of control signal is a preset high potential, and the other is a preset low potential.

5. The gate driving circuit according to claim 4, characterized in that: In the first time t1, the gate driving sub-circuits from level n+1 to level x are all connected to the control signal of the first type; In the second time t2, the gate driving sub-circuits of the n+1th to xth stages are all connected to the control signal of the first type; Wherein, x>n.

6. The gate driving circuit according to claim 5, characterized in that: In the third time t3, the gate driving sub-circuits of the kth to mth levels are all connected to the control signal of the first type, the gate driving sub-circuits of the m+1th to nth levels are all connected to the control signal of the second type, and the gate driving sub-circuits of the n+1th to xth levels are all connected to the control signal of the second type; Among them, t3>0.

7. A method for driving a display panel, characterized in that: The display panel includes a plurality of cascaded gate driving sub-circuits, each of the gate driving sub-circuits correspondingly controls a row of sub-pixels, and the driving method of the display panel includes: The gate driving subcircuit generates a potential of the first node according to the first-level transmission signal, the second-level transmission signal, the clock signal and a preset low potential; According to the potential of the first node and the control signal, a driving signal is output to the pixel row corresponding to the gate driving sub-circuit.

8. The method for driving a display panel according to claim 7, wherein: The step of generating a driving signal according to the potential of the first node and the control signal and outputting the driving signal to the pixel row corresponding to the gate driving sub-circuit comprises: When the control signal is a preset high potential, a preset low potential is output to the pixel row corresponding to the gate driving sub-circuit.

9. The method for driving a display panel according to claim 7, wherein: The step of generating a driving signal according to the potential of the first node and the control signal and outputting the driving signal to the pixel row corresponding to the gate driving sub-circuit comprises: When the control signal is a preset low potential, the potential of the first node is output to the pixel row corresponding to the gate driving sub-circuit.

10. The method for driving a display panel according to claim 7, wherein: The step of outputting a driving signal to a pixel row corresponding to the gate driving sub-circuit according to the potential of the first node and the control signal comprises: In a first time t1, the control signal of the first type is input to the gate driving sub-circuits of the kth to mth levels, and the control signal of the first type is input to the gate driving sub-circuits of the m+1th to nth levels, so as to output the driving signal of the first type to the pixel rows of the kth to nth rows; In the second time t2, the control signal of the first type is input to the gate driving sub-circuit of the kth to mth levels, so as to output the driving signal of the first type to the pixel rows of the kth to mth rows; the control signal of the second type is input to the gate driving sub-circuit of the m+1th to nth levels, so as to output the driving signal of the second type to the pixel rows of the m+1th to nth rows; Among them, n>m>k, t1>0, t2>0, one of the first type of control signal and the second type of control signal is a preset high potential, and the other is a preset low potential.

11. The method for driving a display panel according to claim 10, wherein: The method further comprises: In a first time t1, the control signal of the first type is input to the gate driving sub-circuits of the n+1th to xth levels, so as to output the driving signal of the first type to the pixel rows of the n+1th to xth rows; In the second time t2, the control signal of the first type is input to the gate driving sub-circuits of the n+1th to xth levels, so as to output the driving signal of the first type to the pixel rows of the n+1th to xth rows; Wherein, x>n.

12. The method for driving a display panel according to claim 11, characterized in that: The method further comprises: In the third time t3, the control signal of the first type is input to the gate driving sub-circuit of the kth to mth level, so as to output the driving signal of the first type to the pixel rows of the kth to mth level; the control signal of the second type is input to the gate driving sub-circuit of the m+1th to nth level, so as to output the driving signal of the second type to the pixel rows of the m+1th to nth level; and the control signal of the second type is input to the gate driving sub-circuit of the n+1th to xth level, so as to output the driving signal of the second type to the pixel rows of the n+1th to xth level; Among them, t3>0.

13. A display panel, characterized in that: The gate drive circuit comprises the gate drive circuit as claimed in any one of claims 1 to 6.

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