Pixel circuit, display panel and display device

Abstract

The invention discloses a pixel circuit, a display panel and a display device. The pixel circuit comprises a pulse width adjusting module, an amplitude adjusting module, a light-emitting process control module and a light-emitting element, the pulse width adjusting module is used for outputting a pulse width adjusting signal; the amplitude adjusting module is used for outputting a light-emitting driving signal and controlling the pulse width of the light-emitting driving signal; the light-emitting process control module is used for controlling a transmission path of the light-emitting driving signal to the light-emitting element; a time period in which the pulse width light-emitting signal and the amplitude light-emitting signal are both enable levels is a first time period; in the first time period, the light-emitting process control signal comprises at least one non-enabling level, so that a transmission path of the light-emitting driving signal to the light-emitting element is in a turn-off state, the flicker phenomenon generated when two adjacent display frames are refreshed by human eyes can be weakened, and especially for a low-gray-scale display picture, the display effect of the display frame is improved. The visual effect of human eyes on picture flicker can be improved, and the use experience of the display panel can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit, a display panel and a display device. Background Art

[0002] With the development of display technology, users have higher and higher requirements for display quality. In order to meet the demand for higher definition, the resolution of display panels is getting higher and higher.

[0003] Existing display panels, such as display panels using micro light emitting diodes (MicroLED) or organic light emitting diodes (OLED) as light emitting elements, usually use a combination of pulse width modulation (PWM) and pulse amplitude modulation (PAM) to drive pixels to emit light in order to meet the display requirements of high resolution. When driving the pixels to emit light for display, the pixel driving current is placed in a high current output state through pulse amplitude modulation (PAM), and pulse width modulation (PWM) is used to achieve pulse width modulation, thereby achieving grayscale segmentation.

[0004] For a display panel that uses a combination of pulse width modulation (PWM) and pulse amplitude modulation (PAM), a single pulse is used to drive light emission within a display frame during display, so that the flicker problem still exists in low grayscale conditions, which is not conducive to improving display quality. Summary of the invention

[0005] The present invention provides a pixel circuit, a display panel and a display device, so as to improve the flickering phenomenon of the display panel to human eyes and enhance the display quality of the display panel.

[0006] According to one aspect of the present invention, there is provided a pixel circuit, comprising: a pulse width adjustment module, an amplitude adjustment module, a light emitting process control module and a light emitting element;

[0007] The pulse width modulation module at least receives the pulse width light emission signal for outputting a pulse width modulation signal;

[0008] The amplitude adjustment module is electrically connected to the pulse width adjustment module, the amplitude adjustment module at least receives the amplitude light emitting signal for outputting the light emitting driving signal, and the amplitude adjustment module also receives the pulse width adjustment signal for controlling the pulse width of the light emitting driving signal;

[0009] The light-emitting process control module is at least electrically connected to the amplitude adjustment module; the light-emitting process control module at least receives the light-emitting process control signal, and is used to control the transmission path of the light-emitting drive signal to the light-emitting element;

[0010] The time period in which the pulse width light-emitting signal and the amplitude light-emitting signal are both at the enable level is the first time period; within the first time period, the light-emitting process control signal includes at least one non-enable level, so that the transmission path of the light-emitting drive signal to the light-emitting element is in the off state; the time length of the non-enable level is less than the time length of the first time period.

[0011] According to another aspect of the present invention, a display panel is provided, comprising the above-mentioned pixel circuit.

[0012] According to another aspect of the present invention, a display device is provided, comprising the above-mentioned display panel.

[0013] The pixel circuit provided by the present invention outputs a pulse width modulation signal at least according to a pulse width light-emitting signal through a pulse width modulation module, outputs a light-emitting drive signal at least according to an amplitude light-emitting signal through an amplitude modulation module, and controls the pulse width of the light-emitting drive signal according to the pulse width modulation signal, thereby controlling the light-emitting brightness and light-emitting duration of the light-emitting element. By setting a light-emitting process control module to control the transmission path of the light-emitting drive signal to the light-emitting element at least according to the light-emitting process control signal, the light-emitting element can be controlled to be turned off or emit light during the light-emitting stage of the light-emitting element. By setting the light-emitting process control signal to include at least one non-enable level in a first time period in which both the pulse width light-emitting signal and the amplitude light-emitting signal are enable levels, the light-emitting process control signal can be turned off briefly during the light-emitting stage of a display frame, which will not be captured by the human eye and will not produce a flickering visual effect. In addition, by controlling the light-emitting element to be turned off briefly in the first time period, the flickering phenomenon of the human eye when refreshing two adjacent display frames can be weakened, especially for low-grayscale display images, the visual effect of the human eye on the flickering of the image can be improved, which is conducive to improving the user experience of the display panel.

[0014] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0017] Figure 2 is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0018] Figure 3 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0019] Figure 4 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0020] Figure 5 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0021] Figure 6 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0022] Figure 7 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0023] Figure 8 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0024] Fig. 9 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0025] Fig.10 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0026] Fig.11 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0027] Fig.12 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0028] Fig.13 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0029] Fig.14 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0030] Fig.15 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0031] Fig.16is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0032] Fig.17 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0033] Fig.18 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0034] Fig.19 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0035] Fig. 20 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0036] Fig.21 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention is shown in FIG.

[0037] Fig. 22 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0038] Fig.23 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0040] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0041] As described in the background technology, when preparing a display panel, a display panel that uses a combination of pulse width modulation PWM and pulse amplitude modulation PAM is used. The driving signal used to drive the light-emitting element in a display frame has only one valid pulse. Both pulse width modulation PWM and pulse amplitude modulation PAM are composed of multiple electronic switches to achieve corresponding functions. In low grayscale display, the driving signal outputs a valid pulse for a long time. In the process of driving the light-emitting element to continuously emit light, the electronic switches in pulse width modulation PWM and pulse amplitude modulation PAM will have leakage current, resulting in the driving signal being a valid pulse. The driving current at the start stage will be significantly greater than the driving current at the end, so that the luminous brightness of the light-emitting element in a display frame will gradually decrease, so that when refreshing the display screen of the next frame, there will be obvious flickering, affecting the user's visual experience.

[0042] In order to solve the above technical problems, an embodiment of the present invention provides a pixel circuit, including: a pulse width adjustment module, an amplitude adjustment module, a light-emitting process control module and a light-emitting element; the pulse width adjustment module at least receives a pulse width light-emitting signal for outputting a pulse width adjustment signal; the amplitude adjustment module is electrically connected to the pulse width adjustment module, the amplitude adjustment module at least receives the amplitude light-emitting signal for outputting a light-emitting drive signal, and the amplitude adjustment module also receives the pulse width adjustment signal for controlling the pulse width of the light-emitting drive signal; the light-emitting process control module is at least electrically connected to the amplitude adjustment module; the light-emitting process control module at least receives a light-emitting process control signal for controlling a transmission path of the light-emitting drive signal to the light-emitting element; a time period in which the pulse width light-emitting signal and the amplitude light-emitting signal are both at an enable level is a first time period; within the first time period, the light-emitting process control signal includes at least one non-enable level, so that the transmission path of the light-emitting drive signal to the light-emitting element is in a shut-off state; the time length of the non-enable level is less than the time length of the first time period.

[0043] By adopting the above technical scheme, the pulse width modulation module outputs a pulse width modulation signal at least according to the pulse width light-emitting signal, the amplitude modulation module outputs a light-emitting drive signal at least according to the amplitude light-emitting signal, and the pulse width of the light-emitting drive signal is controlled according to the pulse width modulation signal, so that the light-emitting brightness and light-emitting duration of the light-emitting element can be controlled. By setting the light-emitting process control module to control the transmission path of the light-emitting drive signal to the light-emitting element at least according to the light-emitting process control signal, the light-emitting element can be controlled to be turned off or emit light during the light-emitting stage of the light-emitting element. By setting the light-emitting process control signal to include at least one non-enable level in the first time period in which the pulse width light-emitting signal and the amplitude light-emitting signal are both enable levels, the light-emitting process control signal can be turned off briefly during the light-emitting stage of a display frame, which will not be captured by the human eye and will not produce a flickering visual effect. In addition, by controlling the light-emitting element to be turned off briefly in the first time period, the flickering phenomenon of the human eye when refreshing two adjacent display frames can be weakened, especially for low-grayscale display images, the visual effect of the human eye on the flickering of the image can be improved, which is conducive to improving the user experience of the display panel.

[0044] The above is the core idea of ​​the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention.

[0045] Figure 1 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 1 As shown, the pixel circuit 01 includes: a pulse width modulation module 10, an amplitude modulation module 20, a light emitting process control module 30 and a light emitting element D0; the pulse width modulation module 10 at least receives a pulse width light emitting signal PWM-EM for outputting a pulse width modulation signal; the amplitude modulation module 20 is electrically connected to the pulse width modulation module 10, the amplitude modulation module 20 at least receives an amplitude light emitting signal PAM-EM for outputting a light emitting drive signal, and the amplitude modulation module 20 also receives a pulse width modulation signal for controlling the pulse width of the light emitting drive signal; the light emitting process control module 30 is at least electrically connected to the amplitude modulation module 20; the light emitting process control module 30 at least receives a light emitting process control signal VCT for controlling a transmission path of the light emitting drive signal to the light emitting element D0; the time period in which the pulse width light emitting signal PWM-EM and the amplitude light emitting signal PAM-EM are both at an enable level is a first time period T1; within the first time period T1, the light emitting process control signal DC includes at least one non-enable level, so that the transmission path of the light emitting drive signal to the light emitting element D0 is in a shut-off state; the time length of the non-enable level is less than the time length of the first time period T1.

[0046] Exemplarily, in the embodiment of the present invention, the light emitting element D0 may be, but is not limited to, a micro light emitting diode (Micro Light Emitting Diode, MicroLED) or an organic light emitting diode (Organic Light Emitting Diode, OLED) and other elements, and may be designed according to actual conditions during specific implementation. The anode of the light emitting element D0 is used to receive a light emitting drive signal, and the cathode of the light emitting element D0 is electrically connected to the light emitting element D0. When the voltage of the light emitting drive signal is greater than the conduction threshold of the light emitting element D0, the light emitting element D0 is turned on to emit light.

[0047] Specifically, the pixel circuit 01 generates a light-emitting drive signal under the control of the pulse width modulation module 10 and the amplitude modulation module 20. For a light-emitting element driven by a current mode, the light-emitting drive signal may be a drive current. The pulse width modulation circuit 10 may be used to control the pulse width of the light-emitting drive signal, and the amplitude modulation module 20 may be used to control the pulse amplitude of the light-emitting drive signal. The pulse width modulation circuit 10 at least receives the pulse width light-emitting signal PWM-EM, and can output a pulse width modulation signal at least according to the pulse width light-emitting signal PWM-EM. The amplitude modulation module 20 at least receives the amplitude light-emitting signal PAM-EM, and can output a light-emitting drive signal at least according to the amplitude light-emitting signal PAM-EM, so as to control the light-emitting brightness of the light-emitting element D0. By setting the amplitude modulation module 20 to be electrically connected to the pulse width modulation module 10, the amplitude modulation module 20 can also receive the pulse width modulation signal output by the pulse width modulation module 10, so that the pulse width of the light-emitting drive signal can be controlled according to the pulse width modulation signal, so as to control the light-emitting duration of the light-emitting element D0.

[0048] The light-emitting process control module 30 may be electrically connected between the amplitude adjustment module 20 and the light-emitting element D0, or in other feasible embodiments, the light-emitting process control module 30 may also be electrically connected to other positions that may affect the transmission of the light-emitting drive signal to the light-emitting element D0. Under the control of the light-emitting process control signal VCT, the current path of the light-emitting drive signal may be controlled to be in an on state or an off state, so that the light-emitting drive signal is transmitted to the light-emitting element D0 when the current path is in an on state, and cannot be transmitted to the light-emitting element D0 when the current path is in an off state.

[0049] In a display frame, after the grayscale data is written, the pulse width light emitting signal PWM-EM and the amplitude light emitting signal PAM-EM can be controlled to be at the enable level, so that the amplitude adjustment module 20 can generate a light emitting driving signal for controlling the light emitting element D0 to emit light. Figure 2 is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention, such as Figure 2As shown, the time end when the pulse width light-emitting signal PWM-EM and the amplitude light-emitting signal PAM-EM are both at the enable level V1 can be taken as the first time period T1, and the first time period T1 is the light-emitting stage of the current display frame. In the first time period T1, the light-emitting process control signal VCT can be controlled to include at least one non-enable level V2′, so that the light-emitting process control module 30 is in an open circuit state under the control of the non-enable level V2′ of the light-emitting process control signal VCT, so that the light-emitting driving signal used to control the conduction of the light-emitting element D0 cannot be transmitted to the light-emitting element D0. The time length t2 of the non-enable level V2′ is less than the time length t1 of the first time period T1, so that the light-emitting process control signal VCT maintains the non-enable level V2′ for a shorter time, and maintains the enable level V2 for a longer time, so that the light-emitting element D0 re-emits light after being turned off for a short time. In this way, since the light emitting element D0 is turned off for a short time in the first time period T1, it will not be captured by the human eye and thus will not produce a flickering visual effect. In addition, by controlling the light emitting element D0 to be turned off briefly in the first time period T1, the flickering phenomenon when two adjacent display frames are refreshed by the human eye can be weakened, especially for low grayscale display images, which can improve the visual effect of the flickering image to the human eye and is beneficial to improving the user experience of the display panel.

[0050] Exemplarily, in the first time period T1, the light emitting process control signal VCT includes N valid pulses; N≥2 and N is an integer; the light emitting process control signal VCT between two adjacent valid pulses is at a non-enable level V2′.

[0051] Specifically, it can be arranged that within the first time period T1, the light emitting process control signal VCT has a plurality of (may be greater than or equal to 2) interval non-enable levels V2', that is, it can include a plurality of valid pulses. Figure 2 It is exemplarily shown that in the first time period T1 , since the light emitting process control signal VCT has a non-enable level V2 ′, the light emitting process control signal VCT includes 2 effective pulses, which can enable the light emitting element D0 to emit light twice in the light emitting stage. Figure 3 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention, such as Figure 3As shown, in the first time period T1, since the light-emitting process control signal VCT has two non-enable levels V2′, the light-emitting process control signal VCT includes three valid pulses, which can make the light-emitting element D0 emit light three times in the light-emitting stage. In this way, the flickering phenomenon of the human eye when refreshing two adjacent display frames can be further weakened, thereby further improving the visual effect of the human eye on the flickering of the picture, and effectively improving the user experience of the display panel. In other feasible embodiments, the light-emitting process control signal VCT in the first time period T1 includes multiple (greater than three) valid pulses, so that the light-emitting process of the light-emitting element D0 in the first time period T1 is divided into multiple times of light emission, so as to further improve the visual effect of the human eye on the flickering of the picture, and the embodiment of the present invention does not make specific limitations on this.

[0052] Exemplarily, in the first time period T1, the time length t2 of the non-enable level V2′ of the light-emitting process signal VCT is less than the pulse width t3 of the effective pulse, so as to ensure that the light-emitting element D0 has a longer light-emitting time and a shorter non-lighting time in the light-emitting stage. In the first time period T1, while ensuring the normal display of the picture, the human eye will not capture the short-term shutdown of the light-emitting element D0, thereby preventing the human eye from producing a flickering visual effect, and can weaken the flickering phenomenon of the human eye when refreshing two adjacent display frames.

[0053] It should be noted that the above embodiment is only exemplified by taking the enable level V1 of the pulse width lighting signal PWM-EM and the amplitude lighting signal PAM-AM as a low level, the non-enable level V1′ as a high level, and the enable level V2 of the lighting process control signal VCT as a high level, and the non-enable level V2′ as a low level as an example. It can be understood that the enable level and non-enable level of the pulse width lighting signal PWM-EM, the amplitude lighting signal PAM-AM and the lighting process control signal VCT are related to the specific settings in the circuit. In other feasible embodiments of the present invention, the enable level V1 of the pulse width lighting signal PWM-EM and the amplitude lighting signal PAM-AM can be a high level, the non-enable level V1′ can be a low level, and the enable level V2 of the lighting process control signal VCT is a low level, and the non-enable level V2′ is a high level. The embodiment of the present invention does not specifically limit this.

[0054] The pixel circuit provided by the embodiment of the present invention outputs a pulse width modulation signal at least according to the pulse width light-emitting signal through the pulse width modulation module, outputs a light-emitting drive signal at least according to the amplitude light-emitting signal through the amplitude modulation module, and controls the pulse width of the light-emitting drive signal according to the pulse width modulation signal, so that the light-emitting brightness and light-emitting duration of the light-emitting element can be controlled. By setting the light-emitting process control module to control the transmission path of the light-emitting drive signal to the light-emitting element at least according to the light-emitting process control signal, the light-emitting element can be controlled to be turned off or emit light during the light-emitting stage of the light-emitting element. By setting the light-emitting process control signal to include at least one non-enable level in the first time period in which the pulse width light-emitting signal and the amplitude light-emitting signal are both enable levels, the light-emitting process control signal can be turned off temporarily during the light-emitting stage of a display frame, which will not be captured by the human eye and will not produce a flickering visual effect. In addition, by controlling the light-emitting element to be turned off temporarily in the first time period, the flickering phenomenon of the human eye when refreshing two adjacent display frames can be weakened, especially for low-grayscale display images, the visual effect of the human eye on the flickering of the image can be improved, which is conducive to improving the user experience of the display panel.

[0055] Optional, Figure 4 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Figure 4 As shown, the light-emitting process control module 30 includes a switch unit 31 and a light-emitting process control unit 32. The light-emitting process control unit 32 is electrically connected to the control end of the switch unit 31, and the light-emitting process control unit 32 receives a light-emitting process control signal VCT; the light-emitting process control unit 32 is used to output a switch control signal at least according to the light-emitting process control signal VCT; the switch unit 31 is at least electrically connected to the amplitude adjustment module 20; the switch unit 31 is used to turn on or off according to the switch control signal, and transmit the light-emitting drive signal to the light-emitting element D0 when turned on.

[0056] Specifically, the light-emitting process control unit 32 is used to output a switch control signal according to the light-emitting process control signal VCT to control the switch unit 31 to be turned on or off. The switch unit 31 can be electrically connected to the transmission path of the light-emitting drive signal to the light-emitting element D0, or the switch unit 31 can also be electrically connected to the path between the source signal for generating the light-emitting drive signal and the output end of the light-emitting drive signal, so that the amplitude adjustment module 20 can be controlled to transmit the light-emitting drive signal to the light-emitting element D0 by controlling the state of the switch unit 31. Among them, when the switch unit 31 is turned on, the transmission path of the light-emitting drive signal to the light-emitting element D0 is turned on, so that the light-emitting drive signal is transmitted to the light-emitting element D0, and the light-emitting element D0 can emit light according to the light-emitting drive signal; and when the switch unit 31 is turned off, the transmission path of the light-emitting drive signal to the light-emitting element D0 is turned off, so that the light-emitting drive signal cannot be transmitted to the light-emitting element D0, and the light-emitting element D0 does not emit light.

[0057] Optional, reference Figure 4 The first end of the switch unit 31 is electrically connected to the output end of the amplitude adjustment module 20, and the second end of the switch unit 31 is electrically connected to the light emitting element D0.

[0058] Specifically, the switch unit 31 can be disposed between the output end of the amplitude adjustment module 20 and the light emitting element D0, and when the switch unit 31 is turned on, the light emitting drive signal output by the amplitude adjustment module 20 is transmitted to the light emitting element D0 through the turned-on switch unit 31, and when the light emitting drive signal is a drive current capable of driving the light emitting element D0 to emit light, the light emitting element D0 can emit light. When the switch unit 31 is turned off, the output end of the amplitude adjustment module 20 and the light emitting element D0 are in an open circuit state, the light emitting drive signal cannot be transmitted to the light emitting element D0, and the light emitting element D0 does not emit light.

[0059] Optional, Figure 5 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Figure 5 As shown, the switch unit 31 includes a switch transistor M30; a first electrode of the switch transistor M30 is electrically connected to a first end of the switch unit 31, a second electrode of the switch transistor M30 is electrically connected to a second end of the switch unit 31, and a gate of the switch transistor M30 is electrically connected to a light emitting process control unit 32.

[0060] Specifically, the light-emitting process control unit 32 outputs a switching control signal which can be provided to the gate of the switching transistor M30, so that the switching transistor M30 can be turned on or off under the control of the switching control signal, so that when the switching transistor M30 is turned on, the current path between the output end of the amplitude adjustment module 20 and the light-emitting element D0 is in an on state, thereby enabling the transmission of the light-emitting drive rod signal; and when the switching transistor M30 is turned off, the current path between the output end of the amplitude adjustment module 20 and the light-emitting element D0 is in an open circuit state, so that the light-emitting drive rod signal cannot be transmitted to the light-emitting element D0.

[0061] Exemplarily, the switch transistor M30 may be a P-type MOS tube or an N-type MOS tube. When the switch transistor M30 is a P-type MOS tube, the effective level of the switch transistor M30 is a low level, that is, when the switch control signal is a low level, the switch transistor M30 is controlled to be turned on, and when the switch control signal is a high level, the switch transistor M30 is controlled to be turned off. When the switch transistor M30 is an N-type MOS tube, the effective level of the switch transistor M30 is a high level, that is, when the switch control signal is a high level, the switch transistor M30 is controlled to be turned on, and when the switch control signal is a low level, the switch transistor M30 is controlled to be turned off.

[0062] Optional, reference Figure 5The light-emitting process control unit includes a first light-emitting process control transistor M31, a second light-emitting process control transistor M32, a third light-emitting process control transistor M33 and a fourth light-emitting process control transistor M34; the gate of the first light-emitting process control transistor M31 and the gate of the second light-emitting process control transistor M32 both receive the light-emitting process control signal VCT, the first electrode of the first light-emitting process control transistor M31 and the first electrode of the second light-emitting process control transistor M32 both receive the first voltage signal VC1, the second electrode of the first light-emitting process control transistor M31 is electrically connected to the first control node Q1, and the second electrode of the second light-emitting process control transistor M32 is electrically connected to the control end of the switch unit 31; the first electrode and the gate of the third light-emitting process control transistor M33 both receive the second voltage signal VC2, and the second electrode of the third light-emitting process control transistor M33 is electrically connected to the first control node Q1; the gate of the fourth light-emitting process control transistor M34 is electrically connected to the first control node Q1, the first electrode of the fourth light-emitting process control transistor M34 receives the second voltage signal VC2, and the second electrode of the fourth light-emitting process control transistor M34 is electrically connected to the control end of the switch unit 31.

[0063] Exemplarily, the channel types of the first light emitting process control transistor M31, the second light emitting process control transistor M32, the third light emitting process control transistor M33, the fourth light emitting process control transistor M34 and the switch transistor M30 can be the same, so that the preparation process of the pixel circuit 01 can be simplified, thereby simplifying the preparation process of the display panel. The first light emitting process control transistor M31, the second light emitting process control transistor M32, the third light emitting process control transistor M33, the fourth light emitting process control transistor M34 and the switch transistor M30 can all be N-channel transistors, at which time the enable level of the light emitting process control signal VCT is a low level, the non-enable level is a high level, the first voltage signal VC1 is a low level, and the second voltage signal VC2 is a high level. Alternatively, the first light-emitting process control transistor M31, the second light-emitting process control transistor M32, the third light-emitting process control transistor M33, the fourth light-emitting process control transistor M34 and the switch transistor M30 may all be P-type MOS transistors, in which case the enable level of the light-emitting process control signal VCT is high, the non-enable level is low, the first voltage signal VC1 is high, and the second voltage signal VC2 is low. The first light-emitting process control transistor M31, the second light-emitting process control transistor M32, the third light-emitting process control transistor M33, the fourth light-emitting process control transistor M34 and the switch transistor M30 may all be P-type MOS transistors to exemplarily illustrate this embodiment.

[0064] Specifically, the second voltage signal VC2 controls the third light-emitting process control transistor M33 to be always in the on state, so that the second voltage signal VC2 is transmitted to the first node Q1 through the third light-emitting process control transistor M33. When the light-emitting process control signal VCT is at a high level, the first light-emitting process control transistor M31 and the second light-emitting process control transistor M32 are turned off, and the first voltage signal VC1 cannot be transmitted to the first node Q1 and the control end of the switch unit 31, so that the first node Q1 remains at the second voltage signal VC2, so that the fourth light-emitting process control transistor M34 is turned on under the control of the second voltage signal VC2, so that the second voltage signal VC2 is transmitted to the control end of the switch unit 31 through the fourth light-emitting process control transistor M34, so that the switch transistor M30 in the switch unit 31 is turned on under the control of the second voltage signal VC2.

[0065] When the light-emitting process control signal VCT is at a low level, the first light-emitting process control transistor M31 and the second light-emitting process control transistor M32 are turned on, and at this time, the first voltage signal VC1 is transmitted to the first node Q1 through the first light-emitting process control transistor M31, so that the potential of the first node Q1 increases, so that the fourth light-emitting process control transistor M34 is turned off, so that the second voltage signal VC2 cannot be transmitted to the control end of the switch unit 31. At this time, the first voltage signal VC1 is transmitted to the control end of the switch unit 31 through the turned-on second light-emitting process control transistor M32, so that the switch transistor M30 in the switch unit 31 is turned off at the first voltage signal VC1.

[0066] An embodiment of the present invention provides a specific circuit structure of a luminous process control module 30, so that the luminous process control unit 32 can transmit different switch control signals to the switch unit 31 under the control of the luminous process control signal VCT, so that the switch unit 31 can be turned on or off under the control of the luminous process control unit 32.

[0067] Optional, Figure 6 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Figure 6As shown, the amplitude adjustment module 20 includes: an amplitude data writing unit 21, an amplitude voltage input unit 22, an amplitude driving transistor M20 and an amplitude driving output unit 23; the input end of the amplitude data writing unit 21 receives the amplitude data signal PAM-DATA, the control end of the amplitude data writing unit 21 receives the first amplitude scanning signal PAM-S1, and the output end of the amplitude data writing unit 21 is electrically connected to the gate of the amplitude driving transistor M20; the amplitude data writing unit 21 is used to write the amplitude data signal PAM-DATA to the gate of the amplitude driving transistor M20 under the control of the first amplitude scanning signal PAM-S1; the input end of the amplitude voltage input unit 22 receives the amplitude voltage signal PAM-VDD, and the control end of the amplitude voltage input unit 22 receives the amplitude light emitting signal PAM-S1. AM-EM, and the output end of the amplitude input unit 22 is electrically connected to the first electrode of the amplitude driving transistor M20; the amplitude voltage input unit 22 is used to transmit the amplitude voltage signal PAM-VDD to the first electrode of the amplitude driving transistor M20 under the control of the amplitude light-emitting signal PAM-EM; the gate of the amplitude driving transistor M20 is also electrically connected to the pulse width modulation module 10, the second electrode of the amplitude driving transistor M20 is electrically connected to the input end of the driving output unit 23, and the amplitude driving transistor M20 outputs the light-emitting driving signal according to the amplitude data signal PAM-DATA, the amplitude voltage signal PAM-VDD and the pulse width modulation signal; the control end of the amplitude driving output unit 23 receives the amplitude light-emitting signal PAM-EM, and the output end of the amplitude driving output unit 23 is used to output the light-emitting driving signal.

[0068] Specifically, the amplitude data writing unit 21 can control the transmission path of the amplitude data signal PAM-DATA to the gate of the amplitude driving transistor M20 under the control of the first amplitude scanning signal PAM-S1, so that when the amplitude data writing unit 21 is turned on, the amplitude data signal PAM-DATA is written to the gate of the amplitude driving transistor M20, and when the amplitude data writing unit 21 is turned off, the amplitude data signal PAM-DATA is stopped from being written to the gate of the amplitude driving transistor M20. The amplitude voltage input unit 22 can control the transmission path of the amplitude voltage signal PAM-VDD to the first electrode of the amplitude driving transistor M20 under the control of the amplitude light emitting signal PAM-EM, so that when the amplitude voltage input unit 22 is turned on, the amplitude voltage signal PAM-VDD is transmitted to the first electrode of the amplitude driving transistor M20, and when the amplitude voltage input unit 22 is turned off, the amplitude voltage signal PAM-VDD is stopped from being transmitted to the first electrode of the amplitude driving transistor M20. The gate of the amplitude driving transistor M20 also receives the pulse width modulation signal provided by the pulse width modulation module 10, so that the amplitude driving transistor M20 can generate a driving current (i.e., a light-emitting driving signal) according to the amplitude data signal PAM-DATA, so as to control the light-emitting brightness of the light-emitting element D0, and control the duration of generating the driving current according to the pulse width modulation signal, so as to control the light-emitting duration of the light-emitting element D0. The amplitude driving output unit 23 can output the light-emitting driving signal under the control of the amplitude light-emitting signal PAM-EM, so that when the amplitude driving output unit 23 is turned on, the light-emitting driving signal is output through its output terminal, and when the amplitude driving output unit 23 is turned off, the light-emitting driving signal is stopped from being output.

[0069] Optional, reference Figure 6 The first end of the switch unit 31 is electrically connected to the output end of the amplitude voltage input unit 22, and the second end of the switch unit 31 is electrically connected to the first electrode of the amplitude driving transistor M20.

[0070] Specifically, when the amplitude voltage input unit 22 is turned on, when the switch unit 31 is turned on, the amplitude voltage signal PAM-VDD can be transmitted to the first electrode of the amplitude driving transistor M20, then when the amplitude driving transistor M20 is turned on according to the amplitude data signal PAM-DATA, the amplitude voltage signal PAM-VDD can be transmitted to the amplitude driving output unit 23 according to its degree of conduction, so that when the amplitude driving output unit 23 is turned on, the amplitude voltage signal PAM-VDD can be transmitted to the light-emitting element D0 as a light-emitting driving signal, so that the light-emitting element D0 emits light according to the light-emitting driving signal; when the switch unit 31 is turned off, the amplitude voltage signal PAM-VDD cannot be transmitted to the first electrode of the amplitude driving transistor M20, so that the amplitude driving transistor M20 cannot provide the light-emitting driving signal to the amplitude driving output unit 23, and the light-emitting element D0 does not emit light.

[0071] For example, Figure 7 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Figure 7 As shown, the amplitude data writing unit 21 includes a first amplitude data writing transistor M21 and a second amplitude data writing transistor M22. The gate of the first amplitude data writing transistor M21 receives the first amplitude scanning signal PAM-S1, the first electrode of the first amplitude data writing transistor M21 receives the amplitude data signal PAM-DATA, and the second electrode of the first amplitude data writing transistor M21 is electrically connected to the first electrode of the amplitude driving transistor M20. The gate of the second amplitude data writing transistor M22 receives the first amplitude scanning signal PAM-S1, the first electrode of the second amplitude data writing transistor M22 is electrically connected to the second electrode of the amplitude driving transistor M20, and the second electrode of the second amplitude data writing transistor M22 is electrically connected to the gate of the amplitude driving transistor M20. The first amplitude data writing transistor M21 and the second amplitude data writing transistor M22 are turned on or off under the control of the first amplitude scanning signal PAM-S1, and when the first amplitude data writing transistor M21 and the second amplitude data writing transistor M22 are turned on, the amplitude data signal PAM-DATA is written to the gate of the amplitude driving transistor M20. The second amplitude data writing transistor M22 can be a dual-gate transistor to reduce leakage current.

[0072] The amplitude voltage input unit 22 includes an amplitude voltage input transistor M23, a gate of which receives the amplitude light emitting signal PAM-EM, a first electrode of which receives the amplitude voltage signal PAM-VDD, and a second electrode of which is electrically connected to a first electrode of the amplitude driving transistor M20. The amplitude voltage input transistor M23 is turned on or off under the control of the amplitude light emitting signal PAM-EM, and when the amplitude voltage input transistor M23 is turned on, the amplitude voltage signal PAM-VDD is transmitted to the first electrode of the amplitude driving transistor M20.

[0073] The amplitude drive output unit 23 includes an amplitude drive output transistor M24, a gate of which receives the amplitude light emitting signal PAM-EM, a first electrode of which is electrically connected to a second electrode of the amplitude drive transistor M20, and a second electrode of which is electrically connected to the light emitting element D0. The amplitude drive output transistor M24 is turned on or off under the control of the amplitude light emitting signal PAM-EM, and when the amplitude drive output transistor M24 is turned on, the light emitting drive signal provided by the amplitude drive transistor M20 is output to the light emitting element D0.

[0074] Exemplary, reference Figure 7, the first electrode of the switch transistor M30 in the switch unit 31 can be set to be electrically connected to the second electrode of the amplitude voltage input transistor M23, and the second electrode of the switch transistor M30 can be electrically connected to the second electrode of the amplitude driving transistor M20. Then, when the amplitude voltage input transistor M23, the amplitude driving output transistor M24 and the amplitude driving transistor M20 are all turned on, if the switch transistor M30 is turned on, a signal transmission path is formed between the amplitude voltage signal PAM-VDD and the first power supply signal PVEE electrically connected to the cathode of the light emitting element D0, so that the light emitting element D0 can be driven to emit light; and if the switch transistor M30 is turned off, the amplitude voltage input transistor M23 and the amplitude driving transistor M20 are disconnected, and the light emitting driving signal cannot be provided to the light emitting element D0, so that the light emitting element D0 does not emit light.

[0075] Optional, Figure 8 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Figure 8 As shown, a first end of the switch unit 31 is electrically connected to the second electrode of the amplitude driving transistor M20 , and a second end of the switch unit 31 is electrically connected to the input end of the amplitude driving output unit 23 .

[0076] Specifically, when the amplitude voltage input unit 22, the amplitude driving transistor M20 and the amplitude driving output unit 23 are all turned on, when the switch unit 31 is turned on, a signal transmission path is formed between the amplitude voltage signal PAM-VDD and the first power signal PVEE electrically connected to the cathode of the light-emitting element D0, so that the light-emitting element D0 can be driven to emit light according to the light-emitting driving signal. When the switch unit 31 is turned off, the amplitude driving transistor M20 and the amplitude driving output unit 23 are disconnected, so that the light-emitting driving signal provided by the amplitude driving transistor M20 cannot be transmitted to the amplitude driving output unit 23, so that the amplitude driving output unit 23 cannot provide the light-emitting driving signal to the light-emitting element D0, and the light-emitting element D0 does not emit light.

[0077] For example, Fig. 9 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Fig. 9As shown, the first electrode of the switch transistor M30 in the switch unit 31 is electrically connected to the second electrode of the amplitude driving transistor M20, and the second electrode of the switch transistor M30 is electrically connected to the first electrode of the amplitude driving output transistor M24. When the amplitude voltage input transistor M23, the amplitude driving output transistor M24 and the amplitude driving transistor M20 are all turned on, if the switch transistor M30 is turned on, a signal transmission path can be formed between the amplitude voltage signal PAM-VDD and the first power supply signal PVEE electrically connected to the cathode of the light emitting element D0, so that the light emitting element D0 can be driven to emit light; and if the switch transistor M30 is turned off, the amplitude driving transistor M20 and the amplitude driving output transistor M24 are disconnected, and the light emitting driving signal cannot be provided to the light emitting element D0, so that the light emitting element D0 does not emit light.

[0078] The above embodiment introduces several positions where the light-emitting process control module can be set, so that the light-emitting state of the light-emitting element can be controlled by controlling the light-emitting process control module, and the number of times the light-emitting element emits light can be controlled by controlling the state of the light-emitting process control module during the light-emitting stage, so as to improve the visual effect of the flickering of the picture to the human eye. And a specific structure of the light-emitting process control module is introduced to exemplarily explain the working principle of the light-emitting process control module. In other feasible embodiments of the present invention, the light-emitting process control module can also be implemented by other circuit structures. The following is a specific introduction to several feasible implementation methods of the light-emitting process control module.

[0079] Optional, Fig.10 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Fig.10 As shown, the light-emitting process control unit 32 includes a fifth light-emitting process control transistor M35 and a sixth light-emitting process control transistor M36; the gates of the fifth light-emitting process control transistor M35 and the sixth light-emitting process control transistor M36 both receive a light-emitting process control signal VCT; the first electrode of the fifth light-emitting process control transistor M35 receives a first voltage signal VC1, and the second electrode of the fifth light-emitting process control transistor M35 is electrically connected to the control end of the switch unit 31; the first electrode of the sixth light-emitting process control transistor M36 receives a second voltage signal VC2, and the second electrode of the sixth light-emitting process control transistor M36 is electrically connected to the control end of the switch unit 31; the channel types of the fifth light-emitting process control transistor M35 and the sixth light-emitting process control transistor M36 are different.

[0080] Exemplarily, the fifth light emitting process control transistor M35 can be set as an N-channel transistor, and the sixth light emitting process control transistor M36 can be set as a P-channel transistor; or, the fifth light emitting process control transistor M35 can be set as a P-channel transistor, and the sixth light emitting process control transistor M36 can be set as an N-channel transistor. When the fifth light-emitting process control transistor M35 is an N-channel transistor, the sixth process light-emitting control transistor M36 and the switching transistor M30 are P-channel transistors, the first voltage signal VC1 can be set to a low level signal, and the second voltage signal VC2 can be set to a high level signal. At this time, the enable level of the light-emitting process control signal VCT is a low level, and the non-enable level is a high level, that is, the switching transistor M30 is turned on when the light-emitting process control signal VCT is a low level, and the switching transistor M30 is turned off when the light-emitting process control signal VCT is a high level; or the first voltage signal VC1 can be set to a high level signal, and the second voltage signal VC2 can be set to a low level signal. At this time, the enable level of the light-emitting process control signal VCT is a high level, and the non-enable level is a low level, that is, the switching transistor M30 is turned on when the light-emitting process control signal VCT is a high level, and the switching transistor M30 is turned off when the light-emitting process control signal VCT is a low level. Alternatively, when the fifth light-emitting process control transistor M35 and the switch transistor M30 are P-channel transistors, and the sixth light-emitting process control transistor M36 is an N-channel transistor, the first voltage signal VC1 can be set to a high-level signal, and the second voltage signal VC2 can be set to a low-level signal. At this time, the enable level of the light-emitting process control signal VCT is a high level, and the non-enable level is a low level; or the first voltage signal VC1 is a low-level signal, and the second voltage signal VC2 is a high-level signal. At this time, the enable level of the light-emitting process control signal VCT is a low level, and the non-enable level is a high level. That is, the enable level and non-enable level of the light-emitting process control signal VCT are related to the channel type of the fifth light-emitting process control transistor M35 and the sixth light-emitting process control transistor M36, the first voltage signal VC1, the second voltage signal VC2, and the channel type of the switch transistor M30, and the embodiment of the present invention can be set according to the design requirements. The following explains the working principle of the light-emitting process control module 30 by taking the fifth light-emitting process control transistor M35 and the switch transistor M30 as P-channel transistors, the sixth process light-emitting control transistor M36 as an N-channel transistor, the first voltage signal VC1 as a high-level signal, the second voltage signal VC2 as a low-level signal, so that the enable level of the light-emitting process control signal VCT is a high level and the non-enable level is a low level as an example.

[0081] Specifically, when the light-emitting process control signal VCT is at a low level, the fifth light-emitting process control transistor M35 is turned on and the sixth light-emitting process control transistor M36 is turned off, so that the first voltage signal VC1 is transmitted to the gate of the switch transistor M30 in the switch unit 31 through the fifth light-emitting process control transistor M35, so that the switch transistor M30 is turned off. When the light-emitting process control signal VCT is at a high level, the fifth light-emitting process control transistor M35 is turned off and the sixth light-emitting process control transistor M36 is turned on, so that the second voltage signal VC2 is transmitted to the gate of the switch transistor M30 in the switch unit 31 through the sixth light-emitting process control transistor M36, so that the switch transistor M30 is turned on. The fifth light-emitting process control transistor M35 is turned on and the sixth light-emitting process control transistor M36 constitute an inverter, and the corresponding switch control signal is provided to the switch transistor M30 by controlling the states of the fifth light-emitting process control transistor M35 and the sixth light-emitting process control transistor M36, so that the control of the switch transistor M30 can be realized.

[0082] Optional, Fig.11 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Fig.11 As shown, the light-emitting process control unit 32 includes a seventh light-emitting process control transistor M37 and an eighth light-emitting process control transistor M38; the channel type of the seventh light-emitting process control transistor M37 is the same as the channel type of the eighth light-emitting process control transistor M38; the light-emitting process control signal VCT includes a first light-emitting process control signal VCT1 and a second light-emitting process control signal VCT2, and the polarities of the first light-emitting process control signal VCT1 and the second light-emitting process control signal VCT2 are different; the gate of the seventh light-emitting process control transistor M37 receives the first light-emitting process control signal VCT1, the first electrode of the seventh light-emitting process control transistor M37 receives the first voltage signal VC1, and the second electrode of the seventh light-emitting process control transistor M37 is electrically connected to the control end of the switch unit 31; the gate of the eighth light-emitting process control transistor M38 receives the second light-emitting process control signal VCT2, the first electrode of the eighth light-emitting process control transistor M38 receives the second voltage signal VC2, and the second electrode of the eighth light-emitting process control transistor M38 is electrically connected to the control end of the switch unit 31.

[0083] Specifically, the seventh light-emitting process control transistor M37 and the eighth light-emitting process control transistor M38 can both be N-channel transistors or P-channel transistors. In a preferred embodiment, the seventh light-emitting process control transistor M37 and the eighth light-emitting process control transistor M38 can be set to have the same channel type as the switch transistor M30, so that the preparation process of the pixel circuit can be simplified. On this basis, by setting the polarities of the first light-emitting process control signal VCT1 and the second light-emitting process control signal VCT2 to be different, the seventh light-emitting process control transistor M37 and the eighth light-emitting process control transistor M38 can be in an asynchronous conduction state, so that the corresponding switch control signal can be provided to the switch transistor M30 by controlling one of the seventh light-emitting process control transistor M37 and the eighth light-emitting process control transistor M38 to be turned on. Taking the seventh light-emitting process control transistor M37, the eighth light-emitting process control transistor M38 and the switch transistor M30 as P-channel transistors as an example, when the first light-emitting process control signal VCT1 is at a low level and the second light-emitting process control signal VCT2 is at a high level, the seventh light-emitting process control transistor M37 is turned on and the eighth light-emitting process control transistor M38 is turned off, so that the first voltage signal VC1 can be transmitted to the gate of the switch transistor M30; and when the first light-emitting process control signal VCT1 is at a high level and the second light-emitting process control signal VCT2 is at a low level, the seventh light-emitting process control transistor M37 is turned off and the eighth light-emitting process control transistor M38 is turned on, so that the second voltage signal VC2 can be transmitted to the gate of the switch transistor M30. One of the first voltage signal VC1 and the second voltage signal VC2 is a high-level signal and the other is a low-level signal, so that when the switch transistor M30 needs to be controlled to be turned on, the low-level signal can be transmitted to the gate of the switch transistor M30, and when the switch transistor M30 needs to be controlled to be turned off, the high-level signal can be transmitted to the gate of the switch transistor M30. Exemplarily, the first voltage signal VC1 can be set as a high-level signal and the second voltage signal VC2 can be set as a low-level signal. At this time, the enable level of the first light-emitting process control signal VCT1 is high, and the disable level is low, and the enable level of the second light-emitting process control signal VCT2 is low, and the disable level is high, that is, when the first light-emitting process control signal VCT1 is high and the second light-emitting process control signal VCT2 is low, the switching transistor M30 in the switch unit 31 is turned on, and when the first light-emitting process control signal VCT1 is low and the second light-emitting process control signal VCT2 is high, the switching transistor M30 in the switch unit 31 is turned off.

[0084] The above embodiments specifically introduce several feasible implementation methods of the light emitting process control module, but are not limited thereto. The following embodiments exemplarily introduce the specific circuit structures of the amplitude adjustment module and the pulse width adjustment module.

[0085] Optional, Fig.12 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Fig.12 As shown, the amplitude adjustment module 20 also includes: an amplitude reset unit 24 and a first storage unit 25; the input end of the amplitude reset unit 24 receives the amplitude reset signal PAM-REF, the control end of the amplitude reset unit 24 receives the second amplitude scan signal PAM-S2, and the output end of the amplitude reset unit 24 is electrically connected to the gate of the amplitude driving transistor M20; the amplitude reset unit 24 is used to be turned on or off according to the second amplitude scan signal PAM-S2, and transmit the amplitude reset signal PAM-REF to the gate of the amplitude driving transistor M20 when turned on; the first end of the first storage unit 25 receives the amplitude voltage signal PAM-VDD, and the second end of the first storage unit 25 is electrically connected to the gate of the amplitude driving transistor M20.

[0086] Specifically, when the potential of the gate of the amplitude driving transistor M20 needs to be reset, the amplitude reset unit 24 can be controlled to be turned on, so that the amplitude reset signal PAM-REF is transmitted to the gate of the amplitude driving transistor M20, which can ensure that the accurate amplitude data signal PAM-DATA is subsequently written to the gate of the amplitude driving transistor M20, thereby ensuring the accurate light emission of the light emitting element D0. The first storage unit 25 can store the gate potential of the amplitude driving transistor M20, and can stabilize the gate potential of the amplitude driving transistor M20.

[0087] For example, Fig.13 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Fig.13 As shown, the amplitude reset unit 24 includes an amplitude reset transistor M25, the gate of the amplitude reset transistor M25 receives the second amplitude scanning signal PAM-S2, the first electrode of the amplitude reset transistor M25 receives the amplitude reset signal PAM-REF, and the second electrode of the amplitude reset transistor M25 is electrically connected to the gate of the amplitude driving transistor M20. The amplitude reset transistor M25 can be turned on or off under the control of the second amplitude scanning signal PAM-S2, and transmits the amplitude reset signal PAM-REF to the gate of the amplitude driving transistor M20 when the amplitude reset transistor M25 is turned on. The first storage unit 25 may include a first storage capacitor C1, which can store the gate potential of the amplitude driving transistor M20 and stabilize the gate potential of the amplitude driving transistor M20. Among them, the amplitude reset transistor M25 can be a dual-gate transistor to reduce leakage.

[0088] Optional, Fig.14 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Fig.14As shown, the pulse width modulation module 10 includes: a pulse width driving transistor M10, a pulse width data writing unit 11, a pulse width voltage input unit 12 and a pulse width control output unit 13; the input end of the pulse width data writing unit 11 receives the pulse width data signal PWM-DATA, the control end of the pulse width data writing unit 11 receives the first pulse width scanning signal PWM-S1, and the output end of the pulse width data writing unit 11 is electrically connected to the gate of the pulse width driving transistor M10; the pulse width data writing unit 11 is used to write the pulse width data signal PWM-DATA to the gate of the pulse width driving transistor M10 under the control of the first pulse width scanning signal PWM-S1; the input end of the pulse width voltage input unit 12 receives the pulse width voltage signal PWM-VDD, the control end of the pulse width voltage input unit 12 receives the pulse width light emitting signal PWM-EM, and the output end of the pulse width voltage input unit 12 is electrically connected to the pulse width driving transistor M10 The first electrode of the pulse width driving transistor M10 is electrically connected; the pulse width voltage input unit 12 is used to transmit the pulse width voltage signal PWM-VDD at the first electrode of the pulse width driving transistor M10 under the control of the pulse width light-emitting signal PWM-EM; the gate of the pulse width driving transistor M10 also receives the sweep signal SWEEP, and the second electrode of the pulse width driving transistor M10 is electrically connected to the pulse width control output unit 13; the pulse width driving transistor M10 is used to output a pulse width adjustment signal to the pulse width control output unit 13 according to the sweep signal SWEEP, the pulse width data signal PWM-DATA and the pulse width voltage signal PWM-VDD; the control end of the pulse width control output unit 13 receives the pulse width light-emitting signal PWM-EM, and the output end of the pulse width control output unit 13 is electrically connected to the amplitude adjustment module 20; the pulse width control output unit 13 is used to output a pulse width adjustment signal to the amplitude adjustment module 20 under the control of the pulse width light-emitting signal PWM-EM.

[0089] Specifically, the pulse width data writing unit 11 can control the transmission path of the pulse width data signal PWM-DATA to the gate of the pulse width driving transistor M10 under the control of the first pulse width scanning signal PWM-S1, so that when the pulse width data writing unit 11 is turned on, the pulse width data signal PWM-DATA is written to the gate of the pulse width driving transistor M10, and when the pulse width data writing unit 11 is turned off, the pulse width data signal PWM-DATA is stopped from being written to the gate of the pulse width driving transistor M10. The pulse width voltage input unit 12 can control the transmission path of the pulse width voltage signal PWM-VDD to the first electrode of the pulse width driving transistor M10 under the control of the pulse width light emitting signal PWM-EM, so that when the pulse width voltage input unit 12 is turned on, the pulse width voltage signal PWM-VDD is transmitted to the first electrode of the pulse width driving transistor M10, and when the pulse width voltage input unit 12 is turned off, the pulse width voltage signal PWM-VDD is stopped from being transmitted to the first electrode of the pulse width driving transistor M10. The gate of the pulse width driving transistor M10 also receives the sweep signal SWEEP, so that the pulse width driving transistor M10 can generate a control current (i.e., a pulse width modulation signal) according to the pulse width data signal PWM-DATA, so as to control the light emitting duration of the light emitting element D0. The pulse width control output unit 13 can output the pulse width modulation signal under the control of the pulse width light emitting signal PWM-EM, so that when the pulse width control output unit 13 is turned on, the pulse width modulation signal is output through its output terminal, and when the pulse width control output unit 13 is turned off, the pulse width modulation signal is stopped from being output.

[0090] For example, Fig.15 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Fig.15As shown, the pulse width data writing unit 11 includes a first pulse width data writing transistor M11 and a second pulse width data writing transistor M12. The gate of the first pulse width data writing transistor M11 receives the first pulse width scanning signal PWM-S1, the first electrode of the first pulse width data writing transistor M11 receives the pulse width data signal PWM-DATA, and the second electrode of the first pulse width data writing transistor M11 is electrically connected to the first electrode of the pulse width driving transistor M10. The gate of the second pulse width data writing transistor M12 receives the first pulse width scanning signal PWM-S1, the first electrode of the second pulse width data writing transistor M12 is electrically connected to the second electrode of the pulse width driving transistor M10, and the second electrode of the second pulse width data writing transistor M12 is electrically connected to the gate of the pulse width driving transistor M10. The first pulse width data writing transistor M11 and the second pulse width data writing transistor M12 are turned on or off under the control of the first pulse width scanning signal PWM-S1, and when the first pulse width data writing transistor M11 and the second pulse width data writing transistor M12 are turned on, the pulse width data signal PWM-DATA is written to the gate of the pulse width driving transistor M10. The second pulse width data writing transistor M12 may be a dual-gate transistor for reducing leakage current.

[0091] The pulse width voltage input unit 12 includes a pulse width voltage input transistor M13, a gate of the pulse width voltage input transistor M13 receives the pulse width light emitting signal PWM-EM, a first electrode of the pulse width voltage input transistor M13 receives the pulse width voltage signal PWM-VDD, and a second electrode of the pulse width voltage input transistor M13 is electrically connected to a first electrode of the pulse width driving transistor M10. The pulse width voltage input transistor M13 is turned on or off under the control of the pulse width light emitting signal PWM-EM, and when the pulse width voltage input transistor M13 is turned on, the pulse width voltage signal PWM-VDD is transmitted to the first electrode of the pulse width driving transistor M10.

[0092] The pulse width control output unit 13 includes a pulse width control output transistor M14, the gate of the pulse width control output transistor M14 receives the pulse width light emitting signal PWM-EM, the first electrode of the pulse width control output transistor M14 is electrically connected to the second electrode of the pulse width driving transistor M10, and the second electrode of the pulse width control output transistor M14 is electrically connected to the amplitude adjustment module 20. The pulse width control output transistor M14 is turned on or off under the control of the pulse width light emitting signal PWM-EM, and when the pulse width control output transistor M14 is turned on, the pulse width adjustment signal provided by the pulse width driving transistor M10 is output to the amplitude adjustment module 20, specifically, the pulse width adjustment signal is output to the gate of the amplitude driving transistor M20.

[0093] Optional, Fig.16 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Fig.16As shown, the pulse width regulation module 10 also includes: a pulse width reset unit 14 and a second storage unit 15; the input end of the pulse width reset unit 14 receives the pulse width reset signal PWM-REF, the control end of the pulse width reset unit 14 receives the second pulse width scanning signal PWM-S2, and the output end of the pulse width reset unit 14 is electrically connected to the gate of the pulse width driving transistor M10; the pulse width reset unit 14 is used to write the pulse width reset signal PWM-REF to the gate of the pulse width driving transistor M10 under the control of the second pulse width scanning signal PWM-S2; the first end of the second storage unit 15 receives the sweep signal SWEEP, and the second end of the second storage unit 15 is electrically connected to the gate of the pulse width driving transistor M10.

[0094] Specifically, when the potential of the gate of the pulse width driving transistor M10 needs to be reset, the pulse width reset unit 14 can be controlled to be turned on, so that the pulse width reset signal PWM-REF is written to the gate of the pulse width driving transistor M10, which can ensure the accuracy of the pulse width data signal PWM-DATA subsequently written to the gate of the pulse width driving transistor M10, thereby ensuring the accuracy of the light emitting duration of the light emitting element D0. The second storage unit 15 can store the gate potential of the pulse width driving transistor M10, and can stabilize the gate potential of the pulse width driving transistor M10.

[0095] For example, Fig.17 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Fig.17 As shown, the pulse width reset unit 24 includes a pulse width reset transistor M15, the gate of the pulse width reset transistor M15 receives the second pulse width scan signal PWM-S2, the first electrode of the pulse width reset transistor M15 receives the pulse width reset signal PWM-REF, and the second electrode of the pulse width reset transistor M15 is electrically connected to the gate of the pulse width drive transistor M10. The pulse width reset transistor M15 can be turned on or off under the control of the second pulse width scan signal PWM-S2, and transmits the pulse width reset signal PWM-REF to the gate of the pulse width drive transistor M10 when the pulse width reset transistor M15 is turned on. The second storage unit 15 may include a second storage capacitor C2, which can store the gate potential of the pulse width drive transistor M10 and stabilize the gate potential of the pulse width drive transistor M10. Among them, the pulse width reset transistor M15 can be a dual-gate transistor for reducing leakage current.

[0096] Optional, reference Fig.16 The pixel circuit 01 also includes: a light-emitting reset module 40; an input end of the light-emitting reset module 40 receives a light-emitting reset signal REF0, a control end of the light-emitting reset module 40 receives a light-emitting scanning signal S0, and an output end of the light-emitting reset module 40 is electrically connected to the light-emitting element D0; the light-emitting reset module 40 is used to transmit the light-emitting reset signal REF0 to the light-emitting element D0 under the control of the light-emitting scanning signal S0.

[0097] Specifically, the light emitting reset module 40 can be turned on or off under the control of the light emitting reset signal REF0, and transmit the light emitting reset signal REF0 to the light emitting element D0 when turned on, so as to reset the anode potential of the light emitting element D0 to ensure the subsequent accurate light emission of the light emitting element D0.

[0098] Exemplary, reference Fig.17 The light emitting reset module 40 includes a light emitting reset transistor M41, a gate of the light emitting reset transistor M41 receives a light emitting scan signal S0, a first electrode of the light emitting reset transistor M41 receives a light emitting reset signal REF0, and a second electrode of the light emitting reset transistor M41 is electrically connected to the light emitting element D0. The light emitting scan signal S0 can reuse the first amplitude scanning signal PAM-S1, and the light emitting reset signal REF0 can reuse the amplitude reset signal PAM-REF.

[0099] Fig.17 It is exemplarily shown that each transistor in the pulse width adjustment module 10, the amplitude adjustment module 20, the light emitting process control module 30 and the light emitting reset module 40 is a P-type tube. On this basis, taking the first voltage signal VC1 as a high-level signal and the second voltage signal VC2 as a low-level signal as an example, the working process of the pixel circuit is exemplarily explained. Fig.18 is another driving timing diagram of a pixel circuit provided by an embodiment of the present invention, and is combined with reference to Fig.17 Fig.18 The working process of the pixel circuit 01 includes a reset phase T2, a write compensation phase T3 and a first time period T1.

[0100] In the reset phase T2, the second pulse width scanning signal PWM-S2 and the second amplitude scanning signal PAM-S2 are at a low level, and the frequency sweep signal SWEEP is the first frequency sweep voltage Vswp1. Then the pulse width reset transistor M15 and the amplitude reset transistor M25 are turned on, and the pulse width reset signal PWM-REF is written to the gate of the pulse width driving transistor M10 through the pulse width reset transistor M15, which can reset the gate potential of the pulse width driving transistor M10 and the second storage capacitor C2. And the amplitude reset signal PAM-REF is written to the gate of the amplitude driving transistor M20 through the amplitude reset transistor M25, which can reset the gate potential of the amplitude driving transistor M20 and the first storage capacitor C1. At the same time, the light emitting process control signal VCT is at a low level, the first light emitting process control transistor M31 and the second light emitting process control transistor M32 are turned on, and the fourth light emitting process control transistor M34 is turned off. The first voltage signal VC1 is transmitted to the gate of the switch transistor M30 through the turned-on second light emitting process control transistor M32, and the switch transistor M30 is turned off.

[0101] In the write compensation stage T3, the first pulse width scan signal PWM-S1 and the first amplitude scan signal PAM-S1 are at a low level, and the frequency sweep signal SWEEP is maintained at the first frequency sweep voltage Vswp1. Then the first pulse width data write transistor M11 and the second pulse width data write transistor M12 are turned on under the control of the first pulse width scan signal PWM-S1, and the pulse width data signal PWM-DATA is written into the gate of the pulse width drive transistor M10 and threshold compensation is performed. And the first amplitude data write transistor M21 and the second amplitude data write transistor M22 are turned on under the control of the first amplitude scan signal PAM-S1, and the amplitude data signal PAM-DATA is written into the gate of the amplitude drive transistor M20 and threshold compensation is performed. At the same time, the light emitting reset transistor M41 is turned on under the control of the first amplitude scan signal PAM-S1, and the amplitude reset signal PAM-REF is written into the anode of the light emitting element D0 to reset the anode potential of the light emitting element D0.

[0102] In the first time period T1, the pulse width light-emitting signal PWM-EM and the amplitude light-emitting signal PAM-EM are both at low levels, and the pulse width voltage input transistor M13 and the pulse width control output transistor M14 are turned on under the control of the pulse width light-emitting signal PWM-EM, forming a signal transmission path from the pulse width voltage signal PWM-VDD to the amplitude adjustment module 20. And the amplitude voltage input transistor M23 and the amplitude control output transistor M24 are turned on under the control of the amplitude light-emitting signal PAM-EM, forming a signal transmission path from the amplitude voltage signal PAM-VDD to the light-emitting process control module 30. At the same time, the sweep signal SWEEP gradually changes from the second sweep voltage Vswp2 to the first sweep voltage Vswp1, so that the sweep signal SWEEP includes a falling edge. In the process of the sweep signal SWEEP changing, due to the coupling effect of the second storage capacitor C2, the change amount of the sweep signal SWEEP is coupled to the gate of the pulse width driving transistor M10, and the gate potential of the driving transistor M10 is pulled down. When the gate signal of the pulse width driving transistor M10 does not reach its conduction condition, the pulse width driving transistor M10 is in the off state, so that the amplitude driving transistor M20 generates a corresponding driving current Id according to the amplitude data signal PAM-DATA and the amplitude voltage signal PAM-VDD written to its gate in the write compensation stage T3. At time ta, after the coupling amount of the sweep signal SWEEP pulls down the gate signal of the pulse width driving transistor M10 to meet the conduction condition of the pulse width driving transistor M10, the pulse width voltage signal PWM-VDD can be provided to the gate of the amplitude driving transistor M20 in the amplitude adjustment module 20 through the pulse width voltage input transistor M13, the pulse width driving transistor M10 and the pulse width control output transistor M14 in sequence, so that the gate potential of the amplitude driving transistor M20 is instantly pulled up, so that the amplitude driving transistor M20 is turned off and cannot output the driving current Id.

[0103] During the process from the starting time tb of the first time period T1 to the turn-off time ta of the amplitude driving transistor M20, in the tb-tc stage, the td-te stage and the tf-ta stage, the light emitting process control signal VCT is at a high level, then the first light emitting process control transistor M31 and the second light emitting process control transistor M32 are turned off, and the first node Q1 is kept as the second voltage signal VC2, so that the fourth light emitting process control transistor M34 is turned on under the control of the second voltage signal VC2, so that the second voltage signal VC2 is transmitted to the gate of the switch transistor M30 through the fourth light emitting process control transistor M34, so that the switch transistor M30 in the switch unit 31 is turned on under the control of the second voltage signal VC2. That is, in the tb-tc stage, the td-te stage and the tg-ta stage, the driving current Id generated by the amplitude driving transistor M20 can be transmitted to the light emitting element D0 through the switch transistor M30, so that the driving current Id′ received by the light emitting element D0 is the same as the driving current Id generated by the amplitude driving transistor M20, so that the light emitting element D0 can emit light.

[0104] In the tc~td stage and the te~tf stage, the light emitting process control signal VCT is at a low level, the first light emitting process control transistor M31 and the second light emitting process control transistor M32 are turned on, the fourth light emitting process control transistor M34 is turned off, and the first voltage signal VC1 is transmitted to the gate of the switch transistor M30 through the turned-on second light emitting process control transistor M32, and the switch transistor M30 is turned off. That is, the driving current Id generated by M20 in the tc~td stage and the te~tf stage cannot be transmitted to the light emitting element D0, so that the driving current Id′ received by the light emitting element D0 is zero, so that the light emitting element D0 stops emitting light.

[0105] It can be understood that in the first time period T1, the light-emitting duration of the light-emitting element D0 is related to the falling edge duration of the sweep signal SWEEP and the pulse width data signal PWM-DATA, that is, when the pulse width data signal PWM_DATA is the same, the shorter the falling edge duration of the sweep signal SWEEP, the higher the degree of decline of the sweep signal SWEEP per unit time, the greater the coupling amount to the gate signal of the pulse width driving transistor M10 per unit time, the faster the turn-on condition of the pulse width driving transistor M10 can be met, so that the time required to turn off the amplitude driving transistor M20 is shorter, that is, the time duration for the amplitude driving transistor M20 to provide the driving current Id to the light-emitting element D0 is shorter, thereby achieving the purpose of controlling the light-emitting duration of the light-emitting element D0.

[0106] Exemplarily, the pulse width data signal PWM-DATA can be multiplexed into the pulse width voltage signal PWM-VDD, the amplitude data signal PAM-DATA and the amplitude reset signal, so that the number of signals can be reduced. In this embodiment, the pulse width data signal PWM-DATA can also be multiplexed into the first voltage signal VC1, and the first power supply signal PVEE can be multiplexed into the second voltage signal VC2.

[0107] Optional, Fig.19 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Fig.19 The amplitude adjustment module 20 further includes: a compensation unit 26; the compensation unit 26 receives the amplitude voltage signal PAM-VDD, the reference voltage signal Vini, the first amplitude scanning signal PAM-S1, the second amplitude scanning signal PAM-S2 and the pulse width light-emitting signal PWM-EM, and the compensation unit 26 is electrically connected to the first electrode of the amplitude driving transistor M20; the compensation unit 26 is used to write the amplitude voltage signal PAM-VDD to the first electrode of the amplitude driving transistor M20 under the control of the first amplitude scanning signal PAM-S1 and the pulse width light-emitting signal PWM-EM, and write the reference voltage signal Vini to the first electrode of the amplitude driving transistor M20 under the control of the second amplitude scanning signal PAM-S2 and the pulse width light-emitting signal PWM-EM. The amplitude voltage signal PAM-VDD provided to the amplitude driving transistor M20 can be compensated to avoid the amplitude voltage signal PAM-VDD being unable to drive the light-emitting element D0 to emit light accurately due to the voltage drop caused by the internal resistance of the signal line.

[0108] For example, from reference Fig.19 The compensation unit 26 includes a first compensation transistor M26, a second compensation transistor M27, a third compensation transistor M28 and a third storage capacitor C3. The first electrode of the first compensation transistor M26 receives the amplitude voltage signal PAM-VDD, the gate of the first compensation transistor M26 receives the second amplitude scanning signal PAM-S2, the second electrode of the first compensation transistor M26 and the first electrode of the first storage capacitor C1, the first electrode of the third storage capacitor C3 and the first electrode of the third compensation transistor M28 are electrically connected to the second node Q2; the first electrode of the second compensation transistor M27 receives the amplitude voltage signal PAM-VDD, the gate of the second compensation transistor M27 receives the first amplitude scanning signal PAM-S1, and the second electrode of the second compensation transistor M27 is electrically connected to the second node Q2; the gate of the third compensation transistor M28 receives the pulse width light emitting signal PWM-EM, and the second electrode of the third compensation transistor M28 is electrically connected to the first electrode of the amplitude driving transistor M20; the second electrode of the third storage capacitor C3 receives the reference voltage signal Vini, and the second electrode of the first storage capacitor C1 is electrically connected to the gate of the amplitude driving transistor M20.

[0109] Specifically, combined with reference Fig.18 and Fig.19 In the reset phase T2, the first compensation transistor M26 is turned on under the control of the second amplitude scanning signal PAM-S2, and the amplitude voltage signal PAM-VDD is written to the second node Q2 through the first compensation transistor M26. In the write compensation phase T3, the second compensation transistor M27 is turned on under the control of the first amplitude scanning signal PAM-S1, and the amplitude voltage signal PAM-VDD is written to the second node Q2 through the second compensation transistor M27. In the first time period T1, the third compensation transistor M28 is turned on under the control of the pulse width emission signal PWM-EM, so that the amplitude voltage signal PWM-VDD of the second node Q2 can be transmitted to the first electrode of the amplitude driving transistor M20, and the voltage provided to the amplitude driving transistor M20 can be compensated. Among them, the third storage capacitor C3 and the first storage capacitor C1 can store the potential of the second node Q2, so that the second node Q2 remains stable.

[0110] Exemplarily, after the writing compensation stage T3, the moment (first moment th) when the pulse width light-emitting signal PWM-EM changes from the non-enabled level to the enabled level can be set before the moment (second moment tb) when the amplitude light-emitting signal PAM-EM changes from the non-enabled level to the enabled level. In this way, before the amplitude voltage input transistor M23 is turned on, the amplitude voltage signal PAM-VDD can be written to the first storage capacitor C1 through the third compensation transistor M28, thereby being coupled to the gate of the amplitude driving transistor M20 through the first storage capacitor C1, and the gate potential of the amplitude driving transistor M20 can be stabilized. After the amplitude voltage input transistor M23 is turned on under the control of the amplitude light-emitting signal PAM-EM at the second moment tb, the voltage drop of the amplitude voltage signal PAM-VDD due to the internal resistance of the signal line can be avoided to affect the gate potential of the amplitude driving transistor M20, thereby further ensuring the accuracy of the driving current Id generated by the amplitude driving transistor M20.

[0111] Optional, continue to refer to Fig.19 The pulse width regulation module 10 also includes: a frequency sweeping reset unit 16; an input end of the frequency sweeping reset unit 16 receives a frequency sweeping reset signal Vswp1, a control end of the frequency sweeping reset unit 16 receives a first pulse width scanning signal PWM-S1, and an output end of the frequency sweeping reset unit 16 is electrically connected to a gate of the pulse width driving transistor M10 through a second storage unit 15; the frequency sweeping reset unit 16 is used to write the frequency sweeping reset signal Vswp1 to the second storage unit 15 under the control of the first pulse width scanning signal PWM-S1.

[0112] Specifically, the frequency sweep reset unit 16 is turned on or off under the control of the first pulse width sweep signal PWM-S1 , and writes the frequency sweep reset signal Vswp1 to the second storage unit 15 when turned on, so as to reset the second storage unit 15 .

[0113] For example, continue to refer to Fig.19 The sweep reset unit 16 includes a sweep reset transistor M16, the gate of the sweep reset transistor M16 receives the first pulse width scanning signal PWM-S1, the first electrode of the sweep reset transistor M16 receives the sweep reset signal Vswp1, and the second electrode of the sweep reset transistor M16 is electrically connected to the gate of the pulse width driving transistor M10 through the second storage capacitor C2. Fig.16 In the write compensation stage T3, the sweep frequency reset transistor M16 is turned on under the control of the first pulse width scanning signal PWM-S1, so that the sweep frequency reset signal Vswp1 is written to the second storage capacitor C2, thereby resetting the second storage capacitor C2, and ensuring the accuracy of the sweep frequency signal SWEEP written to the second storage capacitor C2 in the first time period T1.

[0114] Optional, Fig. 20 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Fig. 20 As shown, the amplitude adjustment module 20 also includes a light-emitting control unit 27, the control end of the light-emitting control unit 27 is electrically connected to the output end of the pulse width adjustment module 10, the input end of the light-emitting control unit 27 is electrically connected to the output end of the amplitude drive output unit 23, and the output end of the light-emitting control unit 27 is electrically connected to the light-emitting process control module 30; the light-emitting control module 50 is used to output a light-emitting drive signal to the light-emitting element D0 under the control of the pulse width adjustment signal. The pixel circuit 01 also includes a reset module 50, the input end of the reset module 50 receives a reset signal VSET, the control end of the reset module 50 receives a reset control signal SET, and the output end of the reset module 50 is electrically connected to the control end of the light-emitting control unit 27 and the output end of the pulse width adjustment module 10; the reset module 50 is used to output a reset signal VSET to the control end of the light-emitting control unit 27 under the control of the reset control signal SET.

[0115] Specifically, the light-emitting control unit 27 can be turned on or off according to the pulse width modulation signal, and when turned on, the light-emitting driving signal output by the amplitude drive output unit 23 is transmitted to the light-emitting process control module 30, and the pulse width modulation signal can be used to control the duration of the amplitude adjustment module 20 outputting the light-emitting driving signal. The reset module 50 can reset the signal at the control end of the light-emitting control unit 27 to ensure that the state of the light-emitting control unit 27 can be accurately controlled in the first time period T1.

[0116] Exemplary, reference Fig. 20, the light-emitting control unit 27 includes a light-emitting control transistor M29, the gate of which is electrically connected to the output end of the pulse width modulation module 10, the first electrode of which is electrically connected to the output end of the amplitude drive output unit 23, and the second electrode of which is electrically connected to the light-emitting process control module 30, so that the light-emitting control transistor M29 can be turned on or off under the control of the pulse width modulation module 10, and when turned on, transmits the light-emitting drive signal output by the amplitude drive output unit 23 to the light-emitting process control module 30. In this way, the light-emitting control point is changed from the gate of the amplitude drive transistor M20 to the independent light-emitting control transistor M29, which reduces the influence of a single node on the output drive current of the amplitude adjustment module 20 and improves the accuracy of the output drive current of the amplitude adjustment module 20.

[0117] The reset module 50 includes a reset transistor M51 and a fourth storage capacitor C4, the gate of the reset transistor M51 receives the reset control signal SET, the first electrode of the reset transistor M51 receives the reset signal VSET, and the second electrode of the reset transistor M51 is electrically connected to the control end of the light emitting control unit 27 and the output end of the pulse width modulation module 10, so that the reset transistor M51 can be turned on or off under the control of the reset control signal SET, and write the reset signal VSET to the gate of the light emitting control transistor M29 when turned on, and can reset the gate potential of the light emitting control transistor M29, so as to ensure the accuracy of the subsequent writing of the pulse width modulation signal, so as to ensure that the state of the light emitting control transistor M29 can be accurately controlled in the first time period T1. The first plate of the fourth storage capacitor C4 receives the reset signal VSET, and the second plate of the fourth storage capacitor C4 is electrically connected to the control end of the light emitting control unit 27 and the output end of the pulse width modulation module 10, so as to stabilize the gate potential of the light emitting control transistor M29.

[0118] For example, Fig.21 is another driving timing diagram of a pixel circuit provided by an embodiment of the present invention, and is combined with reference to Fig. 20 and Fig.21 In the reset stage T2, the reset transistor M51 is turned on under the control of the reset control signal SET, and the reset signal VSET is written to the gate of the light emitting control transistor M29. The reset signal VSET can be a low level signal, which can control the light emitting control transistor M29 to be in a conducting state. The working principle of the write compensation stage T3 is the same as the working principle of the write compensation stage T3 in the above embodiment, which will not be repeated here. In the first time period T1, Fig.17 and Fig. 20The difference is that the pulse width modulation signal output by the pulse width modulation module 10 is provided to the gate of the light emitting control transistor M29, and the sweep signal SWEEP gradually changes from the second sweep voltage Vswp2 to the first sweep voltage Vswp1 until time ta, after the coupling amount of the sweep signal SWEEP pulls down the gate signal of the pulse width driving transistor M10 to meet the conduction condition of the pulse width driving transistor M10, the pulse width voltage signal PWM-VDD can be provided to the gate of the light emitting control transistor M29 in the amplitude adjustment module 20 through the pulse width voltage input transistor M13, the pulse width driving transistor M10 and the pulse width control output transistor M14 in sequence, so that the gate potential of the light emitting control transistor M29 is instantly pulled up, so that the light emitting control transistor M29 is turned off and cannot transmit the driving current Id generated by the amplitude driving transistor M20, that is, the driving current Id′ received by the light emitting element D0 jumps to zero (non-enable signal) at time ta and remains zero in the subsequent stage, so that the light emitting element D0 stops emitting light. At the same time, the pulse width light emitting signal PWM-EM and the amplitude light emitting signal PAM-EM jump to the non-enable level at the time tg, so the driving current Id generated by the amplitude driving transistor M20 in the stage ta~tg remains as the enable signal until the amplitude light emitting signal PAM-EM jumps to the non-enable level at the time tg, and the driving current Id generated by the amplitude driving transistor M20 jumps from the enable signal to the non-enable signal. Among them, the reset control signal SET can reuse the second pulse width scanning signal PWM-S2 or the second amplitude scanning signal PAM-S2, which can reduce the number of signals and simplify the circuit structure of the display panel.

[0119] Based on the same inventive concept, an embodiment of the present invention further provides a display panel, the display panel comprising a pixel circuit provided by any embodiment of the present invention, Fig. 22 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention, such as Fig. 22 As shown, a plurality of pixel circuits are arranged in an array in the display panel 02. Therefore, the display panel provided in the embodiment of the present invention includes the technical features of the pixel circuit provided in any embodiment of the present invention, and can achieve the beneficial effects of the pixel circuit provided in any embodiment of the present invention. For the similarities, reference can be made to the above description of the pixel circuit provided in the embodiment of the present invention, which will not be repeated here.

[0120] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes a display panel provided by any embodiment of the present invention. Therefore, the display device provided by the embodiment of the present invention includes the technical features of the display panel provided by any embodiment of the present invention, and can achieve the beneficial effects of the display panel provided by any embodiment of the present invention. The similarities can be referred to the above description of the display panel provided by the embodiment of the present invention, and will not be repeated here.

[0121] Fig.23It is a structural schematic diagram of a display device provided in an embodiment of the present invention. The display device 03 can be any electronic product with a display function, including but not limited to the following categories: vehicle-mounted displays, VR displays, televisions, laptops, desktop displays, tablet computers, digital cameras, mobile phones, smart bracelets, smart glasses, vehicle-mounted displays, medical equipment, industrial control equipment, touch interactive terminals, etc.

[0122] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0123] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A pixel circuit, characterized in that: include: Pulse width adjustment module, amplitude adjustment module, light emitting process control module and light emitting element; The pulse width modulation module at least receives the pulse width light emission signal for outputting a pulse width modulation signal; The amplitude adjustment module is electrically connected to the pulse width adjustment module, the amplitude adjustment module at least receives the amplitude light emitting signal for outputting the light emitting driving signal, and the amplitude adjustment module also receives the pulse width adjustment signal for controlling the pulse width of the light emitting driving signal; The light-emitting process control module is at least electrically connected to the amplitude adjustment module; the light-emitting process control module at least receives the light-emitting process control signal, and is used to control the transmission path of the light-emitting drive signal to the light-emitting element; The time period in which the pulse width light-emitting signal and the amplitude light-emitting signal are both at the enable level is the first time period; within the first time period, the light-emitting process control signal includes at least one non-enable level, so that the transmission path of the light-emitting drive signal to the light-emitting element is in the off state; the time length of the non-enable level is less than the time length of the first time period.

2. The pixel circuit according to claim 1, characterized in that: The light emitting process control module includes a switch unit and a light emitting process control unit; The light-emitting process control unit is electrically connected to the control end of the switch unit, and the light-emitting process control unit receives a light-emitting process control signal; the light-emitting process control unit is used to output a switch control signal at least according to the light-emitting process control signal; The switch unit is at least electrically connected to the amplitude adjustment module; the switch unit is used to be turned on or off according to the switch control signal, and transmit the light-emitting drive signal to the light-emitting element when turned on.

3. The pixel circuit according to claim 2, characterized in that: The first end of the switch unit is electrically connected to the output end of the amplitude adjustment module, and the second end of the switch unit is electrically connected to the light emitting element.

4. The pixel circuit according to claim 2, characterized in that: The amplitude adjustment module includes: an amplitude data writing unit, an amplitude voltage input unit, an amplitude driving transistor and an amplitude driving output unit; The input end of the amplitude data writing unit receives the amplitude data signal, the control end of the amplitude data writing unit receives the first amplitude scanning signal, and the output end of the amplitude data writing unit is electrically connected to the gate of the amplitude driving transistor; the amplitude data writing unit is used to write the amplitude data signal to the gate of the amplitude driving transistor under the control of the first amplitude scanning signal; The input end of the amplitude voltage input unit receives the amplitude voltage signal, the control end of the amplitude voltage input unit receives the amplitude light emitting signal, and the output end of the amplitude input unit is electrically connected to the first electrode of the amplitude driving transistor; the amplitude voltage input unit is used to transmit the amplitude voltage signal to the first electrode of the amplitude driving transistor under the control of the amplitude light emitting signal; The gate of the amplitude driving transistor is also electrically connected to the pulse width modulation module, the second electrode of the amplitude driving transistor is electrically connected to the input end of the driving output unit, and the amplitude driving transistor outputs the light emitting driving signal according to the amplitude data signal, the amplitude voltage signal and the pulse width modulation signal; The control end of the amplitude drive output unit receives the amplitude light-emitting signal, and the output end of the amplitude drive output unit is used to output the light-emitting drive signal.

5. The pixel circuit according to claim 4, characterized in that: The first end of the switch unit is electrically connected to the output end of the amplitude voltage input unit, and the second end of the switch unit is electrically connected to the first electrode of the amplitude driving transistor.

6. The pixel circuit according to claim 4, characterized in that: The first end of the switch unit is electrically connected to the second electrode of the amplitude driving transistor, and the second end of the switch unit is electrically connected to the input end of the amplitude driving output unit.

7. The pixel circuit according to claim 2, characterized in that: The switch unit includes a switch transistor; The first electrode of the switch transistor is electrically connected to the first end of the switch unit, the second electrode of the switch transistor is electrically connected to the second end of the switch unit, and the gate of the switch transistor is electrically connected to the light emitting process control unit.

8. The pixel circuit according to claim 2, characterized in that: The light emitting process control unit includes a first light emitting process control transistor, a second light emitting process control transistor, a third light emitting process control transistor and a fourth light emitting process control transistor; The gate of the first light emitting process control transistor and the gate of the second light emitting process control transistor both receive the light emitting process control signal, the first electrode of the first light emitting process control transistor and the first electrode of the second light emitting process control transistor both receive a first voltage signal, the second electrode of the first light emitting process control transistor is electrically connected to the first control node, and the second electrode of the second light emitting process control transistor is electrically connected to the control end of the switch unit; The first electrode and the gate of the third light emitting process control transistor both receive a second voltage signal, and the second electrode of the third light emitting process control transistor is electrically connected to the first control node; The gate of the fourth light emitting process control transistor is electrically connected to the first control node, the first electrode of the fourth light emitting process control transistor receives the second voltage signal, and the second electrode of the fourth light emitting process control transistor is electrically connected to the control end of the switch unit.

9. The pixel circuit according to any one of claim 2, characterized in that: The light emitting process control unit includes a fifth light emitting process control transistor and a sixth light emitting process control transistor; The gates of the fifth light emitting process control transistor and the sixth light emitting process control transistor both receive the light emitting process control signal; The first electrode of the fifth light emitting process control transistor receives the first voltage signal, and the second electrode of the fifth light emitting process control transistor is electrically connected to the control end of the switch unit; The first electrode of the sixth light emitting process control transistor receives the second voltage signal, and the second electrode of the sixth light emitting process control transistor is electrically connected to the control end of the switch unit; The fifth light emission control transistor and the sixth light emission control transistor have different channel types.

10. The pixel circuit according to claim 2, characterized in that: The light emitting process control unit includes a seventh light emitting process control transistor and an eighth light emitting process control transistor; the channel type of the seventh light emitting process control transistor is the same as the channel type of the eighth light emitting process control transistor; The lighting process control signal includes a first lighting process control signal and a second lighting process control signal, and the first lighting process control signal and the second lighting process control signal have different polarities; The gate of the seventh light emitting process control transistor receives the first light emitting process control signal, the first electrode of the seventh light emitting process control transistor receives the first voltage signal, and the second electrode of the seventh light emitting process control transistor is electrically connected to the control end of the switch unit; The gate of the eighth light emitting process control transistor receives the second light emitting process control signal, the first electrode of the eighth light emitting process control transistor receives the second voltage signal, and the second electrode of the eighth light emitting process control transistor is electrically connected to the control end of the switch unit.

11. The pixel circuit according to claim 1, characterized in that: In the first time period, the light emitting process control signal includes N valid pulses; N ≥ 2 and N is an integer; The light emitting process control signal between two adjacent effective pulses is at the non-enable level.

12. The pixel circuit according to claim 11, characterized in that: In the first time period, the duration of the non-enable level of the light emitting process signal is shorter than the pulse width of the effective pulse.

13. The pixel circuit according to claim 4, characterized in that: The amplitude adjustment module also includes: an amplitude resetting unit and a first storage unit; The input end of the amplitude reset unit receives an amplitude reset signal, the control end of the amplitude reset unit receives a second amplitude scanning signal, and the output end of the amplitude reset unit is electrically connected to the gate of the amplitude driving transistor; the amplitude reset unit is used to be turned on or off according to the second amplitude scanning signal, and transmit the amplitude reset signal to the gate of the amplitude driving transistor when turned on; A first terminal of the first storage unit receives the amplitude voltage signal, and a second terminal of the first storage unit is electrically connected to the gate of the amplitude driving transistor.

14. The pixel circuit according to claim 1, characterized in that: Also includes: Light emitting reset module; The input end of the light-emitting reset module receives a light-emitting reset signal, the control end of the light-emitting reset module receives a light-emitting scanning signal, and the output end of the light-emitting reset module is electrically connected to the light-emitting element; the light-emitting reset module is used to transmit the light-emitting reset signal to the light-emitting element under the control of the light-emitting scanning signal.

15. The pixel circuit according to claim 1, characterized in that: The pulse width modulation module includes: a pulse width driving transistor, a pulse width data writing unit, a pulse width voltage input unit and a pulse width control output unit; The input end of the pulse width data writing unit receives the pulse width data signal, the control end of the pulse width data writing unit receives the first pulse width scanning signal, and the output end of the pulse width data writing unit is electrically connected to the gate of the pulse width driving transistor; the pulse width data writing unit is used to write the pulse width data signal to the gate of the pulse width driving transistor under the control of the first pulse width scanning signal; The input end of the pulse width voltage input unit receives the pulse width voltage signal, the control end of the pulse width voltage input unit receives the pulse width light emitting signal, and the output end of the pulse width voltage input unit is electrically connected to the first electrode of the pulse width driving transistor; the pulse width voltage input unit is used to transmit the pulse width voltage signal to the first electrode of the pulse width driving transistor under the control of the pulse width light emitting signal; The gate of the pulse width driving transistor also receives a frequency sweep signal, and the second electrode of the pulse width driving transistor is electrically connected to the pulse width control output unit; the pulse width driving transistor is used to output a pulse width adjustment signal to the pulse width control output unit according to the frequency sweep signal, the pulse width data signal and the pulse width voltage signal; The control end of the pulse width control output unit receives the pulse width light emitting signal, and the output end of the pulse width control output unit is electrically connected to the amplitude regulating module; the pulse width control output unit is used to output a pulse width regulating signal to the amplitude regulating module under the control of the pulse width light emitting signal.

16. The pixel circuit according to claim 15, characterized in that: The pulse width modulation module further includes: a pulse width resetting unit and a second storage unit; The input end of the pulse width reset unit receives a pulse width reset signal, the control end of the pulse width reset unit receives a second pulse width scan signal, and the output end of the pulse width reset unit is electrically connected to the gate of the pulse width driving transistor; the pulse width reset unit is used to write the pulse width reset signal to the gate of the pulse width driving transistor under the control of the second pulse width scan signal; A first end of the second storage unit receives the frequency sweep signal, and a second end of the second storage unit is electrically connected to the gate of the pulse width driving transistor.

17. A display panel, characterized in that: The pixel circuit comprises the pixel circuit according to any one of claims 1 to 16.

18. A display device, characterized in that: Comprising the display panel as claimed in claim 17.

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