Array substrate, display driver, display screen module and terminal

Abstract

The embodiment of the invention provides an array substrate, a display driver, a display screen module and a terminal, relates to the technical field of electronics, and aims to provide a terminal capable of improving a display effect or reducing power consumption. The array substrate comprises two groups of parallel light-emitting driving array circuits, and the two groups of parallel light-emitting driving array circuits respectively output an anti-creeping control signal and a light-emitting duty ratio control signal. However, the two groups of light-driven array circuits are controlled by clock signals with different frequencies, so that the frequencies of the anti-creeping control signal and the light-emitting duty ratio control signal are decoupled, and the display effect and the power consumption are decoupled. The controlled clock frequency of the light-emitting duty ratio control signal is adjusted to be smaller than the controlled clock frequency of the anti-creeping control signal, the display effect can be improved under the condition that power consumption is not increased, and power consumption can be reduced under the condition that the display effect is guaranteed.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to an array substrate, a display driver, a display screen module, and a terminal. Background Art

[0002] At present, in the process of displaying images on a self-luminous display screen, a scanning drive circuit arranged in a non-display area needs to provide a scanning signal and a light-emitting control signal, and cooperate with a data drive circuit to provide an image data signal to drive a pixel circuit arranged in an effective display area to perform image display. In recent years, in order to improve the integration of display screens, a gate scanning drive circuit, a light-emitting scanning drive circuit and a pixel array are fabricated together on an array substrate, which are often referred to as gate drive array (GOA) circuits and light-emitting drive array (EOA) circuits in the art.

[0003] The image display of the display screen is affected by the GOA circuit and the EOA circuit, so the display effect and power consumption of the display screen are also affected by the GOA circuit and the EOA circuit, especially the EOA circuit has a more obvious impact on the display effect and power consumption of the display screen. How to improve the display effect without increasing power consumption, or reduce power consumption while ensuring the display effect, is a technical problem that technicians in this field are trying to solve. Summary of the invention

[0004] The embodiments of the present application provide an array substrate, a display driver, a display screen module, and a terminal, which are used to provide a terminal that can improve display effects without increasing power consumption, or reduce power consumption while ensuring display effects.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] According to a first aspect of an embodiment of the present application, an array substrate is provided, on which a light-emitting unit may be provided or not provided. The array substrate comprises: a first light-emitting drive array circuit, a second light-emitting drive array circuit and a pixel circuit. The first light-emitting drive array circuit comprises a first clock signal terminal, a second clock signal terminal, a starting anti-leakage control signal terminal and a first output terminal, and is used to generate an anti-leakage control signal according to a first clock signal received by the first clock signal terminal, a second clock signal received by the second clock signal terminal and a starting anti-leakage control signal received by the starting anti-leakage control signal terminal. The second light-emitting drive array circuit comprises a third clock signal terminal, a fourth clock signal terminal, a starting light-emitting duty cycle control signal terminal and a second output terminal, and is used to generate a light-emitting duty cycle control signal according to a third clock signal received by the third clock signal terminal, a fourth clock signal received by the fourth clock signal terminal and a starting light-emitting duty cycle control signal received by the starting light-emitting duty cycle control signal terminal. The pixel circuit comprises a light-emitting control signal terminal; the light-emitting control signal terminal is used to receive an anti-leakage control signal to prevent leakage of a data voltage. The light-emitting control signal terminal is also used to receive a light-emitting duty cycle control signal to drive the light-emitting unit to emit light. Wherein, f1 is the frequency of the first clock signal and the second clock signal, f2 is the frequency of the third clock signal and the fourth clock signal, and f2 <f1。

[0007] The array substrate provided in the embodiment of the present application controls the first light-emitting drive array circuit by a clock signal of a first frequency, and controls the second light-emitting drive array circuit by a clock signal of a second frequency, so that the frequency of the anti-leakage control signal and the frequency of the light-emitting duty cycle control signal are decoupled, so that the frequency of the light-emitting duty cycle control signal can be independently regulated while the anti-leakage control signal matches the screen refresh frequency, thereby achieving decoupling of display effect and power consumption. By setting the second frequency to be less than the first frequency, the frequency (propagation speed) of the light-emitting duty cycle control signal can be reduced, and the bright and dark space period of the display screen using the array substrate can be increased, so as to achieve improved display effect without increasing power consumption, and also reduce power consumption while ensuring display effect.

[0008] In addition, by reducing the frequency of the light-emitting duty cycle control signal, the switching frequency requirements that the pixel circuit in the array substrate can withstand can be reduced, so that some array substrates that cannot meet high-frequency switching requirements meet the requirements and reduce the yield loss of the array substrate.

[0009] In one possible implementation, the array substrate also includes a logic operation circuit; the input end of the logic operation circuit is coupled to the first output end and the second output end, and the output end is coupled to the light-emitting control signal end, and is used to perform logic operations on the anti-leakage control signal and the light-emitting duty cycle control signal, and output the operation result as the light-emitting control signal to the light-emitting control signal end.

[0010] By performing a logical operation on the anti-leakage control signal and the light-emitting duty cycle control signal and then outputting them to the light-emitting control signal terminal, the light-emitting control signal terminal only receives one final light-emitting control signal. Then, the structure of the pixel circuit in the array substrate does not need to be modified, and the pixel circuits in the related art are all applicable to the embodiments of the present application, which can reduce the workload of modification. Moreover, if only one light-emitting control signal is output, only one output switch needs to be set, and the width of the frame does not increase.

[0011] In a possible implementation, the value of f2 / f1 is 1 / 5 to 3 / 4, which is a value range applicable to range light.

[0012] In a possible implementation, the value of f2 / f1 is 1 / 3 to 1 / 2. If the second frequency is too small, the user will see the black bar moving, affecting the display effect. If the second frequency is too large, the power will increase. Therefore, setting the second frequency in the range of 1 / 3 to 1 / 2 of the first frequency can ensure the display effect with lower power consumption.

[0013] In a possible implementation, the logic operation circuit includes an OR operation circuit. This is an implementation with a simple structure.

[0014] In a possible implementation, the logic operation circuit includes an AND operation circuit. This is an implementation with a simple structure.

[0015] In a possible implementation, the first light-emitting driving array circuit includes a plurality of cascaded first light-emitting driving units, the first-stage first light-emitting driving units are coupled to the starting anti-leakage control signal terminal, and each stage of the first light-emitting driving units are coupled to the first clock signal terminal and the second clock signal terminal; the second light-emitting driving array circuit includes a plurality of cascaded second light-emitting driving units, the first-stage second light-emitting driving units are coupled to the starting light-emitting duty cycle control signal terminal, and each stage of the second light-emitting driving units are coupled to the third clock signal terminal and the fourth clock signal terminal. This is a simple implementation.

[0016] In a possible implementation, the array substrate includes a plurality of pixel circuits arranged in an array; the logic operation circuit includes a plurality of logic operation units, the input end of the logic operation unit is correspondingly coupled to the first output end of the first light-emitting driving unit and the second output end of the second light-emitting driving unit located at the same level, and the light-emitting control signal end of the pixel circuit located at the same row is coupled to the output end of the same logic operation unit. This is a simple implementation.

[0017] In a possible implementation, the light-emitting control signal terminals of the pixel circuits located in multiple rows are coupled to the output terminals of the same logic operation unit. In this way, the pixel circuits in multiple rows share the same set of logic operation units, first light-emitting driving units, and second light-emitting driving units, which can reduce the number of devices in the non-display area, save costs, and facilitate the realization of a narrow border.

[0018] In a second aspect of the embodiments of the present application, a display driver is provided, including: a timing circuit and a starting light-emitting control signal generation circuit; the timing circuit is used to generate a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, f1 is the frequency of the first clock signal and the second clock signal, f2 is the frequency of the third clock signal and the fourth clock signal, and f2 < f1; the starting light-emitting control signal generation circuit is used to generate a starting anti-leakage control signal and a starting light-emitting duty ratio control signal. The beneficial effects of the display driver provided in the second aspect of the embodiments of the present application are the same as those of the array substrate provided in the first aspect, and will not be elaborated here.

[0019] In a possible implementation, the value of f2 / f1 is from 1 / 5 to 3 / 4.

[0020] In a possible implementation, the value of f2 / f1 is from 1 / 3 to 1 / 2.

[0021] In a third aspect of the embodiments of the present application, a display screen module is provided, including an array substrate and a display driver, and the display driver is bonded to the array substrate; the array substrate includes the array substrate according to any one of the first aspect; and / or, the display driver includes the display driver according to any one of the second aspect.

[0022] In a fourth aspect of the embodiments of the present application, a terminal is provided, including a housing and a display screen module, and the display screen module is disposed in the housing; the display screen module includes the display screen module according to the third aspect. Description of the Drawings

[0023] Figure 1A It is an architecture diagram of an electronic device provided by the embodiments of the present application;

[0024] Figure 1B It is a schematic diagram of a display screen module provided by the embodiments of the present application;

[0025] Figure 2 It is a circuit schematic diagram of a sub-pixel provided by the embodiments of the present application;

[0026] Figure 3 It is a driving timing diagram of a pixel circuit provided by the embodiments of the present application;

[0027] Figure 4A-4CA schematic diagram of the on-off state of a transistor in a pixel circuit driving process provided by an embodiment of the present application;

[0028] Figure 5 A waveform diagram of a light-emitting control signal provided in an embodiment of the present application;

[0029] Figure 6 It is the brightness distribution diagram of the display screen at a certain moment in a frame;

[0030] Figure 7 A schematic diagram of the layout of an array substrate provided in an embodiment of the present application;

[0031] Figure 8 A waveform diagram of an anti-leakage control signal and a light-emitting duty cycle control signal provided in an embodiment of the present application;

[0032] Fig. 9 Provide waveform diagrams of a first timing signal, a second timing signal, a third timing signal, and a fourth timing signal in an embodiment of the present application;

[0033] Fig.10 It is the brightness distribution diagram of the display screen at a certain moment in a frame;

[0034] Figure 11A-Figure 12 A schematic diagram of the layout of an array substrate provided in an embodiment of the present application;

[0035] Fig.13 A schematic diagram of the structure of a display screen module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0037] In the following, the terms "second", "first", etc. are used only for convenience of description and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "second", "first", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0038] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0039] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. In addition, the term "coupled" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be a direct contact or an indirect contact through an intermediate medium.

[0040] In the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0041] The present application embodiment provides a terminal. The terminal is, for example, a consumer electronic product with a display function, a home electronic product, a car-mounted electronic product, or a financial terminal product. Consumer electronic products include mobile phones, tablet computers, laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) terminals, augmented reality (AR) terminals, drones, etc. Home electronic products include smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (e.g., soybean milk machines, sweeping robots), etc. Car-mounted electronic products include car navigators, car-mounted high-density digital video discs (DVDs), etc. Financial terminal products include automated teller machines (ATMs), self-service terminals, etc. The present application embodiment does not impose any special restrictions on the specific form of the above-mentioned terminals.

[0042] Figure 1A This is an architecture diagram of a terminal 1 provided in an embodiment of the present application. Figure 1B A schematic diagram of a display screen module 3 provided in an embodiment of the present application.

[0043] Take the mobile phone as an example. Figure 1AAs shown, the terminal 1 mainly includes a cover plate 2, a display screen module 3, a middle frame 4 and a rear shell 5. The rear shell 5 and the display screen module 3 are respectively located on both sides of the middle frame 4, and the middle frame 4 and the display screen module 3 are arranged in the rear shell 5, the cover plate 2 is arranged on a side of the display screen module 3 away from the middle frame 4, and the display surface of the display screen module 3 faces the cover plate 2. Figure 1A In the figure, the terminal 1 is taken as an example of a straight screen mobile phone. The terminal 1 in the embodiment of the present application may also be a folding screen mobile phone. Figure 1A The figure is for illustration only.

[0044] In some embodiments, Figure 1B As shown, the display screen module 3 includes a display screen and a display driver 20. The display screen can be an organic light emitting diode (OLED) display screen, which can realize self-luminescence. The display screen can also be a mini organic light emitting diode (micro OLED) display screen. The display screen includes an effective display area (AA) and a non-display area BB located around the effective display area AA, and the effective display area AA is used to display images. The display screen can include one effective display area AA, and the display screen can also include multiple effective display areas AA.

[0045] The display screen includes an array substrate 10, and the effective display area AA of the display screen is the effective display area of ​​the array substrate 10. The array substrate 10 includes a plurality of sub-pixels (SP), each of which is provided with a pixel circuit 11 and a light-emitting unit 12, the pixel circuit 11 is used to drive the light-emitting unit 12 to emit light, and the light-emitting unit 12 may be, for example, an OLED.

[0046] In the present application, the sub-pixel SP array arrangement is taken as an example for description, and the sub-pixels SP arranged in a row along the horizontal direction X are called the same row of sub-pixels SP, and the pixel circuits 11 in the same row of sub-pixels SP are called a row of pixel circuits 11. The sub-pixels SP arranged in a row along the vertical direction Y are called the same column of sub-pixels SP, and the pixel circuits 11 in the same column are called a column of pixel circuits 11.

[0047] The display driver 20 may be a display driver integrated circuit (DDIC). In this case, the display driver 20 may be bonded to the array substrate 10 via a pad disposed in the non-display area BB of the array substrate 10 .

[0048] The display driver 20 may be coupled to a system on chip (SOC) via a mobile industry processor interface (MIPI) interface. Of course, the display driver 20 may also be coupled to the SOC via other serial / deserial (SerDes) high-speed interfaces, and the SOC is used to provide image data to the display driver 20.

[0049] The display driver 20 is used to provide the array substrate 10 with a scanning start signal, a timing signal and a data signal required for the display screen to emit light. The signals sent by the display driver 20 will be described in detail later in conjunction with the structure of the pixel circuit 11 and will not be described here for the time being.

[0050] In some embodiments, the pixel circuit 11 generally includes a plurality of transistors, and the pixel circuit 11 generates a driving current to drive the light-emitting unit 12 to emit light, so as to realize the light emission of the sub-pixel SP.

[0051] In some embodiments, the array substrate 10 includes a light emitting unit 12 , and the array substrate 10 may be equivalent to a display screen of the terminal 1 .

[0052] In some other embodiments, the array substrate 10 does not include the light emitting unit 12 , and the array substrate 10 and the light emitting unit 12 are assembled to form a display screen of the terminal 1 .

[0053] Figure 2 A schematic diagram of a sub-pixel circuit provided in an embodiment of the present application.

[0054] In some embodiments, Figure 2 As shown, the pixel circuit 11 includes an anode reset circuit 111 , a first node initialization circuit 112 , a writing and threshold compensation circuit 113 and a light emitting control circuit 114 . Figure 2 The pixel circuit 11 shown is only for illustration and is not intended to be limiting.

[0055] The anode reset circuit 111 is coupled to the first initialization voltage terminal Vinit1, the first scan signal terminal S1 and the output terminal of the pixel circuit 11 (the anode of the light-emitting unit 12), and is used to transmit the first initialization voltage of the first initialization voltage terminal Vinit1 to the anode of the light-emitting unit 12 under the control of the first scan signal s1 of the first scan signal terminal S1, so as to initialize the anode of the light-emitting unit 12.

[0056] The first node initialization circuit 112 is coupled to the second initialization voltage terminal Vinit2, the second scan signal terminal S2, the third scan signal terminal S3, the first node N1 and the second node N2, and is used to transmit the second initialization voltage of the second initialization voltage terminal Vinit2 to the first node N1 and the second node N2 under the control of the second scan signal s2 of the second scan signal terminal S2 and the third scan signal s3 of the third scan signal terminal S3, so as to initialize the first node N1 and the second node N2.

[0057] The write and threshold compensation circuit 113 is coupled to the fourth scan signal terminal S4, the third scan signal terminal S3, the second node N2, the first power supply voltage terminal ELVDD and the data voltage terminal Vdata, and is used to transmit the data voltage of the data voltage terminal Vdata to the write and threshold compensation circuit 113 under the control of the fourth scan signal s4 of the fourth scan signal terminal S4 and the third scan signal s3 of the third scan signal terminal S3, for data writing and threshold compensation.

[0058] The light emitting control circuit 114 is coupled to the light emitting control signal terminal EM, the first power supply voltage terminal ELVDD, the writing and threshold compensation circuit 113 and the light emitting unit 12, and is used to provide a driving current to the light emitting unit 12 under the control of the light emitting control signal provided by the light emitting control signal terminal EM.

[0059] The light emitting unit 12 is coupled to the second power supply voltage terminal ELVSS, and is configured to emit light under the driving of the driving current.

[0060] In the embodiment of the present application, the first power supply voltage terminal ELVDD is a high-level power supply voltage terminal, and the second power supply voltage terminal ELVSS is a low-level power supply voltage terminal for illustration, but this is not limiting.

[0061] In some embodiments, reference Figure 2 , the pixel circuit 11 includes 7 transistors and 1 storage capacitor, which is commonly referred to as a 7T1C pixel circuit in the art. The anode reset circuit 111 includes a seventh transistor T7, the first node initialization circuit 112 includes a fourth transistor T4 and a third transistor T3, the write and threshold compensation circuit 113 includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst, and the light emitting control circuit 114 includes a fifth transistor T5 and a sixth transistor T6. The first transistor T1 is a driving transistor, and the remaining transistors are switch transistors. The first node initialization circuit 112 and the write and threshold compensation circuit 113 share the third transistor T3.

[0062] In the following description, the control electrode of the transistor may be, for example, the gate electrode of the transistor, and the first electrode of the transistor and the second electrode of the transistor may be the source electrode and the drain electrode of the transistor, respectively. This is explained here and will not be further explained below.

[0063] A control electrode of the fourth transistor T4 is coupled to the second scan signal terminal S2 , a first electrode of the fourth transistor T4 is coupled to the second initialization voltage terminal Vinit2 , and a second electrode of the fourth transistor T4 is coupled to the fourth node N4 .

[0064] A control electrode of the third transistor T3 is coupled to the third scan signal terminal S3 , a first electrode of the third transistor T3 is coupled to the fourth node N4 , and a second electrode of the third transistor T3 is coupled to the first node N1 .

[0065] A control electrode of the second transistor T2 is coupled to the fourth scan signal terminal S4 , a first electrode of the second transistor T2 is coupled to the data voltage terminal Vdata, and a second electrode of the second transistor T2 is coupled to the third node N3 .

[0066] The control electrode of the first transistor T1 is coupled to the first node N1, the first electrode of the first transistor T1 is coupled to the third node N3, the second electrode of the first transistor T1 is coupled to the second node N2, and the second node N2 is also coupled to the fourth node N4.

[0067] One end of the storage capacitor Cst is coupled to the first node N1 , and the other end of the storage capacitor Cst is coupled to the first power voltage terminal ELVDD.

[0068] A control electrode of the fifth transistor T5 is coupled to the light emitting control signal terminal EM, a first electrode of the fifth transistor T5 is coupled to the first power supply voltage terminal ELVDD, and a second electrode of the fifth transistor T5 is coupled to the third node N3.

[0069] A control electrode of the sixth transistor T6 is coupled to the light emitting control signal terminal EM, a first electrode of the sixth transistor T6 is coupled to the second node N2 , and a second electrode of the sixth transistor T6 is coupled to the anode of the light emitting unit 12 .

[0070] A control electrode of the seventh transistor T7 is coupled to the first scan signal terminal S1 , a first electrode of the seventh transistor T7 is coupled to the first initialization voltage terminal Vinit1 , and a second electrode of the seventh transistor T7 is coupled to the anode of the light emitting unit 12 .

[0071] A control electrode of the eighth transistor T8 is coupled to the first scan signal terminal S1 , a first electrode of the eighth transistor T8 is coupled to the second initialization voltage terminal Vinit2 , and a second electrode of the eighth transistor T8 is coupled to the second node N2 .

[0072] For example, in the pixel circuit 11, the third transistor T3 and the fourth transistor T4 are oxide TFTs, which are N-type transistors and are turned on under the control of a high-level signal. The third transistor T3 and the fourth transistor T4 can also be other types of transistors, which are not limited in the embodiments of the present application. The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are LTPS TFTs, which are P-type transistors and are turned on under the control of a low-level signal. The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 can also be other types of transistors, which are not limited in the embodiments of the present application.

[0073] Figure 3 A driving timing diagram of a pixel circuit provided in an embodiment of the present application, Figure 4A-4C A schematic diagram of the on-off state of a transistor during a pixel circuit driving process provided in an embodiment of the present application.

[0074] Combination Figure 3 and Figure 4A-4C As shown, the light emitting process of the pixel circuit 11 in one frame can be divided into an initialization phase t1 , a writing and compensation phase t2 , and a light emitting phase t3 .

[0075] In the initialization phase t1:

[0076] like Figure 3 and Figure 4A As shown, the second scanning signal s2 of the second scanning signal terminal S2 and the third scanning signal s3 of the third scanning signal terminal S3 change from high level to low level and then from low level to high level. Thus, the fourth transistor T4 and the third transistor T3 change from off to on and then from on to off.

[0077] The first scan signal s1 of the first scan signal terminal S1, the fourth scan signal s4 of the fourth scan signal terminal S4 and the light control signal em of the light control signal terminal EM all maintain a high level, so the seventh transistor T7, the eighth transistor T8, the second transistor T2, the fifth transistor T5 and the sixth transistor T6 all remain in the off state.

[0078] In the initialization stage t1, the first transistor T1, the third transistor T3 and the fourth transistor T4 are turned on respectively, and the voltage control of the fourth node N4, the voltage control of the second node N2 and the voltage control of the first node N1 are realized. Since the third transistor T3 and the fourth transistor T4 are respectively used as switch tubes, the first node N1 is electrically connected to the control electrode of the first transistor T1, and the second node N2 is electrically connected to the fourth node N4, so in the initialization stage t1, the control electrode voltage control of the first transistor T1, the voltage control of the node N1, the voltage control of the second node N2 and the voltage control of the fourth node N4 are realized, so that the control electrode voltage of the first transistor T1, the voltage of the first node N1, the voltage of the second node N2 and the voltage of the fourth node N4 are respectively the second initialization voltage of the second initialization voltage terminal Vinit2, that is, the control electrode voltage of the first transistor T1, the voltage of the first node N1, the voltage of the second node N2 and the voltage of the fourth node N4 are reset.

[0079] In the writing and compensation phase t2:

[0080] like Figure 3 and Figure 4B As shown, the fourth scanning signal s4 of the fourth scanning signal terminal S4 changes from a high level to a low level, and then changes from a low level to a high level. Thus, the second transistor T2 changes from off to on, and then changes from on to off. The third scanning signal s3 of the third scanning signal terminal S3 changes from a low level to a high level, and then changes from a high level to a low level. Thus, the third transistor T3 changes from off to on, and then changes from on to off.

[0081] In the writing and compensation phase t2, the second transistor T2, the third transistor T3 and the first transistor T1 are turned on respectively, so that the data voltage of the data voltage terminal Vdata is stored in the storage capacitor Cst, and the writing of the data voltage is completed. The compensation of the threshold voltage of the first transistor T1 is also achieved. The compensation process of the threshold voltage of the first transistor T1 can be considered as the process of the first transistor T1 changing from the on state to the off state.

[0082] In the writing and compensation phase t2, the light emitting control signal em of the light emitting control signal terminal EM and the second scanning signal s2 of the second scanning signal terminal S2 are both kept at a high level. Therefore, the fifth transistor T5, the sixth transistor T6 and the fourth transistor T4 are all kept in the off state.

[0083] In some embodiments, the anode of the light emitting unit 12 is initialized at the same time during the writing and compensation phase t2. Of course, the anode of the light emitting unit 12 is initialized once or multiple times at any time before the light emitting phase t3.

[0084] For example, the first scanning signal s1 of the first scanning signal terminal S1 changes from a high level to a low level, and then changes from a low level to a high level. Thus, the seventh transistor T7 changes from off to on, and then changes from on to off.

[0085] The seventh transistor T7 is turned on, so as to control the anode voltage of the light emitting unit 12 , so that the anode voltage of the light emitting unit 12 is the first initialization voltage of the first initialization voltage terminal Vinit1 , and the anode voltage of the light emitting unit 12 is reset.

[0086] In the light-emitting phase t3:

[0087] like Figure 3 and Figure 4C As shown, the light emitting control signal em changes from high level to low level, and then changes from low level to high level. Thus, the sixth transistor T6 and the fifth transistor T5 change from off to on, and then from on to off.

[0088] The first scan signal s1 of the first scan signal terminal S1, the second scan signal s2 of the second scan signal terminal S2, the third scan signal s3 of the third scan signal terminal S3 and the fourth scan signal s4 of the fourth scan signal terminal S4 respectively maintain a high level, and the seventh transistor T7, the fourth transistor T4, the third transistor T3 and the second transistor T2 all remain in the off state.

[0089] In the light emitting stage t3 , the fifth transistor T5 , the first transistor T1 , and the sixth transistor T6 are turned on respectively to transmit the driving current to the light emitting unit 12 , and the light emitting unit 12 emits light under the driving current.

[0090] It can be known from the above description that the timing of the light-emitting control signal em of the light-emitting control signal terminal EM in one frame is: in the initialization stage t1 and the writing and compensation stage t2, the transistor in the light-emitting control circuit 114 is controlled to remain in the off state. In the writing and compensation stage t2, the light-emitting control signal em of the light-emitting control signal terminal EM controls the light-emitting control circuit 114 to be turned off, which can prevent the data voltage of the data voltage terminal Vdata from leaking to the first power supply voltage terminal ELVDD and / or the second power supply voltage terminal ELVSS. In the light-emitting stage t3, the light-emitting control signal em of the light-emitting control signal terminal EM controls the light-emitting control circuit 114 to be turned on, and the light-emitting brightness of the display screen can be adjusted by the duty cycle. The duty cycle of the light-emitting control signal em can be adjusted by pulse-width modulation (PWM) technology.

[0091] The following is a schematic description of the origins of the scan signals received by the first scan signal terminal S1 , the second scan signal terminal S2 , the third scan signal terminal S3 , the fourth scan signal terminal S4 , and the light emitting control signal terminal EM in the pixel circuit 11 .

[0092] like Figure 1B As shown, in some embodiments, the array substrate 10 further includes a light emitting drive array circuit EOA, and the light emitting drive array circuit EOA is used to transmit a light emitting control signal em to the light emitting control signal terminals EM of the plurality of pixel circuits 11 in the array substrate 10 .

[0093] In some embodiments, Figure 1B As shown, the light emitting drive array circuit EOA includes a plurality of cascaded light emitting drive units eoa, and each light emitting drive unit eoa is used to provide a light emitting control signal em for a row of pixel circuits 11.

[0094] Of course, two or more light emitting drive array circuits EOA may also be provided in the array substrate 10 , and each light emitting drive array circuit EOA is used to provide a light emitting control signal em for some pixel circuits 11 in a row.

[0095] Each level of the light-emitting driving unit eoa receives the first clock signal clk1 and the second clock signal clk2, and the first clock signal clk1 and the second clock signal clk2 are used to control the propagation speed of the light-emitting control signal em. The light-emitting driving unit eoa of the first level receives the starting light-emitting control signal STV-em, and outputs the light-emitting control signal em. Starting from the second level, the light-emitting driving unit eoa of each level receives the light-emitting control signal em output by the light-emitting driving unit EOA of the previous level, and outputs the light-emitting control signal em corresponding to the light-emitting driving unit eoa of the current level. Taking the effective display area AA including 10 rows of pixel circuits 11 as an example, the light-emitting driving array circuit EOA includes 10 levels of cascaded light-emitting driving units eoa, and the generated light-emitting control signal em includes the first level light-emitting control signal em1 to the tenth level light-emitting control signal em10.

[0096] In some embodiments, the start light emission control signal STV-em, the first clock signal clk1 and the second clock signal clk2 are provided by the display driver 20. The light emission drive array circuit EOA is used to receive the start light emission control signal STV-em and the first clock signal clk1 and the second clock signal clk2 sent by the display driver 20, and generate the light emission control signal em required by the pixel circuit 11.

[0097] Of course, one light-emitting driving unit eoa can provide a light-emitting control signal em for a row of pixel circuits 11, and one light-emitting unit eoa can also provide a light-emitting control signal em for multiple rows of pixel circuits 11 at the same time. Figure 1B This is only an illustration and is not intended to be limiting.

[0098] like Figure 1BAs shown, in some embodiments, the array substrate 10 further includes a first scanning array circuit 13. The first scanning array circuit 13 has a similar structure to the light emitting drive array circuit EOA and is used to transmit a first scanning signal s1 to each row of pixel circuits 11. The first scanning signal s1 generated by the first scanning array circuit 13 includes a first-level first scanning signal s1(1) to an n-th-level first scanning signal s1(n), where n is the number of rows of pixel circuits 11 in the effective display area AA. The starting first scanning signal STV-s1 required by the first scanning array circuit 13 is provided by the display driver 20.

[0099] For example, Figure 1B As shown, the first scanning signal s1 required by a row of pixel circuits 11 is provided by the first scanning array circuit 13 located at one side of the effective display area AA.

[0100] Alternatively, for example, the first scan signal s1 required for a row of pixel circuits 11 is provided by the first scan array circuits 13 located on both sides of the effective display area AA, and each first scan array circuit 13 provides the first scan signal s1 for, for example, half a row of pixel circuits 11 .

[0101] The array substrate 10 further includes a second scanning array circuit 14. The second scanning array circuit 14 has a similar structure to the light emitting drive array circuit EOA and is used to transmit a second scanning signal s2 to each row of pixel circuits 11. The second scanning signal s2 generated by the second scanning array circuit 14 includes a first-level second scanning signal s2(1) to an n-th-level second scanning signal s2(n). The start second scanning signal STV-s2 required by the second scanning array circuit 14 is provided by the display driver 20.

[0102] The array substrate 10 further includes a third scanning array circuit 15. The third scanning array circuit 15 has a similar structure to the light emitting drive array circuit EOA and is used to transmit a third scanning signal s3 to each row of pixel circuits 11. The third scanning signal s3 generated by the third scanning array circuit 15 includes a first-level third scanning signal s33(1) to an n-th-level third scanning signal s3(n). The start third scanning signal STV-s3 required by the third scanning array circuit 15 is provided by the display driver 20.

[0103] The array substrate 10 further includes a fourth scanning array circuit 16. The fourth scanning array circuit 16 has a structure similar to that of the light emitting drive array circuit EOA and is used to transmit a fourth scanning signal s4 to each row of pixel circuits 11. The fourth scanning signal s4 generated by the fourth scanning array circuit 16 includes a first-level fourth scanning signal s4(1) to an n-th-level fourth scanning signal s4(n). The start fourth scanning signal STV-s4 required by the fourth scanning array circuit 16 is provided by the display driver 20.

[0104] Each pixel circuit 11 cycles through the initialization phase t1, the writing and compensation phase t2, and the light-emitting phase t3, and is controlled by the light-emitting drive array circuit EOA, the first scanning array circuit 13, the second scanning array circuit 14, the third scanning array circuit 15, and the fourth scanning array circuit 16 located in the non-display area BB to perform frame-by-frame and line-by-line scanning.

[0105] In some embodiments, the clock signals required by the first scan array circuit 13, the second scan array circuit 14, the third scan array circuit 15 and the fourth scan array circuit 16 are also provided by the display driver 20. Figure 1B The required clock signal is not shown.

[0106] Figure 1B The structures of the light-emitting drive array circuit EOA, the first scanning array circuit 13, the second scanning array circuit 14, the third scanning array circuit 15 and the fourth scanning array circuit 16 and their arrangement positions in the array substrate 10 are only for illustration and are not limited in any way.

[0107] Figure 5 A waveform diagram of a light emitting control signal provided in an embodiment of the present application, Figure 6 It is the brightness distribution diagram of the display screen at a certain moment in a frame.

[0108] In some embodiments, the light emitting control signal em output by each light emitting driving unit eoa is as follows: Figure 5 As shown, in each frame, the light emitting control signal em has a first high level pulse A1, which is used to control the light emitting control circuit 114 to turn off, so as to prevent the data voltage at the data voltage terminal Vdata from leaking to the first power supply voltage terminal ELVDD and / or the second power supply voltage terminal ELVSS. The switching gap (toggle) between the first high level pulse A1 and the second high level pulse A2 is a duty cycle to adjust the light emitting brightness. For example Figure 5 The luminous brightness is adjusted by 4-pulse PWM.

[0109] Then, for example, if the screen refresh frequency of the display screen is 120 Hz, the frequency of the light emitting control signal em is 480 (4*120) Hz, and the frequency of any pixel circuit 11 in the light emitting stage t3 is 480 Hz. Figure 5 As shown, at any time, there are always 4 cycles of light-dark alternation in the display screen, that is, 4 cycles of the light control signal em alternating on and off. Figure 5 The vertical line in is the selected time line. Among the multiple lines of light control signals em in the display screen, 4 lines of light control signals em intersect with the time line, and the intersection of the 4 lines of light control signals em is a black stripe. Figure 6As shown, at any time, the entire display screen has 4 rows of black stripes, and the bright and dark spatial period of the display screen is 1 / 4*screen height, and the screen height is the size of the effective display area AA of the display screen in the column direction of the pixel circuit 11.

[0110] Since eye protection requires that the fluctuation of the luminous flux in the user's gaze range is as low as possible, this requires that the bright and dark spatial cycle of the display screen is as small as possible. At a certain frame rate and a certain propagation rate (the frequency of the clock signal is constant), the frequency of the light-emitting control signal em is required to be higher. In particular, the light-emitting control signal em not only controls whether the light-emitting unit 12 emits light, but also has the function of preventing pixel leakage during writing. However, the light-emitting control signal em is the input of a resistor-capacitor model, resulting in a higher switching frequency of the light-emitting control signal em, and a higher heat dissipation power consumption, which will result in a relatively large power consumption of the entire terminal 1.

[0111] For example, in order to achieve a better eye protection effect, if the bright and dark space period of the display screen is expected to be 1 / 12*screen height, and the screen refresh rate of the display screen is 120hz, then the frequency of the light control signal em needs to be 12*120hz=1440hz. This will cause the power consumption of the terminal 1 to increase, and because the light-emitting material in the light-emitting unit 12 includes parasitic capacitance, under the influence of the parasitic capacitance, the instantaneous light control signal em of the light-emitting unit 12 switch will have a slope and a decline. If the switching frequency is too high, the proportion of the slope and the decline is too large, which will affect the display effect.

[0112] In order to reduce power consumption, it is hoped that the frequency of the light control signal EM is 480 Hz. This will result in the bright and dark space period of the display screen being 1 / 4*screen height, and the eye protection effect is poor.

[0113] Based on this, the embodiment of the present application provides a terminal 1, which can reduce power consumption while achieving the same eye protection effect, and improve the eye protection effect at the same power consumption.

[0114] Figure 7 A schematic diagram of the layout of an array substrate provided in an embodiment of the present application.

[0115] The present application embodiment provides an array substrate 10, such as Figure 7 As shown, the array substrate 10 includes a pixel circuit 11, a first light emitting driving array circuit EOA1 and a second light emitting driving array circuit EOA2.

[0116] The first light emitting driving array circuit EOA1 is disposed in the non-display area BB of the array substrate 10 . For example, the first light emitting driving array circuit EOA1 is disposed on one side or both sides of the pixel circuit 11 array along the row direction of the pixel circuit 11 .

[0117] The second light emitting drive array circuit EOA2 is disposed in the non-display area BB of the array substrate 10 . For example, the second light emitting drive array circuit EOA2 is disposed on one side or both sides of the pixel circuit 11 array along the row direction of the pixel circuit 11 .

[0118] In some embodiments, the first light emitting driving array circuit EOA1 and the second light emitting driving array circuit EOA2 are located on the same side of the array of pixel circuits 11. This can simplify the wiring layout on the array substrate 10.

[0119] The first light-emitting drive array circuit EOA1 includes a first clock signal terminal CLK1, a second clock signal terminal CLK2, a starting anti-leakage control signal terminal STV-EM1, and a first output terminal OT1. The first clock signal terminal CLK1 is used to receive the first clock signal clk1, the second clock signal terminal CLK2 is used to receive the second clock signal clk2, and the starting anti-leakage control signal terminal STV-EM1 is used to receive the starting anti-leakage control signal STV-em1. The first light-emitting drive array circuit EOA1 is used to generate an anti-leakage control signal em1 according to the first clock signal clk1 received by the first clock signal terminal CLK1, the second clock signal clk2 received by the second clock signal terminal CLK2, and the starting anti-leakage control signal STV-em1 received by the starting anti-leakage control signal terminal STV-EM1.

[0120] The anti-leakage control signal em1 is used to transmit a cutoff signal to the light-emitting control signal terminal EM during the writing and compensation phase t2. The light-emitting control circuit 114 is turned off under the control of the anti-leakage control signal em1 to prevent the data voltage of the data voltage terminal Vdata from leaking to the first power supply voltage terminal ELVDD and / or the second power supply voltage terminal ELVSS.

[0121] Figure 8 A waveform diagram of an anti-leakage control signal and a light-emitting duty cycle control signal provided in an embodiment of the present application.

[0122] In some embodiments, the structure of the first light emitting drive array circuit EOA1 is similar to Figure 1B The structure of the light emitting drive array circuit EOA in the terminal 1 shown in the figure is the same. The first clock signal clk1 and the second clock signal clk2 received by the first light emitting drive array circuit EOA1 are the same as those of the first clock signal clk1 and the second clock signal clk2 received by the first light emitting drive array circuit EOA1. Figure 1BThe first clock signal clk1 and the second clock signal clk2 received by the light emitting drive array circuit EOA are also the same. However, the initial anti-leakage control signal STV-em1 received by the first light emitting drive array circuit EOA1 is only a partial waveform of the initial light emitting control signal STV-em received by the light emitting drive array circuit EOA, and only includes the waveform of the initial light emitting control signal STV-em corresponding to the writing and compensation stage t2. Then, the anti-leakage control signal em1 only includes the waveform of the light emitting control signal em corresponding to the writing and compensation stage t2.

[0123] The embodiment of the present application does not limit the structure of the first light emitting drive array circuit EOA1, and the light emitting drive array circuit EOA in the related art is applicable to the embodiment of the present application.

[0124] For example, the first light-emitting driving array circuit EOA1 includes a plurality of cascaded first light-emitting driving units eOA1, and each stage of the first light-emitting driving unit eOA1 includes a first output terminal OT1. Each stage of the first light-emitting driving unit eOA1 is also coupled to the first clock signal terminal CLK1 and the second clock signal terminal CLK2, and the first clock signal clk1 and the second clock signal clk2 are used to control the propagation speed of the anti-leakage control signal em1 output by the first output terminal OT1. The first stage of the first light-emitting driving unit eOA1 is coupled to the starting anti-leakage control signal terminal STV-EM1, and the remaining stages of the first light-emitting driving units eOA1 are coupled to the first output terminal OT1 of the previous stage of the first light-emitting driving unit eOA1. The first stage of the first light-emitting driving unit eOA1 receives the starting anti-leakage control signal STV-em1, and outputs the anti-leakage control signal em1 from the first output terminal OT1 of its own stage. The remaining stages of the first light-emitting driving units eOA1 receive the anti-leakage control signal em1 output by the first light-emitting driving unit eOA1 of the previous stage, and output the anti-leakage control signal em1 from the first output terminal OT1 of its own stage.

[0125] The topological structure of each level of the first light-emitting driving unit eoa1 may be the same or different. The present embodiment does not limit the structure of the first light-emitting driving unit eoa1, and the structure of the light-emitting driving unit eoa in the related art is applicable to the present embodiment.

[0126] The second light-emitting drive array circuit EOA2 includes a third clock signal terminal CLK3, a fourth clock signal terminal CLK4, a starting light-emitting duty cycle control signal terminal STV-EM2, and a second output terminal OT2, wherein the third clock signal terminal CLK3 is used to receive a third clock signal clk3, the fourth clock signal terminal CLK4 is used to receive a fourth clock signal clk4, and the starting light-emitting duty cycle control signal terminal STV-EM2 is used to receive a starting light-emitting duty cycle control signal STV-em2. The second light-emitting drive array circuit EOA2 is used to generate a light-emitting duty cycle control signal em2 according to the third clock signal clk3 received by the third clock signal terminal CLK3, the fourth clock signal clk4 received by the fourth clock signal terminal CLK4, and the starting light-emitting duty cycle control signal STV-em2 received by the starting light-emitting duty cycle control signal terminal STV-EM2.

[0127] The light-emitting duty cycle control signal em2 is used to transmit a start control signal to the light-emitting control signal terminal EM in the light-emitting stage t3. The light-emitting control circuit 114 is turned on under the control of the light-emitting duty cycle control signal em2, so that the driving current generated by the pixel circuit 11 is transmitted to the light-emitting unit 12, driving the light-emitting unit 12 to emit light.

[0128] In some embodiments, the structure of the second light-emitting driving array circuit EOA2 is the same as that of the first light-emitting driving array circuit EOA1, but the third clock signal clk3 and the fourth clock signal clk4 received by the second light-emitting driving array circuit EOA2 are different from the first clock signal clk1 and the second clock signal clk2 received by the first light-emitting driving array circuit EOA1. Moreover, the start light-emitting duty cycle control signal STV-em2 received by the second light-emitting driving array circuit EOA2 is only Figure 1B The partial waveform of the start light control signal STV-em received by the light driving array circuit EOA in the terminal 1 shown only includes the waveform of the start light control signal STV-em corresponding to the light stage t3. Then, the light duty cycle control signal em2 only includes the waveform of the light control signal em corresponding to the light stage t3.

[0129] The embodiment of the present application does not limit the structure of the second light emitting drive array circuit EOA2, and the light emitting drive array circuit EOA in the related art is applicable to the embodiment of the present application.

[0130] For example, the second light-emitting driving array circuit EOA2 includes a plurality of cascaded second light-emitting driving units eOA2, and each level of the second light-emitting driving unit eOA2 includes a second output terminal OT2. Each level of the second light-emitting driving unit eOA2 is also coupled to the third clock signal terminal CLK3 and the fourth clock signal terminal CLK4. The third clock signal clk3 and the fourth clock signal clk4 are used to control the propagation speed of the light-emitting duty cycle control signal em2 output by the second output terminal OT2. The first level of the second light-emitting driving unit eOA2 is coupled to the starting light-emitting duty cycle control signal terminal STV-EM2, and the remaining levels of the second light-emitting driving unit eOA2 are coupled to the second output terminal OT2 of the second light-emitting driving unit eOA2 of the previous level. The first level of the second light-emitting driving unit eOA2 receives the starting light-emitting duty cycle control signal STV-em2, and outputs the light-emitting duty cycle control signal em2 from the second output terminal OT2 of its own level. The second light emitting driving unit eoo2 of the remaining stages receives the light emitting duty cycle control signal em2 outputted by the second light emitting driving unit eoo2 of the previous stage, and outputs the light emitting duty cycle control signal em2 from the second output terminal OT2 of the own stage.

[0131] The topological structure of each level of the second light-emitting driving unit eao2 may be the same or different. The present embodiment does not limit the structure of the second light-emitting driving unit eao2, and the structure of the light-emitting driving unit eao in the related art is applicable to the present embodiment.

[0132] The array substrate 10, for example, includes a plurality of pixel circuits 11 arranged in an array, and the plurality of pixel circuits 11 are disposed in the effective display area AA of the array substrate 10. The pixel circuit 11 includes a light-emitting control circuit 114, and the light-emitting control circuit 114 is coupled to the light-emitting control signal terminal EM, and the light-emitting control signal terminal EM is used to receive the anti-leakage control signal em1 and the light-emitting duty cycle control signal em2, and the light-emitting control circuit 114 is used to be turned off under the control of the anti-leakage control signal em1 received by the light-emitting control signal terminal EM to prevent the pixel from leaking during writing. The light-emitting control circuit 114 is also used to be turned on under the control of the light-emitting duty cycle control signal em2 received by the light-emitting control signal terminal EM to drive the light-emitting unit 12 to emit light.

[0133] In some embodiments, the frequencies of the first clock signal clk1 and the second clock signal clk2 are a first frequency f1, the frequencies of the third clock signal clk3 and the fourth clock signal clk4 are a second frequency f2, and the first frequency f1 is different from the second frequency f2.

[0134] In the embodiment of the present application, the frequency (or transmission speed) of the anti-leakage control signal em1 is controlled by the first frequency f1, and the frequency of the light-emitting duty cycle control signal em2 is controlled by the second frequency f2. The frequency of the anti-leakage control signal em1 can be decoupled from the frequency of the light-emitting duty cycle control signal em2, so as to achieve the decoupling of the refresh logic and the dimming logic, and they can be independently regulated without the need for synchronous regulation. The flexibility of signal control in the array substrate 10 is improved, thereby broadening the applicable scenarios of the array substrate 10.

[0135] In some embodiments, the first frequency f1 is different from the second frequency f2.

[0136] By setting the first frequency f1 and the second frequency f2 to be different, the first frequency f1 is set as a comprehensive optimization frequency, and the second frequency f2 is also set as a comprehensive optimization frequency, so as to optimize the performance of the terminal 1 including the array substrate 10 .

[0137] Fig. 9 The waveform diagrams of the first timing signal, the second timing signal, the third timing signal and the fourth timing signal are provided for the embodiment of the present application.

[0138] In some embodiments, Fig. 9 As shown, the waveforms of the first timing signal clk1 and the third timing signal clk3 are the same, but their frequencies are different, and the second frequency f2 of the third timing signal clk3 is less than the first frequency f1 of the first timing signal clk1. Similarly, the waveforms of the second timing signal clk2 and the fourth timing signal clk4 are the same, but their combined frequencies are different, and the second frequency f2 of the fourth timing signal clk4 is less than the first frequency f1 of the second timing signal clk2.

[0139] In this way, the PWM dimming enable signal can be generated at a lower frequency to reduce power consumption.

[0140] In some embodiments, the first frequency f1 is equal to a screen refresh frequency of the terminal 1. The screen refresh frequency of the terminal 1 may include, for example, 10 Hz, 20 Hz, 30 Hz, 60 Hz, 120 Hz, 144 Hz, and the like.

[0141] By setting the first frequency f1 to be equal to the screen refresh frequency of the terminal 1, it can be ensured that the refresh rate of the terminal 1 is not affected, so as to adapt to the current mainstream terminal 1 products.

[0142] In some embodiments, the ratio of the second frequency f2 to the first frequency f1 is 1 / 5 to 3 / 4. For example, the ratio of the second frequency f2 to the first frequency f1 is 1 / 4, 1 / 3, 2 / 5, 7 / 15, 1 / 2, 8 / 15, 3 / 5, 2 / 3, 11 / 15, etc.

[0143] For example, the ratio of the second frequency f2 to the first frequency f1 is 1 / 3 to 1 / 2. For example, the ratio of the second frequency f2 to the first frequency f1 is 5 / 12, 11 / 24, 11 / 30, 2 / 5, 13 / 30, 7 / 15, 23 / 49, etc.

[0144] For example, the second frequency f2 is greater than 40 Hz and less than 60 Hz.

[0145] If the second frequency f2 is too small, the user will see the black bar moving, affecting the display effect. If the second frequency f2 is too large, the power will increase. Therefore, setting the second frequency f2 within the range of 1 / 3 to 1 / 2 of the first frequency f1 can ensure the display effect with lower power consumption.

[0146] For example, Figure 8 As shown, the first frequency f1 is 120 Hz, the second frequency f2 is 1 / 3 of the first frequency f1, and the second frequency f2 is 40 Hz. In one frame, the leakage prevention control signal em1 is a single pulse signal, and the light emission duty cycle control signal em2 is a 4-pulse signal.

[0147] Then, the refresh frequency of the pixel circuit 11 is 120 Hz, and the switching frequency of the pixel circuit 11 is 4*120 Hz=480 Hz. However, since the second frequency f2 is 1 / 3 of the first frequency f1, the propagation rate of the luminous duty cycle control signal em2 will be reduced. The bright and dark spatial period of the display screen = propagation rate*starting signal period. When the starting signal period remains unchanged, the reduction in propagation rate will cause the bright and dark spatial period of the display screen to decrease. That is, the bright and dark spatial period of the display screen is proportional to the frequency of the clock signal. When the frequency of the clock signal decreases (the second frequency f2 decreases), the bright and dark spatial period of the display screen will also decrease. Figure 8 As shown, after the propagation rate of the luminous duty cycle control signal em2 is reduced by 1 / 3, at any time, there are always 12 (3*4) cycles of light-dark alternation in the display screen, that is, 12 cycles of luminous duty cycle control signal em2 alternating on and off. Figure 8 The vertical line in is the selected time line. Among the multiple lines of luminous duty cycle control signals em2 in the display screen, 12 lines of luminous duty cycle control signals em2 intersect with the time line. The intersection of the 12 lines of luminous duty cycle control signals em2 is a black stripe. Fig.10As shown, at any time, the display screen has 12 rows of black stripes, and the bright and dark spatial period of the display screen is 1 / 12*screen height. Compared with the solution in which the array substrate 10 includes the light-emitting drive array circuit EOA (hereinafter referred to as the above-mentioned solution), when the switching frequency of the pixel circuit 11 of the above-mentioned solution is 480hz, the bright and dark spatial period of the display screen is only 1 / 4*screen height. Therefore, under the same power consumption, the display and eye protection effects can be improved. If the array substrate 10 includes the light-emitting drive array circuit EOA, the bright and dark spatial period of the display screen must reach 1 / 12*screen height, and the switching frequency of the pixel circuit 11 needs to reach 12*120hz=1440hz. In the embodiment of the present application, to achieve the same eye protection effect, the switching frequency of the pixel circuit 11 only needs 480hz. Therefore, under the same display and eye protection effects, the embodiment of the present application can reduce power consumption.

[0148] Or, for example, the first frequency f1 is 120 Hz, and the second frequency f2 is 40 Hz. In one frame, the leakage prevention control signal em1 is a single pulse signal, and the light-emitting duty cycle control signal em2 is a 32-pulse signal.

[0149] Then, the refresh frequency of the pixel circuit 11 is 120 Hz, and the switching frequency of the pixel circuit 11 is 32*120 Hz=3840 Hz. In the above scheme, when the switching frequency of the pixel circuit 11 is 3840 Hz, the bright and dark spatial period of the display screen is only 1 / 32*screen height. In the present application scheme, when the switching frequency of the pixel circuit 11 is 3840 Hz, the bright and dark spatial period of the display screen is only 1 / 3*1 / 32*screen height=1 / 96*screen height. Therefore, at the same power consumption, the display and eye protection effects can be improved. If the bright and dark spatial period of the display screen in the present application scheme reaches 1 / 32*screen height, the switching frequency of the pixel circuit 11 only needs to be 1280 Hz. Therefore, under the same display and eye protection effects, the embodiments of the present application can reduce power consumption.

[0150] Based on this, the array substrate 10 provided in the embodiment of the present application controls the first light-emitting drive array circuit EOA1 through the clock signal of the first frequency f1, and controls the second light-emitting drive array circuit EOA2 through the clock signal of the second frequency f2, so that the frequency of the anti-leakage control signal em1 and the frequency of the light-emitting duty cycle control signal em2 are decoupled, so that the frequency of the light-emitting duty cycle control signal em2 can be independently regulated while the anti-leakage control signal em1 matches the screen refresh frequency. By setting the second frequency f2 to be less than the first frequency f1, the spatial propagation speed of the light-emitting duty cycle control signal em2 can be reduced. When the frequency of the light-emitting duty cycle control signal em2 is fixed, the number of bright and dark spatial cycles of the display screen using the array substrate 10 can be increased, and the bright and dark spatial cycles of the display screen can be reduced to meet the requirements of high display effect and high eye protection effect. By setting the second frequency f2 to be lower than the first frequency f1, the frequency of the luminous duty cycle control signal em2 can be reduced when the number of bright and dark spatial cycles of the display screen using the array substrate 10 is fixed, so as to achieve the purpose of reducing power consumption and reduce the requirements for the switching frequency that the pixel circuit 11 in the array substrate 10 can withstand, so that some array substrates 10 that cannot meet high-frequency switching requirements meet the requirements, thereby reducing the yield loss of the array substrate 10.

[0151] Figure 11A-Figure 12 A schematic diagram of the layout of an array substrate provided in an embodiment of the present application.

[0152] In some embodiments, Fig.11A As shown, the array substrate 10 further includes a logic operation circuit 17, and the logic operation circuit 17 is arranged at the output ends of the first light emitting drive array circuit EOA1 and the second light emitting drive array circuit EOA2.

[0153] The logic operation circuit 17 includes an input terminal and an output terminal. The input terminal of the logic operation circuit 17 is coupled to the first output terminal OT1 and the second output terminal OT2, and the output terminal is coupled to the light-emitting control signal terminal EM. It is used to perform logic operations on the anti-leakage control signal em1 and the light-emitting duty cycle control signal em2, and output the operation result as the light-emitting control signal em to the light-emitting control signal terminal EM.

[0154] The logic operation circuit 17 is used to perform logic operations on the anti-leakage control signal em1 and the luminous duty cycle control signal em2. When the anti-leakage control signal em1 and the luminous duty cycle control signal em2 are both on signals, the luminous control signal em output after the logic operation is an on signal; when one of the anti-leakage control signal em1 and the luminous duty cycle control signal em2 is an off signal, the luminous control signal em output after the logic operation is an off signal.

[0155] For example, the logic operation circuit 17 includes multiple logic operation units 171, the input end of the logic operation unit 171 is coupled to the first output end OT1 of the first light-emitting driving unit eoa1 and the second output end OT2 of the second light-emitting driving unit eoa2 located at the same level, and the light-emitting control signal end EM of the pixel circuit 11 located in the same row is coupled to the output end of the same logic operation unit 171.

[0156] Optional, such as Fig.11A As shown, the output terminal of a logic operation unit 171 is coupled to the light emitting control signal terminal EM of a row of pixel circuits 11 to provide a light emitting control signal em for the row of pixel circuits 11 .

[0157] Or, alternatively, Fig. 11B As shown, an output terminal of a logic operation unit 171 is coupled to the light-emitting control signal terminal EM of the multiple rows of pixel circuits 11 to provide the light-emitting control signal em for the multiple rows of pixel circuits 11 .

[0158] For example, the light emitting control signal terminals EM of the pixel circuits 11 in multiple rows are coupled to the output terminal of the same logic operation unit 171 . Fig. 11B In the figure, the light emitting control signal terminals EM of the pixel circuits 11 located in two adjacent rows are coupled to the output terminal of the same logic operation unit 171 as an example for illustration.

[0159] In this way, multiple rows of pixel circuits 11 share the same set of logic operation units 171, first light-emitting driving units eoa1 and second light-emitting driving units eoo2, which can reduce the number of devices in the non-display area BB, save costs and facilitate the realization of a narrow frame.

[0160] In some embodiments, the pixel circuit 11 may be a 7T1C structure pixel circuit commonly used in the art. The present embodiment does not limit the structure of the pixel circuit 11, and pixel circuits in related technologies are applicable to the present embodiment.

[0161] In some embodiments, Fig.11A As shown, the logic operation circuit 17 includes an OR operation circuit, and the logic operation unit 171 includes an OR gate.

[0162] For example, in the anti-leakage control signal em1 and the light-emitting duty cycle control signal em2, the high-level signal is "1" and the low-level signal is "0". When the anti-leakage control signal em1 and the light-emitting duty cycle control signal em2 are both "0", the light-emitting control signal em is "0", which is a low-level signal. When one of the anti-leakage control signal em1 and the light-emitting duty cycle control signal em2 is "1", the light-emitting control signal em is "1", which is a high-level signal.

[0163] For example, Figure 2As shown, the transistor in the light-emitting control circuit 114 is a P-type transistor, which is turned on under the control of a low-level signal and turned off under the control of a high-level signal. In other words, the light-emitting control circuit 114 is turned on when the light-emitting control signal em is "0" and turned off when the light-emitting control signal em is "1". Then, as long as the anti-leakage control signal em1 is "1" or the light-emitting control signal em is "1", the light-emitting control circuit 114 can be controlled to be turned off. Only when the anti-leakage control signal em1 and the light-emitting duty cycle control signal em2 are both "0", can the light-emitting control circuit 114 be controlled to be turned on.

[0164] Of course, the embodiment of the present application does not limit the logic operation unit 171 to include an OR gate, and any logic circuit that can achieve the same effect as the OR gate is applicable to the embodiment of the present application. For example, the logic operation unit 171 includes an AND gate plus a NOT gate.

[0165] In other embodiments, Fig.12 As shown, the logic operation circuit 17 includes an AND operation circuit, and the logic operation unit 171 includes an AND gate.

[0166] For example, in the anti-leakage control signal em1 and the light-emitting duty cycle control signal em2, the high-level signal is "1" and the low-level signal is "0". When the anti-leakage control signal em1 and the light-emitting duty cycle control signal em2 are both "1", the light-emitting control signal em is "1", which is a high-level signal. When one of the anti-leakage control signal em1 and the light-emitting duty cycle control signal em2 is "0", the light-emitting control signal em is "0", which is a low-level signal.

[0167] For example, the transistor in the light-emitting control circuit 114 is an N-type transistor, which is turned on under the control of a high-level signal and turned off under the control of a low-level signal. In other words, the light-emitting control circuit 114 is turned on when the light-emitting control signal em is "1" and turned off when the light-emitting control signal em is "0". Then, the light-emitting control circuit 114 can be turned on only when the anti-leakage control signal em1 and the light-emitting duty cycle control signal em2 are both "1". As long as the anti-leakage control signal em1 is "0" or the light-emitting control signal em is "0", the light-emitting control circuit 114 can be turned off.

[0168] Of course, the embodiment of the present application does not limit the logic operation unit 171 to include an AND gate, and any logic circuit that can achieve the same effect as the AND gate is applicable to the embodiment of the present application. For example, the logic operation unit 171 includes an OR gate plus a NOT gate.

[0169] By performing a logical operation on the anti-leakage control signal em1 and the light-emitting duty cycle control signal em2 and then outputting them to the light-emitting control signal terminal EM, the light-emitting control signal terminal EM only receives one final light-emitting control signal em. Therefore, the structure of the pixel circuit 11 in the array substrate 10 does not need to be modified, and the pixel circuit 11 in the related art is applicable to the embodiment of the present application, which can reduce the workload of modification. Moreover, if only one light-emitting control signal em is output, only one output switch needs to be set, and the width of the frame does not increase.

[0170] In some embodiments, Fig.12 As shown, the array substrate 10 also includes circuit structures such as a first scanning array circuit 13, a second scanning array circuit 14, a third scanning array circuit 15 and a fourth scanning array circuit 16. The embodiment of the present application does not limit the specific structure and setting position of the first scanning array circuit 13, the second scanning array circuit 14, the third scanning array circuit 15 and the fourth scanning array circuit 16, and the structures in the relevant technology are applicable to the embodiment of the present application.

[0171] Fig.13 A schematic diagram of the structure of a display screen module provided in an embodiment of the present application.

[0172] The embodiment of the present application provides a display driver 20, which can be bound to the array substrate 10. Fig.13 As shown, the display driver 20 includes a timing circuit 21 and a start light emission control signal generating circuit 22 .

[0173] The timing circuit 21 is used to generate the above-mentioned first clock signal clk1, second clock signal clk2, third clock signal clk3 and fourth clock signal clk4, transmit the first clock signal clk1 and the second clock signal clk2 to the first light-emitting drive array circuit EOA1, and transmit the third clock signal clk3 and the fourth clock signal clk4 to the second light-emitting drive array circuit EOA2.

[0174] The timing circuit 21 may be, for example, a timing control unit (TCON).

[0175] The start light emitting control signal generating circuit 22 is used to generate a start light emitting anti-leakage control signal STV-em1 and a start light emitting duty cycle control signal STV-em1, transmit the start light emitting anti-leakage control signal STV-em1 to the first light emitting drive array circuit EOA1, and transmit the start light emitting duty cycle control signal STV-em1 to the second light emitting drive array circuit EOA2.

[0176] The present application also provides a display screen module, such as Fig.13As shown, the display screen module 3 includes any of the above array substrates 10 and / or any of the above display drivers 20, and the display driver 20 is bound to the non-display area BB of the array substrate 10. For example, the display driver module is bound to one side of the pixel circuit 11 array along the column direction of the pixel circuit 11 array.

[0177] The display screen module 3 provided in the embodiment of the present application can be applied to the terminal 1 provided in the embodiment of the present application. The terminal 1 includes a shell, and the display screen module 3 is arranged in the shell. The shell, for example, includes the above-mentioned rear shell 5.

[0178] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An array substrate, characterized in that: include: The first light-emitting driving array circuit comprises a first clock signal terminal, a second clock signal terminal, a starting anti-leakage control signal terminal, and a first output terminal, and is used to generate an anti-leakage control signal according to a first clock signal received by the first clock signal terminal, a second clock signal received by the second clock signal terminal, and a starting anti-leakage control signal received by the starting anti-leakage control signal terminal; a second light-emitting driving array circuit, comprising a third clock signal terminal, a fourth clock signal terminal, a start light-emitting duty cycle control signal terminal, and a second output terminal, and configured to generate a light-emitting duty cycle control signal according to a third clock signal received by the third clock signal terminal, a fourth clock signal received by the fourth clock signal terminal, and a start light-emitting duty cycle control signal received by the start light-emitting duty cycle control signal terminal; The pixel circuit comprises a light emitting control signal terminal; the light emitting control signal terminal is used to receive the anti-leakage control signal and the light emitting duty cycle control signal; Wherein, f1 is the frequency of the first clock signal and the second clock signal, f2 is the frequency of the third clock signal and the fourth clock signal, and f2 <f1。 2. The array substrate according to claim 1, characterized in that: The array substrate also includes a logic operation circuit; The input end of the logic operation circuit is coupled to the first output end and the second output end, and the output end is coupled to the light-emitting control signal end, and is used to perform logic operations on the anti-leakage control signal and the light-emitting duty cycle control signal, and output the operation result as a light-emitting control signal to the light-emitting control signal end.

3. The array substrate according to claim 1 or 2, characterized in that: The value of f2 / f1 is 1 / 5 to 3 / 4.

4. The array substrate according to any one of claims 1 to 3, characterized in that: The value of f2 / f1 is 1 / 3 to 1 / 2.

5. The array substrate according to any one of claims 1 to 4, characterized in that: The logic operation circuit includes an OR operation circuit.

6. The array substrate according to any one of claims 1 to 4, characterized in that: The logic operation circuit includes an AND operation circuit.

7. The array substrate according to any one of claims 1 to 6, characterized in that: The first light-emitting driving array circuit comprises a plurality of cascaded first light-emitting driving units, wherein the first light-emitting driving units of the first stage are coupled to the starting anti-leakage control signal terminal, and the first light-emitting driving units of each stage are coupled to both the first clock signal terminal and the second clock signal terminal; The second light-emitting driving array circuit includes a plurality of cascaded second light-emitting driving units, wherein the first-stage second light-emitting driving units are coupled to the starting light-emitting duty cycle control signal terminal, and each stage of the second light-emitting driving units are coupled to both the third clock signal terminal and the fourth clock signal terminal.

8. The array substrate according to claim 7, characterized in that: The array substrate comprises a plurality of pixel circuits arranged in an array; the logic operation circuit comprises a plurality of logic operation units; An input terminal of the logic operation unit is coupled to the first output terminal of the first light-emitting driving unit and the second output terminal of the second light-emitting driving unit located at the same level; The light emitting control signal terminals of the pixel circuits in the same row are coupled to the output terminal of the same logic operation unit.

9. The array substrate according to claim 8, characterized in that: The light emitting control signal terminals of the pixel circuits in multiple rows are coupled to the output terminal of the same logic operation unit.

10. A display driver, characterized in that: include: Timing circuit and start light emission control signal generating circuit; The timing circuit is used to generate a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, f1 is the frequency of the first clock signal and the second clock signal, f2 is the frequency of the third clock signal and the fourth clock signal, and f2 <f1; The start light emission control signal generating circuit is used to generate a start leakage prevention control signal and a start light emission duty cycle control signal.

11. The display driver according to claim 10, characterized in that: The value of f2 / f1 is 1 / 5 to 3 / 4.

12. The display driver according to claim 11, characterized in that: The value of f2 / f1 is 1 / 3 to 1 / 2.

13. A display screen module, characterized in that: It comprises an array substrate and a display driver, wherein the display driver is bound to the array substrate; The array substrate comprises the array substrate according to any one of claims 1 to 9; and / or, The display driver comprises the display driver according to any one of claims 10-12.

14. A terminal, characterized in that: It comprises a shell and a display screen module, wherein the display screen module is arranged in the shell; the display screen module comprises the display screen module according to claim 13.

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