Display panel and display device

Abstract

The embodiment of the invention discloses a display panel and a display device. The display panel comprises at least two display areas, and the at least two display areas comprise a first display area and a second display area; the pixel circuit at least comprises a first pixel circuit and a second pixel circuit, the first pixel circuit is located in the first display area, and the second pixel circuit is located in the second display area; the pixel circuit receives bias adjustment signals, the bias adjustment signals comprise a first bias adjustment signal and a second bias adjustment signal, and when the refresh rate of the first display area is f1, the first pixel circuit receives the first bias adjustment signal, and the refresh rate of the second display area is f2, the second pixel circuit receives the second bias adjustment signal; wherein f1 is not equal to f2, and the first bias adjusting signal is different from the second bias adjusting signal. According to the embodiment of the invention, the problem of non-uniform display in the display process with different partition refresh rates can be improved, and the display effect is improved.

Description

[0001] This application is a divisional application of application number 202211021959.4, application date August 24, 2022, and invention name “A display panel and display device”. Technical Field

[0002] Embodiments of the present invention relate to display technology, and more particularly to a display panel and a display device. Background Art

[0003] With the development of display technology, new display panels such as organic light emitting diode (OLED) display panels and micro light emitting diode (micro LED) display panels have emerged in an endless stream and are widely favored by consumers.

[0004] Electronic products will use different refresh rates for display in different application scenarios. For example, a higher refresh rate driving method is used to drive the display of dynamic images (such as sports events or game scenes) to ensure the smoothness of the displayed image; a lower refresh rate driving method is used to drive the display of slow-motion images or static images to reduce power consumption.

[0005] In some special application scenarios, there is also a dynamic partition refresh display technology for the display screen, which can divide the display screen into several partitions, and the refresh rate of each partition can be set independently. This technology can achieve the effect of reducing the display drive power consumption. However, when the current display panel implements the above partition refresh rate control, it may have the problem of uneven display, which affects the display effect. Summary of the invention

[0006] Embodiments of the present invention provide a display panel and a display device to improve the problem of uneven display during a display process in which partitions have different refresh rates, thereby improving the display effect.

[0007] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0008] At least two display areas, the at least two display areas comprising a first display area and a second display area;

[0009] A pixel circuit, the pixel circuit at least comprising a first pixel circuit and a second pixel circuit, the first pixel circuit is located in the first display area, and the second pixel circuit is located in the second display area;

[0010] The pixel circuit receives a bias adjustment signal, the bias adjustment signal includes a first bias adjustment signal and a second bias adjustment signal, when the refresh rate of the first display area is f1, the first pixel circuit receives the first bias adjustment signal, and when the refresh rate of the second display area is f2, the second pixel circuit receives the second bias adjustment signal;

[0011] Wherein, f1≠f2, the first bias adjustment signal is different from the second bias adjustment signal.

[0012] In a second aspect, an embodiment of the present invention provides a display panel, including:

[0013] At least two display areas, the at least two display areas comprising a first display area and a second display area;

[0014] A pixel circuit, the pixel circuit at least comprising a first pixel circuit and a second pixel circuit, the first pixel circuit is located in the first display area, and the second pixel circuit is located in the second display area;

[0015] The pixel circuit receives a reset signal, the reset signal includes a first reset signal and a second reset signal, when the refresh rate of the first display area is f1, the first pixel circuit receives the first reset signal, and when the refresh rate of the second display area is f2, the second pixel circuit receives the second reset signal;

[0016] The display panel includes a plurality of light-emitting elements, the light-emitting elements include a first light-emitting element and a second light-emitting element, wherein the first light-emitting element is located in the first display area, the second light-emitting element is located in the second display area, the first light-emitting element is connected to a first node of the first pixel circuit, the first reset signal is provided to the first node, the second light-emitting element is connected to a second node of the second pixel circuit, and the second reset signal is provided to the second node;

[0017] Wherein, f1≠f2, the first reset signal is different from the second reset signal.

[0018] In a third aspect, an embodiment of the present invention further provides a display device, comprising the above-mentioned display panel.

[0019] The display panel provided by the embodiment of the present invention includes at least two display areas, the at least two display areas include a first display area and a second display area, wherein the first display area and the second display area can realize display at different refresh rates; a pixel circuit, the pixel circuit includes at least a first pixel circuit and a second pixel circuit, the first pixel circuit is located in the first display area, and is used to provide a driving current for a light-emitting element in the first display area, and the second pixel circuit is located in the second display area, and is used to provide a driving current for a light-emitting element in the second display area; the pixel circuit receives a bias adjustment signal, the bias adjustment signal includes a first bias adjustment signal and a second bias adjustment signal, when the refresh rate of the first display area is f1, the first pixel circuit receives the first bias adjustment signal, and when the refresh rate of the second display area is f2, the second pixel circuit receives the second bias adjustment signal; wherein f1≠f2, the first bias adjustment signal is different from the second bias adjustment signal. The bias state of the driving transistor in the pixel circuit is adjusted by the bias adjustment signal. The size of the bias adjustment signal affects the adjustment process of the bias state of the driving transistor. When the first display area and the second display area have different refresh rates in order to achieve different display functions, the requirements for the pixel circuit are different, resulting in different bias states of the driving transistor. Different bias adjustment signals are required to adjust the bias states of the driving transistor in the pixel circuits corresponding to the first display area and the second display area respectively, which is beneficial to avoid uneven display in different display areas and improve the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0021] Figure 2 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0023] Figure 4 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0024] Figure 5 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0025] Figure 6 A timing diagram of a driving signal of a pixel circuit provided by an embodiment of the present invention;

[0026] Figure 7 A timing diagram of a driving signal of a pixel circuit provided by an embodiment of the present invention;

[0027] Figure 8A timing diagram of a driving signal of a pixel circuit provided by an embodiment of the present invention;

[0028] Fig. 9 A timing diagram of a driving signal of a pixel circuit provided by an embodiment of the present invention;

[0029] Fig.10 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0030] Fig.11 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0031] Fig.12 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0032] Fig.13 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0033] Fig.14 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0034] Fig.15 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0035] Fig.16 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0037] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. It should be noted that the directional words such as "upper", "lower", "left", "right" and the like described in the embodiments of the present invention are described at the angles shown in the accompanying drawings and should not be understood as limitations on the embodiments of the present invention. In addition, in the context, it is also necessary to understand that when it is mentioned that an element is formed "on" or "under" another element, it can not only be directly formed "on" or "under" another element, but also indirectly formed "on" or "under" another element through an intermediate element. The terms "first", "second" and the like are only used for descriptive purposes and do not indicate any order, quantity or importance, but are only used to distinguish different components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0038] With the development of display, the resolution of display panels is getting higher and higher, resulting in higher power consumption of display panels. In order to reduce the power consumption of display panels, the prior art proposes a dynamic partition refresh display technology with different partition refresh rates. However, during dynamic display, the refresh rates of different partitions are different. The prior art does not optimize the driving process of different display areas, which will reduce the display effect or cause poor display.

[0039] In order to solve the above problems, an embodiment of the present invention provides a display panel, including: at least two display areas, the at least two display areas include a first display area and a second display area; a pixel circuit, the pixel circuit includes at least a first pixel circuit and a second pixel circuit, the first pixel circuit is located in the first display area, and the second pixel circuit is located in the second display area; the pixel circuit receives a bias adjustment signal, the bias adjustment signal includes a first bias adjustment signal and a second bias adjustment signal, when the refresh rate of the first display area is f1, the first pixel circuit receives the first bias adjustment signal, and when the refresh rate of the second display area is f2, the second pixel circuit receives the second bias adjustment signal; wherein, f1≠f2, the first bias adjustment signal is different from the second bias adjustment signal.

[0040] The display panel provided in this embodiment can be an organic light emitting diode display panel, a micro light emitting diode display panel, or other types of display panels. Among them, the display panel can be set with different numbers of display areas according to the actual display screen, such as two display areas, three display areas, four display areas or more display areas, and the refresh rates of different display areas can be the same or different. Specifically, for slow-motion images or static images, a lower refresh rate can be used to reduce power consumption. For sports events or game scenes, a higher refresh rate is required to avoid flickering and improve the display effect. For some application scenarios, some display areas (such as the central display area) need to have a high refresh rate while other display areas (using the edge display areas on both sides) need to have a low refresh rate. The specific implementation can be designed according to actual conditions. The first display area and the second display area can realize display at different refresh rates. For example, the refresh rate of the first display area can be 30Hz, and the refresh rate of the second display area can be 60Hz. For display panels that can achieve high refresh rates, the refresh rate of a certain display area can also be set to 90Hz or 120Hz, etc.

[0041] Take the display panel including two display areas as an example. Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Figure 1The display panel includes a first display area 101 and a second display area 102; a pixel circuit, the pixel circuit includes a first pixel circuit 110 and a second pixel circuit 120, the first pixel circuit 110 is located in the first display area 101, and is used for the light emitting element ( Figure 1 The second pixel circuit 120 is located in the second display area 102 and is used to provide a driving current to the light emitting element (not shown) in the second display area 102. Figure 1 The pixel circuit 110 receives a bias adjustment signal, the bias adjustment signal includes a first bias adjustment signal and a second bias adjustment signal, when the refresh rate of the first display area 101 is f1, the first pixel circuit 110 receives the first bias adjustment signal, and when the refresh rate of the second display area 102 is f2, the second pixel circuit 120 receives the second bias adjustment signal; wherein, f1≠f2, the first bias adjustment signal is different from the second bias adjustment signal. Because the bias adjustment signal is a signal received by the pixel circuit for adjusting the bias state of the driving transistor, the size of the bias adjustment signal affects the adjustment process of the bias state of the driving transistor. When the refresh rates of different display areas are different, the duration of a frame display is different, and the duration of the light emission of the light-emitting element is different. Since the driving current when the light-emitting element emits light is provided by the driving transistor being turned on, when the light-emitting time of the light-emitting elements in different display areas is different, the working states of the driving transistors in the pixel circuits in different display areas are different, resulting in different bias states of the driving transistors. Different bias adjustment signals are required to respectively adjust the bias states of the driving transistors in the pixel circuits corresponding to the first display area 101 and the second display area 102, thereby facilitating the optimization of the display effect.

[0042] It should be noted that, in a specific implementation, the first bias adjustment signal and the second bias adjustment signal may be provided by the same bus in a time-sharing manner, or may be provided independently by corresponding buses. For example, Figure 1 As shown, the first bias adjustment signal can be provided by the first bias adjustment signal line 210, and the second bias adjustment signal can be provided by the second bias adjustment signal line 220. The second signal bus 202 is used to provide a signal for the first bias adjustment signal line 210, and the third signal bus 203 is used to provide a signal for the second bias adjustment signal line 220. In this way, the first bias adjustment signal and the second adjustment signal can be provided simultaneously without being affected. For example, when two adjacent rows of pixel circuits are respectively located in two display areas with different refresh rates, the bias adjustment signals are respectively provided by setting corresponding bias adjustment signal lines. When the first bias adjustment signal is provided to the pixel circuit of the previous row, the second bias adjustment signal can be provided to the pixel circuit of the next row synchronously, thereby improving the display effect. The specific implementation can be designed according to actual conditions.

[0043] The technical solution of the embodiment of the present invention adjusts the bias state of the driving transistor in the pixel circuit through a bias adjustment signal. The size of the bias adjustment signal affects the adjustment process of the bias state of the driving transistor. When the refresh rates of the first display area and the second display area are different in order to achieve different display functions, the requirements for the pixel circuit are different, resulting in different bias states of the driving transistor. Different bias adjustment signals are required to adjust the bias states of the driving transistor in the pixel circuits corresponding to the first display area and the second display area respectively, which is beneficial to avoid uneven display in different display areas and improve the display effect.

[0044] Figure 2 A schematic diagram of a pixel circuit according to an embodiment of the present invention is provided. Figure 3 A schematic diagram of another pixel circuit provided by an embodiment of the present invention. Figure 2 or Figure 3 Optionally, the pixel circuit 10 includes a data writing module 11, a driving module 12, a compensation module 13 and a bias adjustment module 14; the driving module 11 includes a driving transistor T3, and the driving transistor T3 is used to provide a driving current for the light-emitting element 20 of the display panel; the data writing module 11 is connected to the first electrode (N3) of the driving transistor T3, and is used to provide a data signal Data for the driving transistor T3; the bias adjustment module 14 is connected to the first electrode (N3, reference Figure 2 ) or the second pole (N4, reference Figure 3 ), used to provide a bias adjustment signal V0 for the driving transistor T3; the compensation module 13 is connected between the gate (N2) and the second electrode (N4) of the driving transistor T3, and is used to compensate for the threshold voltage of the driving transistor T3.

[0045] In addition, the pixel circuit 10 may further include an initialization module 15, which is used to provide an initialization signal Vref1 for the gate of the driving transistor T3; a reset module 16, which is used to provide a reset signal Vref2 for the light-emitting element 20; and a light-emitting control module 17, which is used to selectively allow the light-emitting element 20 to enter the light-emitting stage. Optionally, the light-emitting control module 17 includes a first light-emitting control module 171 and a second light-emitting control module 172, the first light-emitting control module 171 is connected between the first power supply signal terminal PVDD and one pole of the driving transistor T3, and the second light-emitting control module 172 is connected between the other pole of the driving transistor T3 and the light-emitting element 20.

[0046] Optionally, in this embodiment, the control end of the data writing module 11 receives a first scanning signal S1, and the first scanning signal S1 controls the opening and closing of the data writing module 11; the control end of the compensation module 13 receives a second scanning signal S2, and the second scanning signal S2 controls the opening and closing of the compensation module 13; the control end of the bias adjustment module 14 receives a bias adjustment control signal SV, and the bias adjustment control signal SV controls the opening and closing of the bias adjustment module 14; the control end of the initialization module 15 receives a third scanning signal S3, and the third scanning signal S3 controls the opening and closing of the reset module 15; the control end of the reset module 16 receives a fourth scanning signal S4, and the fourth scanning signal S4 controls the opening and closing of the reset module 16; the control end of the light-emitting control module 17 receives a light-emitting control signal EM, and the light-emitting control signal EM controls the opening and closing of the light-emitting control module 17.

[0047] In addition, optionally, in the present embodiment, the data writing module 11 includes a data writing transistor T2, and the first scanning signal S1 controls the turning on and off of the data writing transistor T2; the compensation module 13 includes a compensation transistor T4, and the second scanning signal S2 controls the turning on and off of the compensation transistor T4; the bias adjustment module 14 includes a bias adjustment transistor T8, and the bias adjustment control signal SV controls the turning on and off of the bias adjustment transistor T8; the initialization module 15 includes an initialization transistor T5, and the third scanning signal S3 controls the turning on and off of the initialization transistor T5; the reset module 16 includes a reset transistor T7, and the fourth scanning signal S4 controls the turning on and off of the reset transistor T7; the first light-emitting control module 171 includes a first light-emitting control transistor T1, and the second light-emitting control module 172 includes a second light-emitting control transistor T6, and the light-emitting control signal EM controls the turning on and off of the first light-emitting control transistor T1 and the second light-emitting control transistor T6.

[0048] It should be noted that, when conditions permit, at least two of the first scanning signal S1, the second scanning signal S2, the third scanning signal S3, the fourth scanning signal S4, the bias adjustment control signal SV, the light emitting control signal EM and other signals can be the same signal. For example, when the bias adjustment transistor T8 and the reset transistor T6 are transistors of the same type, the bias adjustment control signal SV and the fourth scanning signal S4 can be the same signal.

[0049] It should be noted that Figure 2 and Figure 3All transistors are PMOS transistors, and the pixel circuit 10 also includes a storage capacitor C1, a first electrode of the storage capacitor C1 is connected to the first power signal terminal PVDD, and a second electrode is connected to the gate of the driving transistor T3, for storing the signal transmitted to the gate of the driving transistor T2. In other embodiments, all transistors can also be set to be PMOS transistors, or both PMOS transistors and NMOS transistors (for example, the compensation transistor T4 and the initialization transistor T5 are set to be NMOS transistors, and the others are all PMOS transistors). The fact that all transistors in the pixel circuit shown in this embodiment are PMOS transistors is only exemplary, and can be designed according to actual conditions during specific implementation. The embodiment of the present invention does not limit the specific structure of the pixel circuit.

[0050] In the above manner, a bias adjustment module 14 is provided in the pixel circuit 10, and the bias adjustment module 14 is used to provide a bias adjustment signal for the driving transistor T3. Because the potential difference between the gate and the first pole or the second pole of the driving transistor T3 during the light emission process may cause a bias problem, that is, when the driving transistor T3 is a PMOS type transistor, when the driving transistor T3 is turned on, but its gate voltage is greater than the voltage of the first pole or the second pole, a bias problem will occur; when the driving transistor T3 is an NMOS type transistor, when the driving transistor T3 is turned on, but its gate voltage is less than the voltage of the first pole or the second pole, a bias problem will occur. The bias problem often causes a reverse electric field to be generated inside the driving transistor T3, resulting in carrier polarization, thereby causing the threshold voltage of the driving transistor T3 to shift. The threshold voltage of the driving transistor T3 shifts, causing the driving current generated by the driving transistor T3 to be unstable, especially when the working state of the driving transistor T3 is different when displaying in display areas with different refresh rates, and the problem of uneven display will occur. In this embodiment, different bias adjustment signals are provided to the first electrode or the second electrode of the driving transistor T3 in different display areas, and the voltage difference between the gate of the driving transistor T3 and the first electrode or the second electrode is adjusted in time to offset the bias problem and avoid the threshold voltage of the driving transistor T3 from shifting, thereby facilitating the reduction of the display unevenness phenomenon.

[0051] Figure 4 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention. Figure 4 Optionally, the bias adjustment module 14 is connected to the first electrode of the driving transistor T3 , and the data writing module 11 is multiplexed as the bias adjustment module 14 .

[0052] It can be understood that the working process of the display panel generally includes a refresh frame and a hold frame. The refresh frame includes a data writing stage. The data writing stage writes the data signal Data into the gate of the driving transistor T3 to control the brightness of the light-emitting element 20. When the frame is held, the driving transistor T3 controls the light-emitting element 20 to continue to emit light. In a certain embodiment, the bias adjustment module 14 can be controlled to load the bias adjustment signal within the time period of the hold frame, and the hold frame does not include the data writing stage. Therefore, the data writing module 11 can be multiplexed as the bias adjustment module 14, thereby simplifying the circuit structure and reducing the design difficulty of the display panel.

[0053] Continue to refer Figure 2 or Figure 3 Optionally, the pixel circuit 10 further includes an initialization module 15, which is connected to the gate of the driving transistor T3 and is used to provide an initialization signal Vref1 to the gate of the driving transistor T3. When the display panel switches the screen, the gate of the driving transistor T3 is initialized by the initialization module 15, so as to avoid the influence of the previous frame display screen on the driving transistor T3.

[0054] Figure 5 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention. Figure 5 Optionally, the pixel circuit 10 further includes an initialization module 15 , which is connected to the second electrode of the driving transistor T3 , and the initialization module 15 is multiplexed as a bias adjustment module 14 .

[0055] It can be understood that, in another embodiment, the initialization module 15 can be set to be connected to the second electrode of the driving transistor T3. In this case, in the initialization stage, the initialization transistor T5 and the compensation transistor T4 are controlled to be turned on at the same time, and the initialization signal Vref1 is provided to the gate of the driving transistor T3 after passing through the initialization transistor T5 and the compensation transistor T4. Since the initialization stage is also located in the refresh frame, the stage of providing the bias adjustment signal can be located in the hold frame, so the initialization module 15 can be multiplexed as the bias adjustment module 14, such as Figure 5 shown.

[0056] The technical solution of the embodiment of the present invention realizes the bias adjustment of the driving transistor in different pixel circuits by designing different bias adjustment signals to improve the display effect. In specific implementation, in a certain embodiment, the voltage values ​​of different bias adjustment signals can be set to be different; in another embodiment, since the duration of each frame of display is different when displayed at different refresh rates, the number of loading times of the bias adjustment signal can also be set to be different. Optionally, a frame of display includes a refresh frame and a hold frame; in the first display area, the number of times the first bias adjustment signal is loaded in the same refresh frame or the same hold frame is n1, and the voltage value of the first bias adjustment signal is V1; in the second display area, the number of times the second bias adjustment signal is loaded in the same refresh frame or the same hold frame is n2, and the voltage value of the second bias adjustment signal is V2; wherein, n1=n2, V1≠V2.

[0057] Among them, the refresh frame is used to refresh the display screen so that the signal of the gray value to be displayed is written into the pixel circuit, and the hold frame is used to hold the display screen. Specifically, the higher the refresh rate, the more refresh times it indicates. For example, when the refresh rate is 60Hz, it means that 60 pictures can be displayed within 1s. In specific implementation, the refresh frame and the hold frame can be set to a certain time, and the duration of the refresh frame and the hold frame can be the same or different. Taking the refresh frame and the hold frame as the same duration as an example, for example, when the refresh rate is 60Hz, a frame of display screen can be set to include a refresh frame and a hold frame. When the refresh rate becomes 30Hz, a frame of display screen can be set to include a refresh frame and three hold frames. Since the number of refresh frames is reduced, the refresh rate is reduced. In this embodiment, the bias adjustment signal can be loaded in the refresh frame stage or in the hold frame stage. It can be selected according to actual conditions in specific implementation.

[0058] It can be understood that when the refresh rate f1 of the first display area is different from the refresh rate f2 of the second display area, the working states of the driving transistors in the first pixel circuit and the second pixel circuit are different. In this embodiment, the number of times the first bias adjustment signal is loaded in the same refresh frame or the same hold frame can be set to be the same as the number of times the second bias adjustment signal is loaded in the same refresh frame or the same hold frame, and the voltage value of the first bias adjustment signal is different from the voltage value of the second bias adjustment signal, that is, n1=n2, V1≠V2, which is conducive to effectively improving the uniformity of the first display area and the second display area and improving the display effect.

[0059] In specific implementation, optionally, f1 > f2 and V1 < V2; or f1 < f2 and V1 > V2. It can be understood that when the refresh rate is low, the time for maintaining a frame of display image is long. The inventor's research finds that to keep the state of the driving transistor stable, when a higher bias voltage is adopted, it is beneficial to make up for the characteristic shift caused by the driving transistor maintaining the same working state for a long time, thereby improving the driving performance of the driving transistor. That is, when f1 > f2, V1 < V2; or when f1 < f2, V1 > V2. For example, when f1 = 30Hz and f2 = 60Hz, f1 < f2, and at this time, the voltage value of the first bias adjustment signal is set to be greater than the voltage value of the second bias adjustment signal. When f1 = 60Hz and f2 = 30Hz, f1 > f2, and at this time, the voltage value of the first bias adjustment signal is set to be less than the voltage value of the second bias adjustment signal. In specific implementation, the specific voltage value of the bias adjustment signal can be designed according to the actual situations such as the size of the display area, the refresh rate of the display area, and the emission brightness of the light-emitting element. The embodiments of the present invention do not limit this.

[0060] Exemplarily, taking the first bias adjustment signal and the second bias adjustment signal being loaded on the hold frame, f1 > f2, and the pixel circuit adopting Figure 2 the structure shown as an example, Figure 6 is a timing schematic diagram of the driving signal of a pixel circuit provided by an embodiment of the present invention, where a corresponds to the first pixel circuit and b corresponds to the second pixel circuit. Referring to Figure 6 , a frame of display image includes a refresh frame Z1 and a hold frame Z2. Since f1 > f2, optionally, the duration of the hold frame in the second display area is greater than that in the first display area. The refresh frame Z1 includes an initialization stage P1, a data writing stage P2, and a light-emitting stage P3. In the initialization stage P1, the third scan signal S3 controls the initialization transistor T5 to conduct, and the initialization signal Vref1 is written into the gate (N2 node) of the driving transistor T3; in the data writing stage P2, the first scan signal S1 controls the data writing transistor T2 to conduct, the second scan signal S2 controls the compensation transistor T4 to conduct, and the data signal Data is written into the gate of the driving transistor T3 to realize data writing and threshold compensation; in the light-emitting stage P3, the light-emitting control signal EM controls the first light-emitting control transistor T1 and the second light-emitting control transistor T6 to conduct, and the light-emitting element 20 emits light. The hold frame Z2 includes at least one bias adjustment stage P4 and a light-emitting stage P3 ( Figure 6 only one is taken as an example in the figure). In the bias adjustment stage P4, the bias adjustment control signal SV controls the bias adjustment transistor T8 to conduct, and the bias adjustment signal V0 is loaded to the first pole (N3 node) of the driving transistor. In this embodiment, f1 > f2, and the loading times of the first bias adjustment signal and the second bias adjustment signal are the same (exemplarily n1 = n2 = 3) while the voltages are different (V1 < V2).

[0061] In another embodiment, the voltage values of the first bias adjustment signal and the second bias adjustment signal can also be set to be the same, while the number of times the bias adjustment signal is loaded within the same refresh frame or hold frame is different. Optionally, a frame of display screen includes a refresh frame and a hold frame; in the first display area, the number of times the first bias adjustment signal is loaded within the same refresh frame or the same hold frame is n1, and the voltage value of the first bias adjustment signal is V1; in the second display area, the number of times the second bias adjustment signal is loaded within the same refresh frame or the same hold frame is n2, and the voltage value of the second bias adjustment signal is V2; where n1≠n2 and V1 = V2.

[0062] It can be understood that when the refresh rate f1 of the first display area is different from the refresh rate f2 of the second display area, the operating states of the driving transistors in the first pixel circuit and the second pixel circuit are different. In this embodiment, the voltage values of the first bias adjustment signal and the second bias adjustment signal can be set to be the same, while the number of times the first bias adjustment signal is loaded within the same refresh frame or the same hold frame is different from the number of times the second bias adjustment signal is loaded within the same refresh frame or the same hold frame, that is, V1 = V2 and n1≠n2, which can also effectively improve the uniformity of the first display area and the second display area and enhance the display effect.

[0063] In specific implementation, optionally, f1>f2 and n1<n2; or f1<f2 and n1>n2. It can be understood that when the refresh rate is low, the time for a frame of display screen to be held is long. The inventor has found through research that to keep the state of the driving transistor stable, when the voltage value of the bias adjustment signal is constant, increasing the number of times the bias adjustment signal is loaded is beneficial to increasing the average voltage of the bias adjustment signal, which can be equivalent to increasing the bias voltage and improving the performance of the driving transistor. That is, when f1>f2, n1<n2; or when f1<f2, n1>n2. For example, when f1 = 30Hz and f2 = 60Hz, f1<f2, and at this time, the number of times the first bias adjustment signal is loaded is set to be greater than the number of times the second bias adjustment signal is loaded. When f1 = 60Hz and f2 = 30Hz, f1>f2, and at this time, the number of times the first bias adjustment signal is loaded is set to be less than the number of times the second bias adjustment signal is loaded. In specific implementation, the specific number of times the bias adjustment signal is loaded can be designed according to actual situations such as the size of the display area, the refresh rate of the display area, and the emission brightness of the light-emitting element. The embodiments of the present invention do not limit this.

[0064] Exemplarily, taking the first bias adjustment signal and the second bias adjustment signal being loaded in the hold frame, f1>f2, and the pixel circuit adopting Figure 2 the structure shown as an example, Figure 7 is a timing diagram of the driving signal of another pixel circuit provided by the embodiment of the present invention, where a corresponds to the first pixel circuit and b corresponds to the second pixel circuit. Refer to Figure 7 , different from Figure 6 , in this embodiment, V1 = V2, n1 < n2 (for example, n1 = 2, n2 = 3), and similar technical effects can also be achieved. The working process of the pixel circuit is similar to that of Figure 6 , which will not be elaborated here.

[0065] Combined with Figure 2 to Figure 5 's pixel circuit, it can be seen that in addition to the bias state of the driving transistor T3 affecting the light emission of the light-emitting element, the reset signal Vref2 provided by the reset module 16 for the light-emitting element 20 will also affect the light emission of the light-emitting element. In another embodiment, optionally, the pixel circuit receives a reset signal, the reset signal includes a first reset signal and a second reset signal, the first pixel circuit receives the first reset signal, and the second pixel circuit receives the second reset signal; the display panel includes a plurality of light-emitting elements, the light-emitting elements include a first light-emitting element and a second light-emitting element, wherein, the first light-emitting element is located in the first display area, the second light-emitting element is located in the second display area, the first light-emitting element is connected to the first node of the first pixel circuit, the first reset signal is provided to the first node, the second light-emitting element is connected to the second node of the second pixel circuit, and the second reset signal is provided to the second node; wherein, the first reset signal is different from the second reset signal.

[0066] It can be understood that in this embodiment, the first node is the anode of the light-emitting element in the first display area, and the second node is the anode of the light-emitting element in the second display area. By adjusting the anode reset signal of the light-emitting element, the light-emitting state of the light-emitting elements in different refresh rate display areas can be adjusted, thereby improving the display effect. In specific implementation, the first reset signal and the second reset signal can be provided by the same bus in a time-sharing manner, or can be independently provided by the corresponding buses respectively, and can be designed according to the actual situation in specific implementation.

[0067] The technical solution of the embodiment of the present invention adjusts the anode voltage of the light-emitting element through the reset signal. When the first display area and the second display area have different refresh rates in order to achieve different display functions, the light-emitting time of the light-emitting element is different. By adjusting the reset signals of different display areas, it is beneficial to avoid display unevenness in different display areas and improve the display effect.

[0068] Optionally, a frame of display screen includes a refresh frame and a hold frame; in the first display area, the number of times the first reset signal is loaded within the same refresh frame or the same hold frame is n3, and the voltage value of the first reset signal is V3; in the second display area, the number of times the second reset signal is loaded within the same refresh frame or the same hold frame is n4, and the voltage value of the second reset signal is V4; wherein, n3 = n4, V3 ≠ V4.

[0069] It can be understood that when the refresh rate f1 of the first display area is different from the refresh rate f2 of the second display area, the light-emitting states (such as the continuous light-emitting time) of the first light-emitting element and the second light-emitting element are different. In this embodiment, it can be set that the number of times the first reset signal is loaded within the same refresh frame or the same hold frame is the same as the number of times the second reset signal is loaded within the same refresh frame or the same hold frame, and the voltage value of the first reset signal is different from the voltage value of the second reset signal, that is, n3 = n4, V3 ≠ V4, which is beneficial to effectively improve the uniformity of the first display area and the second display area and enhance the display effect.

[0070] In specific implementation, optionally, f1 > f2, V3 > V4; or f1 < f2, V3 < V4. It can be understood that when the refresh rate is low, the time for a frame of display image to be held is long, that is, the continuous light-emitting time of the light-emitting element is long. The inventor has found that when a lower reset voltage is used, it is beneficial for the light-emitting element to better recover to its initial state after long-term light emission, thereby avoiding affecting the precise control of the subsequent light-emitting brightness. That is, when f1 > f2, V3 > V4; or when f1 < f2, V3 < V4. For example, when f1 = 60Hz and f2 = 30Hz, f1 > f2, and at this time, the voltage value of the first reset signal is set to be greater than the voltage value of the second reset signal. When f1 = 30Hz and f2 = 60Hz, f1 < f2, and at this time, the voltage value of the first reset signal is set to be less than the voltage value of the second reset signal. In specific implementation, the specific voltage value of the reset signal can be designed according to actual situations such as the size of the display area, the refresh rate of the display area, and the light-emitting brightness of the light-emitting element. The embodiments of the present invention do not limit this.

[0071] Exemplarily, taking the first reset signal and the second reset signal being loaded in the refresh frame, f1 > f2, and the pixel circuit adopting Figure 2 the structure shown as an example, Figure 8 is a timing diagram of the driving signal of another pixel circuit provided by the embodiment of the present invention, where a corresponds to the first pixel circuit and b corresponds to the second pixel circuit. Referring to Figure 8 , in the initialization stage P1, the fourth scan signal S4 controls the reset transistor T7 to conduct, and the reset signal Vref2 is provided to the anode (N1 node) of the light-emitting element 20. In this embodiment, it is set that f1 > f2, and the number of times the first reset signal and the second reset signal are loaded is the same (schematically n3 = n4 = 2), while the voltage values are different (V3 > V4).

[0072] In another embodiment, the voltage values of the first reset signal and the second reset signal may also be set to be the same, while the number of times the reset signal is loaded within one frame of the display screen is different. Optionally, one frame of the display screen includes a refresh frame and a hold frame; in the first display area, the number of times the first reset signal is loaded within the same refresh frame or the same hold frame is n3, and the voltage value of the first reset signal is V3; in the second display area, the number of times the second reset signal is loaded within the same refresh frame or the same hold frame is n4, and the voltage value of the second reset signal is V4; where n3≠n4 and V3 = V4.

[0073] It can be understood that when the refresh rate f1 of the first display area is different from the refresh rate f2 of the second display area, the light-emitting states (such as the continuous light-emitting time) of the first light-emitting element and the second light-emitting element are different. In this embodiment, the voltage values of the first reset signal and the second reset signal can be set to be the same, while the number of times the first reset signal is loaded within the same refresh frame or the same hold frame is different from the number of times the second reset signal is loaded within the same refresh frame or the same hold frame, that is, V3 = V4 and n3≠n4, which can also effectively improve the uniformity of the first display area and the second display area and enhance the display effect.

[0074] In specific implementation, optionally, f1>f2 and n3<n4; or f1<f2 and n3>n4. It can be understood that when the refresh rate is low, the time for one frame of the display screen to be held is long, that is, the continuous light-emitting time of the light-emitting element is long. The inventors have found that to make the light-emitting element better recover to its initial state and avoid being affected by the long-time light emission on its performance, by increasing the number of times the reset signal is loaded, it is beneficial to make the light-emitting element better recover to its initial state, thereby avoiding affecting the precise control of the subsequent light-emitting brightness. That is, when f1>f2, n3<n4; or when f1<f2, n3>n4. For example, when f1 = 60Hz and f2 = 30Hz, f1>f2, and at this time, the number of times the first reset signal is loaded is set to be less than the number of times the second reset signal is loaded. When f1 = 30Hz and f2 = 60Hz, f1<f2, and at this time, the number of times the first reset signal is loaded is set to be greater than the number of times the second reset signal is loaded. In specific implementation, the specific number of times the reset signal is loaded can be designed according to the actual situations such as the size of the display area, the refresh rate of the display area, and the light-emitting brightness of the light-emitting element. The embodiments of the present invention do not limit this.

[0075] Exemplarily, similar to the above embodiment, Fig. 9 is a timing diagram of the driving signal of another pixel circuit provided by the embodiment of the present invention, where a corresponds to the first pixel circuit and b corresponds to the second pixel circuit. Refer to Fig. 9 , in this embodiment, f1>f2 is set, and the number of times the first reset signal and the second reset signal are loaded is different (schematically, n3 = 2 and n4 = 3), while the voltage values are the same (V3 = V4).

[0076] It should be noted that Figure 6 and Figure 7 In the embodiment shown, the loading method of the reset signal is not shown. Figure 8 and Fig. 9 In the illustrated embodiment, the loading method of the bias adjustment signal is not shown. In a specific implementation, the two loading methods can be combined and set according to actual conditions, and can be selected according to actual conditions in a specific implementation.

[0077] In a certain embodiment, optionally, the display panel further includes a bias adjustment signal output terminal, and the bias adjustment signal output terminal is used to provide a bias adjustment signal.

[0078] In a specific implementation, the bias adjustment signal output terminal may be located in a non-display area of ​​the display panel. Fig.10 A schematic diagram of another display panel provided by an embodiment of the present invention, referring to Fig.10 Optionally, the display panel also includes a bias adjustment signal output terminal 30, the bias adjustment signal output terminal 30 includes a first bias adjustment signal output terminal 31, and the first bias adjustment signal output terminal 31 is used to provide a first bias adjustment signal to the first pixel circuit 110 in a first time period and provide a second bias adjustment signal to the second pixel circuit 120 in a second time period.

[0079] Among them, since the bias adjustment signal is not continuously loaded into the pixel circuit, the corresponding bias adjustment signal can be provided to the first display area 101 and the second display area 102 respectively by time-division multiplexing. In specific implementation, the bias adjustment signal terminal 30 can be built into the driver chip, and the embodiment of the present invention is not limited to this. In other embodiments, the voltage amplitude and loading frequency of the first bias adjustment signal and the second bias adjustment signal can be the same or different, and can be designed according to the time situation in specific implementation.

[0080] Optional, continue to refer to Fig.10 The display panel further includes a first signal bus 201, the first pixel circuit 110 is electrically connected to the first bias adjustment signal output terminal 31 through the first signal bus 201, and the second pixel circuit 120 is electrically connected to the first bias adjustment signal output terminal 31 through the first signal bus 201. Specifically, the first signal bus 201 is connected to the first pixel circuit 110 through the first bias adjustment signal line 210, and is connected to the second pixel circuit 120 through the second bias adjustment signal line 220. The first signal bus 201 can be set in the border area of ​​the display panel, wherein Fig.10 The fact that the first signal bus 201 is only arranged in a frame area of ​​the display panel is merely illustrative and does not limit the embodiment of the present invention.

[0081] Fig.11 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Fig.11 Optionally, the bias adjustment signal output terminal 30 includes a second bias adjustment signal output terminal 32 and a third bias adjustment signal output terminal 33, the second bias adjustment signal output terminal 32 is used to provide a first bias adjustment signal to the first pixel circuit 110, and the third bias adjustment signal output terminal 33 is used to provide a second bias adjustment signal to the second pixel circuit 120.

[0082] By respectively providing independent bias adjustment signal output terminals for the first pixel circuit 110 and the second pixel circuit 120, when the second bias adjustment signal output terminal 32 provides the first bias adjustment signal to the first pixel circuit 110, the third bias adjustment signal output terminal 33 can simultaneously provide the second bias adjustment signal to the second pixel circuit 120, thereby simplifying the driving timing.

[0083] Optional, continue to refer to Fig.11 The display panel also includes a second signal bus 202 and a third signal bus 203 , the first pixel circuit 110 is electrically connected to the second bias adjustment signal terminal 32 via the second signal bus 202 , and the second pixel circuit 120 is electrically connected to the third bias adjustment signal terminal 33 via the third signal bus 203 .

[0084] Specifically, the second signal bus 202 is connected to the first pixel circuit 110 through the first bias adjustment signal line 210, and the third signal bus 203 is connected to the second pixel circuit 120 through the second bias adjustment signal line 220. The second signal bus 202 and the third signal bus 203 can be set in the border area of ​​the display panel, wherein Fig.11 The second signal bus 202 and the third signal bus 203 shown in the figure are respectively located at the left and right borders, which is only for illustration and is not a limitation to the embodiment of the present invention.

[0085] It should be noted that the display panel also includes a reset signal terminal. The specific configuration of the reset signal terminal may be similar to the configuration of the bias adjustment signal terminal, which will not be described in detail here.

[0086] Optionally, in the first working mode, the display panel includes m1 display areas with different refresh rates, where m1 is an integer greater than or equal to 3. The display panel includes m1 bias adjustment signal output terminals, and different bias adjustment signal output terminals provide different bias adjustment signals for pixel circuits of corresponding display areas.

[0087] For example, Fig.12 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention, referring to Fig.12, Optionally, the display panel includes four display areas 101, 102, 103, and 104, and four bias adjustment signal output terminals 31, 32, 33, and 34. Each bias adjustment signal output terminal is connected to the pixel circuit of the corresponding display area ( Fig.12 not shown in the figure). In the first working mode, the refresh rates of the display areas 101, 102, 103, and 104 are different, and the bias adjustment signal output terminals 31, 32, 33, and 34 can respectively provide different bias adjustment signals for the corresponding pixel circuits. In another working mode, the refresh rates of the display areas 101, 102, 103, and 104 can be the same, and the bias adjustment signal output terminals 31, 32, 33, and 34 can respectively provide the same bias adjustment signal for the corresponding pixel circuits. In more working modes, at least two display areas can have the same refresh rate, and the embodiments of the present invention do not limit this.

[0088] It should be noted that in other embodiments, it is also possible to set the refresh rates of at least two different display areas to be the same. When the refresh rates of two display areas are the same, their pixel circuits can receive the same bias adjustment signal and / or reset signal. Specifically, optionally, the display panel includes m1 display areas, where m1 is an integer greater than or equal to 3. In the second working mode, the refresh rates of at least two display areas are the same. Optionally, the display panel includes m2 bias adjustment signal output terminals, m2 < m1, and at least one bias adjustment signal output terminal provides the same bias adjustment signal for the pixel circuits of at least two display areas with the same refresh rate.

[0089] Taking the display panel including four display areas as an example,示例性的, Fig.13 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Refer to Fig.13 , the display panel includes four display areas 101, 102, 103, and 101'. In a certain working mode, the refresh rates of 101 and 101' are the same. The display panel further includes three bias adjustment signal output terminals 31, 32, and 33, where 31 simultaneously provides a bias adjustment signal for the display areas 101 and 101'. Further, the pixel circuits of at least two display areas with the same refresh rate receive the same reset signal. This helps to simplify the number of bias adjustment signal terminals and the structure of the display panel.

[0090] Optionally, the display panel further includes a plurality of scan signal lines extending in a first direction and a plurality of data signal lines extending in a second direction, and the first direction and the second direction intersect; at least two display areas with different refresh rates are arranged along the first direction; or, at least two display areas with different refresh rates are arranged along the second direction.

[0091] Exemplarily, taking two display areas as an example, Fig.14A schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Fig.14 The display panel includes a plurality of scan signal lines 401 extending along a first direction x and a plurality of data signal lines 402 extending along a second direction y, and the first display area 101 and the second display area 102 are arranged along the second direction y.

[0092] It can be understood that the display panel also includes a first scanning circuit 501 corresponding to the first display area 101 and a second scanning circuit 502 corresponding to the second display area 102, wherein the first scanning circuit 501 may include multiple cascaded first shift registers, and the second scanning circuit 502 may include multiple cascaded second shift registers, and when the scanning frequencies of the first scanning circuit 501 and the second scanning circuit 502 are different, the refresh rates of the first display area 101 and the second display area 102 are different.

[0093] Fig.14 In the previously shown embodiment, display areas with different resolutions are arranged vertically (in the extension direction of the data signal line). In another embodiment, such as in applications such as folding screens, display areas with different resolutions can also be arranged horizontally (in the extension direction of the scan line). For example, Fig.15 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention, referring to Fig.15 The display panel includes a plurality of scan signal lines 401 extending along a first direction x and a plurality of data signal lines 402 extending along a second direction y, and the first display area 101 and the second display area 102 are arranged along the second direction y.

[0094] It can be understood that the display panel also includes a first scanning circuit 501 corresponding to the first display area 101 and a second scanning circuit 502 corresponding to the second display area 102, wherein the first scanning circuit 501 may include multiple cascaded first shift registers, and the second scanning circuit 502 may include multiple cascaded second shift registers, and when the scanning frequencies of the first scanning circuit 501 and the second scanning circuit 502 are different, the refresh rates of the first display area 101 and the second display area 102 are different.

[0095] An embodiment of the present invention further provides a display panel, including: at least two display areas, where the at least two display areas include a first display area and a second display area; a pixel circuit, the pixel circuit at least includes a first pixel circuit and a second pixel circuit, the first pixel circuit is located in the first display area, and the second pixel circuit is located in the second display area; the pixel circuit receives a reset signal, the reset signal includes a first reset signal and a second reset signal, when the refresh rate of the first display area is f1, the first pixel circuit receives the first reset signal, and when the refresh rate of the second display area is f2, the second pixel circuit receives the second reset signal; the display panel includes a plurality of light-emitting elements, the light-emitting elements include a first light-emitting element and a second light-emitting element, wherein, the first light-emitting element is located in the first display area, the second light-emitting element is located in the second display area, the first light-emitting element is connected to a first node of the first pixel circuit, the first reset signal is provided to the first node, the second light-emitting element is connected to a second node of the second pixel circuit, and the second reset signal is provided to the second node; wherein, f1≠f2, and the first reset signal is different from the second reset signal.

[0096] The technical solution of the embodiment of the present invention adjusts the anode voltage of the light-emitting element through the reset signal. When the refresh rates of the first display area and the second display area are different in order to achieve different display functions, the light-emitting time of the light-emitting element is different. By adjusting the reset signals of different display areas, it is beneficial to avoid uneven display in different display areas and improve the display effect.

[0097] Optionally, a frame of display screen includes a refresh frame and a hold frame; in the first display area, the number of times the first reset signal is loaded within the same refresh frame or the same hold frame is n3, and the voltage value of the first reset signal is V3; in the second display area, the number of times the second reset signal is loaded within the same refresh frame or the same hold frame is n4, and the voltage value of the second reset signal is V4; wherein, n3=n4, V3≠V4.

[0098] Optionally, f1>f2, V3>V4; or, f1<f2, V3<V4.

[0099] Optionally, a frame of display screen includes a refresh frame and a hold frame; in the first display area, the number of times the first reset signal is loaded within the same refresh frame or the same hold frame is n3, and the voltage value of the first reset signal is V4; in the second display area, the number of times the second reset signal is loaded within the same refresh frame or the same hold frame is n4, and the voltage value of the second reset signal is V4; wherein, n3≠n4, V3=V4.

[0100] Optionally, f1>f2, n3<n4; or, f1<f2, n3>n4.

[0101] It is understandable that the technical solution of setting different reset signals in this embodiment is similar to the above-mentioned embodiment and will not be described in detail here. Unlike the above-mentioned embodiment, this embodiment does not set a bias adjustment signal. In specific implementation, different bias adjustment signals can also be applied to pixel circuits in different display areas, and the implementation method is similar to the above-mentioned embodiment.

[0102] Fig.16 A schematic diagram of the structure of a display device provided by an embodiment of the present invention. Fig.16 The display device 1 includes any one of the display panels 2 provided in the embodiments of the present invention. The display device 1 can be a mobile phone, a computer, a smart wearable device, etc.

[0103] Since the display device provided in this embodiment includes any one of the display panels provided in the above embodiments, including the same or corresponding technical effects as the display panel, it will not be described in detail here.

[0104] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: Comprising: At least two display areas, at least two of the display areas including a first display area and a second display area; A pixel circuit, the pixel circuit at least including a first pixel circuit and a second pixel circuit, the first pixel circuit being located in the first display area, and the second pixel circuit being located in the second display area; The pixel circuit receives a bias adjustment signal, the bias adjustment signal including a first bias adjustment signal and a second bias adjustment signal. When the refresh rate of the first display area is f1, the first pixel circuit receives the first bias adjustment signal, and when the refresh rate of the second display area is f2, the second pixel circuit receives the second bias adjustment signal; A first signal bus, the first signal bus being electrically connected to the first pixel circuit and the second pixel circuit respectively.

2. The display panel according to claim 1, characterized in that: It further includes a plurality of first bias adjustment signal lines and second bias adjustment signal lines; At least one of the first bias adjustment signal lines is connected to the first pixel circuit and the first signal bus respectively; At least one of the second bias adjustment signal lines is connected to the second pixel circuit and the first signal bus respectively.

3. The display panel according to claim 2, characterized in that: The extending direction of the first bias adjustment signal line and / or the second bias adjustment signal line intersects with the extending direction of the first signal bus.

4. The display panel according to claim 2, characterized in that: The arrangement direction of the first display area and the second display area intersects with the extending direction of the first bias adjustment signal line and / or the second bias adjustment signal line.

5. The display panel according to claim 1, characterized in that: The display panel further includes a border area, and the first signal bus is located in the border area.

6. The display panel according to claim 1, characterized in that: The arrangement direction of the first display area and the second display area is the same as the extending direction of the first signal bus.

7. The display panel according to claim 1, characterized in that: The display panel further includes a bias adjustment signal output terminal, and the bias adjustment signal output terminal includes a first bias adjustment signal output terminal; The first signal bus is electrically connected to the first bias adjustment output terminal.

8. The display panel according to claim 7, characterized in that: In a first working mode, the display panel includes m1 display areas with different refresh rates, where m1 is an integer greater than or equal to 3; The display panel includes m1 bias adjustment signal output terminals, and different bias adjustment signal output terminals provide different bias adjustment signals for the pixel circuits of corresponding display areas.

9. The display panel according to claim 7, characterized in that: The display panel includes m1 display areas, where m1 is an integer greater than or equal to 3. In a second working mode, the refresh rates of at least two of the display areas are the same; The display panel includes m2 bias adjustment signal output terminals, m2 < m1, and at least one of the bias adjustment signal output terminals provides the same bias adjustment signal for the pixel circuits of at least two display areas with the same refresh rate.

10. The display panel according to claim 1, characterized in that: The first bias adjustment signal is different from the second bias adjustment signal.

11. The display panel according to claim 10, characterized in that: A frame of display picture includes a refresh frame and a hold frame; In the first display area, the number of times the first bias adjustment signal is loaded within the same refresh frame or the same hold frame is n1, and the voltage value of the first bias adjustment signal is V1; In the second display area, the number of times the second bias adjustment signal is loaded within the same refresh frame or the same hold frame is n2, and the voltage value of the second bias adjustment signal is V2; where n1 ≠ n2, or V1 ≠ V2.

12. The display panel according to claim 11, wherein f1 > f2, V1 < V2; or f1 < f2, V1 > V2.

13. The display panel according to claim 11, wherein f1 > f2, n1 < n2; or f1 < f2, n1 > n2.

14. The display panel according to claim 1, characterized in that: The first signal bus is configured to provide the first bias adjustment signal to the first pixel circuit in a first period and provide the second bias adjustment signal to the second pixel circuit in a second period.

15. The display panel according to claim 1, characterized in that: The display panel further includes a plurality of scan signal lines extending in a first direction and a plurality of data signal lines extending in a second direction, and the first direction and the second direction intersect; At least two display areas with different refresh rates are arranged along the first direction; or At least two display areas with different refresh rates are arranged along the second direction.

16. A display panel, characterized in that: The display panel includes: At least two display areas, where the at least two display areas include a first display area and a second display area; Pixel circuits, where the pixel circuits at least include a first pixel circuit and a second pixel circuit, the first pixel circuit is located in the first display area, and the second pixel circuit is located in the second display area; The pixel circuits receive reset signals, where the reset signals include a first reset signal and a second reset signal. When the refresh rate of the first display area is f1, the first pixel circuit receives the first reset signal, and when the refresh rate of the second display area is f2, the second pixel circuit receives the second reset signal; The display panel includes a plurality of light-emitting elements, where the light-emitting elements include a first light-emitting element and a second light-emitting element. The first light-emitting element is connected to a first node of the first pixel circuit, and the first reset signal is provided to the first node. The second light-emitting element is connected to a second node of the second pixel circuit, and the second reset signal is provided to the second node; The first reset signal and the second reset signal are provided by the same bus in a time-division manner; or the first reset signal and the second reset signal are independently provided by corresponding buses.

17. The display panel according to claim 16, characterized in that: The display panel further includes a reset signal terminal, and the reset signal terminal is electrically connected to the bus.

18. A display device, characterized in that: The display panel includes the display panel according to any one of claims 1 - 17.

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