Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a driving circuit; the driving circuit comprises N levels of shift register units which are cascaded with each other. In the same shift register unit, an initial control module is used for at least receiving an input signal and a first clock signal and controlling signals of a first initial node and a second initial node; the stage transmission output module is used for at least receiving a signal of a first initial node, a signal of a second initial node, a first level signal and a second level signal, and controlling a stage transmission signal; the driving control module is used for at least receiving a signal of a first initial node, a signal of a second initial node and a driving control signal, and controlling a signal of a first driving node; the driving output module is used for at least receiving a signal of a first driving node, a signal of a first initial node, a first level signal and a second level signal, and controlling a gate driving signal of a driving output node; the active auxiliary module is used for controlling a signal transmission path of the first level signal to the driving output node.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] At present, with the development of display technology, display panels have penetrated into all aspects of people's daily life. Display panels can use different image refresh rates for display in different application scenarios. For example, a higher image refresh rate drive (also called high-frequency drive) is used to drive dynamic images to ensure the smoothness of the image; while a lower image refresh rate drive (also called low-frequency drive) is used to drive static images to reduce power consumption.

[0003] In order to realize the image refresh function, each pixel circuit of the display panel is usually scanned with a scanning cycle matching the image refresh frequency. At this time, a driving circuit is usually provided in the display panel, and the driving circuit provides the enable level of the gate driving signal to each row of pixel circuits in turn, so that the display unit driven by each row of pixel circuits can display.

[0004] In order to meet the diversified display effects of partition display, the driving circuit can choose whether to transmit the enable level of the gate driving signal to the pixel circuit according to the refresh frequency of the area where the pixel is located. However, when the driving circuit outputs the effective pulse of the gate driving signal for a long time, the gate driving signal may fluctuate and affect the display effect. Summary of the invention

[0005] The present invention provides a display panel and a display device, which can improve the stability of a gate driving signal.

[0006] According to one aspect of the present invention, there is provided a display panel, comprising: a driving circuit;

[0007] The driving circuit includes N-stage shift register units cascaded to each other; the shift register unit includes an initial control module, a stage transmission output module, a driving control module, an active auxiliary module and a driving output module;

[0008] In the same shift register unit, the initial control module is used to at least receive an input signal and a first clock signal, and control signals of a first initial node and a second initial node;

[0009] The level transmission output module is used to receive at least the signal of the first initial node, the signal of the second initial node, the first level signal and the second level signal, and control the level transmission signal;

[0010] The driving control module is used to receive at least the signal of the first initial node, the signal of the second initial node and the driving control signal, and control the signal of the first driving node;

[0011] The driving output module is used to receive at least the signal of the first driving node, the signal of the first initial node, the first level signal and the second level signal, and control the signal of the driving output node; the driving output node is used to output a gate driving signal;

[0012] The active auxiliary module is used to receive the signal of the first driving node and the first level signal, and control the signal transmission path of the first level signal to the driving output node;

[0013] Among them, the stage transmission signal of the i-th stage shift register unit is the input signal of the j-th stage shift register unit; i, j and N are all positive integers, i≠j, and i≤N, j≤N.

[0014] According to another aspect of the present invention, a display device is provided, comprising: the above-mentioned display panel.

[0015] The display panel provided by the present invention uses the level transmission signal output by the intermediate transmission output module of each level of the shift register unit as the input signal of the shift register unit of other levels, and controls the driving output module to output the gate driving signal through the driving control module, and uses it as the driving signal of the pixel circuit in the display panel, so that the initial output signal and the gate driving signal output by the same shift register unit to other levels are independent of each other and do not affect each other, thereby ensuring that the level transmission and shifting of the signal can be performed between the shift register units, and at the same time, the polarity of the gate output signal provided to the pixel circuit can be flexibly controlled, so that the driving modes of the pixel circuits in different rows in the display panel can be the same or different, thereby making the display panel meet Diversified display requirements broaden the application scenarios of display panels. For example, different areas of the display panel can have different refresh frequencies. On this basis, when the driving control signal and the first initial node are both at non-enable levels, the first level signal is provided to the driving output node through the active auxiliary module, so that the gate driving signal output by the driving output node always remains as an active signal when the driving control signal remains at the non-enable level. Therefore, the active gate driving signal is not easily interfered by other signals, which is beneficial to improving the stability of the gate driving signal, and can avoid the gate driving signal floating and causing large fluctuations under the influence of parasitic capacitance, thereby effectively improving the display effect of the display panel.

[0016] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 It is a structural schematic diagram of a shift register unit in the prior art;

[0019] Figure 2 It is a signal timing diagram of a shift register unit in the prior art;

[0020] Figure 3 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0021] Figure 4 is a structural schematic diagram of a shift register unit provided by an embodiment of the present invention;

[0022] Figure 5 is a driving timing diagram of a shift register unit provided by an embodiment of the present invention;

[0023] Figure 6 is another driving timing diagram of a shift register unit provided by an embodiment of the present invention;

[0024] Figure 7 is a driving timing diagram of another shift register unit provided by an embodiment of the present invention;

[0025] Figure 8 is a driving timing diagram of another shift register circuit provided by an embodiment of the present invention;

[0026] Fig. 9 is a driving timing diagram of another shift register circuit provided by an embodiment of the present invention;

[0027] Fig.10 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0028] Fig.11 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0029] Fig.12 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0030] Fig.13 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0031] Fig.14is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0032] Fig.15 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0033] Fig.16 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0034] Fig.17 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0035] Fig.18 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0036] Fig.19 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0037] Fig. 20 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0038] Fig.21 is a driving timing diagram of another shift register unit provided by an embodiment of the present invention;

[0039] Fig. 22 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0040] Fig.23 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0041] Fig.24 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0042] Fig.25 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0043] Fig.26 is a driving timing diagram of another shift register circuit provided by an embodiment of the present invention;

[0044] Fig. 27 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0045] Fig.28 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0046] Fig.29 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0047] Fig.30 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0048] Fig.31 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0050] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0051] As described in the background technology, Figure 1 It is a structural diagram of a shift register unit in the prior art, such as Figure 1 As shown, the shift register unit 01′ includes an initial control module 011′, a level transmission output module 012′, a driving control module 013′ and a driving output module 014′. The initial control module 011′ receives at least an input signal Vin′ and a first clock signal ck1′, and controls the signal of the first initial node N1′ and the second initial node N2′. The level transmission output module 012′ receives the signal of the first initial node N1′ and the signal of the second initial node N2′, and outputs a level transmission signal Vnext′. The level transmission signal Vnext′ can be used as an input signal of the next level shift register unit 01′. The driving control module 013′ receives the level transmission signal Vnext′ and the driving control signal Vct′, and is used to control the signal of the driving node N3′. The driving output module 014′ receives the signal of the driving node N3′ and the signal of the second initial node N2′, and outputs a gate driving signal Gout′.

[0052] When high-frequency display is performed, the driving control signal Vct′ in the shift register unit 01′ corresponding to the high-frequency display area can be maintained at an enable level, so that the gate driving signal Gout′ of the shift register unit 01′ is consistent with the frequency of the effective level of the level transmission signal Vnext′, that is, when the level transmission signal Vnext′ is at an effective level, the driving node N3 is at an enable level, so that the driving output module 014′ outputs the effective level of the gate driving signal Gout′, thereby performing high-frequency refresh on the pixel to achieve high-frequency display. When the driving control signal Vct′ in the shift register 01′ during low-frequency display can be a non-enable level, then no matter whether the level transmission signal Vnext′ is at an effective level or an invalid level, the driving node N3 is maintained at a non-enable level, so that the driving output module 014′ cannot output the effective level of the gate driving signal Gout′, so that the scanning signal Gout′ provided to the pixel circuit has a reduced frequency of occurrence of the enable level, thereby achieving low-frequency display.

[0053] Figure 2 This is a signal timing diagram of a shift register unit in the prior art. Figure 1 and Figure 2 , the shift register unit 01′ during low-frequency display, in the T1′ stage, when the signal V_N2′ of the second initial node N2′ is at a non-enable level and the signal of the first initial node N1′ is at an enable level so that the level transfer signal Vnext′ is at a valid level, the gate drive signal Gout′ output by the drive output module 014′ can only be maintained at an invalid level according to the previous potential. At this stage, the gate drive signal Gout′ can only be a passive signal. Although it can continue to be maintained at an invalid level, it is very susceptible to the influence of other signals. For example, there is parasitic capacitance between the signal line transmitting the gate drive signal Gout′ and other signal lines or components. The coupling effect of the parasitic capacitance will cause the potential of the gate drive signal Gout′ to fluctuate, affecting the display effect of the display panel.

[0054] In order to solve the above technical problems, an embodiment of the present invention provides a display panel, which includes a driving circuit; the driving circuit includes N-stage shift register units cascaded with each other; the shift register unit includes an initial control module, a stage transmission output module, a driving control module, an active auxiliary module and a driving output module; in the same shift register unit, the initial control module is used to at least receive an input signal and a first clock signal, and control the signal of the first initial node and the second initial node; the stage transmission output module is used to at least receive the signal of the first initial node and the signal of the second initial node, and control the stage transmission signal; the driving control module is used to at least receive the signal of the first initial node and the signal of the second initial node, and control the stage transmission signal; The invention relates to a method for transmitting a gate drive signal to a gate driver of a first driving node and a gate driver of a second driving node; a signal of an initial node, a signal of a second initial node and a driving control signal to control the signal of the first driving node; a driving output module is used to receive at least the signal of the first driving node and the signal of the first initial node, and control the signal of the driving output node; the driving output node is used to output a gate driving signal; an active auxiliary module is used to receive the signal of the first driving node and a first level signal, and is used to control the transmission path of the first level signal to the driving output node; wherein the level transmission signal of the i-th level shift register unit is the input signal of the j-th level shift register unit; i, j and N are all positive integers, i≠j, and i≤N, j≤N.

[0055] By adopting the above technical solution, by using the level transmission signal output by the intermediate transmission output module of each level of shift register unit as the input signal of the shift register unit of other levels, and controlling the drive output module to output the gate drive signal through the drive control module, and using it as the drive signal of the pixel circuit in the display panel, the initial output signal and the gate drive signal output by the same shift register unit to other levels can be independent of each other and do not affect each other, thereby ensuring that the level transmission and shifting of the signal can be performed between the shift register units, and at the same time, the polarity of the gate output signal provided to the pixel circuit can be flexibly controlled, so that the driving modes of the pixel circuits in different rows in the display panel can be the same or different, thereby making the display panel meet multiple Diversified display needs can be met to broaden the application scenarios of display panels. For example, different areas of the display panel can have different refresh frequencies. On this basis, when the driving control signal and the first initial node are both at non-enable levels, a first level signal is provided to the driving output node through an active auxiliary module, so that the gate driving signal output by the driving output node always remains as an active signal when the driving control signal remains at a non-enable level. Therefore, the active gate driving signal is not easily interfered by other signals, which is beneficial to improving the stability of the gate driving signal and can avoid the gate driving signal floating and causing large fluctuations under the influence of parasitic capacitance, thereby effectively improving the display effect of the display panel.

[0056] The above is the core idea of ​​the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention.

[0057] Figure 3 is a schematic structural diagram of a display panel provided by an embodiment of the present invention, Figure 4 is a schematic diagram of a structure of a shift register unit provided by an embodiment of the present invention, and is combined with reference to Figure 3 and Figure 4 , the display panel 100 includes a driving circuit 10; the driving circuit 10 includes N-stage shift register units G (G1, G2, ..., Gi, ..., Gj, ..., Gn-1, Gn) cascaded with each other; the shift register unit G includes an initial control module 110, a stage transmission output module 120, a driving control module 130, an active auxiliary module 140 and a driving output module 150; in the same shift register unit G: the initial control module 110 is used to at least receive an input signal Vin and a first clock signal CK1, and control a signal of a first initial node N1 and a signal of a second initial node N2; the stage transmission output module 120 is used to at least receive a signal of a first initial node N1, a signal of a second initial node N2, a first level signal Vgl and a second level signal Vgh, and control a stage transmission signal Vnext; the driving control module 130 Used to at least receive the signal of the first initial node N1, the signal of the second initial node N2 and the drive control signal Vct, and control the signal of the first drive node N3; the drive output module 150 is used to at least receive the signal of the first drive node N3, the signal of the first initial node N1, the first level signal Vgl and the second level signal Vgh, and control the signal of the drive output node N4; the drive output node N4 is used to output the gate drive signal Gout; the active auxiliary module 140 is used to receive the signal of the first drive node N3 and the first level signal Vgl, and control the signal transmission path of the first level signal Vgl to the drive output node N4; wherein, the level transfer signal Vnext of the i-th stage shift register unit Gi is the input signal of the j-th stage shift register unit Gj; i, j and N are all positive integers, i≠j, and i≤N, j≤N.

[0058] It should be noted that the above description is only an exemplary description taking the example that the driving circuit 10 is located in the non-display area A1 and the pixel circuit 20 is located in the display area A2. In other embodiments of the present invention, the pixel circuit 20 and the driving circuit 10 may also be both located in the display area A2, so that the number of devices arranged in the non-display area A1 of the display panel 100 is sufficiently small, thereby reducing the size of the non-display area A1 of the display panel 100, which is beneficial to the narrow frame of the display panel 100 and enables the display panel 100 to have a higher screen-to-body ratio.

[0059] For ease of description, without special limitations, the embodiments of the present invention take the example that the driving circuit 10 is located in the non-display area A1 of the display panel 100 and the pixel circuit 20 is located in the display area A2 of the display panel 100 to exemplarily illustrate the technical solutions of the embodiments of the present invention.

[0060] Continue to refer Figure 3 and Figure 4 , the output end of the level transmission output module 120 of the x-th level shift register unit Gx can be electrically connected to the input end of the initial control module 110 of the y-th level shift register unit Gy, so that the level transmission signal Vnext output by the level transmission output module 120 of the x-th level shift register unit Gx can be the input signal Vin of the initial control module 110 of the y-th level shift register unit Gy. Among them, the x-th level shift register unit Gx and the y-th level shift register unit Gy can be two adjacent levels of shift register units. At this time, if x is equal to i, then y can be equal to i+1. Alternatively, the x-th level shift register unit Gx and the y-th level shift register unit Gy can also be two non-adjacent levels of shift register units. At this time, yx can be a positive integer greater than or equal to 2. On the premise that the core inventive point of the embodiment of the present invention can be realized, the values ​​of x and y in the embodiment of the present invention are not specifically limited.

[0061] For ease of description, without special limitation, the embodiments of the present invention take the x-th stage shift register unit and the y-th stage shift register unit as two adjacent stages of shift register units as an example to exemplarily illustrate the technical solutions of the embodiments of the present invention.

[0062] Continue to refer Figure 3 and Figure 4In the same shift register unit G, the initial control module 110 and the stage transmission output module 120 can be electrically connected to the first initial node N1 and the second initial node N2, respectively, and the initial control module 110 can also be electrically connected to the first initial node N1 and the second initial node N2 with the driving control module 130, and the initial control module 110 can also be electrically connected to the first initial node N1 with the driving output module 150. The driving output module 150 is also electrically connected to the initial control module 110 at the first driving control node N3, and the active auxiliary module 140 is electrically connected to the first driving control node N3 and the driving output module 150, respectively. For the first-stage shift register unit G1, the input signal Vin received by its initial control module 110 may be a start signal Stv provided by a start control circuit (not shown in the figure), so that the first-stage shift register unit G1 can at least respond to the start signal Stv and the first clock signal CK1, and provide corresponding signals to its first initial node N1 and the second initial node N2 respectively; and for the other-stage shift register units G except the first-stage shift register unit G1, the input end of its initial control module 110 may be electrically connected to the output end of the stage transmission output module 120 of the previous-stage shift register unit G, so that the shift register units G of each stage can at least respond to the stage transmission signal Vnext and the first clock signal CK1 output by the initial output module 120 of the previous-stage shift register unit G, so as to provide corresponding signals to its first initial node N1 and the second initial node N2. Wherein, in the same shift register unit G, the polarities of the signals of the first initial node N1 and the second initial node N2 may be the same or opposite. In an optional embodiment, at least part of the time, the polarities of the signals of the first initial node N1 and the second initial node N2 are opposite, that is, when the signal of the first initial node N1 is at a high level, the signal of the second initial node N2 may be at a low level; or, when the signal of the first initial node N1 is at a low level, the signal of the second initial node N2 is at a high level.

[0063] Correspondingly, in the same shift register unit G, the level transmission output module 120 can output the corresponding level transmission signal Vnext according to the signal of the first initial node N1 and the signal of the second initial node N2 received by it. For example, when the signal of the first output node N1 is at the enable level, the initial output module 120 can output the first level signal Vgl as the initial output signal Vnext, and when the signal of the second output node N2 is at the enable level, the initial output module 120 can output the second level signal Vgh as the initial output signal Vnext.

[0064] The driving control module 130 may provide a corresponding signal to the first driving node N3 at least according to the received signal of the first initial node N1, the signal of the second initial node N2 and the driving control signal Vct. For example, when the driving control signal Vct is at an enable level, the driving control module 130 may transmit the signal of the second initial node N2 to the first driving node N3 under the control of the first initial node N1, so that the signal of the first driving node N3 is the same as the signal of the second initial node N2. When the driving control signal Vct is at a non-enable level, the driving control module 130 may control the signal transmission path between the second initial node N2 and the first driving node N3 to be disconnected under the control of the first initial node N1, so that the signal of the second initial node N2 cannot be transmitted to the first driving node N3, and at the same time, the signal of the first driving node N3 is kept at a non-enable level. In this way, by setting the driving control module 130 in the shift register unit G, the driving control module 130 controls the signal of the first driving node N3 at least according to the driving control signal Vct, the signal of the first initial node N1 and the signal of the second initial node N2, so that the signal of the first driving node N3 is simultaneously controlled by the driving control signal Vct, the signal of the first initial node N1 and the signal of the second initial node N2, so that the signal of the first driving node N3 can be the same as or different from the signal of the second initial node N2.

[0065] The driving output module 150 may output a corresponding gate driving signal Gout according to at least the received signal of the first driving node N3, the signal of the first initial node N1, the first level signal Vgl, and the second level signal Vgh. For example, when the signal of the first driving node N3 is at the enable level, the driving output module 150 may output the second level signal Vgh as the gate driving signal Gout; and when the signal of the first initial node N1 is at the enable level, the driving output module 150 may output the first level signal Vgl as the gate driving signal Gout. In this way, when the signal of the first driving node N3 is the same as the signal of the second initial node N2, the gate driving signal Gout output by the driving output module 150 is the same as the level transmission signal Vnext output by the level transmission output module 120, and when the signal of the first driving node N3 is different from the signal of the second initial node N2, the gate driving signal Gout output by the driving output module 150 may be different from the level transmission signal Vnext output by the level transmission output module 120, so that the current level shift register unit G can provide the corresponding level transmission signal Vnext to the next level shift register unit, ensuring that the next level shift register unit G can work normally. Under the premise, the signal of the first driving node N3 of the current level shift register unit G can be controlled according to display requirements, that is, the gate driving signal Gout output by the current level shift register unit G is controlled according to display requirements, thereby meeting the diversified display requirements of the display panel 100.

[0066] Among them, when the driving control signal Vct is at a non-enable level, the signal of the first driving node N3 is kept at a non-enable level. At this time, if the signal of the first initial node N1 is at an enable level, the driving output module 150 outputs the received first level signal Vgl to the driving output node N4 as the gate driving signal Gout. At this time, the gate driving signal Gout is a stable active signal. When the signal of the first initial node N1 is at a non-enable level, the active auxiliary module 140 can transmit the received first level signal Vgl to the driving output node N4 as the gate driving signal Gout under the control of the first driving node N3. When the driving control signal Vct is the first level signal Vgl, which is not synchronized with the level transmission signal Vnext, that is, when the level transmission signal Vnext outputs the second level signal Vgh, the gate driving signal Gout still outputs the first level signal Vgl. When the second level signal Vgh is an enable level that enables the pixel circuit 20 to be refreshed, the shift register unit G can stop outputting the enable level of the gate drive signal Gout to the pixel when the drive control signal Vct remains at a non-enable level, so that the pixel circuit 20 electrically connected to the shift register unit G stops refreshing. In this way, the drive control signal Vct of the current stage shift register unit G can be controlled according to display requirements, which can meet the diversified display requirements of the display panel 100.

[0067] Furthermore, when the driving control signal Vct is at a non-enable level and the signal at the first initial node N1 is at a non-enable level, the received first level signal Vgl is transmitted to the driving output node N4 as the gate driving signal Gout through the active auxiliary module 140 under the control of the first driving node N3, so that the gate driving signal Gout output by the driving output node N4 can always be maintained as an active signal in the stage when the driving control signal Vct is maintained at a non-enable level. Compared with the prior art in which the driving control signal Vct and the first initial node N1 are both at a non-enable level, the gate driving signal Gout is maintained as the first level signal Vgl of the previous stage according to the previous potential, the active gate driving signal Gout is not easily interfered by other signals, which is beneficial to improving the stability of the gate driving signal Gout.

[0068] It can be understood that the level transmission signal Vnext and the gate drive signal Gout can both be pulse signals composed of a high level and a low level, and one of the high level and the low level is an enable level, and the other is a non-enable level. When the level transmission signal Vnext output by the same shift register unit G is different from the gate drive signal Gout, the level transmission signal Vnext output by the same shift register unit G and the gate drive signal Gout can have different periods, different durations of enable levels, different numbers of pulses of enable levels, etc., which can be set according to actual needs, and the embodiment of the present invention does not make specific limitations on this. One of the first level signal Vgl and the second level signal Vgh is a high level signal, and the other is a low level signal. For the convenience of explanation, unless otherwise specified, the following embodiments all use the first level signal Vgl as a low level signal and the second level signal Vgh as a high level signal to elaborate on the technical solution of the present invention in detail.

[0069] In addition, by setting the drive control module 130 in the shift register unit, the gate drive signal Gout output by the drive output module 150 is controlled by controlling the signal of the first drive node N3. Compared with the situation where the drive output module 150 is directly electrically connected to the second initial node N2 and the drive output module 150 directly receives the drive control signal Vct, the existence of the drive control module 130 can isolate the drive control signal Vct and the signal of the second initial node N2 from the signal of the first drive node N3, thereby preventing the second initial node N2 and the drive control signal Vct from fluctuating, thereby affecting the accuracy of the gate drive signal Gout output by the drive output module 150.

[0070] The display panel provided by the embodiment of the present invention uses the level transmission signal output by the intermediate transmission output module of each level of the shift register unit as the input signal of the shift register unit of other levels, and controls the driving output module to output the gate driving signal through the driving control module, and uses it as the driving signal of the pixel circuit in the display panel, so that the initial output signal and the gate driving signal output by the same shift register unit to other levels are independent of each other and do not affect each other, thereby ensuring that the level transmission and shifting of the signal can be performed between the shift register units, and at the same time, the polarity of the gate output signal provided to the pixel circuit can be flexibly controlled, so that the driving modes of the pixel circuits in different rows in the display panel can be the same or different, thereby making the display panel The invention meets diversified display requirements and broadens the application scenarios of display panels. For example, different areas of the display panel can have different refresh frequencies. On this basis, when the driving control signal and the first initial node are both at non-enable levels, the first level signal is provided to the driving output node through the active auxiliary module, so that the gate driving signal output by the driving output node always remains as an active signal when the driving control signal remains at the non-enable level. Therefore, the active gate driving signal is not easily interfered by other signals, which is beneficial to improving the stability of the gate driving signal and avoiding large fluctuations caused by the floating of the gate driving signal under the influence of parasitic capacitance, thereby effectively improving the display effect of the display panel.

[0071] Optional, Figure 5 is a driving timing diagram of a shift register unit provided by an embodiment of the present invention, such as Figure 5 As shown, the working mode of the display panel 100 includes a first mode Mode1, in which at least part of the display frame in the first mode Mode1 is a first display frame F1; the first display frame F1 includes a refresh phase T01 and a hold phase T02; the driving circuit 10 includes at least one first shift register unit G01; in the refresh phase T01, the driving control signal Vct includes a non-enable level, so that the level transmission signal Vnext01 output by the first shift register unit G01 includes a second level Vgh, and the gate driving signal Gout01 is a first level Vgl. The second level Vgh can be an effective level of the level transmission signal Vnext and the gate driving signal Gout, and the second level Vgl can be an invalid level of the level transmission signal and the gate driving signal Gout.

[0072] In the multi-frequency driving mode, different areas of the display panel 100 have different refresh frequencies. Figure 3, the display area A2 may include a low-frequency display area A21 and a high-frequency display area A22, and the refresh frequency of the pixel circuit 20 located in the low-frequency display area A21 is lower than the refresh frequency of the pixel circuit 20 in the high-frequency display area A22. At least part of the display frame of the multi-frequency driving mode is the first display frame F1. The first shift register unit G01 may be a shift register unit G electrically connected to the pixel circuit 20 in the low-frequency display area A21. In the first display frame F1, the gate drive signal Gout output by the first shift register unit G01 does not include a valid pulse, so that the pixel circuit 20 located in the low-frequency display area A21 does not perform signal refresh and maintains the grayscale of the previous display frame; while the signal of the pixel circuit 20 located in the high-frequency display area A22 can be refreshed to the grayscale of the current display frame. The first display frame F1 includes a refresh phase T01 and a hold phase T02. The refresh phase T01 refers to a phase in which at least part of the shift register units G can output valid pulses of the gate drive signal Gout to control at least part of the pixel circuits 20 to perform signal refresh; the hold phase T01 refers to a phase in which the drive circuit 10 cannot output valid pulses of the gate drive signal Gout, and can control each row of pixel circuits 20 to stop signal refresh and maintain the display phase of the current grayscale. In the refresh phase T01, the first shift register unit G01 can output valid pulses of the level transfer signal Vnext to drive the shift register units G at all levels, and at the same time, the drive control signal Vct includes a non-enable level, so that the gate drive signal Gout output by the first shift register unit G01 is maintained at the first level Vgl, so that the gate drive signal Gout01 output by the first shift register unit G01 does not perform signal refresh on the electrically connected pixel circuit 20 while ensuring the normal drive of the shift register units G at all levels, so that the pixel circuit 20 maintains the grayscale of the previous display frame.

[0073] It should be noted that Figure 5 An exemplary description is given by taking the enable level of the level transmission signal Vnext and the gate drive signal Gout as a high level, the non-enabled level as a low level, and the enable level of the drive control signal Vct as a low level, and the non-enabled level as a high level as an example. It can be understood that in other feasible embodiments of the present invention, it can also be set that the enable level of the level transmission signal Vnext and the gate drive signal Gout is a low level, the non-enabled level is a high level, the enable level of the drive control signal Vct is a high level, and the non-enabled level is a low level, and the embodiment of the present invention does not specifically limit this. For the sake of convenience of explanation, in the absence of special instructions, the following embodiments all take the enable level of the level transmission signal Vnext and the gate drive signal Gout as a high level, the non-enabled level as a low level, and the enable level of the drive control signal Vct as a low level, and the non-enabled level as a high level to elaborate on the technical solution of the present invention in detail.

[0074] Optional, Figure 6 is another driving timing diagram of the shift register unit provided by an embodiment of the present invention, combined with reference to Figure 4 , Figure 5 and Figure 6 In the refresh stage T01, when the driving control signal Vct is at the non-enable level (t01 stage), the level transfer signal Vnex01 output by the same first shift register unit G01 is the second level Vgh, and the gate driving signal Gout01 is the first level Vgl (t02 stage), the signal V_N1 of the first initial node N1 is at the non-enable level, the signal V_N2 of the second initial node N2 is at the enable level, and the signal V_N3 of the first driving node N3 is at the non-enable level.

[0075] Specifically, in the same first shift register unit G01, when the signal at the second initial node N2 is at the enable level, the level transmission output module 120 can be controlled to output the second level signal Vgh as the level transmission signal Vnext01, that is, the level transmission signal Vnext01 is at the second level Vgh. At the same time, the signal at the first initial node N1 is at the non-enable level, so that the level transmission output module 120 cannot output the first level signal Vgl, so that the level transmission signal Vnext01 remains at the second level Vgh. Moreover, in the t01 stage when the transmission control signal Vct is at the non-enable level in the refresh stage T01, the signal at the first drive output node N3 is at the non-enable level, so that the signal at the first drive node N3 is not synchronized with the signal at the second initial node N2, and the signal at the first drive node N3 can be kept at the non-enable level, so that the drive output module 150 stops outputting the second level signal Vgh to the drive output node N4.

[0076] Optional, continue to combine references Figure 4 , Figure 5 and Figure 6 When the signal at the first driving node N3 is at a non-enable level, the active auxiliary module 140 controls the transmission path of the first level signal Vgl to the driving output node N4 to be in a conducting state; when the signal at the first driving node N3 is at an enable level, the active auxiliary module 140 controls the signal transmission path of the first level signal Vgl to the driving output node N4 to be in a shut-off state.

[0077] Specifically, when the signal of the first driving node N3 is at a non-enable level (such as the t01 stage and the T02 stage), the driving output module 150 cannot output the second level signal Vgh to the driving output node N4. In this stage, the active auxiliary module 140 can output the first level signal Vgl to the driving output node N4 under the potential control of the first driving output node N3, so that the gate driving signal Gout output by the driving output node N4 is the first level Vgl, which can make the gate driving signal Gout output by the driving output node N3 always an active signal, avoid the gate driving signal Gout floating, and help to improve the stability of the gate driving signal Gout.

[0078] Optional, combined with reference Figure 3 , Figure 4 and Figure 5 In the holding stage T02, the driving control signal Vct is at a non-enable level, and the level transfer signal Vnext and the gate driving signal Gout output by each level of the shift register unit G are both at the first level Vgl.

[0079] Specifically, in the holding stage T02 of the first display frame F1, the level transfer signal Vnext output by each level of the shift register unit G does not include the second level, so that each level of the shift register unit G stops driving. At the same time, the driving control signal Vct is set to a non-enable level, so that the gate driving signal Gout output by each level of the shift register unit G does not include the second level, so that each row of pixel circuits 20 in the display area A2 does not perform signal refresh, so that each row of pixel circuits 20 maintains the grayscale of the refresh stage T01 for display.

[0080] Optional, continue to combine references Figure 3 , Figure 4 and Figure 5 The driving circuit 10 further includes a second shift register unit G02; in the refresh phase T01 of the first display frame F1, the driving control signal Vct includes an enable level, so that the level transfer signal Vnext02 and the gate driving signal Gout02 output by the second shift register unit G02 both include the second level Vgh.

[0081] Specifically, in the refresh phase T01 of the first display frame F1, the level transmission signal Vnext02 output by each level of the second shift register G02 includes the second level Vgh, so as to realize the driving of each level of the second shift register G02. The second shift register G02 can be electrically connected to the pixel circuit 20 of the high-frequency display area A22. In the refresh phase T01 of the first display frame F1, the driving control signal Vct is set to include an enable level (such as the t03 phase), so that the level transmission signal Vnext02 output by the second shift register G02 includes the second level Vgh, and the output gate driving signal Gout02 also includes the second level Vgh (such as the t04 phase), so that the signal of the electrically connected pixel circuit 20 can be refreshed. In this way, in the refresh stage T01, the level transfer signal Vnext output by each second shift register unit G02 and the first shift register unit G01 includes the second level Vgh, so that each level of shift register unit G normally outputs the effective pulse of the level transfer signal Vnext, thereby realizing the driving of each level of shift register unit G, and the gate drive signal Gout02 output by each second shift register unit G02 includes the second level Vgh and the gate drive signal Gout01 output by the first shift register unit G01 always remains at the first level Vgl, so that only the pixel circuit 20 electrically connected to the second shift register unit G02 performs signal refresh and displays with the refreshed grayscale, while the pixel circuit 20 electrically connected to the first shift register unit G01 does not perform signal refresh and maintains the grayscale of the previous display frame for display, so that the pixel circuit 20 electrically connected to the second shift register unit G02 and the pixel circuit 20 electrically connected to the first shift register unit G01 have different signal refresh frequencies, thereby realizing the diversified display function of the display panel.

[0082] Optional, Figure 7 is another driving timing diagram of a shift register unit provided by an embodiment of the present invention, combined with reference to Figure 4 , Figure 5 and Figure 7 In the refresh stage T01, when the drive control signal Vct is at the enable level (t03 stage), the level transfer signal Vnext02 and the gate drive signal Gout02 output by the same second shift register unit G02 are both at the second level Vgh, the signal of the first initial node N1 is at the non-enable level, the signal of the second initial node N2 is at the enable level, and the signal of the first drive node N3 is at the enable level.

[0083] Specifically, in the same second shift register unit G02, when the signal at the second initial node N2 is at the enable level, the level transmission output module 120 can be controlled to output the second level signal Vgh as the level transmission signal Vnext01, that is, the level transmission signal Vnext01 is at the second level Vgh. At the same time, the signal at the first initial node N1 is at the non-enable level, so that the level transmission output module 120 cannot output the first level signal Vgl, so that the level transmission signal Vnext01 remains at the second level Vgh, which can prevent the level transmission output module 120 from outputting two levels of signals at the same time, thereby preventing signal collision from damaging the circuit. Furthermore, in the stage t03 when the transmission control signal Vct is at the enable level in the refresh stage T01, the signal of the first driving output node N3 can be made the same as the signal of the second initial node N2, so that when the signal of the second initial node N2 is at the enable level in the stage t04, the signal of the first driving node N3 is also at the enable level, and then when the level transmission signal Vnext01 is at the second level Vgh, the driving output module 150 can output the second level signal Vgh to the driving output node N4 under the control of the first driving node N3, so that the gate driving signal Gout02 is at the second level Vgh. That is, in the process of driving the control signal Vct at the enable level in the refresh stage T01, the second shift register unit G02 simultaneously outputs the effective pulses of the level transmission signal Vnext02 and the gate driving signal Gout02, and while realizing the driving of the next-stage shift register unit G, the signal of the electrically connected pixel circuit 20 is refreshed to achieve a higher refresh frequency.

[0084] Optional, Figure 8 is another driving timing diagram of a shift register circuit provided by an embodiment of the present invention, such as Figure 8 As shown, part of the display frame of the first mode Mode1 is the second display frame F2; in the second display frame F2, the level transmission signal Vnext01 and the gate drive signal Gout01 output by the first shift register unit G01 both include the second level Vgh, and the level transmission signal Vnext02 and the gate drive signal Gout02 output by the second shift register unit G02 both include the second level Vgh; the first mode Mode1 includes multiple display cycles; the display cycle includes at least one first display frame F1 and at least one second display frame F2; wherein, the second display frame F2 is located before the first display frame F1.

[0085] Specifically, in the first mode Mode1, in the refresh stage T03 of the second display frame F2 of the display panel 100, the level transmission signal Vnext01 and the gate drive signal Gout01 output by the first shift register unit G01 both include the second level Vgh to drive each level of the shift register unit G; at the same time, the level transmission signal Vnext02 and the gate drive signal Gout02 output by the second shift register unit G02 both include the second level Vgh, so that the pixel circuit 20 located in the high-frequency display area A22 and the pixel circuit 20 located in the low-frequency display area A21 can both perform signal refresh. The second display frame F2 is located before the first display frame F1. After the pixel circuit 20 in the high-frequency display area A22 and the pixel circuit 20 in the low-frequency display area A21 in the second display frame F2 are both refreshed with signals, only the pixel circuit 20 in the high-frequency display area A22 is refreshed in the first display frame F1 to display the rewritten grayscale data, while the pixel circuit 20 in the low-frequency display area A21 is not refreshed with signals and maintains the grayscale of the second display frame F2 for display.

[0086] For example, taking the display cycle including a second display frame F2 and a first display frame F1 as an example, continue to refer to Figure 3 and Figure 8 The pixel circuit 20 located in the high-frequency display area A22 can perform signal refresh and rewrite data signals in each display frame, while the pixel circuit 20 located in the low-frequency display area A21 can perform signal refresh and rewrite data signals only in the second display frame F2, which makes the signal refresh frequency of the pixel circuit 20 located in the high-frequency display area A22 twice the signal refresh frequency of the pixel circuit 20 located in the low-frequency display area A21.

[0087] It can be understood that when the display cycle includes a second display frame and d first display frames, the signal refresh frequency of the pixel circuit 20 located in the low-frequency display area A21 is f1, and the signal refresh frequency of the pixel circuit 20 located in the high-frequency display area A22 is f2, then f1 / f2=1 / (d+1).

[0088] Optional, Fig. 9 is another driving timing diagram of a shift register circuit provided by an embodiment of the present invention, such as Fig. 9As shown, the working mode of the display panel 100 includes a second mode Mode2; in the second mode Mode2, the frequency of the level transmission signal Vnext01 output by the first shift register unit G01 is equal to the frequency of the gate drive signal Gout01; the frequency of the level transmission signal Vnext02 output by the second shift register unit G02 is equal to the frequency of the gate drive signal Gout02; and the frequency Gout01 of the gate drive signal output by the first shift register unit G01 is equal to the frequency of the gate drive signal Gout02 output by the second shift register unit G02.

[0089] Specifically, in the second mode Mode2, the refresh frequencies of the various regions of the display panel 100 may be the same, and at this time, the frequencies of the effective pulses of the gate drive signals Gout01 of the shift register units G at each level are the same, so that the refresh frequencies of the pixel circuits 20 of each row in the display area A2 are the same. The second mode Mode2 may be a global high-frequency display mode, and at this time, the frequencies of the gate drive signals Gout of the shift register units G at each level may be the same as the frequency of the level transmission signal Vnext, that is, the frequencies of the effective pulses of the gate drive signals Gout are the same as the frequencies of the effective pulses of the level transmission signal Vnext, so as to achieve high-frequency refresh of the pixel circuits 20 of each row in the display area A2.

[0090] Exemplary, reference Fig. 9 In the second mode Mode2, the driving control signal Vct is kept at the enable level. In this way, when the shift register unit G of each stage transmits the valid pulse of the signal Vnext at the output stage, it can simultaneously output the valid pulse of the gate driving signal Gout, and can refresh the signal of the electrically connected pixel circuit 20 while driving the shift register unit G of the next stage, thereby realizing high-frequency refreshing of the pixel circuits 20 of each row in the display area A2.

[0091] It should be noted that, in the shift register unit, since the initial control module at least receives the input signal and the first clock signal to control the signals of the first initial node and the second initial node, the stage transmission output module at least receives the signals of the first initial node and the second initial node, the drive control module at least receives the signal of the first initial node and the drive control signal to control the signal of the first drive node, and the drive output module at least receives the signals of the first drive node and the first initial node, the input signal and the first clock signal control the signals of the first initial node and the second initial node, the signals of the first initial node and the second initial node can control the stage transmission signal output by the stage transmission output module, the first initial node and the drive control signal can control the signal of the first drive node, and the first drive node and the first initial node can control the gate drive signal output by the drive output module. The stage transmission signal and the gate drive signal can be the same or different, which is related to the specific structure of the stage transmission output module, the drive control module and the drive output module. The structure of the initial control module, the stage transmission output module, the drive control module and the drive output module are exemplarily described below with a typical example.

[0092] Optional, Fig.10 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present invention, such as Fig.10 As shown, the active auxiliary module 140 includes an active auxiliary transistor M41; the gate of the active auxiliary transistor M41 is electrically connected to the first driving node N3, the first electrode of the active auxiliary transistor M41 receives the first level signal Vgl, and the second electrode of the active auxiliary transistor M41 is electrically connected to the driving output node N4.

[0093] Specifically, the active auxiliary transistor M41 can be turned on or off under the control of the potential of the first driving node N3. When the first driving node N3 is at a non-enable level so that the drive output module 150 cannot output the second level signal Vgh to the drive output node N4, the active auxiliary transistor M41 is turned on under the control of the potential of the first driving node N3, so that the active auxiliary transistor M41 outputs the first level signal Vgl to the drive output node N4, so that the gate drive signal Gout is the first level signal Vgl. When the first driving node N3 is at an enable level so that the drive output module 150 outputs the second level signal Vgh as the gate drive signal Gout, the active auxiliary transistor M41 is turned off under the control of the potential of the first driving node N3, so that the active auxiliary transistor M41 cannot transmit the first level signal Vgl to the drive output node N4, so that the gate drive signal Gout remains as the second level signal Vgh.

[0094] Exemplarily, the active auxiliary transistor M41 may be an N-type MOS transistor or a P-type MOS transistor. When the active auxiliary transistor M41 is an N-type MOS transistor, the enable level of the first driving node N3 is a low level, and the non-enable level is a high level, that is, when the first driving node N3 is a high level, the control driving output module 150 cannot output the second level signal Vgh to the driving output node N4, and the active auxiliary transistor M41 is controlled to be turned on, so that the driving output node N4 outputs the first level signal Vgl as the gate driving signal Gout; and when the first driving node N3 is a low level, the control driving output module 150 outputs the second level signal Vgh to the driving output node N4 as the gate driving signal Gout, and the control active auxiliary transistor M41 is turned off, so that the active auxiliary transistor M41 cannot output the first level signal Vgl to the driving output node N4. Alternatively, when the active auxiliary transistor M41 is a P-type MOS tube, the enable level of the first driving node N3 is a high level, and the non-enable level is a low level, that is, when the first driving node N3 is a high level, the control driving output module 150 outputs the second level signal Vgh to the driving output node N4, and controls the active auxiliary transistor M41 to be disconnected, so that the gate driving signal Gout is the second level signal Vgh; and when the first driving node N3 is a low level, the control driving output module 150 cannot output the second level signal Vgh to the driving output node N4, and controls the active auxiliary transistor M41 to be turned on so that the gate driving signal Gout is the first level signal Vgl. The embodiment of the present invention does not specifically limit the channel type of the active auxiliary transistor M41. In the absence of special instructions, the embodiment of the present invention takes the active auxiliary transistor M41 as a P-type MOS tube as an example for explanation.

[0095] Optional, Fig.11 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.11 As shown, the driving control module 130 includes: a first driving control unit 131 and a second driving control unit 132; the first driving control unit 131 is used to receive the driving control signal Vct, the signal of the first initial node N1 and the signal of the second initial node N2, and control the signal of the first driving node N3; the second driving control unit 132 is used to receive the signal of the first initial node N1 and the second level signal Vgh, and control the signal of the first driving node N3.

[0096] Specifically, the first driving control unit 131 can control the signal transmission path between the second initial node N2 and the first driving node N3 under the joint action of the first initial node N1 and the driving control signal Vct. In an exemplary embodiment, when the first initial node N1 and the driving control signal Vct are both at the enable level, the signal transmission path between the second initial node N2 and the first driving node N3 can be controlled to be turned on, so that the signal of the first driving node N3 is the same as the signal of the second initial node N2. The second driving control unit 132 can control the signal transmission path of the second level signal Vgh to the first driving node N3 under the control of the first initial node N1. For example, when the first initial node N1 is at an enable level so that the drive output module 150 outputs the first level signal Vgl as the gate drive signal Gout, the second drive control unit 132 is controlled to be turned on so that the second level signal Vgh is transmitted to the first drive node N3, and when the first initial node N1 is at a non-enable level so that the drive output module 150 cannot output the first level signal Vgl to the drive output node N4, the second drive control unit 132 is controlled to be turned off so that the second level signal Vgh cannot be transmitted to the first drive node N3. In this way, the signal of the first drive node N3 can be controlled according to the signal of the first initial node N1 and the drive control signal Vct.

[0097] Optional, Fig.12 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.12 As shown, the first drive control unit 131 includes a first drive control transistor M31, a second drive control transistor M32 and a first storage capacitor C1; the gate of the first drive control transistor M31 is electrically connected to the first initial node N1, and the first electrode of the first drive control transistor M31 receives the drive control signal Vct; the gate of the second drive control transistor M32 is electrically connected to the second electrode of the first drive control transistor M31 and the first electrode plate of the first storage capacitor C1, the first electrode of the second drive control transistor M32 is electrically connected to the second initial node N2, and the second electrode of the second drive control transistor M32 is electrically connected to the first drive node N3; the second electrode plate of the first storage capacitor C1 receives a fixed signal.

[0098] Specifically, when the first initial node N1 is at an enable level, the first drive control transistor M31 is turned on, and the drive control signal Vct can be transmitted to the gate of the second drive control transistor M32. If the drive control signal Vct is an enable signal at this time, the second drive control transistor M32 can be controlled to be turned on, so that the signal of the second initial node N2 is transmitted to the first drive node N3 through the second drive control transistor M32. Therefore, when it is necessary to synchronize the signal of the first drive node N3 with the signal of the second initial node N2, the drive control signal Vct can be controlled to be at an enable level when the signal of the first initial node N1 is at an enable level, so that the signal transmission path between the second initial node N2 and the first drive node N3 can be controlled to be turned on. Conversely, when it is necessary to isolate the signal of the first drive node N3 from the signal of the second initial node N2, the drive control signal Vct can be controlled to be at a non-enable level when the signal of the first initial node N1 is at an enable level, so that the second drive control transistor M32 can be controlled to be turned off, so that the signal of the second initial node N2 and the signal of the first drive node N3 are isolated from each other and do not affect each other.

[0099] The first plate of the first storage capacitor C1 is electrically connected to the gate of the second drive control transistor M32, and the second plate of the first storage capacitor C1 can be electrically connected to a fixed signal terminal to receive a fixed signal. Fig.12 The second plate of the first storage capacitor C1 is shown to receive the first level signal Vgl. In other feasible embodiments of the present invention, the second plate of the first storage capacitor C1 can also receive the second level signal Vgh, and can store the gate potential of the second drive control transistor M32. In the stage where the drive control signal Vct is at the enable level, when the signal of the first initial node N1 is at the enable level, the enable level of the drive control signal Vct is written to the gate of the second drive control transistor M32 and the first storage capacitor C1. After the signal of the first initial node N1 jumps from the enable level to the non-enable level, the first storage capacitor C1 can keep the gate potential of the second drive control transistor M32 at the enable level, so as to ensure that the second drive control transistor M32 always remains in the on state during the stage where the drive control signal Vct remains at the enable level. In the stage where the drive control signal Vct is at the non-enable level, when the signal at the first initial node N1 is at the enable level, the non-enable level of the drive control signal Vct is written to the gate of the second drive control transistor M32 and the first storage capacitor C1. Then, after the signal at the first initial node N1 jumps from the non-enable level to the enable level, the first storage capacitor C1 can keep the gate potential of the second drive control transistor M32 at the non-enable level, so as to ensure that the second drive control transistor M32 always remains in the disconnected state in the stage where the drive control signal Vct remains at the non-enable level.

[0100] Optional, reference Fig.12 The second driving control unit 132 includes a third driving control transistor M33 and a second storage capacitor C2; the gate of the third driving control transistor M33 is electrically connected to the first initial node N1, the first electrode of the third driving control transistor M33 receives the second level signal Vgh, and the second electrode of the third driving control transistor M33 is electrically connected to the first driving node N3; the first plate of the second storage capacitor C2 receives a fixed signal, and the second plate of the second storage capacitor C2 is electrically connected to the first driving node N3.

[0101] Specifically, when the first initial node N1 is at the enable level, the third drive control transistor M33 is turned on, so that the second level signal Vgh is transmitted to the first drive node N3; the enable level of the first initial node N1 simultaneously controls the drive output module 150 to output the first level signal Vgl to the drive output node N4 as the gate drive signal Gout, and controls the active auxiliary module 140 to output the first level signal Vgl to the drive output node N4, and the second level signal Vgh of the first drive node N3 controls the drive output module 150 to be unable to transmit the second level signal Vgh to the drive output node N4, so that the drive output node N4 remains as the first level signal Vgl. When the first initial node N1 is at the non-enable level, the third drive control transistor M33 is disconnected, so that the third drive control transistor M33 cannot transmit the second level signal Vgh to the first drive node N3; at this time, when the drive control signal Vct is at the non-enable level, the first drive node N3 and the second initial node N2 are isolated from each other, and the second storage capacitor C2 keeps the first drive node N3 at the second level signal Vgh; and if the drive control signal Vct is at the enable level, the signal of the first drive node N3 is controlled by the second initial node N2, and is the same as the signal of the second initial node N2. The fixed signal electrically connected to the second storage capacitor C2 can be the first level signal Vgl or the second level signal Vgh, Fig.12 It is exemplarily shown that the second plate of the second storage capacitor C2 receives the second level signal Vgh. In other feasible embodiments of the present invention, the second plate of the second storage capacitor C2 can also receive the first level signal Vgl, and can store the signal of the first driving node N3.

[0102] Optional, Fig.13 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.13As shown, the driving output module 150 includes a first driving output unit 151 and a second driving output unit 152; the first driving output unit 151 is used to receive the signal of the first initial node N1 and the first level signal Vgl, and control the gate driving signal Gout; the second driving output unit 152 is used to receive the signal of the first driving node N3 and the second level signal Vgh, and control the gate driving signal Gout.

[0103] Specifically, the first driver output unit 151 receives the signal of the first initial node N1 and the first level signal Vgl, and can control the signal transmission path of the first level signal Vgl to the driver output node N4 under the control of the first initial node N1. The second driver output unit 152 receives the signal of the first driver node N3 and the second level signal Vgh, and can control the signal transmission path of the second level signal Vgh to the driver output node N4 under the control of the first driver node N3. In this way, the signal of the first initial node N1, the first level signal Vgl, the signal of the first driver node N3 and the second level signal Vgh can determine the polarity and amplitude of the gate drive signal Gout.

[0104] In an exemplary embodiment, when the signal at the first initial node N1 is at an enable level, the first drive output unit 151 may transmit the first level signal Vgl to the drive output node N4, so that the gate drive signal Gout is the first level signal Vgl, and when the signal at the first drive node N3 is at an enable level, the second drive output unit 152 may transmit the second level signal Vgh to the drive output node N4, so that the gate drive signal Gout is the second level signal Vgh.

[0105] In an alternative embodiment, Fig.14 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.14 As shown, the first driving output unit 151 includes a first driving output transistor M51; the gate of the first driving output transistor M51 is electrically connected to the first initial node N1, the first electrode of the first driving output transistor M51 receives the first level signal Vgl, and the second electrode of the first driving output transistor M51 is electrically connected to the driving output node N4. In this way, the first driving output transistor M51 can be turned on or off under the control of the signal of the first initial node N1, and when the signal of the first initial node N1 controls the first driving output transistor M51 to be turned on, the first level signal Vgl received by the first electrode of the first driving output transistor M51 can be transmitted to its driving output node N4, so that the first level signal Vgl is used as the gate driving signal Gout output by the driving output node N4.

[0106] Optional, reference Fig.14, the second driving output unit 152 includes a second driving output transistor M52; the gate of the second driving output transistor M52 is electrically connected to the first driving node N3, the first electrode of the second driving output transistor M52 receives the second level signal Vgh, and the second electrode of the second driving output transistor M52 is electrically connected to the driving output node N4. In this way, the second driving output transistor M52 can be turned on or off under the control of the signal of the first driving node N3, and when the signal of the first driving node N3 controls the second driving output transistor M52 to be turned on, the second level signal Vgh received by the first electrode of the second driving output transistor M52 can be transmitted to the driving output node N4, so that the second level signal Vgh is used as the gate driving signal Gout output by the driving output node N4.

[0107] Optional, Fig.15 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.15 As shown, the level transmission output module 120 includes a first-level transmission output unit 121 and a second-level transmission output unit 122; the first-level transmission output unit 121 is used to receive the signal of the first initial node N1 and the first level signal Vgl, and control the level transmission signal Vnext; the second-level transmission output unit 122 is used to receive the signal of the second initial node N2 and the second level signal Vgh, and control the level transmission signal Vnext.

[0108] Specifically, the first-stage transmission output unit 121 receives the signal of the first initial node N1 and the first level signal Vgl, so that the first-stage transmission output unit 121 can output the level transmission signal Vnext under the control of the signal of the first initial node N1 and the first level signal Vgl. The second-stage transmission output unit 122 receives the signal of the second initial node N2 and the second level signal Vgh, so that the second-stage transmission output unit 122 can output the level transmission signal Vnext under the control of the signal of the second initial node N2 and the second level signal Vgh. In this way, the signal of the first initial node N1, the first level signal Vgl, the signal of the second initial node N2 and the second level signal Vgh can determine the polarity and amplitude of the level transmission signal Vnext.

[0109] In an exemplary embodiment, when the signal of the first initial node N1 is at an enable level, the first-level transmission output unit 121 can control the level transmission signal Vnext to be consistent with the first level signal Vgl, and when the signal of the second initial node N2 is at an enable level, the second-level transmission output unit 122 can control the level transmission signal Vnext to be consistent with the second level signal Vgh.

[0110] Optional, Fig.16 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.16As shown, the first-stage transmission output unit 121 includes a first-stage transmission output transistor M21; the gate of the first-stage transmission output transistor M21 is electrically connected to the first initial node N1, the first electrode of the first-stage transmission output transistor M21 receives the first level signal Vgl, and the second electrode of the first-stage transmission output transistor M21 outputs the level transmission signal Vnext. In this way, the first-stage transmission output transistor M21 can be turned on or off under the control of the signal of the first initial node N1, and when the signal of the first initial node N1 controls the first-stage transmission output transistor M21 to be turned on, the first level signal Vgl received by the first electrode of the first-stage transmission output transistor M21 can be transmitted to its second electrode, so that the first level signal Vgl is used as the level transmission signal Vnext output by the second electrode of the first-stage transmission output transistor M21.

[0111] Optional, reference Fig.16 , the second-stage transmission output unit 122 includes a second-stage transmission output transistor M22; the gate of the second-stage transmission output transistor M22 is electrically connected to the second initial node N2, the first electrode of the second-stage transmission output transistor M22 receives the second level signal Vgh, and the second electrode of the second-stage transmission output transistor M22 outputs the level transmission signal Vnext. In this way, the second-stage transmission output transistor M22 can be turned on or off under the control of the signal of the second initial node N2, and when the signal of the second-stage transmission node N2 controls the second-stage transmission output transistor M22 to be turned on, the second voltage signal Vgh received by the first electrode of the second-stage transmission output transistor M22 can be transmitted to its second electrode, so that the second voltage signal Vgh is used as the level transmission signal Vnext output by the second electrode of the second-stage transmission output transistor M22.

[0112] Optional, Fig.17 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.17 As shown, the initial control module 110 includes a first initial control unit 111 and a second initial control unit 112; the first initial control unit 111 is used to receive the input signal Vin and the first clock signal CK1, and control the signal of the first initial node N1; the second initial control unit 112 is used to receive the signal of the first initial node N1, the first level signal Vgl and the second level signal Vgh, and control the signal of the second initial node N2.

[0113] Specifically, the first initial control unit 111 can provide a signal to the first initial node N1 under the control of the first clock signal CK1 and the input signal Vin, so that the first clock signal CK1 and the input signal Vin can control the polarity and amplitude of the first initial node N1; the second initial control unit 112 can provide a signal to the second initial node N2 under the control of the signal of the first initial node N1, the first level signal Vgl and the second level signal Vgh, so that the signal of the first initial node N1, the first level signal Vgl and the second level signal Vgh can control the polarity and amplitude of the second initial node N2.

[0114] In an exemplary embodiment, when the first clock signal CK1 is at an enable level, the first initial control unit 111 may transmit the input signal Vin to the first initial node N1, so that the signal of the first initial node N1 is consistent with the input signal Vin. For the second initial control unit 112, when the signal of the first initial node N1 is at an enable level, the second initial control unit 112 may transmit the second level signal Vgh to the second initial node N2, so that the signal of the second initial node N2 is consistent with the second level signal Vgh; and when the signal of the first initial node N1 is at a non-enable level, the second initial control unit 112 may transmit the first level signal Vgl to the second initial node N2, so that the signal of the second initial node N2 is consistent with the first level signal Vgl.

[0115] Optional, Fig.18 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.18 As shown, the first initial control unit 111 includes an input subunit 111a; the input subunit 111a is used to receive the input signal Vin and the first clock signal CK1, and control the signal of the first initial node N1. The first initial control unit 111 can provide a signal to the first initial node N1 under the control of the first clock signal CK1 and the input signal Vin, so that the first clock signal CK1 and the input signal Vin can control the polarity and amplitude of the first initial node N1.

[0116] Optional, Fig.19 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.19As shown, the input subunit 111a includes a first input transistor M11; the gate of the first input transistor M11 receives the first clock signal CK1, the first electrode of the first input transistor M11 receives the input signal Vin, and the second electrode of the first input transistor M11 is electrically connected to the first initial node N1. In this way, the first input transistor M11 can be turned on or off under the control of the first clock signal CK1, and when the signal of the first clock signal CK1 controls the first input transistor M11 to be turned on, the input signal Vin received by the first electrode of the first input transistor M11 can be transmitted to the first initial node N1, so that the signal of the first initial node N1 is consistent with the input signal Vin. Among them, the first input transistor M11 can be an N-type MOS tube or a P-type MOS tube. In the absence of special instructions, the embodiments of the present invention all explain the technical solution by taking the first input transistor M11 as a P-type MOS tube.

[0117] Optional, reference Fig.18 The second initial control unit 112 includes a first initial control subunit 112a and a second initial control subunit 112b; the first initial control subunit 112a is used to receive the second level signal Vgh and the signal of the first initial node N1, and control the signal of the second initial node N2; the second initial control subunit 112b is used to receive the first level signal Vgl and the signal of the first initial node N1, and control the signal of the second initial node N2. The first initial control subunit 112a can provide a signal to the second initial node N2 under the control of the first initial node N1 and the second level signal Vgh, and the second initial control subunit 112b can provide a signal to the second initial node N2 from the first initial node N1 and the first level signal Vgl.

[0118] Exemplarily, the enable levels of the first initial control subunit 112a and the second initial control subunit 112b are different, so that at the same time, the first initial node N1 controls one of them to be in an on state and the other to be in an off state.

[0119] Optional, reference Fig.19, the first initial control subunit 112a includes a first initial control transistor M12; the gate of the first initial control transistor M12 is electrically connected to the first initial node N1, the first electrode of the first initial control transistor M12 receives the second level signal Vgh, and the second electrode of the first initial control transistor M12 is electrically connected to the second initial node N2. In this way, the first initial control transistor M12 can be turned on or off under the control of the signal of the first initial node N1, and when the signal of the first initial node N1 controls the first initial control transistor M12 to be turned on, the second level signal Vgh received by the first electrode of the first initial control transistor M12 can be transmitted to the second initial node N2, so that the signal of the second initial node N2 is consistent with the second level signal Vgh.

[0120] Optional, continue to refer to Fig.19 , the second initial control subunit 112b includes a second initial control transistor M13; the gate of the second initial control transistor M13 is electrically connected to the first initial node N1, the first electrode of the second initial control transistor M13 receives the first level signal Vgl, and the second electrode of the first initial control transistor M13 is electrically connected to the second initial node N2. In this way, the second initial control transistor M13 can be turned on or off under the control of the signal of the first initial node N1, and when the signal of the first initial node N1 controls the second initial control transistor M13 to be turned on, the first level signal Vgl received by the first electrode of the second initial control transistor M13 can be transmitted to the second initial node N2, so that the signal of the second initial node N2 is consistent with the first level signal Vgl.

[0121] Exemplarily, the first initial control transistor M12 can be set to be a P-type MOS transistor and the second initial control transistor M13 can be set to be an N-type MOS transistor. In this case, when the first initial node N1 is at a low level, the first initial control transistor M12 is turned on and the second initial control transistor M13 is turned off, and the second initial node N2 is written with the second level signal Vgh; when the first initial node N1 is at a high level, the first initial control transistor M12 is turned off and the second initial control transistor M13 is turned on, and the second initial node N2 is written with the first level signal Vgl. Alternatively, in another feasible embodiment, the first initial control transistor M12 can also be set to be an N-type MOS transistor and the second initial control transistor M13 can be set to be a P-type MOS transistor. In this case, when the first initial node N1 is at a low level, the first initial control transistor M12 is turned off and the second initial control transistor M13 is turned on, and the second initial node N2 is written with the first level signal Vgl; when the first initial node N1 is at a high level, the first initial control transistor M12 is turned on and the second initial control transistor M13 is turned off, and the second initial node N2 is written with the second level signal Vgh. In the case where there is no special explanation, the embodiments of the present invention all take the first initial control transistor M12 as a P-type MOS transistor and the second initial control transistor M13 as an N-type MOS transistor as an example to explain the technical solution.

[0122] Specifically, when it is necessary to control the first shift register unit G01 in the driving circuit 10 not to output the valid pulse of the gate driving signal Gout01 and only output the valid pulse of the stage transfer signal Vnext01, the driving control signal Vct can be controlled to jump from the enable level to the non-enable level before the first shift register unit G01 outputs the valid pulse of the stage transfer signal Vnext01. Assuming that the moment when the input signal Vin outputs the valid pulse is the third moment t3, the first clock signal CK1 can jump from the enable level to the non-enable level at the second moment t2 before the third moment. The stage before the input signal Vin outputs the valid pulse is the holding stage of the previous display frame, at which the first initial node N1 is maintained at the enable level, so that the first driving control transistor M31 remains in the on state. The first moment t1 at which the control drive control signal Vct jumps from the enable level to the non-enable level is before the second moment t2. The first clock signal CK1 can be maintained at the enable level before the second moment t2, so that the enable level of the drive control signal Vct is written to the gate of the second drive rod control transistor M32, so that the second drive rod control transistor M32 is turned on, so that the current non-enable level of the second initial node N2 is written to the first drive node N3. In this way, the non-enable level can be written to the first drive node N3 before the input signal Vin outputs a valid pulse, which can ensure that the second drive output transistor M52 is disconnected before the input signal Vin outputs a valid pulse, and the second level signal Vgh will not be transmitted to the drive output node, so that the accuracy of the first drive node N3 can be guaranteed, thereby ensuring the accuracy of the output gate drive signal Gout01.

[0123] Optional, continue to refer to Fig.18 The initial control module 110 further includes a storage unit 113; a first end of the storage unit 113 receives a fixed signal, and a second end of the storage unit 113 is electrically connected to the second initial node N2. The storage unit 113 is used to store the signal of the second initial node N2, so that the signal of the second initial node N2 can remain stable.

[0124] Optional, continue to refer to Fig.19 The storage unit 113 includes a third storage capacitor C3; the first plate of the third storage capacitor C3 receives a fixed signal, and the second plate of the third storage capacitor C3 is electrically connected to the second initial node N2. The fixed signal electrically connected to the third storage capacitor C3 can be a first level signal Vgl or a second level signal Vgh, Fig.12 It is exemplarily shown that the fixed signal received by the second plate of the second storage capacitor C2 is the second level signal Vgh. In other feasible embodiments of the present invention, the second plate of the third storage capacitor C3 can also receive the first level signal Vgl, and can store the signal of the second initial node N2, so that the signal of the second initial node N2 remains stable.

[0125] Optional, Fig. 20 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig. 20 As shown, the first initial control unit 111 also includes a charge pump subunit 111b; the first initial node N1 includes a first initial sub-node N1a and a second initial sub-node N1b; the input subunit 111a is also used to receive an input signal Vin and a first clock signal CK1, and control the signal of the first initial sub-node N1a; the charge pump subunit 111b is used to at least receive the signal of the first initial sub-node N1a and the second clock signal CK2, and control the signal of the second initial sub-node N1b; the stage transmission output module 120 is also used to control the stage transmission signal Vnext according to the signal of the second initial node N2 and the signal of the second initial sub-node N1b.

[0126] Specifically, the input subunit 111a controls the transmission path of the input signal Vin to the first initial subnode N1a under the control of the first clock signal CK1. The charge pump subunit 111b can control the coupling amount to the second initial subnode N1b according to the signal of the first initial subnode N1a and the second clock signal CK2, which can improve the charging speed of the level transmission output module 120. For example, when the first initial subnode N1a jumps from the non-enable level to the enable level, the level transmission output module 120 can control the level transmission signal Vnext to quickly jump to the enable level.

[0127] Optional, Fig.21 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.21 As shown, the charge pump subunit 111b includes a first auxiliary transistor M14, a second auxiliary transistor M15 and a first bootstrap capacitor C0; the gate and the first electrode of the first auxiliary transistor M14 are both electrically connected to the first initial subnode N1a, and the second electrode of the first auxiliary transistor M14 is electrically connected to the second initial subnode N1b; the gate of the second auxiliary transistor M15 is electrically connected to the first initial subnode N1a, the first electrode of the second auxiliary transistor M15 receives the second clock signal CK2, the second electrode of the second auxiliary transistor M15 is electrically connected to the first plate of the first bootstrap capacitor C0, and the second plate of the first bootstrap capacitor C0 is electrically connected to the first initial subnode N1a.

[0128] Exemplarily, taking the case where both the first auxiliary transistor M14 and the second auxiliary transistor M15 are P-type MOS transistors, when the input signal Vin is at a low level, if the first clock signal CK1 is at a low level, the first input transistor M11 is turned on, so that the first initial subnode N1a is at a low level, thereby making the first auxiliary transistor M14 and the second auxiliary transistor M15 both turned on, and the second initial subnode N1b is also at a low level, and the polarity of the first clock signal CK1 is opposite to that of the second clock signal CK2, then at this time the second clock signal CK2 is at a high level; at this time, if the first clock signal CK1 jumps from a low level to a high level, is high, the second clock signal CK2 jumps from a high level to a low level, the first input transistor M11 is disconnected, and the first initial sub-node N1a is maintained at a low level, so that the first auxiliary transistor M14 and the second auxiliary transistor M15 are continuously turned on, and under the coupling effect of the first bootstrap capacitor C0, the low level of the second clock signal CK2 makes the potential of the second initial sub-node N1b further pulled down, which can make the first-level transmission output transistor M21 in the level transmission output module 120 fully turned on, so that the level transmission signal Vnext output by the level transmission output module 120 quickly jumps to the first level signal Vgl.

[0129] For example, Fig. 22 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig. 22 As shown, the drive control module 130 and the drive output module 140 can be electrically connected to the second initial subnode N1b. That is, the gate of the first drive control transistor M31 is electrically connected to the second initial subnode N1b, the gate of the third drive control transistor M33 is electrically connected to the second initial subnode N1b, and the gate of the first drive output transistor M51 is electrically connected to the second initial subnode N1b. In this way, when the first initial subnode N1a is kept at a low level and the second clock signal CK2 is at a low level, the first drive control transistor M31, the third drive control transistor M33 and the first drive output transistor M51 can be fully turned on, so that when the first drive control transistor M31 is fully turned on, the gate potential of the second drive control transistor M32 can jump quickly, and when the third drive control transistor M33 is fully turned on, the signal of the first drive node N3 can jump quickly, and when the first drive output transistor M51 is fully turned on, the gate drive signal Gout can jump quickly.

[0130] Optional, reference Fig.21 or Fig. 22 The charge pump subunit 111b further includes a third auxiliary transistor M16; a gate of the third auxiliary transistor M16 is electrically connected to the second initial node N2, a first electrode of the third auxiliary transistor M16 receives the second level signal Vgh, and a second electrode of the third auxiliary transistor M16 is electrically connected to the first plate of the first bootstrap capacitor C0.

[0131] Exemplarily, taking the case where the first auxiliary transistor M14, the second auxiliary transistor M15 and the third auxiliary transistor M16 are all P-type MOS transistors, when the input signal Vin is at a high level, if the first clock signal CK1 is at a low level, the first input transistor M11 is turned on, so that the first initial subnode N1a is at a high level, so that the first auxiliary transistor M14 and the second auxiliary transistor M15 are turned off, and the second initial control transistor M13 is turned on, and the first level signal Vgl is written into the second initial node N2, so that the third auxiliary transistor M16 is turned on, so that the second level signal Vgh is written into the first bootstrap capacitor C0 through the third auxiliary transistor M16. At this time, under the coupling effect of the first bootstrap capacitor C0, the potential of the first initial subnode N1a will be pulled up, so that the first auxiliary transistor M14 is completely turned off, so that the leakage current of the second initial subnode N1b can be reduced, and the signal of the second initial subnode N1b can be kept stable.

[0132] Optional, Fig.23 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.23 As shown, the first initial control unit 111 further includes a voltage stabilizing subunit 111 c ; the input subunit 111 a is electrically connected to the first initial node N1 through the voltage stabilizing subunit 111 c .

[0133] For example, Fig.24 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.24 As shown, the voltage stabilizing subunit 111c includes a first voltage stabilizing transistor M17, which can be a P-type MOS tube. At this time, the gate of the first voltage stabilizing transistor M17 receives the first level signal Vgl, and its first electrode is electrically connected to the second electrode of the first input transistor M11 in the output subunit 111a, and the second electrode is electrically connected to the first initial node N1. In this way, the first voltage stabilizing transistor M17 is always turned on under the control of the first level signal Vgl, so that the first electrode potential of the first voltage stabilizing transistor M17 is basically consistent with the second electrode potential. However, since the turned-on first voltage stabilizing transistor M17 has a certain resistance, when the signal of the first initial node N1 changes, the first voltage stabilizing transistor M17 can reduce the amount of change of the signal of the first initial node N1 with the change of the first electrode signal of the first voltage stabilizing transistor M17. In this way, by arranging the first voltage stabilizing transistor M17 between the second electrode of the first input transistor M11 and the first initial node N1, the stability of the signal of the first initial node N1 can be guaranteed, thereby improving the stability of the output signal Vnext of the first-stage transmission output transistor M21.

[0134] For example, Fig.25is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.25 As shown, the input subunit further includes a second input transistor M18, the gate of the second input transistor M18 receives the first clock signal CK1, the first electrode of the second input transistor M18 receives the input signal Vin, and the second electrode of the second input transistor M18 is electrically connected to the third initial node N5. In this way, the second input transistor M18 can be turned on or off under the control of the first clock signal CK1, and write the input signal Vin to the third initial node N5 when turned on. The channel type of the second input transistor M18 and the first input transistor M1 can be the same, for example, they can both be P-type MOS transistors, so that the potential of the third initial node N5 is the same as the potential of the first initial node N1. At this time, the gate of the first initial control transistor M12 in the first initial control subunit 112a can be electrically connected to the third initial node N5; in another feasible embodiment, the gate of the second initial control transistor M13 in the second initial control subunit 112b can also be electrically connected to the third initial node N5.

[0135] Exemplary, reference Fig.25 , the voltage stabilizing subunit 25 may further include a second voltage stabilizing transistor M19, which may be a P-type MOS tube, whose gate may receive the first level signal Vgl, whose first electrode is electrically connected to the third initial node N5, and whose second electrode is electrically connected to the gate of the second initial control transistor M13 in the second initial control subunit 112b, so that the gate potential of the second initial control transistor M13 can be kept stable. In another feasible embodiment, the second electrode of the second voltage stabilizing transistor M19 may also be electrically connected to the gate of the first initial control transistor M12 in the first initial control subunit 112a, so that the gate potential of the first initial control transistor M12 can be kept stable.

[0136] The above embodiments exemplarily describe the driving circuit and the shift register unit therein, but the driving circuit and the shift register unit therein are not limited to the above embodiments. The following will exemplarily describe the connection relationship between the pixel circuit and the shift register unit and the pixel circuit.

[0137] In an exemplary embodiment, the working principle of the shift register unit G is explained by taking the example that the active auxiliary transistor M41 and the second initial control transistor M13 in the shift register unit G are N-type POS transistors and the other transistors are P-type MOS transistors. Fig.26 is another driving timing diagram of a shift register circuit provided by an embodiment of the present invention, and is combined with reference to Fig.24 and Fig.26Before the stage t11, since the input signal Vin is at a low level, when the first clock signal CK1 controls the first input transistor M11 to turn on, the first input transistor M11 transmits the low-level input signal Vin to the first initial subnode N1a, so that the signal of the first initial subnode N1a is at a low level; the signal of the first initial subnode N1a controls the first initial control transistor M12 to turn on, and writes the second-level signal Vgh to the second initial node N2, so that the signal V_N2 of the second initial node N2 is at a high level; the signal of the first initial subnode N1a controls the first auxiliary transistor M14 to turn on, so that the second initial subnode N1a is at a high level. 1b is the same as the first initial sub-node N1a at a low level, that is, the signal V_N1 of the first initial node N1 is a low level; then the signal V_N1 of the first initial node N1 controls the first-stage transfer output transistor M21, the first drive control transistor M31, the third drive control transistor M33 and the first drive output transistor M51 to remain in the on state, and the signal of the second initial node N2 controls the second-stage transfer output transistor M22 to be disconnected, so that the first-stage transfer output transistor M21 outputs the first level signal Vgl as the stage transfer signal Vnext, and the first drive output transistor M51 outputs the first level signal Vgl as the gate drive signal Gout. The enable level of the drive control signal Vct is written to the gate of the second drive control transistor M32 through the first drive control transistor M31 to control the second drive control transistor M32 to turn on, and the high level signal of the second initial node N2 is transmitted to the first drive node N3. At the same time, the low level of the first initial node N1 controls the third drive control transistor M33, so that the second level signal Vgh received by the first electrode of the third drive control transistor M33 can also be transmitted to the first drive node N3, then the second drive output transistor M52 is disconnected and the active auxiliary transistor M41 is turned on, so that the second drive output transistor M52 cannot transmit the second level signal Vgh to the drive output node N4, and the first level signal Vgl of the first electrode of the active auxiliary transistor M41 is transmitted to the drive output node N4, so that the gate drive signal Gout remains as the low level first level signal Vgl.

[0138] In the t11 stage, the drive control signal Vct remains at a low level, the input signal Vin becomes a high level, and at the same time, the first clock signal CK1 is at a high level, and the second clock signal CK2 is at a low level. At this time, the first clock signal CK1 controls the first input transistor M11 to be disconnected, and the first initial node N1 remains at the low level of the previous stage, and the low level of the second clock signal CK2 is coupled to the first initial node N1 through the first bootstrap capacitor C0, so that the potential of the first initial node N1 is stabilized at a low level; thus, the signal of the second initial node N2 is the same as that in the previous stage and remains at a high level, so that the stage transfer signal Vnext remains at a low level first level signal Vgl, and the gate drive signal Gout remains at a low level first level signal Vgl.

[0139] In the t12 stage, the drive control signal Vct remains at a low level, the input signal Vin remains at a high level, and the first clock signal CK1 is at a low level, and the second clock signal CK2 is at a high level. At this time, the first clock signal CK1 controls the first input transistor M11 to turn on, and the high-level input signal Vin will be transmitted to the first initial node N1 through the first input transistor M11, so that the signal V_N1 of the first initial node N1 becomes a high level. The high-level signal can control the first-stage transmission transistor M21, the first drive control transistor M31, the third drive control transistor M33 and the first drive output transistor M51 to be disconnected, and at the same time, the second initial control transistor M13 is turned on; then the first-level signal Vgl is written to the second initial node through the second initial control transistor M13, so that the signal V_N2 of the second initial node N2 is a low level, and the low-level signal can simultaneously control the second-stage transmission transistor M22 to turn on, so that the high-level first-level signal Vgh is transmitted to the second electrode of the second-stage transmission transistor M22, so that the initial output signal Vnext remains at a high level. At the same time, the first drive control transistor M31 is turned off so that the gate of the second drive control transistor M32 remains as the signal of the previous stage, that is, it remains at a low level, so that the low level signal of the second initial node N2 is transmitted to the first drive node through the second drive control transistor M32, and the low level signal can control the second drive output transistor M52 to be turned on and control the active auxiliary transistor M41 to be turned off, so that the gate drive signal Gout outputs the second level signal Vgh as the gate drive signal Gout, that is, the level transfer signal Vnext and the gate drive signal Gout both output a high level. In addition, the low level signal of the second initial node N2 controls the third auxiliary transistor M16 to be turned on, so that the second level signal Vgh is coupled to the first initial node N1 through the bootstrap capacitor C0, and the potential of the first initial node N1 is further raised, so that the first stage transmission transistor M21, the first drive control transistor M31, the third drive control transistor M33 and the first drive output transistor M51 are completely disconnected.

[0140] In the t13 stage, the input signal Vin jumps to a low level, the first clock signal CK1 is a high level, and the second clock signal CK2 is a low level. At this time, the first clock signal CK1 controls the first input transistor M11 to be disconnected, and the signal of the first initial node N1 remains at the high level of the previous stage; thus, the signal of the second initial node N2 is the same as the previous stage and remains at a low level, so that the stage transfer signal Vnext remains at a high level second level signal Vgh, and the gate drive signal Gout remains at a high level second level signal Vgh.

[0141] In the t14 stage, the input signal Vin and the drive control signal Vct remain at a low level, while the first clock signal CK1 is at a low level and the second clock signal CK2 is at a high level, then the first input transistor M11 is turned on, and the low-level input signal Vin is transmitted to the first initial node N1; the signal V_N1 of the first initial node N1 controls the first initial control transistor M12 to turn on, and writes the second-level signal Vgh to the second initial node N2, so that the signal V_N2 of the second initial node N2 is a high level; then the signal V_N1 of the first initial node N1 controls the first-stage transmission output transistor M21, the first drive control transistor M31, the third drive control transistor M33 and the first drive output transistor M51 to remain in the on state, and the signal of the second initial node N2 controls the second-stage transmission output transistor M22 to be turned off, so that the first-stage transmission output transistor M21 outputs the first-level signal Vgl as the stage transfer signal Vnext, and the first drive output transistor M51 outputs the first-level signal Vgl as the gate drive signal Gout. The enable level of the drive control signal Vct is written to the gate of the second drive control transistor M32 through the first drive control transistor M31 to control the second drive control transistor M32 to turn on, and the high level signal of the second initial node N2 is transmitted to the first drive node N3. At the same time, the second level signal Vgh of the first electrode of the third drive control transistor M33 is also transmitted to the first drive node N3, then the second drive output transistor M52 is disconnected and the active auxiliary transistor M41 is turned on, and the second level signal Vgh cannot be transmitted to the drive output node N4, and the first level signal Vgl of the first electrode of the active auxiliary transistor M41 is transmitted to the drive output node N4, so that the gate drive signal Gout remains as the low level first level signal Vgl.

[0142] In the t15 stage, since the input signal Vin remains at the low level of the t14 stage, the jump of the first clock signal CK1 does not affect the potentials of the first initial node N1, the second initial node N2 and the first driving node N3, so that the stage transfer signal Vnext and the gate driving signal Gout remain as the low-level first level signal Vgl.

[0143] In the t16 stage, the drive control signal Vct is at a high level, the input signal Vin becomes a high level, and the first clock signal CK1 is at a high level, and the second clock signal CK2 is at a low level. At this time, the first clock signal CK1 controls the first input transistor M11 to be disconnected, and the first initial node N1 remains at a low level in the previous stage, and the low level of the second clock signal CK2 is coupled to the first initial node N1 through the first bootstrap capacitor C0, so that the potential of the first initial node N1 is stabilized at a low level; thus, the signal of the second initial node N2 is the same as the previous stage, and remains at a high level, so that the level transfer signal Vnext remains at a low level of the first level signal Vgl, and the gate drive signal Gout remains at a low level of the first level signal Vgl. At the same time, the low level of the first initial node N1 controls the first drive control transistor M31, the third drive control transistor M33 and the first drive output transistor M51 to be turned on, and the first level signal Vgl is transmitted to the drive output node N4 through the first drive output transistor M51, so that the gate drive signal Gout remains at a low level of the first level signal Vgl. In addition, the high level of the drive control signal Vct is transmitted to the gate of the second drive control transistor M32 through the first drive control transistor M31, so that the second drive control transistor M32 is disconnected, and the third drive transistor M33 is turned on under the control of the low level signal of the first initial node N1, so that the second level signal Vgh is transmitted to the first drive node N3, then the second drive output transistor M52 is disconnected and the active auxiliary transistor M41 is turned on, so that the second level signal Vgh of the first electrode of the second drive output transistor M52 cannot be transmitted to the drive output node N4, and the first level signal Vg of the first electrode of the active auxiliary transistor M41 is transmitted to the drive output node N4, so that the gate drive signal Gout remains as the low level first level signal Vgl.

[0144] In the t17 stage, the drive control signal Vct remains at a high level, the input signal Vin remains at a high level, and the first clock signal CK1 is at a low level, and the second clock signal CK2 is at a high level. At this time, the first clock signal CK1 controls the first input transistor M11 to turn on, and the high-level input signal Vin will be transmitted to the first initial node N1 through the first input transistor M11, so that the signal V_N1 of the first initial node N1 becomes a high level, and the high-level signal can control the first-stage transmission transistor M21, the first drive control transistor M31, the third drive control transistor M33 and the first drive output transistor M51 to be disconnected, and at the same time make the second initial control transistor M13 turned on; then the first-level signal Vgl is written to the second initial node through the second initial control transistor M13, so that the signal V_N2 of the second initial node N2 is low level, and the low-level signal can simultaneously control the second-stage transmission transistor M22 to turn on, so that the high-level first-level signal Vgh is transmitted to the second electrode of the second-stage transmission transistor M22, so that the initial output signal Vnext is a high level. At the same time, before the first drive control transistor M31 is disconnected, the high level of the drive control signal Vct is written to the gate of the second drive control transistor M32, so that the gate of the second drive control transistor M32 is disconnected, so that the low level signal of the second initial node N2 cannot be transmitted to the first drive node N3 through the second drive control transistor M32, and the third drive control transistor M33 is turned on under the control of the low level signal of the first initial node N1, so that the second level signal Vgh of the first electrode of the third drive control transistor M33 is transmitted to the first drive node N3, and the second output transistor M52 is controlled to be disconnected, so that the second level signal Vgh of the first electrode of the second output transistor M52 cannot be transmitted to the drive output node N4. In addition, the high level signal of the first drive node N3 controls the active auxiliary transistor M41 to be turned on, so that the first level signal Vgl of the first electrode of the active auxiliary transistor M41 is transmitted to the drive output node, so that the gate drive signal Gout is the low level first level signal Vgl, that is, the stage transfer signal Vnext outputs a high level and the gate drive signal Gout outputs a low level. In addition, the low-level signal of the second initial node N2 controls the third auxiliary transistor M16 to turn on, so that the second-level signal Vgh is coupled to the first initial node N1 through the bootstrap capacitor C0, further pulling up the potential of the first initial node N1, so that the first-stage transmission transistor M21, the first drive control transistor M31, the third drive control transistor M33 and the first drive output transistor M51 are completely disconnected.

[0145] In the t18 stage, the drive control signal Vct remains at a high level, the input signal Vin jumps to a low level, the first clock signal CK1 is at a high level, and the second clock signal CK2 is at a low level. At this time, the first clock signal CK1 controls the first input transistor M11 to be disconnected, and the signal of the first initial node N1 remains at the high level of the previous stage; thus, the signal of the second initial node N2 is the same as the previous stage and remains at a low level, so that the stage transfer signal Vnext remains at a high level second level signal Vgh, and the gate drive signal Gout remains at a low level second level signal Vgl.

[0146] In the t19 stage, the input signal Vin remains at a low level, the drive control signal Vct remains at a high level, and at the same time, the first clock signal CK1 is at a low level and the second clock signal CK2 is at a high level, then the first input transistor M11 is turned on, and the low-level input signal Vin is transmitted to the first initial node N1; the signal V_N1 of the first initial node N1 controls the first initial control transistor M12 to turn on, and writes the second-level signal Vgh to the second initial node N2, so that the signal V_N2 of the second initial node N2 is a high level; then the signal V_N1 of the first initial node N1 controls the first-stage transmission output transistor M21, the first drive control transistor M31, the third drive control transistor M33 and the first drive output transistor M51 to remain in the on state, and the signal of the second initial node N2 controls the second-stage transmission output transistor M22 to be turned off, so that the first-stage transmission output transistor M21 outputs the first-level signal Vgl as the stage transfer signal Vnext, and the first drive output transistor M51 outputs the first-level signal Vgl as the gate drive signal Gout. At the same time, the second level signal Vgh of the first electrode of the third driving control transistor M33 is transmitted to the first driving node N3, the second driving output transistor M52 is disconnected and the active auxiliary transistor M41 is turned on, so that the second driving output transistor M52 cannot transmit the second level signal Vgh to the driving output node N4, and the active auxiliary transistor M41 also transmits the first level signal Vgl of the first electrode to the driving output node N4, so that the gate driving signal Gout remains as the low level first level signal Vgl.

[0147] After stage t19, the input signal Vin remains at a low level, the drive control signal Vct remains at a high level, and the jump of the first clock signal CK1 does not affect the potentials of the first initial node N1, the second initial node N2 and the first drive node N3, so that the stage transfer signal Vnext and the gate drive signal Gout remain at a low level.

[0148] Optional, continue to combine references Fig.24 and Fig.26, during part of the time in the first mode Mode, the driving control signal Vct received by the first shift register unit G01 is the enable level; the transition moment between the enable level and the disable level of the driving control signal Vct is the first moment t1; in the stage where the input signal Vin received by the first shift register unit G01 is a valid pulse, the transition moment between the disable level and the enable level of the first clock signal CK1 is the second moment t2; the first moment t1 is before the second moment t2.

[0149] Specifically, the stage in which the input signal Vin received by the first shift register unit G01 is a valid pulse is the stage t16-t17. In the stage t16-t17, the first clock signal CK1 changes from the non-enable level to the enable level at the second moment t2, so that the signal V_N1 of the first initial node N1 changes from the enable level to the non-enable level at the second moment t2, and the signal V_N2 of the second initial node N2 changes from the non-enable level to the enable level at the second moment t2. Then, at the first moment t1 before the second moment t2, the drive control signal Vct changes from the enable level to the non-enable level, so that the second drive control transistor M32 is disconnected before the second moment t2, and then at the second moment t2, the signal V_N2 of the second initial node N2 changes from the non-enable level to the enable level, and the enable level will not be written to the first drive node N3, so that the gate drive signal Gout can always output the first level signal Vgl, and the accuracy of the gate drive signal Gout can be guaranteed.

[0150] It can be understood that the gate drive signal Gout output by the drive output module 150 of each level of the shift register unit G can be respectively provided to each row of the pixel circuit 20, and the pixel circuit 20 can include a preset module, so that the gate drive signal Gout output by the shift register unit G can control the preset module in the pixel circuit 20 to turn on or off, that is, when the gate drive signal Gout output by the shift register unit G is at an enable level, the preset module of the pixel circuit 20 can be controlled to turn on, and when the gate drive signal Gout output by the shift register unit G is at a non-enable level, the preset module of the pixel circuit 20 can be controlled to turn off, so as to refresh the signal in the pixel circuit 20. Among them, the pixel circuit 20 can also include other modules, and the embodiment of the present invention does not specifically limit the specific structure of the pixel circuit 20.

[0151] Optional, reference Figure 3 The display panel 100 further includes a plurality of pixel circuits 20 arranged in an array and a plurality of scan signal lines SCAN; at least part of the pixel circuits 20 in the same row are electrically connected to the same scan signal line SCAN; and a driving output node N4 of the shift register unit G is electrically connected to at least one scan signal line SCAN.

[0152] Specifically, at least part of the pixel circuits 20 in the same row are electrically connected to the same scan signal line SCAN, so that the gate drive signal Gout transmitted by the scan signal line SCAN can refresh the pixel circuits 20 in a row, thereby realizing the row-by-row scanning of the pixel circuits 20 in each row. The figure exemplarily shows the electrical connection between the drive output node N4 of the shift register unit G and a scan signal line SCAN, at which time each shift register unit G only refreshes the signal of a row of pixel circuits 20. In another feasible embodiment, the shift register unit G can also be set to be electrically connected to two or more scan signal lines SCAN, so that the number of shift register units G can be reduced, which is conducive to realizing a narrow frame of the display panel 100.

[0153] For example, Fig. 27 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention, Fig.28 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Fig. 27 As shown in or 28, the pixel circuit 20 includes a driving transistor T1, a data writing module 210, an initialization module 220, a first light-emitting control module 230, a second light-emitting control module 240 and a light-emitting element D0; the initialization module 220 and the data writing module 210 are electrically connected to the driving transistor T1 respectively; the initialization module 220 is used to at least receive a gate driving signal Gout to initialize the gate of the driving transistor T1; the data writing module 210 is used to write a data signal Vdata to the gate of the driving transistor T1; the first light-emitting control module 230 and the second light-emitting control module 240 are used to control the driving transistor T1 to provide a driving current to the light-emitting element D0.

[0154] The driving transistor T1 can selectively provide a driving current to the light emitting element D0 to drive the light emitting element D0 to emit light; the data writing module 210 is connected to the first end of the driving transistor T1, and is used to provide the data signal Vdata to the driving transistor T1, so that the driving transistor T1 can generate a driving current to drive the light emitting element D0 to emit light according to the data signal Vdata; the initialization module 220 is connected to the control end of the driving transistor T1, and is used to provide a reset signal to the driving transistor T1 to reset the driving transistor T1; the first light emitting control module 230 and the second light emitting control module 240 can control the current path between the positive power supply signal PVDD and the negative power supply signal PVEE, so as to control the time when the driving transistor T1 provides the driving current to the light emitting element D0. The first light emitting control module 230 and the second light emitting control module 240 can be turned on or off under the control of the light emitting control signal EM. When the light emitting control signal EM controls the first light emitting control module 230 and the second light emitting control module 240 to be turned on, the driving transistor T1 can generate a driving current and provide the driving current to the light emitting element D0 to drive the light emitting element D0 to emit light.

[0155] Since the light emitting element D0 is usually a current-type driving element, and the data signal Vdata provided by the data writing module 210 is usually a voltage signal, the driving transistor T1 is set in the driving transistor T1, so that the data signal Vdata provided by the data writing module 210 can be written to the gate of the driving transistor T1, so that the driving transistor T1 can generate a corresponding driving current according to the signal of its gate, and provide it to the light emitting element D0, driving the light emitting element D0 to emit light with a corresponding brightness. At this time, one of the source and the drain of the driving transistor T1 receives the positive power signal PVDD, and the other is coupled to the anode of the light emitting element D0, and the cathode of the light emitting element D0 can receive the negative power signal PVEE, so that there is a voltage difference between the positive power signal PVDD and the negative power signal PVEE, and a current path is formed, so that the driving transistor T1 can generate a driving current and provide it to the light emitting element D0, driving the light emitting element D0 to emit light.

[0156] It is understandable that if Fig. 27 As shown, the active layer material of the driving transistor T1 in the driving transistor T1 may include a low-temperature polysilicon material, so that it has a higher carrier mobility, thereby meeting the requirements of high reaction speed and low power consumption. In this case, the driving transistor T1 may be a PMOS transistor. In other optional embodiments, such as Fig.28As shown, the active layer material of the driving transistor T1 may also include an oxide semiconductor material. In this case, the driving transistor T1 may be an NMOS transistor. Under the premise of being able to achieve the core invention of the embodiment of the present invention, the embodiment of the present invention does not specifically limit the material and type of the driving transistor T1.

[0157] Among them, the control end of the data writing module 210 can receive the first scanning signal S1, and the first scanning signal S1 controls the opening and closing of the data writing module 210; the control end of the initialization module 220 receives the third scanning signal S3, and the third scanning signal S3 controls the opening and closing of the initialization module 220. When the third scanning signal S3 controls the initialization module 220 to turn on, the initialization signal Vref can be transmitted to the gate of the driving transistor T1 to initialize the gate of the driving transistor T1 to clear the data signal Vdata provided to the gate of the driving transistor T1 in the previous driving cycle, and to make accurate writing of the subsequent data signal Vdata. When the first scanning signal S1 controls the data writing module 210 to turn on, the data signal Vdata can be written to the first electrode of the driving transistor T1 through the data writing module 210 to refresh the signal of the first electrode of the driving transistor T1; if the driving transistor T1 is in the on state at this time.

[0158] In an exemplary embodiment, the data writing module 210 may include a data writing transistor T2, a first electrode of the data writing transistor T2 receives a data signal Vdata, a second electrode of the data writing transistor T2 is electrically connected to a first electrode of the driving transistor T1, and a gate of the data writing transistor T2 receives a first scanning signal S1, so that the first scanning signal S1 controls the turning on or off of the data writing transistor T2; the initialization module 220 includes an initialization transistor T3, a first electrode of the initialization transistor T3 receives an initialization signal Vref, a second electrode of the initialization transistor T3 is electrically connected to a gate of the driving transistor T1, and a gate of the initialization transistor T3 receives a third scanning signal S3, so that the third scanning signal S3 controls the turning on or off of the initialization transistor T3. The first light-emitting control module 230 may include a first light-emitting control transistor T4, and the second light-emitting control module 240 may include a second light-emitting control transistor T5. The first electrode of the first light-emitting control transistor T4 receives a positive power supply signal PVDD, the second electrode of the first light-emitting control transistor T4 is electrically connected to the first electrode of the driving transistor T1, the first electrode of the second light-emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T1, and the second electrode of the second light-emitting control transistor T5 is electrically connected to the anode of the light-emitting element D0. The gate of the first light-emitting control transistor T4 and the gate of the second light-emitting control transistor T5 both receive a light-emitting control signal EM, so that the light-emitting control signal EM can control the first light-emitting control transistor T4 and the second light-emitting control transistor T5 to be turned on or off at the same time.

[0159] Based on the above embodiment, the pixel circuit 20 may further include a threshold compensation module 250 and a reset module 260. The threshold compensation module 250 is used to receive a gate drive signal Gout and compensate the threshold compensation voltage to the gate of the driving transistor T1. The reset module 260 provides a reset signal for the light-emitting element.

[0160] The threshold compensation module 250 is connected between the control terminal and the second terminal of the driving transistor T1, so that when the data writing module 210 provides the data signal Vdata to the driving transistor T1, the data signal Vdata can be compensated to ensure that the driving transistor T1 can provide an accurate driving current to the light-emitting element D0 and control the light-emitting accuracy of the light-emitting element D0. The reset module 260 is connected to the anode of the light-emitting element D0, and is used to provide the initialization signal Vini to the light-emitting element D0 to initialize the anode of the light-emitting element D0. The reset module 260 can be turned on or off under the control of the fourth scan signal S4, and when the fourth scan signal S4 controls the reset module 260 to turn on, the initialization signal Vini can be provided to the anode of the light-emitting element D0.

[0161] In an exemplary embodiment, the threshold compensation module 250 includes a compensation transistor T6, a first electrode of the compensation transistor T6 is electrically connected to the second electrode of the driving transistor T1, a second electrode of the compensation transistor T6 is electrically connected to the gate of the driving transistor T1, and the compensation transistor T6 receives a second scanning signal S2, so that the second scanning signal S2 controls the turning on or off of the compensation transistor T6; the reset module 260 may include a reset transistor T7, a first electrode of the reset transistor T7 receives a reset signal Vini, a second electrode of the reset transistor T7 is electrically connected to the anode of the light-emitting element D0, and a gate of the reset transistor T7 receives a fourth scanning signal S4, so that the fourth scanning signal S4 can control the reset transistor T7 to turn on or off.

[0162] Based on the above embodiment, the pixel circuit 20 may further include a storage capacitor Cst, a first plate of which receives a fixed signal (eg, a positive power signal PVDD), and a second plate is electrically connected to the gate of the driving transistor T1 to store the signal at the gate of the driving transistor T1.

[0163] In another embodiment of the present invention, Fig.29 and Fig.30 is a schematic diagram of a structure of another pixel circuit provided by an embodiment of the present invention, with reference to 29 and Fig.30Referring to any of the accompanying drawings, on the basis of the above embodiments, the pixel circuit 20 may further include a bias adjustment module 270, which is connected to the first end or the second end of the driving transistor T1, and is used to provide a bias adjustment signal V0 for the driving transistor T1, so as to bias the driving transistor T1 in the driving transistor T1.

[0164] The first electrode of the driving transistor T1 may be the first end of the driving transistor T1, and the second electrode of the driving transistor T1 may be the second end of the driving transistor T1. In this case, the bias adjustment module 270 may be electrically connected to the first electrode or the second electrode of the driving transistor T1. As long as the bias adjustment of the driving transistor T1 can be achieved, the embodiment of the present invention does not specifically limit this.

[0165] In an optional embodiment, the bias adjustment module 270 can be turned on or off under the control of the bias adjustment control signal SV, and when the bias adjustment control signal SV controls the bias adjustment module 270 to be turned on, the bias adjustment signal V0 can be provided to the first electrode and / or the second electrode of the driving transistor T1 to perform bias adjustment on the driving transistor T1.

[0166] In an exemplary embodiment, the bias adjustment module 270 may include a bias adjustment transistor T8, a first electrode of the bias adjustment transistor T8 receives a bias adjustment signal V0, a ​​second electrode of the bias adjustment transistor T8 is electrically connected to a first electrode or a second electrode of the driving transistor T1, and a gate of the bias adjustment transistor T8 receives a bias adjustment control signal SV, so that the bias adjustment control signal SV can control the bias adjustment transistor T8 to turn on or off.

[0167] It should be noted that Figure 27 to Figure 30 The structures of several pixel circuits are provided for illustrative purposes only, but not all of them are included. Under the premise that the core inventive point of the embodiments of the present invention can be realized, the embodiments of the present invention do not limit the specific structure of the pixel circuit.

[0168] Based on the above-mentioned pixel circuits, the preset module of the pixel circuit 20 in the embodiment of the present invention may include any one of the data writing module 210, the threshold compensation module 230, the initialization module 220, the reset module 260, the first light-emitting control module 230, the second light-emitting control module 240, and the bias adjustment module 270, so that the gate driving signal output by the shift register unit can control any one of the data writing module 210, the threshold compensation module 230, the initialization module 220, the reset module 260, the first light-emitting control module 230, the second light-emitting control module 240, and the bias adjustment module 270 to turn on or off, that is, the gate driving signal output by the shift register unit may include any one of the first scanning signal S1, the second scanning signal S2, the third scanning signal S3, the fourth scanning signal S4, the light-emitting control signal EM, and the bias adjustment control signal SV. For ease of description, this embodiment takes the gate driving signal output by the shift register unit as the third scanning signal S3 that controls the initialization module 220 to turn on or off as an example, and the driving principle of the pixel circuit 20 is introduced below.

[0169] Combined with reference Figure 3 as well as Figure 27 to Figure 30In any of the accompanying drawings, the shift register units G of different levels will provide gate drive signals Gout to the pixel circuits 20 of different rows to control the initialization modules 220 in the pixel circuits 20 of each row to turn on or off. Taking the x-th shift register unit Gx and the y-th shift register unit Gy as examples, when the initialization module 220 in the pixel circuit 20 of the x-th row provides the initialization signal Vref to the gate of the driving transistor T1, the driving output module of the x-th shift register unit Gx can output the enable level of the gate drive signal Goutx to the pixel circuit 20 of the x-th row electrically connected to the shift register unit Gx under the control of the signal of its first driving node, so that the initialization module 220 of the pixel circuit 20 of the x-th row is turned on, and the initialization signal Vref is written to the x-th row. At the same time, the initial output module of the x-th shift register unit Gx can also output the enable level of the initial output signal Vnextx to the y-th shift register unit Gy under the control of the signal of its first initial node N1, as the input signal of the y-th shift register unit Gy, so that the initial control module of the y-th shift register unit Gy controls the signal of its first initial node according to the input signal, so that after the x-th shift register unit Gx outputs the initial output signal Vnextx to the non-enable level, the y-th shift register unit Gy is enabled. The initial output module of the bit register unit Gy can output the enable level of the initial output signal Vnexty to the next-stage shift register unit of the y-th shift register unit Gy according to the signal of its first initial node, so as to serve as the input signal of its next-stage shift register unit, thereby ensuring that the next-stage shift register unit can work normally; at the same time, the drive control module of the y-th stage shift register unit Gy will control the signal of its first drive node according to the signal of its first initial node N1 and the drive control signal Vct, so that the drive output module of the y-th stage shift register unit Gy can be based on The gate drive signal Gouty that responds to the signal output of its first drive node may be the same as or different from its initial output signal Vnexty, and the gate drive signal Gout output by the drive output module of the y-th stage shift register unit Gy can be provided to the y-th row pixel circuit 20 electrically connected to the y-th stage shift register unit Gy, so that the data writing module 210 of the y-th row pixel circuit 20 is turned on or remains turned off to refresh the data signal Vdata in the y-th row pixel circuit 20, or remain unchanged.In this way, each level of shift register unit G provides the enable level of the initial output signal Vnext to its next level shift register unit, and can also provide the enable level of the gate drive signal Gout to the initialization module 220 of the pixel circuit 20, so that the gate drive signal Gout of the initialization module 220 in the pixel circuit 20 is controlled to be different from the initial output signal Vnext provided to the next level shift register unit, so as to ensure that the next level shift register unit works normally, and at the same time, the gate potential of the driving transistor T1 in the pixel circuit 20 can be controlled to be refreshed or remain unchanged according to actual needs, so as to avoid the situation that the input signal Vin required by the next level shift register unit and the gate drive signal required by the pixel circuit 20 electrically connected to the current level shift register unit are different, which affects the normal display of the display panel 100, thereby making the display panel 100 have a diversified structure to meet diversified functional requirements.

[0170] It can be understood that the case where the gate driving signal Gout output by the driving circuit 10 is a control signal of other modules in the pixel circuit 20 is similar to the above case, and the embodiment of the present invention will not elaborate on this one by one.

[0171] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes the display panel provided by the embodiment of the present invention. Therefore, the display device has the technical features of the display panel and the driving method thereof provided by the embodiment of the present invention, and can achieve the beneficial effects of the display panel provided by the embodiment of the present invention. The similarities can be referred to the above description of the display panel provided by the embodiment of the present invention, and will not be repeated here.

[0172] For example, Fig.31 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Fig.31 As shown, the display device 200 includes the display panel 100 provided in the embodiment of the present invention. The display device 200 provided in the embodiment of the present invention can be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., and the embodiment of the present invention does not specifically limit this.

[0173] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: Driving circuit; The driving circuit includes N-stage shift register units cascaded to each other; the shift register unit includes an initial control module, a stage transmission output module, a driving control module, an active auxiliary module and a driving output module; In the same shift register unit, the initial control module is used to at least receive an input signal and a first clock signal, and control signals of a first initial node and a second initial node; The level transmission output module is used to receive at least the signal of the first initial node, the signal of the second initial node, the first level signal and the second level signal, and control the level transmission signal; The driving control module is used to receive at least the signal of the first initial node, the signal of the second initial node and the driving control signal, and control the signal of the first driving node; The driving output module is used to receive at least the signal of the first driving node, the signal of the first initial node, the first level signal and the second level signal, and control the signal of the driving output node; The driving output node is used to output a gate driving signal; The active auxiliary module is used to receive the signal of the first driving node and the first level signal, and control the signal transmission path of the first level signal to the driving output node; Among them, the stage transmission signal of the i-th stage shift register unit is the input signal of the j-th stage shift register unit; i, j and N are all positive integers, i≠j, and i≤N, j≤N.

2. The display panel according to claim 1, characterized in that: The working mode of the display panel includes a first mode, and at least part of the display frames in the first mode are first display frames; The first display frame includes a refresh phase and a hold phase; The driving circuit comprises at least one first shift register unit; In the refresh phase, the driving control signal includes a non-enable level, so that the stage transfer signal output by the first shift register unit includes a second level, and the gate driving signal is a first level.

3. The display panel according to claim 2, characterized in that: In the refresh phase, when the drive control signal is at a non-enable level, the level transfer signal output by the same first shift register unit is at the second level, and when the gate drive signal is at the first level, the signal of the first initial node is at a non-enable level, the signal of the second initial node is at an enable level, and the signal of the first drive node is at a non-enable level.

4. The display panel according to claim 1, characterized in that: When the signal of the first driving node is at a non-enable level, the active auxiliary module controls the signal transmission path of the first level signal to the driving output node to be in a conducting state; When the signal of the first driving node is at an enable level, the active auxiliary module controls a signal transmission path of the first level signal to the driving output node to be in a shut-off state.

5. The display panel according to claim 2, characterized in that: In the holding stage, the driving control signal is at a non-enable level, and the level transmission signal and the gate driving signal output by each level of the shift register unit are both at the first level.

6. The display panel according to claim 2, characterized in that: The driving circuit also includes a second shift register unit; In the refresh phase of the first display frame, the driving control signal includes an enable level, so that the level transfer signal and the gate driving signal output by the second shift register unit both include a second level.

7. The display panel according to claim 6, characterized in that: In the refresh phase, when the drive control signal is at an enable level, when the stage transfer signal and the gate drive signal output by the same second shift register unit are both at the second level, the signal of the first initial node is at a non-enable level, the signal of the second initial node is at an enable level, and the signal of the first drive node is at an enable level.

8. The display panel according to claim 6, characterized in that: The partial display frame of the first mode is a second display frame; In the second display frame, the level transmission signal and the gate driving signal output by the first shift register unit both include the second level, and the level transmission signal and the gate driving signal output by the second shift register unit both include the second level; The first mode includes a plurality of display cycles; the display cycle includes at least one of the first display frames and at least one of the second display frames; The second display frame is located before the first display frame.

9. The display panel according to claim 2, characterized in that: During part of the time in the first mode, the driving control signal received by the first shift register unit is at an enable level; the transition moment between the enable level and the non-enable level of the driving control signal is a first moment; In the stage where the input signal received by the first shift register unit is a valid pulse, the transition moment between the enable level and the disable level of the first clock signal is the second moment; Before the input signal outputs a valid pulse, the first time is before the second time.

10. The display panel according to claim 6, characterized in that: The working mode of the display panel includes a second mode; in the second mode, the frequency of the level transmission signal output by the first shift register unit is equal to the frequency of the gate driving signal; The frequency of the level transmission signal output by the second shift register unit is equal to the frequency of the gate driving signal; And the frequency of the gate driving signal output by the first shift register unit is equal to the frequency of the gate driving signal output by the second shift register unit.

11. The display panel according to claim 10, characterized in that: In the second mode, the driving control signal is maintained at an enable level.

12. The display panel according to claim 1, characterized in that: The active auxiliary module includes an active auxiliary transistor; The gate of the active auxiliary transistor is electrically connected to the first driving node, the first electrode of the active auxiliary transistor receives a first level signal, and the second electrode of the active auxiliary transistor is electrically connected to the driving output node.

13. The display panel according to claim 1, characterized in that: The drive control module includes: a first drive control unit and a second drive control unit; The first driving control unit is used to receive the driving control signal, the signal of the first initial node and the signal of the second initial node, and control the signal of the first driving node; The second driving control unit is used to receive the signal of the first initial node and the second level signal, and control the signal of the first driving node.

14. The display panel according to claim 13, characterized in that: The first drive control unit includes a first drive control transistor, a second drive control transistor and a first storage capacitor; The gate of the first drive control transistor is electrically connected to the first initial node, and the first electrode of the first drive control transistor receives the drive control signal; The gate of the second drive control transistor is electrically connected to the second electrode of the first drive control transistor and the first electrode plate of the first storage capacitor, the first electrode of the second drive control transistor is electrically connected to the second initial node, and the second electrode of the second drive control transistor is electrically connected to the first drive node; The second plate of the first storage capacitor receives a fixed signal.

15. The display panel according to claim 13, characterized in that: The second driving control unit includes a third driving control transistor and a second storage capacitor; The gate of the third drive control transistor is electrically connected to the first initial node, the first electrode of the third drive control transistor receives the second level signal, and the second electrode of the third drive control transistor is electrically connected to the first drive node; The first plate of the second storage capacitor receives a fixed signal, and the second plate of the second storage capacitor is electrically connected to the first driving node.

16. The display panel according to claim 1, characterized in that: The drive output module includes a first drive output unit and a second drive output unit; The first driving output unit is used to receive the signal of the first initial node and the first level signal, and control the gate driving signal; The second driving output unit is used to receive the signal of the first driving node and the second level signal, and control the gate driving signal.

17. The display panel according to claim 16, characterized in that: The first drive output unit includes a first drive output transistor; A gate of the first driving output transistor is electrically connected to the first initial node, a first electrode of the first driving output transistor receives the first level signal, and a second electrode of the first driving output transistor is electrically connected to the driving output node.

18. The display panel according to claim 16, characterized in that: The second drive output unit includes a second drive output transistor; A gate of the second driving output transistor is electrically connected to the first driving node, a first electrode of the second driving output transistor receives a second level signal, and a second electrode of the second driving output transistor is electrically connected to the driving output node.

19. The display panel according to claim 1, characterized in that: The level transmission output module includes a first level transmission output unit and a second level transmission output unit; The first-level transmission output unit is used to receive the signal of the first initial node and the first level signal, and control the level transmission signal; The second-stage transmission output unit is used to receive the signal of the second initial node and the second level signal, and control the stage transmission signal.

20. The display panel according to claim 19, characterized in that: The first-stage transmission-out unit includes a first-stage transmission-out transistor; The gate of the first-stage transmission output transistor is electrically connected to the first initial node, the first electrode of the first-stage transmission output transistor receives the first level signal, and the second electrode of the first-stage transmission output transistor outputs the level transmission signal.

21. The display panel according to claim 19, characterized in that: The second-stage transmission-out unit includes a second-stage transmission-out transistor; The gate of the second-stage transmission output transistor is electrically connected to the second initial node, the first electrode of the second-stage transmission output transistor receives the second level signal, and the second electrode of the second-stage transmission output transistor outputs the level transmission signal.

22. The display panel according to claim 1, characterized in that: The initial control module includes a first initial control unit and a second initial control unit; The first initial control unit is used to receive the input signal and the first clock signal, and control the signal of the first initial node; The second initial control unit is used to receive the signal of the first initial node, the first level signal and the second level signal, and control the signal of the second initial node.

23. The display panel according to claim 22, characterized in that: The first initial control unit includes an input subunit; The input subunit is used to receive the input signal and the first clock signal, and control the signal of the first initial node.

24. The display panel according to claim 23, characterized in that: The input subunit comprises a first input transistor; A gate of the first input transistor receives the first clock signal, a first electrode of the first input transistor receives the input signal, and a second electrode of the first input transistor is electrically connected to the first initial node.

25. The display panel according to claim 23, characterized in that: The first initial control unit further includes a charge pump subunit; the first initial node includes a first initial subnode and a second initial subnode; The input subunit is further used to receive the input signal and the first clock signal, and control the signal of the first initial subnode; The charge pump subunit is used to receive the signal of the first initial subnode and the second clock signal, and control the signal of the second initial subnode; The stage transmission output module is further used to control the stage transmission signal according to the signal of the second initial node and the signal of the second initial sub-node.

26. The display panel according to claim 25, characterized in that: The charge pump subunit includes a first auxiliary transistor, a second auxiliary transistor and a first bootstrap capacitor; The gate and the first electrode of the first auxiliary transistor are both electrically connected to the first initial subnode, and the second electrode of the first auxiliary transistor is electrically connected to the second initial subnode; The gate of the second auxiliary transistor is electrically connected to the first initial subnode, the first electrode of the second auxiliary transistor receives the second clock signal, the second electrode of the second auxiliary transistor is electrically connected to the first plate of the first bootstrap capacitor, and the second plate of the first bootstrap capacitor is electrically connected to the first initial subnode.

27. The display panel according to claim 26, characterized in that: The charge pump subunit further includes a third auxiliary transistor; A gate of the third auxiliary transistor is electrically connected to the second initial node, a first electrode of the third auxiliary transistor receives a second level signal, and a second electrode of the third auxiliary transistor is electrically connected to a first electrode plate of the first bootstrap capacitor.

28. The display panel according to claim 22, characterized in that: The first initial control unit also includes a voltage stabilizing subunit; The input subunit is electrically connected to the first initial node through the voltage stabilizing subunit.

29. The display panel according to claim 22, characterized in that: The second initial control unit includes a first initial control subunit and a second initial control subunit; The first initial control subunit is used to receive the second level signal and the signal of the first initial node, and control the signal of the second initial node; The second initial control subunit is used to receive the first level signal and the signal of the first initial node, and control the signal of the second initial node.

30. The display panel according to claim 29, characterized in that: The first initial control subunit includes a first initial control transistor; A gate of the first initial control transistor is electrically connected to the first initial node, a first electrode of the first initial control transistor receives the second level signal, and a second electrode of the first initial control transistor is electrically connected to the second initial node.

31. The display panel according to claim 29, characterized in that: The second initial control subunit includes a second initial control transistor; A gate of the second initial control transistor is electrically connected to the first initial node, a first electrode of the second initial control transistor receives the first level signal, and a second electrode of the first initial control transistor is electrically connected to the second initial node.

32. The display panel according to claim 22, characterized in that: The initial control module also includes a storage unit; A first terminal of the storage unit receives a fixed signal, and a second terminal of the storage unit is electrically connected to the second initial node.

33. The display panel according to claim 32, characterized in that: The storage unit includes a third storage capacitor; The first plate of the third storage capacitor receives the fixed signal, and the second plate of the third storage capacitor is electrically connected to the second initial node.

34. The display panel according to claim 1, characterized in that: Also includes a plurality of pixel circuits and a plurality of scanning signal lines arranged in an array; At least part of the pixel circuits in the same row are electrically connected to the same scanning signal line; The driving output node of the shift register unit is electrically connected to at least one of the scanning signal lines.

35. The display panel according to claim 1, characterized in that: Also included are a plurality of pixel circuits arranged in an array; The pixel circuit includes a driving transistor, a data writing module, an initialization module, a first light emitting control module, a second light emitting control module and a light emitting element; The initialization module and the data writing module are electrically connected to the driving transistor respectively; The initialization module is used to at least receive the gate drive signal and initialize the gate of the driving transistor; The data writing module is used to write the data signal into the gate of the driving transistor; The first light emitting control module and the second light emitting control module are used to control the driving transistor to provide a driving current to the light emitting element.

36. The display panel according to claim 35, characterized in that: The pixel circuit also includes a threshold compensation module and a reset module; The threshold compensation module is used to receive the gate drive signal and compensate the threshold compensation voltage to the gate of the driving transistor; The reset module provides a reset signal for the light emitting element.

37. A display device, characterized in that: A display panel comprising any one of claims 1 to 36.

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