Memory device and memory module including the same

Abstract

A memory device includes: a bank array including a plurality of memory cells; a row decoder connected to the bank array through a plurality of word lines; and a column decoder connected to the bank array through a plurality of column selection lines. The bank array may include a first region and a second region different from the first region. First metadata for first normal data stored in the first region is stored in the second region, and second metadata for second normal data stored in the second region is stored in the first region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0114053 filed in the Korean Intellectual Property Office on August 29, 2023, and Korean Patent Application No. 10-2024-0022946 filed in the Korean Intellectual Property Office on February 16, 2024, the disclosures of which are incorporated herein by reference in their entirety. Background Art

[0003] Memory devices are used to store data and are classified into volatile memory devices and non-volatile memory devices. When the power supply of a volatile memory device is interrupted, the data stored in it is lost. Dynamic random access memory (DRAM) is a volatile memory device used in various fields such as mobile systems, servers, and graphic devices. Technical Field

[0004] The present application relates to a storage device and a storage module including the storage device. Summary of the invention

[0005] In general, in some implementations, the present disclosure relates to storage devices that efficiently support metadata schemas.

[0006] According to some embodiments, the present disclosure relates to a memory device, comprising: a memory array including a plurality of memory cells; a row decoder connected to the memory array via a plurality of word lines; and a column decoder connected to the memory array via a plurality of column selection lines. The memory array may include a first region and a second region different from the first region. First metadata for first normal data stored in the first region is stored in the second region, and second metadata for second normal data stored in the second region is stored in the first region.

[0007] According to some embodiments, the present disclosure relates to a memory device, including: a memory bank array including a first region and a second region; a row decoder connected to the first region and the second region through a plurality of word lines, the plurality of word lines being arranged to span the first region and the second region; and a column decoder connected to the first region through a plurality of first column selection lines arranged in the first region, and connected to the second region through a plurality of second column selection lines arranged in the second region. First metadata for first normal data stored in the first region may be stored in the second region, and second metadata for second normal data stored in the second region may be stored in the first region.

[0008] According to some embodiments, the present disclosure relates to a storage module including a plurality of storage devices. Each of the plurality of storage devices may include: a storage array including a plurality of storage cells; a row decoder connected to the storage array via a plurality of word lines; and a column decoder connected to the storage array via a plurality of column selection lines. The storage array may include a first region and a second region different from the first region. First metadata for first normal data stored in the first region may be stored in the second region, and second metadata for second normal data stored in the second region may be stored in the first region. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 is a block diagram of an example of a storage system according to some implementations.

[0011] Figure 2 is a block diagram illustrating an example of a memory device according to some embodiments.

[0012] Figure 3 is a diagram illustrating an example of a memory bank array according to some embodiments.

[0013] Figure 4 is a diagram illustrating an example of a memory device according to some embodiments.

[0014] Figure 5 is a diagram illustrating an example of a memory bank according to some embodiments.

[0015] Figure 6 According to some embodiments Figure 5 Detailed view of example area "A".

[0016] 7A to 14B is a detailed view showing an example of a read operation of a memory bank according to some embodiments.

[0017] FIG. 15A to FIG. 15C is a diagram showing an example of allocating normal data and metadata to each column selection line according to some embodiments.

[0018] Fig.16 is a diagram illustrating an example of a memory bank according to some embodiments.

[0019] Fig.17 According to some embodiments Fig.16 Detailed view of example area "D".

[0020] Fig.18 and Fig.19 is a diagram illustrating a storage module according to some embodiments.

[0021] Fig. 20 and Fig.21 is a diagram illustrating an example of a storage module according to some embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0023] Figure 1 is a block diagram of an example of a storage system according to some embodiments. Figure 1 In the embodiment, the memory system 10 may support a metadata mode. The metadata mode may refer to a mode in which normal data and metadata corresponding to the normal data are input / output to the memory device 200 together.

[0024] The storage system 10 may include a plurality of storage bodies B1 to Bn, each of which may include a storage body array. In some embodiments, the storage body array of at least one of the plurality of storage bodies B1 to Bn may include a first region RG1 and a second region RG2, and each region may store normal data and metadata. For example, the first region RG1 may store first normal data, and the second region RG2 may store first metadata corresponding to the first normal data. In some embodiments, a read operation or a write operation on the first normal data and the first metadata may be performed simultaneously. For example, the second region RG2 may store second normal data, and the first region RG1 may store second metadata corresponding to the second normal data. In some embodiments, a write operation or a read operation on the second normal data and the second metadata may be performed simultaneously.

[0025] As described above, the memory system 10 can effectively execute the metadata mode by inputting or outputting metadata in one area of ​​the memory array while inputting or outputting normal data in another area of ​​the memory array.

[0026] exist Figure 1 , the memory system 10 may include a memory controller 100 and a memory device 200. The memory controller 100 may control the memory device 200. For example, the memory controller 100 may control the memory device 200 based on a request from a processor supporting various applications such as a server application, a personal computer (PC) application, or a mobile application. For example, the memory controller 100 may be included in a host including a processor, and may control the memory device 200 based on a request from the processor.

[0027] The memory controller 100 may transmit a command and / or an address to the memory device 200 to control the memory device 200. In addition, the memory controller 100 may transmit data to the memory device 200 or receive data from the memory device 200.

[0028] The memory device 200 may receive data from the memory controller 100 and store the received data. The memory device 200 may read the stored data in response to a request from the memory controller 100 and transmit the read data to the memory controller 100.

[0029] In some embodiments, the memory device 200 may be a memory device including a volatile memory cell. For example, the memory device 200 may be one of various DRAM devices, such as a double data rate synchronous dynamic random access memory (DDRSDRAM) device, a DDR2SDRAM device, a DDR3 SDRAM device, a DDR4 SDRAM device, a DDR5SDRAM device, a DDR6SDRAM device, a low power double data rate (LPDDR) SDRAM device, a LPDDR2 SDRAM device, a LPDDR3 SDRAM device, a LPDDR4SDRAM device, a LPDDR4X SDRAM device, a LPDDR5 SDRAM device, a graphic double data rate synchronous graphic random access memory (GDDR SGRAM) device, a GDDR2 SGRAM device, a GDDR3 SGRAM device, a GDDR4 SGRAM device, a GDDR5 SGRAM device, or a GDDR6 SGRAM device.

[0030] In some embodiments, the memory device 200 may be a stacked memory device in which DRAM chips are stacked, such as a high bandwidth memory (HBM) device, an HBM2 device, or an HBM3 device.

[0031] In some embodiments, the memory device 200 may be a memory module, such as a dual in-line memory module (DIMM). For example, the memory module 100A may be a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM0), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM), or a small outline DIMM (SO-DIMM). However, this is only an example, and the memory device 200 may be another memory module, such as a single in-line memory module (SIMM).

[0032] In some embodiments, the memory device 200 may be an SRAM device, a NAND flash memory device, a NOR flash memory device, an RRAM device, a FRAM device, a PRAM device, a TRAM device, or an MRAM device.

[0033] The memory device 200 may include a plurality of memory banks B1 to Bn. Each of the plurality of memory banks B1 to Bn may include a memory bank array, a row decoder, and a column decoder. For example, the first memory bank B1 may include a first memory bank array BA1, a first row decoder RD1, and a first column decoder CD1.

[0034] The plurality of bank arrays BA1 to BAn may each include memory cells storing data. The row decoder may activate a selected word line among a plurality of word lines based on a row address. The column decoder may activate a selected column selection line among a plurality of column selection lines based on a column address.

[0035] For ease of description, an example is given here in which each memory array includes DRAM cells. However, this is only an example, and each memory array can be implemented to include volatile memory cells different from DRAM cells. In some embodiments, each memory array can be implemented to include the same type of memory cells, or can be implemented to include the same type of memory cells.

[0036] At least one of the plurality of memory bank arrays BA1 to BAn may be provided to store normal data and metadata. Metadata may refer to data used to improve the performance of the memory device or enhance its security. For example, the metadata may be parity data to perform an error correction operation on the corresponding normal data. For example, the metadata may include information about the type, length, and attributes of the corresponding normal data, but example embodiments are not limited thereto.

[0037] In some embodiments, the memory bank array includes a first region RG1 and a second region RG2. The first region RG1 and the second region RG2 may store normal data and metadata, respectively. In an example embodiment, one of the first region RG1 and the second region RG2 may store normal data, and the other region may store metadata corresponding to the normal data.

[0038] For example, the first normal data may be stored in the first region RG1, and the first metadata corresponding to the first normal data may be stored in the second region RG2. In some embodiments, the first metadata may be written to or read from the second region RG2 while the first normal data is written to or read from the first region RG1.

[0039] For example, the second normal data may be stored in the second region RG2, and the second metadata corresponding to the second normal data may be stored in the first region RG1. In some embodiments, the second metadata may be written to the first region RG1 or read from the first region RG1 while the second normal data is written to the second region RG2 or read from the second region RG2.

[0040] As described above, metadata can be written to or read from one area of ​​a storage array while normal data is written to or read from another area of ​​the storage array. The storage system 10 according to the example embodiment can effectively support the metadata mode.

[0041] Figure 2 is a block diagram illustrating an example of a memory device 200 according to some embodiments. In some embodiments, Figure 2 The memory device 200 may correspond to Figure 1 A storage device 200 is provided.

[0042] exist Figure 2 In the embodiment, the memory device 200 may include a control logic circuit 210, an address register 220, a memory body control logic 230, a refresh control circuit 400, a row address multiplexer 240, a column address latch 250, a row decoder group 260, a column decoder group 270, a memory cell array 310, a sense amplifier unit 285, an input / output (I / O) gating circuit 290, an error correction code (ECC) engine 350, and a data input / output (I / O) buffer 320.

[0043] The memory cell array 310 may include a plurality of memory bank arrays 310_1 to 310_n. Each of the plurality of memory bank arrays 310_1 to 310_n may include a plurality of memory cells. For example, each of the plurality of memory cells may be formed at an intersection of a corresponding word line and a corresponding bit line.

[0044] The row decoder group 260 may include a plurality of row decoders 260_1 to 260_n. Each of the plurality of row decoders 260_1 to 260_n may be connected to a corresponding memory bank array among the plurality of memory bank arrays 310_1 to 310_n.

[0045] The sense amplifier unit 285 may include a plurality of sense amplifiers 285_1 to 285 — n. Each of the plurality of sense amplifiers 285_1 to 285 — n may be connected to a corresponding bank array among the plurality of bank arrays 310_1 to 310 — n.

[0046] The column decoder group 270 may include a plurality of column decoders 270_1 to 270_n. Each of the plurality of column decoders 270_1 to 270_n may be connected to a corresponding memory bank array among the plurality of memory bank arrays 310_1 to 310_n through a column selection line CLS.

[0047] In some embodiments, each of the plurality of bank arrays 310_1 to 310_n may include a first region RG1 and a second region RG2. The first region RG1 and the second region RG2 may include a normal data region storing normal data and a metadata region storing metadata, respectively.

[0048] For example, the normal data area of ​​the first area RG1 and the metadata area of ​​the second area RG2 may correspond to each other. For example, metadata corresponding to normal data stored in the normal data area of ​​the first area RG1 may be stored in the metadata area of ​​the second area RG2, and metadata corresponding to normal data stored in the normal data area of ​​the second area RG2 may be stored in the metadata area of ​​the first area RG1.

[0049] The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100. The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230, provide the received row address ROW_ADDR to the row address multiplexer 240, and provide the received column address COL_ADDR to the column address latch 250.

[0050] The bank control logic 230 may generate a bank control signal in response to the bank address BANK_ADDR. For example, among the plurality of row decoders 260_1 to 260_n, a row decoder corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal. Among the plurality of column decoders 270_1 to 270_n, a column decoder corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal.

[0051] The row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220 and receive the refresh row address REF_ADDR from the refresh control circuit 400. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to each of the plurality of row decoders 260_1 to 260_n.

[0052] The refresh control circuit 400 may sequentially increase or decrease the refresh row address REF_ADDR in the normal refresh mode in response to the refresh signal from the control logic circuit 210 .

[0053] In a hammer refresh mode, the refresh control circuit 400 may receive a hammer address HADDR and may output an address of a word line adjacent to a densely accessed word line as a refresh row address REF_ADDR based on the hammer address HADDR.

[0054] Among the plurality of row decoders 260_1 to 260_n, a row decoder selected by the bank control logic 230 may activate a word line corresponding to a row address RA output from the row address multiplexer 240. For example, the selected row decoder may apply a word line driving voltage to a word line corresponding to the row address.

[0055] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and temporarily store the received column address COL_ADDR. For example, in the burst mode, the column address latch 250 may gradually increase the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or gradually increased column address COL_ADDR' to each of the plurality of column decoders 270_1 to 270_n.

[0056] Among the plurality of column decoders 270_1 through 270 — n , a column decoder activated by the bank control logic 230 may activate a sense amplifier corresponding to a bank address BANK_ADDR and a column address COL_ADDR through an input / output gating circuit 290 .

[0057] The input / output gating circuit 290 may include a circuit for inputting / outputting data. The input / output gating circuit 290 may include: a data latch storing code words output from the plurality of memory bank arrays 310_1 to 310_n; and a write driver writing data into the plurality of memory bank arrays 310_1 to 310_n.

[0058] In some embodiments, during a read operation, a codeword CW read from a selected memory bank array among the plurality of memory bank arrays 310_1 to 310_n may be detected by a sense amplifier corresponding to the selected memory bank array and may be stored in a data latch of the input / output gating circuit 290. The codeword CW stored in the data latch may be ECC-decoded by the ECC engine 350 and provided as data DTA to the data input / output buffer 320. The data input / output buffer 320 may generate a data signal DQ based on the data DTA and provide the data signal DQ to the memory controller 100 together with the strobe signal DQS.

[0059] In some embodiments, during a write operation, the data input / output buffer 320 may receive data DTA to be written to a selected memory bank array among the plurality of memory bank arrays 310_1 to 310_n as a data signal DQ. The data input / output buffer 320 may convert the data signal DQ into data DTA and provide the data DTA to the ECC engine 350. The ECC engine 350 may generate a parity bit (or parity data) based on the data DTA and provide a codeword CW including the data DTA and the parity bit to the input / output gating circuit 290. The input / output gating circuit 290 may write the codeword CW to the selected memory bank array.

[0060] The data input / output buffer 320 may convert the data signal DQ into data DTA during a write operation and provide the data DTA to the ECC engine 350. The data input / output buffer 320 may convert the data DTA provided by the ECC engine 350 into the data signal DQ during a read operation.

[0061] The ECC engine 350 may perform ECC encoding on the data DTA during a write operation. The ECC engine 350 may perform ECC decoding on the codeword CW during a read operation.

[0062] The control logic circuit 210 may control the operation of the memory device 200. For example, the control logic circuit 210 may generate a control signal to control the memory device 200 to perform a write operation, a read operation, a normal refresh operation, and a hammer refresh operation. The control logic circuit 210 may include: a command decoder 211 that decodes a command CMD received from the memory controller 100; and a mode register set (MRS) 212 that sets the operation mode of the memory device 200.

[0063] The command decoder 211 may decode the command CMD to generate internal command signals such as an internal activation signal IACT, an internal precharge signal IPRE, an internal read signal IRD, and an internal write signal IWR. The command decoder 211 may decode a chip select signal and a command / address signal to generate a control signal corresponding to the command CMD.

[0064] The mode register set 212 may set the operation mode of the memory device 200. In some embodiments, the mode register set 212 may set the operation mode of the memory device 200 to a metadata mode. "Metadata mode" may refer to a mode in which both user data and metadata are stored in the memory device 200. Metadata may be used to improve the performance and security of the memory device.

[0065] In some embodiments, the mode register set 212 may set the operation mode of the memory device 200 to a general mode. The "general mode" may refer to a mode in which only user data (excluding metadata) is stored in the memory device 200. In the general mode, user data may also be stored in the area in which metadata is stored in the metadata mode.

[0066] In some embodiments, the first region RG1 and the second region RG2 of the memory bank array may be activated during a write operation or a read operation.

[0067] For example, first normal data may be stored in the first region RG1 of the first memory bank array BA1, and first metadata corresponding to the first normal data may be stored in the second region RG2. In some embodiments, during a write operation or a read operation, a column selection line corresponding to the first normal data of the first region RG1 and a column selection line corresponding to the first metadata of the second region RG2 may be activated simultaneously. Accordingly, the first normal data and the corresponding first metadata may be input or output together.

[0068] For example, the second normal data may be stored in the second region RG2 of the first memory bank array BA1, and the second metadata corresponding to the second normal data may be stored in the first region RG1. In some embodiments, during a write operation or a read operation, a column selection line corresponding to the second normal data of the second region RG2 and a column selection line corresponding to the second metadata of the first region RG1 may be activated simultaneously. Accordingly, the second normal data and the corresponding second metadata may be input or output together.

[0069] As described above, normal data and metadata of a memory bank array may be input and output to effectively perform a metadata mode.

[0070] Figure 3is a diagram showing an example of a memory bank array according to some embodiments. In some embodiments, Figure 3 The bank array 310_1 may correspond to, for example Figure 2 For ease of description, Figure 3 , an example in which a single column selection line CSL corresponds to eight bit lines is provided.

[0071] exist Figure 3 In the embodiment, the first memory bank array 310_1 may include a plurality of word lines WL0 to WLi, a plurality of bit lines BL0 to BLj, and a plurality of memory cells MC disposed at intersections of the word lines WL0 to WLi and the bit lines BL0 to BLj.

[0072] In some embodiments, each memory cell MC may be a DRAM cell. For example, each memory cell MC may include a cell transistor connected to a word line and a bit line, and a cell capacitor connected to the cell transistor.

[0073] A single column selection line CSL may be electrically connected to a plurality of bit lines. For example, a single column selection line CSL may be electrically connected to eight bit lines. In some embodiments, 8 bits of data may be read from or written to a memory cell MC via a single word line and a single column selection line CSL. However, this is merely an example, and a single column selection line CSL may be implemented to be electrically connected to a different number of bit lines.

[0074] According to some embodiments, the word lines extending in the row direction may be referred to as rows of the first memory array 310_1. The column selection lines CSL extending in the column direction may be referred to as columns of the first memory array 310_1. However, this is only an example, and the bit lines extending in the column direction may also be referred to as columns of the first memory array 310_1.

[0075] In the following description, the phrase "data is stored in a column selection line" may mean that data is stored in a memory cell corresponding to the column selection line. Likewise, the phrase "data is stored in a word line" may mean that data is stored in a memory cell corresponding to the word line.

[0076] Figure 4 is a diagram illustrating an example of a memory device according to some embodiments, including an arrangement of a bank array and corresponding row and column decoders. Figure 4 The memory device 200 may correspond to, for example, Figure 1 and Figure 2 For convenience of description, an example is provided in which the memory device 200 includes 32 memory bank arrays and a single memory bank group BG includes 4 memory bank arrays.

[0077] exist Figure 4In the embodiment, the first memory bank group BG1 may include first to fourth memory bank arrays BA1 to BA4. For example, the first to fourth memory bank arrays BA1 to BA4 may be disposed adjacent to each other on an upper portion of a substrate not shown, and the third and fourth memory bank arrays BA3 and BA4 may be disposed adjacent to each other on a lower portion of the substrate.

[0078] The first row decoder RD1 and the first column decoder CD1 may correspond to the first memory array BA1, and the second row decoder RD2 and the second column decoder CD2 may correspond to the second memory array BA2. In addition, the third row decoder RD3 and the third column decoder CD3 may correspond to the third memory array BA3, and the fourth row decoder RD4 and the fourth column decoder CD4 may correspond to the fourth memory array BA4.

[0079] In some embodiments, each of the plurality of memory bank arrays BA1 to BA32 may include a first region RG1 and a second region RG2. The first region RG1 and the second region RG2 may include a normal data region storing normal data and a metadata region storing metadata, respectively. For example, metadata corresponding to normal data stored in the normal data region of the first region RG1 may be stored in the metadata region of the second region RG2, and metadata corresponding to normal data stored in the normal data region of the second region RG2 may be stored in the metadata region of the first region RG1.

[0080] The number of memory banks included in a memory bank group and the number of memory bank groups included in a single memory device may vary according to example embodiments.

[0081] Figure 5 is a diagram of an example of a memory bank according to some embodiments, and Figure 6 According to some embodiments Figure 5 Detailed view of example area "A". Figure 5 The first memory bank B1 may correspond to Figures 1 to 4 For ease of description, Figure 5 and Figure 6 An example in which the ratio of normal data to metadata is 8:1 is shown.

[0082] exist Figure 5 In the embodiment, the first memory bank B1 includes a first memory bank array BA1, a first row decoder RD1, and a first column decoder CD1. The first memory bank array BA1 may be divided into a first region RG1 and a second region RG2.

[0083] In some embodiments, the length of the first region RG1 in the row direction and the length of the second region RG2 in the row direction may be the same. For example, a column selection line extending from the ECC block EB in the column direction may be set at the center of the first memory array BA1, and the first memory array BA1 may be divided into a first region RG1 and a second region RG2 relative to the column selection line extending from the ECC block EB in the column direction. Accordingly, the number of column selection lines corresponding to the first region RG1 and the number of column selection lines corresponding to the second region RG2 may be the same. However, this is only an example, and according to some embodiments, the length of the first region RG1 in the row direction and the length of the second region RG2 in the row direction may be different from each other.

[0084] Each of the first region RG1 and the second region RG2 may include a plurality of memory cell clusters (mat) MAT. Each of the plurality of memory cell clusters MAT may be a memory cell cluster connected to a portion of a word line and a portion of a CSL. Each of the plurality of memory cell clusters MAT may include a plurality of memory cells, and each of the plurality of memory cells may be connected to one of the partial word lines connected to the corresponding memory cell cluster MAT and one of the partial CSLs connected to the corresponding memory cell cluster MAT.

[0085] The first column decoder CD1 may include a plurality of CSL blocks CB0 to CB7 and an ECC block EB. Each of the plurality of CSL blocks CB0 to CB7 may be configured to select a column selection line to be activated among a plurality of column selection lines based on a column address decoded by the first column decoder CD1.

[0086] In some embodiments, each CSL block CB may correspond to two CSL groups CS. For example, the zeroth CSL block CB0 may correspond to the zeroth CSL group CS0 and the first CSL group CS1, and the first CSL block CB1 may correspond to the second CSL group CS2 and the third CSL group CS3. Similarly, the sixth CSL block CB6 may correspond to the twelfth CSL group CS12 and the thirteenth CSL group CS13, and the seventh CSL block CB7 may correspond to the fourteenth CSL group CS14 and the fifteenth CSL group CS15.

[0087] Each CSL group CS may include a plurality of column selection lines. For example, each CSL group CS may include 64 column selection lines. A portion of the 64 column selection lines may be allocated to a normal data region, and another portion may be allocated to a metadata region.

[0088] We will now describe in more detail Figure 6An example of a zeroth CCSL block CB0 is shown in FIG. The zeroth CSL block CB0 may be connected to a zeroth CSL group CS0 and a first CSL group CS1. The zeroth CSL group CS0 may include a zeroth column selection line CSL0 to a sixty-third column selection line CSL63, and the first CSL group CS1 may include a zeroth column selection line CSL0 to a sixty-third column selection line CSL63. Therefore, a total of 128 column selection lines may be connected to the zeroth CSL block CB0.

[0089] In the zeroth CSL group CS0, the zeroth column selection line CSL0 to the fifty-fifth column selection line CSL55 may be allocated to the normal data region NDR, and the remaining fifty-sixth column selection line CSL56 to the sixty-third column selection line CSL63 may be allocated to the metadata region MDR. The zeroth column selection line CSL0 to the fifty-fifth column selection line CSL55 of the first CSL group CS1 may be allocated to the normal data region NDR, and the remaining fifty-sixth column selection line CSL56 to the sixty-third column selection line CSL63 may be allocated to the metadata region MDR. As described above, a portion of the column selection lines of each CSL group CS may be allocated to the normal data region NDR, and another portion of the column selection lines may be allocated to the metadata region MDR.

[0090] exist Figure 5 In the embodiment, during a single access operation, a single column selection line can be selected and activated from a single CSL group CS. Since two CSL groups CS correspond to one CSL block CB, during a single access operation, one or two column selection lines can be selected by a single CSL block CB.

[0091] In some embodiments, the first region RG1 and the second region RG2 may store normal data and metadata, respectively. For example, first metadata corresponding to first normal data stored in the normal data region NDR of the first region RG1 may be stored in the metadata region MDR of the second region RG2. For example, second metadata corresponding to second normal data stored in the normal data region NDR of the second region RG2 may be stored in the metadata region MDR of the first region RG1.

[0092] In some embodiments, the first region RG1 and the second region RG2 may be activated simultaneously during a write operation or a read operation. For example, during a write operation, the first normal data and the first metadata corresponding to the first normal data may be stored in the first region RG1 and the second region RG2, respectively. In some embodiments, the column selection line corresponding to the first normal data of the first region RG1 and the column selection line corresponding to the first metadata of the second region RG2 may be activated simultaneously. Accordingly, the first normal data and the corresponding first metadata may be input together.

[0093] For example, during a read operation, first normal data and first metadata corresponding to the first normal data may be read from the first region RG1 and the second region RG2, respectively. In some embodiments, a column selection line corresponding to the first normal data of the first region RG1 and a column selection line corresponding to the first metadata of the second region RG2 may be activated at the same time. Accordingly, the first normal data and the corresponding first metadata may be output at the same time.

[0094] As described above, normal data may be input and output in one area of ​​the first bank array BA1 while metadata is input and output in another area of ​​the first bank array BA1, and thus, the metadata mode may be efficiently performed.

[0095] exist Figure 5 and Figure 6 , the first memory array BA1 is described as including 16 CSL groups, each CSL group including 64 column selection lines. However, it should be understood that this is only an example, and some embodiments may not be limited thereto. The number of CSL groups included in each memory array and the number of column selection lines included in each CSL group may be set differently according to example embodiments.

[0096] Operations of a memory device according to example embodiments will be described below in more detail.

[0097] 7A to 13B is a detailed view showing an example of a read operation of a memory bank according to some embodiments. In some embodiments, 7A to 13B The memory bank can correspond to Figures 1 to 6 storage device.

[0098] For ease of description, an example is provided in which the ratio of normal data to corresponding metadata is 8:1. In addition, an example is provided in which a single column selection line corresponds to eight bit lines and the bit width of each channel is 32 bits. In addition, an example is provided as follows: the index IDs of the zeroth CSL group CS0, the first CSL group CS1, the second CSL group CS2, the third CSL group CS3, the fourth CSL group CS4, the fifth CSL group CS5, the sixth CSL group CS6, and the seventh CSL group CS7 of the first region RG1 are 1, 3, 5, 7, 9, 11, 13, and 15, respectively, and the index IDs of the eighth CSL group CS8, the ninth CSL group CS9, the tenth CSL group CS10, the eleventh CSL group CS11, the twelfth CSL group CS12, the thirteenth CSL group CS13, the fourteenth CSL group CS14, and the fifteenth CSL group CS15 of the second region RG2 are 0, 2, 4, 6, 8, 10, 12, and 14, respectively. In addition, for convenience of description, an example of activating the zeroth word line WL0 will be provided.

[0099] In the following description, the encoding value of normal data will be expressed as "CSLx_Left" or "CSLx_Right", where "x" may refer to the number of the column selection line, "Left" may refer to the first region RG1, and "Right" may refer to the second region RG2. In addition, the encoding value of metadata will be expressed as "MCSLi <j>”, where “i” may refer to the number of the column select line, and “j” may refer to the index ID of the CSL group.

[0100] FIG. 7A to FIG. 7C An example of performing a read operation on first normal data stored in the first region RG1 and first metadata stored in the second region RG2 according to some embodiments is shown. The first metadata may be metadata for the first normal data.

[0101] exist Fig. 7A and Figure 7B , the encoding value for normal data may be "CSL0_Left". Accordingly, the first region RG1 may be selected, and the zeroth column selection line CSL0 included in the selected first region RG1 may be activated, as shown. For example, the zeroth column selection line CSL0 may be activated in each of the zeroth to seventh CSL groups CS0 to CS7 included in the first region RG1.

[0102] Each CSL block CB corresponds to two CSL groups CS, so that each of the zeroth CSL block CB0 to the third CSL block CB3 can activate two zeroth column selection lines CSL0. The two column selection lines activated by each CSL block CB can be referred to as a "CSL subset". In some embodiments, a single column selection line is electrically connected to eight bit lines, so each of the zeroth CSL block CB0 to the third CSL block CB3 can output 16 bits of data. Therefore, a total of 64 bits of first normal data can be output.

[0103] In some embodiments, when the bit width of each channel is implemented as 32 bits, two CSL blocks CB may correspond to a single channel or I / O pin. Accordingly, the first normal data may be output to the outside through two I / O pins. For example, the data of the first normal data corresponding to the zeroth CSL block CB0 and the first CSL block CB1 may be output to the outside through the zeroth I / O pin DQ0, and the data of the first normal data corresponding to the second CSL block CB2 and the third CSL block CB3 may be output to the outside through the first I / O pin DQ1. However, this is only an example, and some embodiments may not be limited thereto. The bit width of each channel may be implemented or set in various ways according to some embodiments.

[0104] In some embodiments, the bit width of each channel can be implemented as 16 bits. In some embodiments, a single CSL block CB can correspond to a single channel or I / O pin. For example, data corresponding to the zeroth CSL block CB0 to the third CSL block CB3 of the first normal data can be output to the outside through the zeroth I / O pin DQ0 to the third I / O pin DQ3, respectively.

[0105] In some embodiments, the bit width of each channel can be implemented as 64 bits. In some embodiments, four CSL blocks CB can correspond to a single channel or I / O pin. For example, data corresponding to the zeroth CSL block CB0 to the third CSL block CB3 of the first normal data can be output to the outside through a single I / O pin (e.g., DQ0).

[0106] exist Fig. 7A and Figure 7B In the example, the encoding value for metadata can be "MCSL56 <0> Accordingly, the eighth CSL group CS8 having an index (ID) value of “0” of the second region RG2 may be selected, and a fifty-sixth column selection line CSL56 may be activated in the selected eighth CSL group CS8.

[0107] In some embodiments, a single column selection line is electrically connected to 8 bit lines so that the fourth CSL block CB4 can output 8 bits of first metadata.

[0108] In some embodiments, when the bit width of each channel is implemented as 32 bits, the first normal data may correspond to two I / O pins. In some embodiments, the first metadata may be output to the outside through two I / O pins in units of 4 bits. For example, 4 bits of the first metadata may be output to the outside through the zeroth I / O pin DQ0, and another 4 bits of the first metadata may be output to the outside through the first I / O pin DQ1.

[0109] In some embodiments, when the bit width of each channel is implemented as 16 bits, the first normal data may correspond to 4 I / O pins. In some embodiments, the first metadata may be output to the outside through 4 I / O pins in units of 2 bits.

[0110] In some embodiments, when the bit width of each channel is implemented as 64 bits, the first normal data may correspond to a single I / O pin. In some embodiments, the first metadata may be output to the outside through a single I / O pin in units of 8 bits.

[0111] exist Figure 7C In the embodiment, the first normal data may be output to the outside through the zeroth data pin DQ0 and the first data pin DQ1 during the first time T1. The first time T1 may be less than or equal to the command transmission time "tCCD_s" between memory banks belonging to different memory bank groups.

[0112] The first metadata may be output to the outside through the zeroth data pin DQ0 and the first data pin DQ1 during the second time T2. In some embodiments, the first metadata may be output continuously after the first normal data is output. The first metadata is output to the outside in units of 4 bits, so that the second time T2 may correspond to two clock times tCK.

[0113] The third time T3 for outputting the first normal data and the corresponding first metadata to the outside may correspond to "tCCD_s+2*tCK", which means that there is no or little time loss when outputting the first normal data and the first metadata. Therefore, according to some embodiments, the metadata mode can be effectively performed without reducing performance.

[0114] According to some embodiments, the first metadata may be output to the outside through an additional data pin different from the zeroth data pin DQ0 and the first data pin DQ1. In some embodiments, the first normal data and the first metadata may be output to the outside together.

[0115] According to some embodiments, the first metadata may be output to the outside through the zeroth data pin DQ0 and the first data pin DQ1 , and then, the first normal data may be output to the outside through the zeroth data pin DQ0 and the first data pin DQ1 .

[0116] Fig. 8A and Figure 8B An example of performing a read operation on the second normal data stored in the second region RG2 and the second metadata stored in the first region RG1 according to some embodiments is shown. The second metadata may be metadata corresponding to the second normal data.

[0117] exist Fig. 8A and Figure 8B , the encoding value for normal data may be "CSL0_Right". Accordingly, the second region RG2 may be selected, and the zeroth column selection line CSL0 included in the selected second region RG2 may be activated, as shown. For example, the zeroth column selection line CSL0 may be activated in each of the eighth CSL group CS8 to the fifteenth CSL group CS15 included in the second region RG2.

[0118] Each CSL block CB corresponds to two CSL groups CS, so that each of the fourth CSL block CB4 to the seventh CSL block CB7 can activate two zeroth column selection lines CSL0. In some embodiments, a single column selection line is electrically connected to 8 bit lines, so that each of the fourth CSL block CB4 to the seventh CSL block CB7 can output 16 bits of data. Therefore, a total of 64 bits of first normal data can be output.

[0119] In some embodiments, when the bit width of each channel is implemented as 32 bits, two CSL blocks CB can correspond to a single channel or I / O pin. Therefore, the second normal data can be output to the outside through two I / O pins. For example, the data of the second normal data corresponding to the fourth CSL block CB4 and the fifth CSL block CB5 can be output to the outside through the zeroth I / O pin DQ0, and the data of the second normal data corresponding to the sixth CSL block CB6 and the seventh CSL block CB7 can be output to the outside through the first I / O pin DQ1. However, this is only an example, and some implementations are not limited to this. FIG. 7A to FIG. 7C As described above, according to some embodiments, the bit width of each channel may be implemented or set in various ways.

[0120] exist Fig. 8A and Figure 8B In the example, the encoding value for metadata can be "MCSL56 <1> Therefore, the zeroth CSL group CS0 having an index (ID) value of “1” of the first region RG1 may be selected, and the fifty-sixth column selection line CSL56 in the selected zeroth CSL group CS0 may be activated.

[0121] In some embodiments, a single column selection line is electrically connected to 8 bit lines so that the zeroth CSL block CB0 can output 8 bits of second metadata.

[0122] In some embodiments, when each channel bit width is implemented as 32 bits, the second normal data may correspond to two I / O pins. In some embodiments, the second metadata may be output to the outside through two I / O pins in units of 4 bits. For example, 4 bits of second metadata may be output to the outside through the zeroth I / O pin DQ0, and another 4 bits of second metadata may be output to the outside through the first I / O pin DQ1. However, this is only an example, and each channel bit width may be implemented or set in various ways according to some implementations.

[0123] In some embodiments, the second metadata may be output continuously after the second normal data is output. For example, the second normal data may be output at the first time T1 (see Figure 7C ) is output to the outside through the zeroth data pin DQ0 and the first data pin DQ1 during the period. The second metadata may be output to the outside through the zeroth data pin DQ0 and the first data pin DQ1 during the period. Figure 7C ) is output to the outside through the zeroth data pin DQ0 and the first data pin DQ1. The second normal data and the corresponding second metadata are output to the outside in the third time period T3 (see Figure 7C ) may correspond to "tCCD_s+2*tCK". Therefore, the metadata mode may be efficiently executed without performance degradation.

[0124] Fig.9A and Fig. 9B An example of performing a read operation on third normal data stored in the first region RG1 and third metadata stored in the second region RG2 according to some embodiments is shown. The third metadata may be metadata for the third normal data.

[0125] exist Fig.9A and Fig. 9B , the encoding value for normal data may be “CSL1_Left.” Therefore, as shown in the figure, the first region RG1 may be selected, and the first column selection line CSL1 included in the selected first region RG1 may be activated.

[0126] In some embodiments, a single column selection line is electrically connected to 8 bit lines so that each of the 0th to 3rd CSL blocks CB0 to CB3 can output 16-bit data. Therefore, a total of 64 bits of third normal data can be output.

[0127] In some embodiments, when the bit width of each channel is implemented as 32 bits, the third normal data can be output to the outside through two I / O pins. For example, the data of the third normal data corresponding to the zeroth CSL block CB0 and the first CSL block CB1 can be output to the outside through the zeroth I / O pin DQ0, and the data of the third normal data corresponding to the second CSL block CB2 and the third CSL block CB3 can be output to the outside through the first I / O pin DQ1. However, this is only an example, and some implementations are not limited thereto. FIG. 7A to FIG. 7C As described above, according to some embodiments, the bit width of each channel may be implemented or set in various ways.

[0128] exist Fig.9A and Fig. 9B In the example, the encoding value for metadata can be "MCSL56 <2> ". Therefore, the ninth CSL group CS9 having an index (ID) value of "2" of the second region RG2 can be selected, and the fifty-sixth column selection line CSL56 can be activated in the selected ninth CSL group CS9. In this case, the single column selection line is electrically connected to 8 bit lines, so that the fourth CSL block CB4 can output 8 bits of third metadata.

[0129] In some embodiments, when the bit width of each channel is implemented as 32 bits, the third metadata can be output to the outside through two I / O pins in units of 4 bits. For example, 4 bits of the third metadata can be output to the outside through the zeroth I / O pin DQ0, and another 4 bits of the third metadata can be output to the outside through the first I / O pin DQ1. However, this is only an example, and according to some implementations, the bit width of each channel can be implemented or set in various ways.

[0130] In some embodiments, the third metadata may be output continuously after the third normal data is output. Similar to the above, the time required for the third normal data and the corresponding third metadata to be output to the outside may correspond to "tCCD_s+2*tCK". Therefore, the metadata mode may be effectively executed without reducing performance.

[0131] Fig. 10A and Fig. 10B An example of performing a read operation on fourth normal data stored in the second region RG2 and fourth metadata stored in the first region RG1 according to some embodiments is shown. The fourth metadata may be metadata for the fourth normal data.

[0132] exist Fig. 10A and Fig. 10B , the encoding value for the normal data may be "CSL1_Right". Therefore, as shown in the figure, the second region RG2 may be selected, and the first column selection line CSL1 included in the selected second region RG2 may be activated. In some embodiments, each of the fourth to seventh CSL blocks CB4 to CB7 may output 16-bit data. Therefore, a total of 64 bits of fourth normal data may be output.

[0133] In some embodiments, when the bit width of each channel is implemented as 32 bits, the data of the fourth normal data corresponding to the fourth CSL block CB4 and the fifth CSL block CB5 can be output to the outside through the zeroth I / O pin DQ0, and the data of the fourth normal data corresponding to the sixth CSL block CB6 and the seventh CSL block CB7 can be output to the outside through the first I / O pin DQ1.

[0134] The encoding value for metadata could be "MCSL56 <3> Therefore, the first CSL group CS1 having an index (ID) value of “3” of the first region RG1 may be selected, and the 56th column selection line CSL56 may be activated in the selected first CSL group CS1. In some embodiments, the zeroth CSL block CB0 may output 8-bit fourth metadata.

[0135] In some embodiments, when the bit width of each channel is implemented as 32 bits, 4 bits of fourth metadata can be output to the outside through the zeroth I / O pin DQ0, and another 4 bits of fourth metadata can be output to the outside through the first I / O pin DQ1.

[0136] The fourth metadata may be output continuously after the fourth normal data is output. Similar to the above, the time required for the fourth normal data and the corresponding fourth metadata to be output to the outside may correspond to "tCCD_s+2*tCK". Therefore, the metadata mode may be effectively executed without reducing performance.

[0137] In this way, a read operation may be performed on the fifth normal data corresponding to "CSL2_Left" and the fifth metadata corresponding to "MCSL56", and a read operation may be performed on the sixth normal data corresponding to "CSL2_Right" and the sixth metadata corresponding to "MCSL56", and the detailed description thereof will be omitted. Similarly, a read operation may be performed on the seventh to fourteenth normal data and the corresponding seventh to fourteenth metadata, and the detailed description thereof will be omitted.

[0138] Fig.11A and Fig. 11B An example of performing a read operation on fifteenth normal data stored in the first region RG1 and fifteenth metadata stored in the second region RG2 according to some embodiments is shown. The fifteenth metadata may be metadata for the fifteenth normal data.

[0139] exist Fig.11A and Fig. 11B , the encoding value for normal data may be "CSL7_Left". Accordingly, as shown in the figure, the first region RG1 may be selected, and the seventh column selection line CSL7 included in the selected first region RG1 may be activated. In some embodiments, each of the zeroth CSL block CB0 to the third CSL block CB3 may output 16 bits of data. Therefore, a total of 64 bits of the fifteenth normal data may be output.

[0140] In some embodiments, when the bit width of each channel is implemented as 32 bits, the data of the fifteenth normal data corresponding to the zeroth CSL block CB0 and the first CSL block CB1 can be output to the outside through the zeroth I / O pin DQ0, and the data of the fifteenth normal data corresponding to the second CSL block CB2 and the third CSL block CB3 can be output to the outside through the first I / O pin DQ1.

[0141] The encoding value for metadata could be "MCSL56 <14> Therefore, the fifteenth CSL group CS15 having an index (ID) value of '14' of the second region RG2 may be selected, and a fifty-sixth column selection line CSL56 may be activated in the selected fifteenth CSL group CS15. In example embodiments, the seventh CSL block CB7 may output 8-bit fifteenth metadata.

[0142] In some embodiments, when each channel bit width is implemented as 32 bits, 4 bits of fifteenth data can be output to the outside through the zeroth I / O pin DQ0, and another 4 bits of fifteenth data can be output to the outside through the first I / O pin DQ1.

[0143] The fifteenth metadata can be output continuously after the fifteenth normal data is output. Similar to the above, the time required for the fifteenth normal data and the corresponding fifteenth metadata to be output to the outside corresponds to "tCCD_s+2*tCK". Therefore, the metadata mode can be effectively executed without reducing performance.

[0144] Fig. 12A and Fig. 12B An example of performing a read operation on sixteenth normal data stored in the first region RG1 and sixteenth metadata stored in the second region RG2 according to some embodiments is shown. The sixteenth metadata may be metadata for the sixteenth normal data.

[0145] exist Fig. 12A and Fig. 12B , the encoding value for normal data may be "CSL7_Right". Therefore, as shown in the figure, the second region RG2 may be selected, and the seventh column selection line CSL7 included in the selected second region RG2 may be activated. In example embodiments, each of the fourth to seventh CSL blocks CB4 to CB7 may output 16-bit data. Therefore, a total of 64-bit sixteenth normal data may be output.

[0146] In some embodiments, when the bit width of each channel is implemented as 32 bits, the data of the sixteenth normal data corresponding to the fourth CSL block CB4 and the fifth CSL block CB5 can be output to the outside through the zeroth I / O pin DQ0, and the data of the sixteenth normal data corresponding to the sixth CSL block CB6 and the seventh CSL block CB7 can be output to the outside through the first I / O pin DQ1.

[0147] The encoding value for metadata could be "MCSL56 <15> Therefore, the seventh CSL group CS7 having an index (ID) value of "15" of the first region RG1 may be selected, and a fifty-sixth column selection line CSL56 may be activated in the selected seventh CSL group CS7. In some embodiments, the third CSL block CB3 may output 8-bit sixteenth metadata.

[0148] In some embodiments, when each channel bit width is implemented as 32 bits, 4 bits of sixteenth data can be output to the outside through the zeroth I / O pin DQ0, and another 4 bits of sixteenth data can be output to the outside through the first I / O pin DQ1.

[0149] The sixteenth metadata may be output continuously after the sixteenth normal data is output. Similar to the above, the time required for the sixteenth normal data and the corresponding sixteenth metadata to be output to the outside may correspond to "tCCD_s+2*tCK". Therefore, the metadata mode may be effectively executed without reducing performance.

[0150] exist 7A to 12B , the normal data may correspond to the zeroth column selection line CSL0 to the seventh column selection line CSL7 of the first region RG1, and the metadata for the normal data may correspond to the fifty-sixth column selection line CSL56 of the second region RG2. In addition, the normal data may correspond to the zeroth column selection line CSL0 to the seventh column selection line CSL7 of the second region RG2, and the metadata for the normal data may correspond to the fifty-sixth column selection line CSL56 of the first region RG1.

[0151] In this way, the normal data may correspond to the eighth column selection line CSL8 to the fifty-fifth column selection line CSL55 of the first region RG1, and the metadata for the normal data may correspond to the fifty-seventh column selection line CSL57 to the sixty-second column selection line CSL62 of the second region RG2. In addition, the normal data may correspond to the eighth column selection line CSL8 to the fifty-fifth column selection line CSL55 of the second region RG2, and the metadata for the normal data may correspond to the fifty-seventh column selection line CSL57 to the sixty-second column selection line CSL62 of the first region RG1.

[0152] Fig.13A and Fig. 13B An example of performing a read operation on the one hundred and eleventh normal data stored in the first region RG1 and the one hundred and eleventh metadata stored in the second region RG2 according to some embodiments is shown. The one hundred and eleventh metadata may be metadata for the one hundred and eleventh normal data.

[0153] The encoding value for the one hundred and eleventh normal data may be "CSL55_Left". Therefore, as shown in the figure, the first region RG1 may be selected, and the fifty-fifth column selection line CSL55 included in the selected first region RG1 may be activated. In some embodiments, each of the zeroth to third CSL blocks CB0 to CB3 may output 16 bits of data. Therefore, a total of 64 bits of the one hundred and eleventh normal data may be output.

[0154] In some embodiments, when the bit width of each channel is implemented as 32 bits, the data of the one-hundred-eleventh normal data corresponding to the zeroth CSL block CB0 and the first CSL block CB1 can be output to the outside through the zeroth I / O pin DQ0, and the data of the one-hundred-eleventh normal data corresponding to the second CSL block CB2 and the third CSL block CB3 can be output to the outside through the first I / O pin DQ1.

[0155] The encoding value for metadata could be "MCSL62 <14> Therefore, the fifteenth CSL group CS15 having an index (ID) value of "14" of the second region RG2 may be selected, and the sixty-second column selection line CSL62 may be activated in the selected fifteenth CSL group CS15. In some embodiments, the seventh CSL block CB7 may output 8-bit one hundred and eleventh data.

[0156] In some embodiments, when the bit width of each channel is implemented as 32 bits, 4 bits of the one hundred and eleventh data can be output to the outside through the zeroth I / O pin DQ0, and another 4 bits of the one hundred and eleventh data can be output to the outside through the first I / O pin DQ1.

[0157] The 111th metadata may be output continuously after the 111th normal data is output. Similar to the above, the time required for the 111th normal data and the corresponding 111th metadata to be output to the outside may correspond to "tCCD_s+2*tCK". Therefore, the metadata mode may be effectively executed without reducing performance.

[0158] Fig.14A and Fig. 14B An example of performing a read operation on the one hundred and twelfth normal data stored in the second region RG2 and the one hundred and twelfth metadata stored in the first region RG1 according to some embodiments is shown. The one hundred and twelfth metadata may be metadata for the one hundred and twelfth normal data.

[0159] The encoding value for the one hundred and twelfth normal data may be "CSL55_Right". Therefore, as shown in the figure, the second region RG2 may be selected, and the fifty-fifth column selection line CSL55 included in the selected second region RG2 may be activated. In some embodiments, each of the fourth to seventh CSL blocks CB4 to CB7 may output 16 bits of data. Therefore, a total of 64 bits of the one hundred and twelfth normal data may be output.

[0160] In some embodiments, when the bit width of each channel is implemented as 32 bits, the data of the one hundred and twelfth normal data corresponding to the fourth CSL block CB4 and the fifth CSL block CB5 can be output to the outside through the zeroth I / O pin DQ0, and the data of the one hundred and twelfth normal data corresponding to the sixth CSL block CB6 and the seventh CSL block CB7 can be output to the outside through the first I / O pin DQ1.

[0161] The encoding value for metadata could be "MCSL62 <15> Therefore, the seventh CSL group CS7 having an index (ID) value of "15" of the first region RG1 may be selected, and the sixty-second column selection line CSL62 may be activated in the selected seventh CSL group CS7. In some embodiments, the third CSL block CB3 may output 8-bit one hundred and twelfth metadata.

[0162] In some embodiments, when the bit width of each channel is implemented as 32 bits, 4 bits of the 112th data can be output to the outside through the zeroth I / O pin DQ0, and another 4 bits of the 112th data can be output to the outside through the first I / O pin DQ1.

[0163] The 112th metadata may be output continuously after the 112th normal data is output. Similar to the above, the time required for the 112th normal data and the corresponding 112th metadata to be output to the outside may correspond to "tCCD_s+2*tCK". Therefore, the metadata mode may be effectively executed without reducing performance.

[0164] exist 7A to 14B In the embodiment, metadata for normal data stored in the first region RG1 can be stored in the second region RG2, and metadata for normal data stored in the second region RG2 can be stored in the first region RG1. Accordingly, normal data and metadata can be input / output together. As a result, the metadata mode can be effectively performed.

[0165] exist 7A to 14B , the zeroth word line WL0 is described as being activated. For example, both normal data and corresponding metadata are described as being stored in a memory cell connected to the same zeroth word line WL0. However, this is merely an example, and some embodiments may also be similarly applicable when other word lines are activated. For example, during a write operation, the first word line WL1 may be activated, and the first normal data may be stored in the first region RG1, and the first metadata for the first normal data may be stored in the second region RG2. In addition, the first word line WL1 may be activated, the second normal data may be stored in the second region RG2, and the second metadata for the second normal data may be stored in the first region RG1.

[0166] As described above, normal data and metadata for normal data may correspond to the same word line, so that metadata is not concentrated on a specific word line. For example, metadata may be dispersed and stored on multiple word lines. In some embodiments, compared to the case where metadata is concentrated and stored on a specific word line, intensive access to a specific word line may be prevented, thereby suppressing the row hammer effect.

[0167] 7A to 14B An example of a read operation in which normal data and corresponding metadata are read out together according to some embodiments is shown. However, it should be understood that this is only an example and some embodiments are not limited thereto. For example, some embodiments may also be applied to a write operation in which normal data and corresponding metadata are read out together.

[0168] FIG. 15A to FIG. 15C An example of allocating normal data and metadata to each column select line according to some embodiments is shown. 7A to 14B Similarly, an example is provided where the ratio of normal data to metadata is 8:1.

[0169] exist Fig.15A In the embodiment, column selection lines CSL0 to CSL55 (0 to 55) can be allocated to store normal data. Column selection lines CSL56 to CSL63 (56 to 63) can be allocated to store metadata. Column selection lines allocated for storing metadata can be referred to as meta column selection lines MCSL.

[0170] In some embodiments, column selection lines may be allocated so that the ratio of normal data to metadata is 8: 1. For example, 8 or 8*N (where N is a positive integer) column selection lines may be allocated for normal data, and 1 or 1*N column selection lines may be allocated for metadata.

[0171] For example, the zeroth column selection line CSL0 to the seventh column selection line CSL7 may be allocated for storing normal data, and the fifty-sixth column selection line MCSL56 may be allocated for storing metadata for normal data. For example, the eighth column selection line CSL8 to the fifteenth column selection line CSL15 may be allocated for storing normal data, and the fifty-seventh column selection line MCSL57 may be allocated for storing metadata for normal data. As described above, for example, the forty-eighth column selection line CSL48 to the fifty-fifth column selection line CSL55 may be allocated for storing normal data, and the sixty-second column selection line MCSL62 may be allocated for storing metadata for normal data.

[0172] In some embodiments, each column selection line allocated for storing normal data may be divided into column selection lines corresponding to the first region RG1 (see Figure 7B ) and the column selection line corresponding to the second region RG2 (see Figure 7B ). In addition, each meta column selection line allocated for storing metadata may be divided into a column selection line corresponding to the first region RG1 and a column selection line corresponding to the second region RG2. Metadata corresponding to normal data stored in the column selection line of the first region RG1 may be stored in the second region RG2, and metadata corresponding to normal data stored in the column selection line of the second region RG2 may be stored in the first region RG1.

[0173] For example, refer to Fig. 15B and Fig. 15C , the column selection line corresponding to the first region RG1 may have a low value L, and the column selection line corresponding to the second region RG2 may have a high value H.

[0174] The zeroth to seventh column selection lines CSL0 to CSL7 having a low value L may be allocated to store first normal data, and the fifty-sixth column selection line MCSL56 having a high value H may be allocated to store first metadata corresponding to the first normal data. The zeroth to seventh column selection lines CSL0 to CSL7 having a high value H may be allocated to store second normal data, and the fifty-sixth column selection line MCSL56 having a low value L may be allocated to store second metadata corresponding to the second normal data.

[0175] Similarly, the eighth to fifteenth column selection lines CSL8 to CSL15 having a low value L may be allocated to store third normal data, and the fifty-seventh meta column selection line MCSL57 having a high value H may be allocated to store third metadata corresponding to the third normal data. The eighth to fifteenth column selection lines CSL8 to CSL15 having a high value H may be allocated to store fourth normal data, and the fifty-seventh meta column selection line MCSL57 having a low value L may be allocated to store fourth metadata corresponding to the fourth normal data.

[0176] In this way, the forty-eighth column selection line CSL48 to the fifty-fifth column selection line CSL55 having the low value L may be allocated for storing the thirteenth normal data, and the sixty-second element column selection line MCSL62 having the high value H may be allocated for storing the thirteenth element data corresponding to the thirteenth normal data. The forty-eighth column selection line CSL48 to the fifty-fifth column selection line CSL55 having the high value H may be allocated for storing the fourteenth normal data, and the sixty-second element column selection line MCSL62 having the low value L may be allocated for storing the fourteenth element data corresponding to the fourteenth normal data. The sixty-third element column selection line MCSL63 may be in an empty state to which no data is allocated.

[0177] Fig.16 is a diagram illustrating an example of a memory bank according to some embodiments. Fig.17 According to some embodiments Fig.16 Detailed view of example area "D". Fig.16 The memory bank B1 may correspond to Figures 1 to 4 One of the memory banks described in .

[0178] In the above description, an example has been provided in which the ratio of normal data to metadata is 8:1. However, this is only an example, and some implementations are not limited thereto. According to some embodiments, the ratio of normal data to metadata may be set in various ways.

[0179] exist Fig.16 , the first memory bank B1 may include a first memory bank array BA1, a first row decoder RD1, and a first column decoder CD1. The first memory bank array BA1 may be electrically connected to the first row decoder RD1 and the first column decoder CD1. The first memory bank array BA1 may be connected to a plurality of word lines WL1_0 to WL1_32k-1 through the first row decoder RD1. In addition, the first memory bank array BA1 may be connected to a plurality of CSL subsets L_CS0 to U_CS(i-1), M_CS0, M_CS1, and U_CS0 to U_CS(i-1) through the first column decoder CD1.

[0180] Each of the first and second regions RG1 and RG2 may include a plurality of memory cell mats MAT. Each of the plurality of memory cell mats MAT may be connected to one of the partial word lines connected to the corresponding memory cell mat MAT and one of the partial CSLs connected to the corresponding memory cell mat MAT.

[0181] The first column decoder CD1 may include a plurality of CSL blocks CB and a single ECC block EB. Each of the CSL block CB and the ECC block EB may be configured to select a column select line based on a column address decoded from the first column decoder CD1. For example, a storage cell cluster MAT connected to a column corresponding to the ECC block EB may store a parity bit generated from the ECC block EB.

[0182] In some embodiments, the ECC block EB may be set to correspond to a center column selection line among a plurality of column selection lines included in the first memory bank array BA1. For example, a plurality of CSL blocks CB may be set to be symmetrical with respect to the ECC block EB. Therefore, the column selection lines connected to the plurality of CSL blocks CB may be set to be symmetrical with respect to the column selection lines M_CS0 and M_CS1 connected to the ECC block EB.

[0183] Relative to the ECC block EB, multiple CSL groups L_CS0 to L_CS(i-1) (where i is a positive integer) can be set on the first side L, and multiple CSL groups U_CS0 to U_CS(i-1) (where i is a positive integer) can be set on the second side U.

[0184] In some embodiments, each CSL group CS may include multiple column selection lines. Fig.17 As shown, the zeroth CSL group L_CS0 on the first side may include a plurality of column selection lines CSL0 to CSLp-1 (where p is a positive integer), and the first CSL group L_CS1 on the first side may include a plurality of column selection lines CSL0 to CSLp-1 (where p is a positive integer).

[0185] In some embodiments, Fig.16 The first side L may correspond to Figure 5 The first region RG1, and Fig.16 The second side U may correspond to Figure 5 For example, metadata for normal data stored on the first side L may be stored on the second side U, and metadata for normal data stored on the second side U may be stored on the first side L. According to some embodiments, the values ​​of i, p, and k may be adjusted in various ways, and the ratio of normal data to metadata may also be adjusted in various ways.

[0186] Fig.18 and Fig.19 is a diagram showing an example of a storage module according to some embodiments. Fig.18 and Fig.19 , the memory module 1000A or 1000B may include a plurality of memory devices 101 to 120 and a register clock driver (RCD) 150. The plurality of memory devices 101 to 120 may be disposed on the left and right sides with respect to the register clock driver 150.

[0187] The memory module 1000A or 1000B may be a dual in-line memory module (DIMM) conforming to the JEDEC standard. For example, the memory module 1000A may be a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM0), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM), a small outline DIMM (SO-DIMM), or other memory modules (such as a single in-line memory module (SIMM)).

[0188] Each of the memory devices 101 to 120 may be Figures 1 to 17 2. The memory devices 101 to 120 may be various DRAM devices, such as double data rate synchronous dynamic random access memory (DDR SDRAM) devices, low power double data rate (LPDDR) SDRAM devices, or graphic double data rate synchronous graphic random access memory (GDDR SGRAM) devices. In some embodiments, each of the memory devices 101 to 120 may be an SRAM device, a NAND flash memory device, a NOR flash memory device, an RRAM device, a FRAM device, a PRAM device, a TRAM device, an MRAM device, etc. The types of the memory devices 101 to 120 may be the same or different from each other.

[0189] The number of storage devices 101 to 120 included in the storage module 1000A or 1000B is merely an example, and the number of storage devices 101 to 120 may be determined based on a memory capacity provided to a user and a capacity of each of the storage devices 101 to 120 .

[0190] According to some embodiments, the plurality of memory devices 101 to 120 may share transmission paths of a clock CK, a command CMD, an address signal ADDR, a data signal DQ, and a data strobe signal DQS. Fig.18 shown.

[0191] In some embodiments, register clock driver 150 may be clocked from memory controller 100 (see Figure 1 ) receives a clock CK, a command CMD, an address ADDR, a data signal DQ, and a data strobe signal DQS. The register clock driver 150 may control the memory devices 101 to 120 based on the clock CK, the command CMD, the address ADDR, the data signal DQ, and the data strobe signal DQS. The register clock driver 150 may function as a buffer for the clock CK, the command CMD, the address ADDR, the data signal DQ, and the data strobe signal DQS.

[0192] According to some embodiments, the plurality of memory devices 101 to 120 may share transmission paths of the clock CK, the command CMD, and the address signal ADDR, but may not share transmission paths of the data signal DQ and the data strobe signal DQS. Fig.19 For example, each of the plurality of memory devices 101 to 120 may be independently powered by the memory controller 100 (see Figure 1 ) receives the data signal DQ and the data strobe signal DQS. Therefore, the memory controller 100 can independently set the operation mode of each of the plurality of memory devices 101 to 120.

[0193] In some embodiments, the register clock driver 150 may receive a clock CK, a command CMD, and an address ADDR from the memory controller 100. The register clock driver 150 may function as a buffer for the clock CK, the command CMD, and the address ADDR.

[0194] According to some embodiments, the memory modules may communicate with the memory controller 100 through different sub-channels, as will be described below. Fig. 20 and Fig.21 shown.

[0195] Fig. 20 and Fig.21 are diagrams showing examples of storage modules 1000C and 1000D according to some embodiments, respectively. Fig. 20 In the embodiment, the memory module 1000C may include a plurality of memory devices 101 to 140 disposed on both surfaces thereof. Each of the memory devices 101 to 140 may be Figures 1 to 17 The memory device 200 described in FIG.

[0196] The plurality of memory devices 101 to 120 disposed on the first surface of the memory module 1000C may be divided into left and right parts with respect to the register clock driver 150. The plurality of memory devices 121 to 140 disposed on the second surface of the memory module 1000C may be divided into left and right parts with respect to the SPD 160.

[0197] The memory devices of the memory module 1000C can communicate with the memory controller 100 through two sub-channels. For example, the memory devices 101 to 110 and 121 to 130 disposed on the left side of the memory module 1000C can communicate with the memory controller 100 through the first sub-channel Sub_Channel 1 (see Figure 1 The memory devices 111 to 120 and 131 to 140 disposed on the right side of the memory module 1000C may communicate with the memory controller 100 through the second sub-channel Sub_Channel 2.

[0198] exist Fig.21 In the embodiment, the memory module 1000D may include a plurality of memory devices 101 to 140 disposed on both surfaces thereof. Each of the memory devices 101 to 140 may be Figures 1 to 17 The memory device 200 described in FIG.

[0199] In addition, the plurality of memory devices 101 to 120 disposed on the first surface of the memory module 1000D may be divided into left and right parts with respect to the register clock driver 150. The plurality of memory devices 121 to 140 disposed on the second surface of the memory module 1000D may be divided into left and right parts with respect to the SPD 160.

[0200] The memory devices of the memory module 1000D may communicate with the memory controller 100 through four sub-channels. For example, the memory devices 101, 102, 106, 107, 121, 122, 126, and 127 disposed on the leftmost side of the memory module 1000D may communicate with the memory controller 100 through the first sub-channel Sub_Channel 1. The memory devices 103, 104, 108, 109, 123, 124, 128, and 129 disposed on the left side of the memory module 1000D may communicate with the memory controller 100 through the second sub-channel Sub_Channel2.

[0201] The memory devices 114, 115, 119, 120, 134, 135, 139, and 140 disposed on the rightmost side of the memory module 1000D may communicate with the memory controller 100 through the fourth sub-channel Sub_Channel 4. The memory devices 112, 113, 117, 118, 132, 133, 137, and 138 disposed on the right side of the memory module 1000D may communicate with the memory controller 100 through the third sub-channel Sub_Channel3.

[0202] A portion of the memory devices 105 , 110 , 111 , 116 , 125 , 130 , 131 , and 136 may be allocated as a chip for an ECC operation or may communicate with the memory controller 100 through the second subchannel or the third subchannel.

[0203] As described above, a storage device according to example embodiments may effectively support a metadata mode.

[0204] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of possible protection. In a single embodiment, specific features described in the present disclosure in the context of independent embodiments can also be implemented in combination. On the contrary, various features described in the context of a single embodiment can also be implemented independently in multiple embodiments, or in appropriate sub-combinations. In addition, although the above-mentioned features may be described as working in certain combinations, in some cases, one or more features from a combination can be deleted from the combination, and the combination can point to a sub-combination or a variant of a sub-combination.< / j>

Claims

1. A storage device, comprising: A memory array including a plurality of memory cells; A row decoder connected to the memory bank array via a plurality of word lines; as well as A column decoder is connected to the memory bank array via a plurality of column select lines CSL, Wherein, the memory bank array comprises: Region 1; and a second region, different from said first region, and The first metadata of the first normal data stored in the first area is stored in the second area, and the second metadata of the second normal data stored in the second area is stored in the first area.

2. The memory device according to claim 1, in, The first region corresponds to a first column selection line among the plurality of column selection lines, wherein the second region corresponds to a second column selection line among the plurality of column selection lines, and The second column selection line is different from the first column selection line.

3. The memory device according to claim 1, wherein: The first region and the second region are commonly connected to the plurality of word lines.

4. The memory device according to claim 1, in, The first normal data and the first metadata are configured to be output through a first data pin, and The second normal data and the second metadata are configured to be output through a second data pin different from the first data pin.

5. The memory device according to claim 4, in, The first normal data and the first metadata are configured to be sequentially output through the first data pin, and The second normal data and the second metadata are configured to be output sequentially through the second data pin.

6. The memory device according to claim 1, in, The first area includes a plurality of first storage unit clusters, The second area includes a plurality of second storage unit clusters. Wherein, each of the plurality of first storage unit clusters comprises: A first normal data area is configured to store the first normal data; and a first metadata area configured to store the second metadata of the second normal data, and Wherein, each of the plurality of second storage unit clusters comprises: A second normal data area is configured to store the second normal data; and The second metadata area is configured to store the first metadata of the first normal data.

7. The memory device according to claim 6, in, The column decoder comprises: a plurality of CSL blocks connected to the plurality of column selection lines; and An error correction code ECC block is set at the center of the plurality of CSL blocks, and wherein the plurality of first storage cell clusters corresponding to the first area and the plurality of second storage cell clusters corresponding to the second area are distinguished based on the ECC block.

8. The memory device according to claim 6, in, Each of the plurality of first storage cell clusters included in the first region corresponds to two CSL groups, wherein each of the plurality of second storage cell clusters included in the second region corresponds to two CSL groups, Wherein, each of the two CSL groups corresponding to the plurality of first storage unit clusters includes: A first column selection line is allocated for storing the first normal data; and a second column selection line allocated for storing the second metadata, and wherein each of the two CSL groups corresponding to the plurality of second storage cell clusters comprises: A third column selection line is allocated for storing the second normal data; and A fourth column selection line is allocated for storing the first metadata.

9. The memory device according to claim 1, in, The first normal data and the first metadata are configured to be output through a first data pin and a second data pin, respectively, and The second normal data and the second metadata are configured to be output through a third data pin and a fourth data pin respectively.

10. A storage device comprising: A memory bank array includes a first region and a second region; a row decoder connected to the first region and the second region through a plurality of word lines, the plurality of word lines being arranged to cross the first region and the second region; as well as a column decoder connected to the first region through a plurality of first column selection lines CSL and connected to the second region through a plurality of second column selection lines, wherein the plurality of first column selection lines are arranged in the first region and the plurality of second column selection lines are arranged in the second region, The first metadata of the first normal data stored in the first area is stored in the second area, and the second metadata of the second normal data stored in the second area is stored in the first area.

11. The memory device according to claim 10, in, The column decoder comprises: a first CSL block connected to a first CSL group and a second CSL group disposed in the first area; and a second CSL block connected to a third CSL group and a fourth CSL group disposed in the second area, The first CSL group disposed in the first area includes: a first plurality of column selection lines allocated for storing the first normal data; and a second plurality of column selection lines allocated for storing the second metadata. The second CSL group disposed in the first area includes: a third plurality of column selection lines allocated for storing the first normal data; and a fourth plurality of column selection lines allocated for storing the second metadata. The third CSL group disposed in the second region includes: a fifth plurality of column selection lines allocated for storing the second normal data; and a sixth plurality of column selection lines allocated for storing the first metadata, and The fourth CSL group arranged in the second area includes: a seventh plurality of column selection lines allocated for storing the second normal data; and an eighth plurality of column selection lines allocated for storing the first metadata.

12. The memory device according to claim 11, wherein: The first CSL block is configured to simultaneously activate a single selected column selection line among the first plurality of column selection lines and a single selected column selection line among the third plurality of column selection lines in response to a column address for the first normal data.

13. The memory device according to claim 12, wherein: The second CSL block is configured to activate a single selected column selection line among the sixth plurality of column selection lines and the eighth plurality of column selection lines in response to a column address for the first metadata.

14. The memory device according to claim 12, in, The column decoder further includes an error correction code (ECC) block disposed between the first CSL block and the second CSL block, and The first area and the second area are distinguished along a column direction line connected to the ECC block.

15. The memory device according to claim 10, in, The first normal data and the first metadata are configured to be sequentially output through a first data pin, The second normal data and the second metadata are configured to be sequentially output through the second data pin, and Wherein, the second data pin is different from the first data pin.

16. A storage module comprising a plurality of storage devices, in, Each of the plurality of storage devices comprises: A memory array including a plurality of memory cells; a row decoder connected to the memory bank array via a plurality of word lines; and A column decoder is connected to the memory array through a plurality of column selection lines CSL, wherein the memory array comprises: Region 1; and a second region, different from said first region, and The first metadata of the first normal data stored in the first area is stored in the second area, and the second metadata of the second normal data stored in the second area is stored in the first area.

17. The storage module according to claim 16, in, The first region corresponds to a first column selection line among the plurality of column selection lines, The second region corresponds to a second column selection line among the plurality of column selection lines. wherein the second column selection line is different from the first column selection line, and The first region and the second region are commonly connected to the plurality of word lines.

18. The semiconductor module according to claim 16, in, The first area includes a plurality of first storage unit clusters, The second area includes a plurality of second storage unit clusters. Wherein, each of the plurality of first storage unit clusters comprises: A first normal data area is configured to store the first normal data; and a first metadata area configured to store the second metadata of the second normal data, and Wherein, each of the plurality of second storage unit clusters comprises: A second normal data area is configured to store the second normal data; and The second metadata area is configured to store the first metadata of the first normal data.

19. The semiconductor module according to claim 18, in, The column decoder comprises: a plurality of CSL blocks connected to the plurality of column selection lines; and An error correction code ECC block is set at the center of the plurality of CSL blocks, and wherein the plurality of first storage cell clusters corresponding to the first area and the plurality of second storage cell clusters corresponding to the second area are distinguished based on the ECC block.

20. The storage module according to claim 16, in, The first normal data and the first metadata are configured to be sequentially output through a first data pin, The second normal data and the second metadata are configured to be sequentially output through the second data pin, and Wherein, the second data pin is different from the first data pin.

Images