Memory device

Abstract

The invention relates to a memory device. A memory device that batch initializes memory cell data by specifying initialization data, or a memory device that batch initializes memory cell data by partially masking an initialization region is provided. There is provided a memory device including a control circuit receiving an initialization mode signal transmitted from an initialization control circuit and generating an internal clock and a write control signal, an IO (input / output) input circuit, and a selection circuit, an IO (Input / Output) input circuit applies a low level to a true side or a complementary side of a bit line according to initialization data transmitted from an initialization control circuit, and a selection circuit simultaneously selects a plurality of word lines and a plurality of bit lines and simultaneously writes the initialization data into a memory cell connected to the selected word lines and bit lines.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-139535 filed on August 30, 2023, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to memory devices, such as SRAM (Static Random Access Memory). Background Art

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2023-88805

[0006] A technology for initializing data of a memory cell has been developed. Patent document 1 discloses a technology for initializing data of a memory cell relatively quickly while suppressing an increase in area. A control circuit of a semiconductor device turns off a first transistor, selects a plurality of word lines, turns off a precharge circuit, turns on a write column switch, and turns off a read column switch based on a reset signal set to a high level. By setting a first bit line to a low level and a second bit line to a high level by a write circuit, a plurality of memory cells are initialized. Summary of the invention

[0007] The initialization described in patent document 1 shortens the initialization time by initializing all memory cell areas at the same time. However, because the data at the time of initialization is fixed inside the SRAM, it can only be initialized to 0 or 1. In addition, only all memory cell areas can be initialized. Therefore, there is a problem that it is impossible to batch initialize all memory cells in a memory having an ECC (error detection and correction) memory or an area where important data is retained.

[0008] Therefore, an object of the present disclosure is to provide a memory device that initializes all memory cell data by designating initialization data, or a memory device that initializes all memory cell data by partially shielding an initialization area.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0010] According to one embodiment, a memory device initializes any region with any data.

[0011] According to one embodiment, a memory device for initializing all memory cell data by designating initialization data, or a memory device for initializing all memory cell data by partially shielding an initialization area may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic diagram showing the status of bulk initialization of a memory device.

[0013] Figure 2 is a schematic diagram showing an example of a state in which the Hamming code of the memory device is masked.

[0014] Figure 3 is a diagram showing still another example of a state in which the Hamming code of the memory device is masked.

[0015] Figure 4 is a schematic diagram showing a case where initialization in the word direction of a memory device is restricted.

[0016] Figure 5 is a schematic diagram showing a case where initialization in the bit direction of a memory device is restricted.

[0017] Figure 6 is a schematic diagram of a circuit of a memory device according to an embodiment.

[0018] Figure 7 is a diagram with additional circuitry for reducing a voltage level in a word line driver of a memory device according to an embodiment.

[0019] Figure 8 is a timing diagram of a memory device according to an embodiment.

[0020] Fig. 9 is a block diagram with an ECC circuit attached to a memory device according to an embodiment. DETAILED DESCRIPTION

[0021] For the purpose of clear explanation, the following description and drawings are appropriately omitted and simplified. Each element described in the drawings is a functional module that performs various processes, which can be configured by hardware (such as a CPU (central processing unit), memory and other circuits), and can be implemented by software (such as a program loaded into the memory). Therefore, these functional modules can be implemented by hardware, software operating on hardware, or a combination of the two. In the drawings, the same elements are identified with the same reference numerals, and their repeated descriptions are omitted when necessary.

[0022] (Description of Memory Device According to Embodiment)

[0023] Figure 1is a schematic diagram showing the status of bulk initialization of a memory device. Figure 2 is a schematic diagram showing an example of a state in which the Hamming code of the memory is masked. Figure 3 is a diagram showing still another example of a state in which the Hamming code of the memory is masked. Figure 4 is a schematic diagram showing a case where initialization in the word direction of a memory device is restricted. Figure 5 is a schematic diagram showing a case where initialization in the bit direction of a memory device is restricted. Figure 6 is a schematic diagram of a circuit of a memory device according to an embodiment. The memory device according to an embodiment will refer to Figures 1 to 6 The memory device 600 is, for example, a SRAM (Static Random Access Memory).

[0024] like Figure 1 As shown in Figure 1, it is possible to batch initialize SRAM macros without ECC. The memory areas are all set to 0. On the other hand, for example, Figure 2 and Figure 3 As shown in Figure 1, it is expected that the SARM macros for ECC applications are not all 0. From the perspective of functional safety, Figure 2 As shown, it is expected to place a value of 1 in the Hamming code of the adjacent bit line. In addition, as Figure 3 As shown, it is expected to place a value of 1 in the Hamming code with a different encoding.

[0025] In addition, if Figure 4 As shown, there may be situations where it is desirable to restrict initialization in the word line direction. Figure 5 As shown, there may be a situation where it is desired to restrict the initialization in the bit line direction. The existing disclosed memory device is a memory device that specifies the initialization data of the memory cell data and initializes the memory cell data in batches, or a memory device that shields part of the initialization area of ​​the memory cell data and initializes the memory cell data in batches, and these states can be implemented in batches.

[0026] like Figure 6 As shown, the memory device 600 according to the embodiment includes an initialization control circuit (not shown), a write / read internal clock generation circuit 601, a write control circuit 602, an internal clock generation circuit 603, a row address decoder and a word multiplex simultaneous selection circuit 604 during initialization, a column address decoder and a column switch multiplex simultaneous selection circuit 605 during initialization, an internal clock generation circuit 607, a bit write mask circuit 608, and a write circuit 609.

[0027] The initialization control circuit sends an initialization mode signal that converts the memory device to an initialization mode. The initialization mode is a state in which initialization is performed. In addition, the initialization control circuit sends initialization data of 0 or 1 to be written to the memory device 600. The initialization data is data for initializing the memory device. In addition, the initialization control circuit can send an initialization address area mask signal that masks the area to be initialized. In addition, the initialization control circuit can send an initialization data mask signal that masks the data to be initialized.

[0028] The write control circuit 602, the internal clock generation circuit 603, and the internal clock generation circuit 607 are collectively referred to as a control circuit. The internal clock generation circuit 603 receives a clock signal and an initialization mode signal from the write / read internal clock generation circuit 601 to generate an internal clock for initialization. The internal clock generation circuit 607 receives a clock signal and an initialization mode signal from the write / read internal clock generation circuit 601 to generate an internal clock for initialization. The write control circuit 602 generates a write control signal that enables an enable signal of the write circuit during initialization to enable writing.

[0029] The row address decoder and word multiplexing simultaneous selection circuit 604 during initialization is also referred to as a word line selection circuit 604. The word line selection circuit 604 has the function of a normal row address decoder. In addition, the word line selection circuit 604 can select a word line with arbitrary changes by capturing the initialization region information input to limit the initialization of the word line direction.

[0030] like Figure 6 As shown in the diagram in, for example, when the initialization mode signal INITM is 1 and the address input A is 000, all word lines are selected. When the initialization mode signal is 1 and the address input A is 001, the even word lines are selected. When the address input A is 010, the odd word lines are selected. When the address input A is 011, the lower half of the word lines are selected. When the address input A is 100, the upper half of the word lines are selected. In this way, multiple word lines can be selected at the same time during initialization.

[0031] The column address decoder and the initialization time column switch multiplex synchronous selection circuit 605 is also called the bit line selection circuit 605. The bit line selection circuit 605 is equipped with the function of the column address decoder. In addition, the bit line selection circuit 605 can capture the initialization area information input and select the column switch with arbitrary changes, thereby limiting the initialization in the bit line direction column by column.

[0032] The word line selection circuit 604 and the bit line selection circuit 605 are collectively referred to as a selection circuit. In this way, the selection circuit masks the initialized portion of the address region based on the initialized address region masking signal input from the initialization control circuit. The word line selection circuit 604 is connected to the word driver segment 700. The bit line selection circuit 605 is connected to the column selector and the precharge segment 610.

[0033] The bit write mask circuit 608 has the function of disabling data input and limiting input in the bit line direction during normal time. Normal time refers to the time when the memory device 600 is used as a memory device. In addition, the bit write mask circuit 608 also has the function of disabling input data and limiting input in the bit line direction during initialization.

[0034] The write circuit 609 has a function of inputting 0 or 1 data during normal time. In addition, the write circuit 609 has a function of inputting 0 or 1 data during initialization. The bit write mask circuit 608 and the write circuit 609 are collectively referred to as an IO input circuit. In this way, the IO input circuit masks part of the IO input of the memory cell according to the initialization data mask signal input from the initialization control circuit.

[0035] The internal clock generation circuit 607 and the IO input circuit are collectively referred to as the write buffer and sense amplifier segment 606. The write buffer and sense amplifier segment 606 is connected to the column selector and precharge segment 610. The column selector and precharge segment 610 are equipped with a BT (Bit True) line and a BB (Bit Bar) line connected to the memory cell. During normal time, a high level is applied to the true side and the complement side of the bit line. Initialization is performed by applying a low level to the true side or the complement side of the bit line.

[0036] With the above configuration, it is possible to provide a memory device that initializes all memory cell data by designating initialization data, or a device that masks part of an initialization area of ​​memory cell data and initializes all memory cell data.

[0037] (Description of Word Driver Segment of Memory Device According to Embodiment)

[0038] Figure 7 is a schematic diagram of a circuit added to reduce the voltage level of a word line driver of a memory device according to an embodiment. Figure 7 , a word driver segment of a memory device according to an embodiment will be described. The word driver segment 700 is a circuit that drives a word line.

[0039] like Figure 7As shown, the word driver segment 700 includes a wiring 701 connected to a word line selection circuit 604 , a word line driver circuit 702 , and a level lowering circuit 703 .

[0040] The wiring 701 is connected to a plurality of word line driver circuits 702. The wiring 701 raises a plurality of word lines in response to a signal generated by a word line selection circuit 604 during initialization.

[0041] A plurality of word line drive circuits 702 are connected to a level reduction circuit 703. The level reduction circuit 703 is a complementary transistor equipped with an N-channel transistor and a P-channel transistor. The level reduction circuit 703 is connected to a gate having a reset write signal, and the output is connected to a power line of the word driver circuit. The level reduction circuit 703 allows flow during the initialization restriction period in the bit line direction, so it turns off the P-channel transistor and turns on the N-channel transistor during the initialization period. Therefore, the level reduction circuit 703 can reduce the high level potential of the word line when it rises. Therefore, the level reduction circuit 703 suppresses the peak current and the charge / discharge current, thereby reducing the power consumption of the memory device 600.

[0042] (Description of Timing Diagram of Memory Device According to Embodiment)

[0043] Figure 8 is a timing diagram of a memory device according to an embodiment. Figure 6 and Figure 8 A timing diagram of a memory device according to an embodiment is described.

[0044] like Figure 6 and Figure 8 As shown, INITM is an initialization mode signal. When the initialization mode signal becomes high, initialization is performed. When the initialization mode signal INITM becomes high, the write control signal WTRSTE of the write control circuit 602 becomes high. In addition, when the initialization mode signal INITM becomes high, the internal clock CPIO of the internal clock generation circuit 607 becomes high.

[0045] Then, according to the initialization data input DIN (0010), LLHL data is input to the BT (Bit True) line. According to the initialization data input DIN (0010), HHLH data is input to the BB (Bit Bar) line.

[0046] In response to the initialization mode signal, a plurality of word lines are selected in a high state, and the memory cells input (0010) data according to the initialization data input DIN (0010).

[0047] With the above configuration, a plurality of word lines are selected, and the selected initialization data is input to the memory cells.

[0048] (Description of Memory Device Having Additional ECC (Error Detection and Correction) Circuit According to Embodiment)

[0049] Fig. 9 is a block diagram of a memory device with additional ECC circuitry according to an embodiment. Fig. 9 , a memory device with an additional ECC circuit according to an embodiment will be described. The ECC circuit is an error detection / correction circuit.

[0050] The memory device 900 with an additional ECC circuit includes a system control circuit 901 , an ECC circuit 902 , and a memory device 903 .

[0051] The MBIST (Memory Built-In Self-Test) circuit 904 is a test circuit that tests the memory before shipment. For example, before the memory device 900 with an additional ECC circuit is shipped, it outputs initialization data MDIN during initialization.

[0052] The system control circuit 901 includes an initialization control circuit. In a memory test after shipment, the system control circuit 901 outputs an initialization mode signal INITM, initialization data CDIN, an initialization address area mask signal CA, and an initialization data mask signal CBWN.

[0053] The ECC circuit 902 is connected to the system control circuit 901. Furthermore, the ECC circuit is connected to the memory device 903. That is, the ECC circuit 902 is arranged between the system control circuit 901 and the memory device 903. The ECC circuit receives initialization data and transmits an error detection / correction code EDIN.

[0054] The memory device 903 is, for example, an SRAM macro. In a memory test after shipment, the memory device 903 captures initialization data including a Hamming code output from the ECC during initialization, and is batch-initialized according to the data DIN.

[0055] The initialization flow of the memory device 900 with an additional ECC circuit is as follows. First, the system control circuit 901 outputs the initialization data including the bit designation signal to the ECC circuit. In addition, the system control circuit 901 outputs the address signal designating the initialization area to the memory device 903. Next, the ECC circuit 902 receives the initialization data and generates a Hamming code. Next, the memory device 903 receives the initialization data including the Hamming code from the ECC circuit 902 and receives the initialization area designation address signal from the system control circuit 901. Next, the system control circuit 901 outputs the initialization mode signal to the memory device 903. Finally, the memory device 903 performs the initialization processing of the designated area.

[0056] With the above configuration, since the ECC circuit is attached, the memory device can process initialization with initialization data including a Hamming code.

[0057] Although the invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited to the described embodiments, and it goes without saying that various modifications can be made without departing from the gist of the present invention.

Claims

1. A memory device, comprising: a control circuit configured to receive an initialization mode signal transmitted from the initialization control circuit and generate an internal clock and a write control signal; an IO input circuit configured to apply a low level to a true side or a complement side of a bit line according to initialization data transmitted from the initialization control circuit; as well as The selection circuit is configured to simultaneously select a plurality of word lines and a plurality of bit lines and simultaneously write the initialization data into memory cells connected to the selected word lines and bit lines.

2. The memory device according to claim 1 , wherein the initialization control circuit generates an initialization address region mask signal that masks the region to be initialized, and the selection circuit masks the initialization of a portion of the address region based on the initialization address region mask signal input from the initialization control circuit.

3. The memory device according to claim 1 , wherein the initialization control circuit generates an initialization data mask signal that masks the data to be initialized, and the IO input circuit masks a portion of the IO input of the memory cell according to the initialization data mask signal output from the initialization control circuit. 4 . The memory device according to claim 1 , wherein a word driver segment connected to the selection circuit lowers a high level potential of the selected plurality of word lines.

5. The memory device according to claim 1, further comprising an error detection / correction circuit placed between the initialization control circuit and the memory device, the error detection / correction circuit capturing the initialization mode signal, the initialization data, the initialization data mask signal for masking the data to be initialized, the initialization address area mask signal for masking the area to be initialized, and the error detection / correction code emitted from the error detection / correction circuit, and batch-initializing the data of the memory cells.

6. The memory device of claim 1, wherein the memory device is a SRAM macro.

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