Management of program disturb in memory devices

Abstract

Exemplary memory devices, memory systems, and methods for reducing program disturb in NAND flash memories are disclosed. An exemplary method includes applying, at a first time and during a channel preparation period of a program operation of a first memory cell in a memory cell array, a first voltage to a first word line coupled to the first memory cell. A second voltage is applied to the first word line at a second time after the first time and during the channel preparation period, where the second voltage is lower than the first voltage. A program voltage is applied to the first word line after the channel preparation period and during a program operation of the first memory cell.

Description

Technical Field

[0001] The present disclosure relates to a memory device, a memory system, and a method for reducing program disturb in a flash memory. Background Art

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations can be performed by flash memory, such as programming (writing) operations and erasing operations, thereby changing the threshold voltage of each memory cell to a corresponding level. For NAND flash memory, an erase operation can be performed at the block level, a programming operation can be performed at the page level, and a read operation can be performed at the page level. Summary of the invention

[0003] The present disclosure relates to a memory device, a memory system, and a method for reducing program disturbance in a NAND flash memory. An exemplary method includes applying a first voltage to a first word line coupled to a first memory cell in a memory cell array at a first time and during a channel preparation period of a programming operation of the first memory cell. Applying a second voltage to the first word line at a second time after the first time and during the channel preparation period, wherein the second voltage is lower than the first voltage. Applying a programming voltage to the first word line after the channel preparation period and during the programming operation of the first memory cell.

[0004] Although generally described as computer-implemented software embodied on a tangible medium that processes and transforms corresponding data, some or all of these aspects may be computer-implemented methods or further incorporated into corresponding systems or other devices to perform this described function. Details of these and other aspects and embodiments of the present disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages will become apparent from these descriptions and drawings, as well as from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 An example of a schematic diagram of a memory device including peripheral circuits according to some aspects of the present disclosure is shown.

[0006] Figure 2 An example of a side view of a cross section of a memory cell array including NAND memory strings according to some aspects of the present disclosure is shown.

[0007] Figure 3 Some exemplary peripheral circuits according to some aspects of the present disclosure are shown.

[0008] Figure 4An exemplary memory cell stack including multiple decks of memory cells according to some aspects of the present disclosure is shown.

[0009] Figure 5A According to some aspects of the present disclosure, Figure 4 During programming of the memory cells in stack 2 Figure 4 Example of voltages of components in a memory cell stack.

[0010] Figure 5B According to some aspects of the present disclosure, Figure 4 During programming of the memory cells in stack 2 Figure 4 Another example of a voltage of a component in a memory cell stack in .

[0011] Figure 5C According to some aspects of the present disclosure, Figure 4 During programming of the memory cells in stack 2 Figure 4 Another example of a voltage of a component in a memory cell stack in .

[0012] Figure 6 According to some aspects of the present disclosure Figure 4 00143] An exemplary memory cell stack in which stack 1 has a memory cell selected for programming.

[0013] Fig. 7A According to some aspects of the present disclosure, Figure 6 During programming of the memory cells in stack 1 Figure 6 Example of voltages of components in a memory cell stack.

[0014] Figure 7B According to some aspects of the present disclosure, Figure 6 During programming of the memory cells in stack 1 Figure 6 Another example of a voltage of a component in a memory cell stack.

[0015] Figure 7C According to some aspects of the present disclosure, Figure 6 During programming of the memory cells in stack 1 Figure 6 Another example of a voltage of a component in a memory cell stack.

[0016] Figure 8 According to some aspects of the present disclosure Figure 4 0048] An exemplary memory cell stack in which stack 0 has memory cells selected for programming.

[0017] Fig. 9AAccording to some aspects of the present disclosure, Figure 8 During programming of the memory cells in stack 0 Figure 8 Example of voltages of components in a memory cell stack.

[0018] Fig. 9B According to some aspects of the present disclosure, Figure 8 During programming of the memory cells in stack 0 Figure 8 Another example of a voltage of a component in a memory cell stack.

[0019] Fig. 9C According to some aspects of the present disclosure, Figure 8 During programming of the memory cells in stack 0 Figure 8 Another example of a voltage of a component in a memory cell stack.

[0020] Fig. 10A According to some aspects of the present disclosure, Figure 4 During fine programming of the memory cells in stack 2 Figure 4 Example of voltages of components in a memory cell stack.

[0021] Fig. 10B According to some aspects of the present disclosure, Figure 4 During fine programming of the memory cells in stack 2 Figure 4 Another example of a voltage of a component in a memory cell stack.

[0022] Fig. 10C According to some aspects of the present disclosure, Figure 4 During fine programming of the memory cells in stack 2 Figure 4 Another example of a voltage of a component in a memory cell stack.

[0023] Fig.11A According to some aspects of the present disclosure, Figure 4 During fine programming of the memory cells in stack 1 Figure 4 Example of voltages of components in a memory cell stack.

[0024] Fig. 11B According to some aspects of the present disclosure, Figure 4 During fine programming of the memory cells in stack 1 Figure 4 Another example of a voltage of a component in a memory cell stack.

[0025] Fig. 11C According to some aspects of the present disclosure, Figure 4 During fine programming of the memory cells in stack 1 Figure 4 Another example of a voltage of a component in a memory cell stack.

[0026] Fig. 12A According to some aspects of the present disclosure, Figure 4 During fine programming of the memory cells in stack 0 Figure 4 Example of voltages of components in a memory cell stack.

[0027] Fig. 12B According to some aspects of the present disclosure, Figure 4 During fine programming of the memory cells in stack 0 Figure 4 Another example of voltages of components in an exemplary memory cell stack.

[0028] Fig. 12C According to some aspects of the present disclosure, Figure 4 During fine programming of the memory cells in stack 0 Figure 4 Another example of voltages of components in an exemplary memory cell stack.

[0029] Fig.13 According to some aspects of the present disclosure Figure 4 An exemplary memory cell stack in which, during a process of programming memory cells in the memory cell stack from the bottom to the top of the memory cell stack, stack 0 has the memory cells selected for programming.

[0030] Fig.14A FIG. 2 shows a memory cell in stack 0 during programming according to some aspects of the present disclosure. Fig.13 Example of voltages of components in a memory cell stack.

[0031] Fig. 14B FIG. 2 shows a memory cell in stack 0 during programming according to some aspects of the present disclosure. Fig.13 Another example of a voltage of a component in a memory cell stack.

[0032] Fig. 14C FIG. 2 shows a memory cell in stack 0 during programming according to some aspects of the present disclosure. Fig.13 Another example of a voltage of a component in a memory cell stack.

[0033] Fig.15 According to some aspects of the present disclosure Figure 4 00143] An exemplary memory cell stack in which stack 1 has a memory cell selected for programming during a process of programming memory cells in the memory cell stack from the bottom to the top of the memory cell stack.

[0034] Fig.16A 1 shows a memory cell in stack 1 during programming according to some aspects of the present disclosure. Fig.15 Example of voltages of components in a memory cell stack.

[0035] Fig. 16B 1 shows a memory cell in stack 1 during programming according to some aspects of the present disclosure. Fig.15 Another example of a voltage of a component in a memory cell stack.

[0036] Fig. 16C 1 shows a memory cell in stack 1 during programming according to some aspects of the present disclosure. Fig.15 Another example of a voltage of a component in a memory cell stack.

[0037] Fig.17 An example of a flow chart of a method for reducing program disturb in a memory device according to some aspects of the present disclosure is shown.

[0038] Fig.18 A block diagram of an exemplary system having a memory device according to some aspects of the present disclosure is shown.

[0039] Fig.19A A diagram of a memory card having a memory device according to some aspects of the present disclosure is shown.

[0040] Fig.19B A diagram of a solid state drive (SSD) having a memory device according to some aspects of the present disclosure is shown.

[0041] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0042] The present specification relates to memory devices, memory systems, methods, and media for reducing program disturb in NAND flash memory. In some cases, program disturb may be caused by hot carrier injection (HCI), in which electrons are injected into memory cells that are not selected for programming but are coupled to a word line (WLn) connected to a memory cell selected for programming. HCI may increase the threshold voltage of the unselected memory cells, thereby causing program disturb. HCI may be due to a large channel potential difference between a memory cell coupled to WLn and a memory cell coupled to a preceding WLn-1 that is immediately adjacent in the programming order of the word lines when a programming voltage is applied to WLn,

[0043] In some cases, the HCI problem described above exists during the channel preparation period before the period of programming the memory cell, especially for NAND flash memory with a reduced gate length to gate spacing ratio (Lg / Ls) or an increased number of programming pulses. In order to reduce HCI-induced program disturbance during the channel preparation period, a bias voltage may be applied to a specific word line during the channel preparation period without affecting the channel potential during the programming period.

[0044] Figure 1 An example of a schematic circuit diagram of a memory device 100 including peripheral circuits according to some aspects of the present disclosure is shown. The memory device 100 may include a memory cell array 101 and a peripheral circuit 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array, wherein the memory cells 106 are provided in the form of an array of NAND memory strings 108, each NAND memory string 108 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and arranged in a vertical stack. Each memory cell 106 is capable of holding a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 106. Each memory cell 106 may be a "floating gate" type memory cell including a floating gate transistor, or may be a "charge trap" type memory cell including a charge trap transistor.

[0045] In some embodiments, each memory cell 106 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first range of voltages, and a second memory state "1" may correspond to a second range of voltages. In some embodiments, each memory cell 106 is a multi-level cell (MLC) capable of storing more than one bit of data in four or more memory states. For example, an MLC is capable of storing two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to present a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erased state to present one of three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used as an erased state.

[0046] like Figure 1As shown in , each NAND memory string 108 may include a source select gate (SSG) 110 located at its source end and a drain select gate (DSG) 112 located at its drain end. The SSG 110 and the DSG 112 may be configured to activate the selected NAND memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 108 in the same block 104 are coupled by the same source line (SL) 114 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 108 in the same block 104 have an array common source (ACS). According to some embodiments, the DSG 112 of each NAND memory string 108 is coupled to a corresponding bit line 116, and data can be read from or written to the corresponding bit line 116 via an output bus (not shown). In some embodiments, each NAND memory string 108 is configured to be selected or deselected by applying a selection voltage or a deselection voltage (e.g., 0V) to the corresponding DSG 112 via one or more DSG lines 113 and / or by applying a selection voltage or a deselection voltage (e.g., 0V) to the corresponding SSG 110 via one or more SSG lines 115.

[0047] like Figure 1 As shown in , the NAND memory strings 108 can be organized into a plurality of blocks 104, each of which can have a common source line 114 (e.g., coupled to the ACS). In some embodiments, each block 104 is the basic data unit of an erase operation, i.e., all memory cells 106 on the same block 104 are erased at the same time. To erase the memory cells 106 in a selected block 104, the source lines 114 coupled to the selected block 104 and the unselected blocks 104 in the same plane as the selected block 104 can be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20V or higher). In some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at the level with any appropriate number of blocks or appropriate fractions of blocks. The memory cells 106 of adjacent NAND memory strings can be coupled by word lines 118, which select which row of memory cells 106 are affected by read and program operations. Each word line 118 may include a plurality of control gates (gate electrodes) at each memory cell 106 and a gate line coupling the control gates. Figure 1 The exemplary word lines shown in illustrative figures include dummy WLs, WL1 , WL2 , WL3 , WL4 , and WL5 located between one or more DSG lines 113 and one or more SSG lines 115 .

[0048] Figure 21 shows an example of a side view of a cross section of a memory cell array 101 including NAND memory strings 108 according to some aspects of the present disclosure. Figure 2 As shown in FIG, NAND memory strings 108 can extend vertically through a memory stack 204 above a substrate 202. The substrate 202 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0049] The memory stack 204 may include alternating gate conductive layers 206 and gate-to-gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate-to-gate dielectric layers 208 in the memory stack 204 may determine the number of memory cells 106 in the memory cell array 101. The gate conductive layers 206 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate, DSG 112, or SSG 110 surrounding the memory cell 106, and may extend laterally as a DSG line 113 at the top of the memory stack 204, as an SSG line 115 at the bottom of the memory stack 204, or as a word line 118 between the DSG line 113 and the SSG line 115.

[0050] The peripheral circuit 102 may be coupled to the memory cell array 101 via the bit line 116, the word line 118, the source line 114, the SSG line 115, and the DSG line 113. The peripheral circuit 102 may include any suitable analog, digital, and mixed signal circuits to facilitate the operation of the memory cell array 101 by applying a voltage signal and / or a current signal to each target memory cell in the memory cells 106 via the bit line 116, the word line 118, the source line 114, the SSG line 115, and the DSG line 113 and sensing the voltage signal and / or the current signal from each target memory cell. The peripheral circuit 102 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 3 Some exemplary peripheral circuits according to some aspects of the present disclosure are shown. The exemplary peripheral circuits include page buffers / sense amplifiers 304, column decoders / bit line drivers 306, row decoders / word line drivers 308, voltage generators 310, control logic 312, registers 314, interfaces 316, and data buses. In some examples, the peripheral circuits may also include Figure 3 Other peripheral circuits not shown.

[0051] The page buffer / sense amplifier 304 may be configured to read data from the memory cell array 101 and program (write) data to the memory cell array 101 according to a control signal from the control logic 312. In one example, the page buffer / sense amplifier 304 may store a page of programming data (write data) to be programmed into one page 120 of the memory cell array 101. In another example, the page buffer / sense amplifier 304 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 106 coupled to the selected word line 118. In yet another example, the page buffer / sense amplifier 304 may also sense a low-power signal representing a data bit stored in the memory cell 106 from the bit line 116 in a read operation and amplify the small voltage swing to a recognizable logic level. The column decoder / bit line driver 306 may be configured to be controlled by the control logic 312 and select one or more NAND memory strings 108 by applying a bit line voltage generated by the voltage generator 310.

[0052] The row decoder / word line driver 308 may be configured to be controlled by the control logic 312 and to select / deselect the block 104 of the memory cell array 101 and to select / deselect the word line 118 of the block 104. The row decoder / word line driver 308 may be further configured to drive the word line 118 using the word line voltage generated by the voltage generator 310. In some embodiments, the row decoder / word line driver 308 may also select / deselect and drive the SSG line 115 and the DSG line 113. As described in detail below, the row decoder / word line driver 308 is configured to apply a read voltage to the selected word line 118 in a read operation for the memory cell 106 coupled to the selected word line 118.

[0053] The voltage generator 310 may be configured to be controlled by the control logic 312 and generate word line voltages (eg, read voltages, program voltages, pass voltages, local voltages, verification voltages, etc.), bit line voltages, and source line voltages to be provided to the memory cell array 101 .

[0054] The control logic 312 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The register 314 may be coupled to the control logic 312 and include a status register, a command register, and an address register to store status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. As described in detail below, the status register in the register 314 may include one or more registers configured to store open block information (e.g., having an ADSV list) indicating (one or more) open blocks among all blocks 104 in the memory cell array 101. In some embodiments, the open block information also indicates the last programming page of each open block.

[0055] The interface 316 may be coupled to the control logic 312 and act as a control buffer to buffer control commands received from a host (not shown) and forward them to the control logic 312, and to buffer status information received from the control logic 312 and forward them to the host. The interface 316 may also be coupled to the column decoder / bit line driver 306 via a data bus and act as a data input / output (I / O) interface and data buffer to buffer and forward data to and from the memory cell array 101.

[0056] Figure 4 An exemplary memory cell stack 400 including multiple stacks of memory cells according to some aspects of the present disclosure is shown. Figure 4 4 shows three exemplary stacks of memory cells from the top to the bottom of the stack 400, namely, stack 2, stack 1, and stack 0. The example of stack 400 is Figure 1 Block 104 is shown in FIG. Stack 2 (eg, the first stack) is located above stack 1 (eg, the second stack), and stack 1 is located above stack 0. Figure 4 Adjacent stacks in the system are connected using inter-stack plugs (IDPs). Figure 4 IDPDMY in stack 1 represents a dummy word line (eg, a fifth word line or a sixth word line) in stack 1 and stack 2 that is adjacent to an inter-stack plug (IDP) connecting stack 1 and stack 2 . Figure 4 IDPDMY in stack 0 represents a pseudo word line in stack 0 and stack 1 adjacent to the IDP connecting stack 0 and stack 1. A memory cell in stack 2 (e.g., a first memory cell) is selected for a programming operation. The programming operation of the memory cell is part of a process of programming the memory cell from the top to the bottom of the stack 400. Therefore, the memory cells located above the memory cell selected for programming in stack 2 have already been programmed. The memory cells in stack 400 can be multi-level cells, for example, triple-level cells (TLC). Reference Figure 2, the order of the process of programming the memory cells in the memory cell stack from the top to the bottom of the memory cell stack is from the memory cells coupled to the word line farther from the substrate 202 to the memory cells coupled to the word line closer to the substrate 202. Figure 4 Three stacks of memory cells are shown, but one or more stacks of memory cells may be included in the stack 400 .

[0057] Figure 5A According to some aspects of the present disclosure, Figure 4 During programming of the memory cells in stack 2 Figure 4 In some embodiments, the selected WLn represents a word line (eg, a first word line) selected for a programming operation of a memory cell (eg, a first memory cell) in stack 2. The selected WLn may be Figure 1 118 in FIG. WLn-1 through WLn-x represent word lines coupled to Figure 4 The word line (e.g., the second word line) of the memory cells in stack 2 of WLn-1 that have been programmed during programming from top to bottom of stack 400. An exemplary range of x in WLn-x may be 3 to 10. Each of WLn-1 to WLn-x may also be Figure 1 4. An example of a word line 118 in FIG. 4. A BSG (eg, a select gate line) represents a word line coupled to one or more select gate transistors (eg, Figure 1 10 (e.g., source select gate transistor) in the stack 400). BTM DMY (e.g., fourth word line) represents one or more dummy word lines in stack 0 of the stack 400 close to the BSG of the stack 400. Other WL (e.g., third word line) represents word lines other than the selected WLn, WLn-1 to WLn-x, BTM DMY, IDPDMY stack 0, and IDPDMY stack 1. ACS (e.g., source line) represents source lines connected to all memory strings in the stack 400, e.g., Figure 1 The channel preparation period represents the time period from t0 to t4, and is in Figure 4 The channel preparation period may be divided into phase 1 and phase 2, where phase 1 is from t0 to t2, and phase 2 is from t2 to t4.

[0058] In some embodiments, to reduce Figure 4In order to prevent program disturbance during a programming operation of memory cells in the stack 2 of the embodiment of the present invention, during the stage 1 of the channel preparation period, a voltage Vpre (e.g., a first voltage) is applied to the selected WLn and WLn-1 to WLn-x at t1 (e.g., a first time), thereby increasing the voltage of the selected WLn and WLn-1 to WLn-x from Vss (e.g., a third voltage) to Vpre, thereby being able to increase the channel potential associated with the memory cells coupled to the word lines WLn-x to WLn during the channel preparation period, and the memory cells coupled to the word lines WLn-x to WLn can be turned on. Thus, the increased channel potential associated with the memory cells coupled to the word lines WLn-x to WLn can help to turn on the memory cells when the programming voltage Vpgm is applied to Figure 4 The memory cell in stack 2 is thus programmed to reduce program disturbance caused by hot current injection when programming the memory cell. An exemplary value of Vss is 0V. An exemplary range of Vpre is 0V to 3.3V. A stage 2 voltage (e.g., Vss or a value greater than 0V) is applied to the selected WLn and WLn-1 to WLn-x at t2 (e.g., a second time), thereby reducing the voltage of the selected WLn and WLn-1 to WLn-x from Vpre to the stage 2 voltage. From t2 to t4, an exemplary range of the stage 2 voltage may be 0V to 2V. At t4, which is the end of the channel preparation period of the memory cell in stack 2 and the beginning of the programming period, a pass voltage Vpass is applied to WLn-1 to WLn-x, thereby increasing the voltage of WLn-1 to WLn-x from the stage 2 voltage (e.g., the fourth voltage) to the pass voltage Vpass. Starting from t4, the voltage of the selected WLn is first increased from the stage 2 voltage (e.g., the second voltage) to the intermediate voltage and then to the programming voltage Vpgm. In some embodiments, when a specific voltage is applied to a line at a specific time, it may take some time for the voltage of the line to reach the specific voltage due to the load effect associated with the line. For example, when Vpre is applied to the selected WLn at t1, it may take some time for the voltage of the selected WLn to increase from Vss to Vpre, as shown in FIG. Figure 5A In some embodiments, the voltage of the line can immediately reach the specific voltage applied at the specific time.

[0059] In some embodiments, during the channel preparation period from t0 to t4, the voltage of the word line represented by the other WL (e.g., the fifth voltage) is maintained at Vss because the memory cells coupled to the word lines represented by the other WL can be kept off during the channel preparation period. During the channel preparation period, the voltage Vpre_dmy (e.g., the sixth voltage) is applied to BTM DMY, IDPDMY stack 0, and IDPDMY stack 1 at t1, thereby increasing the voltage of BTM DMY, IDPDMY stack 0, and IDPDMY stack 1 from the initial voltage to Vpre_dmy, so that the dummy memory cells coupled to the dummy word lines BTM DMY, IDPDMY stack 0, and IDPDMY stack 1 can be turned on during the channel preparation period. An exemplary value of Vpre_dmy may be 2.2V, thereby turning on the corresponding dummy memory cells. During phase 2 of the channel preparation period, the pseudo line voltage is applied to BTM DMY, IDPDMY stack 0 and IDPDMY stack 1 at t3 (e.g., a third time), thereby reducing the voltage of BTM DMY, IDPDMY stack 0 and IDPDMY stack 1 from Vpre-dmy to the pseudo line voltage. t3 may be the same as t2 or t3 may be later than t2. At t4, the pass voltage Vpass is applied to BTM DMY, IDPDMY stack 0 and IDPDMY stack 1, thereby increasing the voltage of BTM DMY, IDPDMY stack 0 and IDPDMY stack 1 from the pseudo line voltage to the pass voltage Vpass.

[0060] In some embodiments, a turn-on voltage (eg, the seventh voltage) is applied to BSG at t1, thereby increasing the voltage of BSG from Vss to the turn-on voltage to turn on a transistor coupled to BSG, for example, Figure 1 110 in the stack 400, thereby connecting the channels of the memory strings in the stack 400 to the ACS, for example, Figure 1 The source line 114 in FIG. 1 is a source line 114 in FIG. 1. An exemplary value of the on-voltage is 2.2 V. During phase 2 of the channel preparation period, the voltage Vss is applied to BSG at t3, thereby causing the voltage of BSG to drop from the on-voltage to Vss.

[0061] In some embodiments, during the channel preparation period from t0 to t4, the voltage of ACS (e.g., the eighth voltage) is maintained at Vss, or a channel precharge voltage may be applied to ACS at t1 to increase the voltage of ACS from Vss to the channel precharge voltage, thereby precharging the channels of the memory strings in the stack 400. In either case, the voltage of ACS (either Vss or the channel precharge voltage) may be used to increase the channel potential of the memory cells in the stack 400. An exemplary value of the channel precharge voltage is 2.2V.

[0062] Figure 5B According to some aspects of the present disclosure, Figure 4 During programming of the memory cells in stack 2 Figure 4 Another example of voltage conditions for components in the stack 400. Except for the selected WLn, the voltage conditions for most components in the stack 400 (e.g., WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are the same as Figure 5A The corresponding voltage conditions in are equivalent. More specifically, Figure 5B As shown in FIG. 1 , at t2 as the beginning of phase 2 of the channel preparation period, a voltage Vpre_WLn (eg, a second voltage) is applied to the selected WLn, thereby causing the voltage of the selected WLn to drop from Vpre to Vpre_WLn, and at Figure 5A In the embodiment, the phase 2 voltage is applied to the selected WLn at t2, so that the voltage of the selected WLn drops from Vpre to the phase 2 voltage. Vpre_WLn may be greater than the phase 2 voltage. An exemplary range of Vpre_WLn is 0V to 3.3V.

[0063] Figure 5C According to some aspects of the present disclosure, Figure 4 During programming of the memory cells in stack 2 Figure 4 Another example of voltage conditions for components in stack 400. Except for WLn-1, the voltage conditions for most components in stack 400 (e.g., WLn-2 to WLn-x, other WLs, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are the same as Figure 5B The corresponding voltage conditions in are equivalent. More specifically, Figure 5C As shown in FIG. 1 , at t2 as the beginning of phase 2 of the channel preparation period, the voltage Vpre_WLn is applied to WLn-1, thereby causing the voltage of WLn-1 to drop from Vpre to Vpre_WLn, and Figure 5B In the embodiment, the phase 2 voltage is applied to WLn-1 at t2, so that the voltage of WLn-1 drops from Vpre to the phase 2 voltage. In some embodiments, the voltage condition of one or more word lines closer to WLn-1 among WLn-2 to WLn-x can be the same as the voltage condition of WLn-1.

[0064] Figure 6 According to some aspects of the present disclosure Figure 4 400, wherein stack 1 (but not stack 2 or stack 0) has memory cells selected for programming. The programming process of stack 400 is from top to bottom, which is similar to Figure 4 Same as in.

[0065] Fig. 7A According to some aspects of the present disclosure, Figure 6 During programming of the memory cells in stack 1 Figure 6 Except for IDPDMY stack 1, the voltage conditions of most components in the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 0, BSG, and ACS) are the same as Figure 5A More specifically, at a given voltage Figure 6 In the case of a top-to-bottom programming process of a memory cell, when WLn-x is located Figure 6 When the memory cell selected for programming is in stack 1 instead of stack 2, Figure 6 The voltage condition of IDPDMY stack 1 is determined by Fig. 7A When WLn-x is located in stack 2 and the memory cell selected for programming is located in stack 1, IDPDMY stack 1 is located between WLn-x and WLn, so the voltage condition of IDPDMY stack 1 is equivalent to Fig. 7A The voltage condition of BTM DMY or IDPDMY stack 0 in the circuit can be turned on to enable the dummy memory cell coupled to IDPDMY stack 1.

[0066] Figure 7B According to some aspects of the present disclosure, Figure 6 During programming of the memory cells in stack 1 Figure 6 Another example of voltages of components in a memory cell stack of FIG. 400. Except for IDPDMY stack 1, the voltage conditions of most components in the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 0, BSG, and ACS) are the same as Figure 5B More specifically, at a given voltage Figure 6 In the case of a top-to-bottom programming process of a memory cell, when WLn-x is located Figure 6 When the memory cell selected for programming is in stack 1 instead of stack 2, Figure 6 The voltage condition of IDPDMY stack 1 is determined by Figure 7BThe voltage conditions of other WLs in the stack are represented by BTM DMY and IDPDMY stack 0. When WLn-x is located in stack 2 and the memory cell selected for programming is located in stack 1, IDPDMY stack 1 is located between WLn-x and WLn, so the voltage condition of IDPDMY stack 1 is equivalent to Figure 7B The voltage condition of BTM DMY or IDPDMY stack 0 is set, thereby enabling the dummy memory cell coupled to IDPDMY stack 1 to be turned on.

[0067] Figure 7C According to some aspects of the present disclosure, Figure 6 During programming of the memory cells in stack 1 Figure 6 Another example of voltages of components in a memory cell stack of FIG. 400. Except for IDPDMY stack 1, the voltage conditions of most components in the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 0, BSG, and ACS) are the same as Figure 5C More specifically, at a given voltage Figure 6 In the case of a top-to-bottom programming process of a memory cell, when WLn-x is located Figure 6 When the memory cell selected for programming is in stack 1 instead of stack 2, Figure 6 The voltage condition of IDPDMY stack 1 is determined by Figure 7C The voltage conditions of other WLs in the stack are represented by BTM DMY and IDPDMY stack 0. When WLn-x is located in stack 2 and the memory cell selected for programming is located in stack 1, IDPDMY stack 1 is located between WLn-x and WLn, so the voltage condition of IDPDMY stack 1 is equivalent to Figure 7C The voltage condition of BTM DMY or IDPDMY stack 0 in the circuit can be turned on to enable the dummy memory cell coupled to IDPDMY stack 1.

[0068] Figure 8 According to some aspects of the present disclosure Figure 4 400, wherein stack 0 (but not stack 2 or stack 1) has the memory cell selected for programming. The programming process of stack 400 is from top to bottom, which is similar to Figure 4 Same as in.

[0069] Fig. 9A According to some aspects of the present disclosure, Figure 8 During programming of the memory cells in stack 0 Figure 8Except for IDPDMY stack 0, the voltage conditions of most components in the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 1, BSG, and ACS) are the same as Fig. 7A More specifically, at a given voltage Figure 8 In the case of a top-to-bottom programming process of a memory cell, when WLn-x is located Figure 8 When the memory cell selected for programming is in stack 0 instead of stack 1, Figure 8 The voltage condition of IDPDMY stack 0 is determined by Fig. 9A When WLn-x is located in stack 1 and the memory cell selected for programming is located in stack 0, IDPDMY stack 0 is located between WLn-x and WLn, so the voltage condition of IDPDMY stack 0 is equivalent to Fig. 9A The voltage condition of BTM DMY in is set so that the dummy memory cell coupled to IDPDMY stack 0 can be turned on.

[0070] Fig. 9B According to some aspects of the present disclosure, Figure 8 During programming of the memory cells in stack 0 Figure 8 Another example of voltages of components in a memory cell stack of FIG. 400. Except for IDPDMY stack 0, the voltage conditions of most components in the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 1, BSG, and ACS) are the same as Figure 7B More specifically, at a given voltage Figure 8 In the case of a top-to-bottom programming process of a memory cell, when WLn-x is located Figure 8 When the memory cell selected for programming is in stack 0 instead of stack 1, Figure 8 The voltage condition of IDPDMY stack 0 is determined by Fig. 9B When WLn-x is located in stack 1 and the memory cell selected for programming is located in stack 0, IDPDMY stack 0 is located between WLn-x and WLn, so the voltage condition of IDPDMY stack 0 is equivalent to Fig. 9B The voltage condition of BTM DMY is set so that the dummy memory cell coupled to IDPDMY stack 0 can be turned on.

[0071] Fig. 9C According to some aspects of the present disclosure, Figure 8 During programming of the memory cells in stack 0 Figure 8 Another example of voltages of components in a memory cell stack of FIG. 400. Except for IDPDMY stack 0, the voltage conditions of most components in the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 1, BSG, and ACS) are the same as Figure 7C More specifically, at a given voltage Figure 8 In the case of a top-to-bottom programming process of a memory cell, when WLn-x is located Figure 8 When the memory cell selected for programming is in stack 0 instead of stack 1, Figure 8 The voltage condition of IDPDMY stack 0 is determined by Fig. 9C When WLn-x is located in stack 1 and the memory cell selected for programming is located in stack 0, IDPDMY stack 0 is located between WLn-x and WLn, so the voltage condition of IDPDMY stack 0 is equivalent to Fig. 9C The voltage condition of BTM DMY in is set so that the dummy memory cell coupled to IDPDMY stack 0 can be turned on.

[0072] In some embodiments, Figure 4 The memory cells in the stack 400 may include multi-level memory cells, for example, quad-level memory cells (QTC). The programming operation of the memory cells in the stack 400 may include coarse programming of the memory cells and fine programming of the memory cells. Coarse programming can be used together with fine programming to achieve a strict threshold distribution without slowing down the programming process of the memory cells too much. In the coarse programming stage, the threshold voltage used to program the memory cells can be increased in a faster manner, while in the fine programming stage, the threshold voltage can be increased in a slower manner to reach the target threshold voltage, while also achieving a stricter threshold distribution.

[0073] In some embodiments, FIG. 5A to FIG. 5C , FIG. 7A to FIG. 7A as well as FIG. 9A to FIG. 9C The voltage conditions shown in and described above may be applied to the coarse programming of the memory cells in the stack 400. More specifically, Figure 5A , Figure 5B or Figure 5C The voltage conditions shown in can be applied to the coarse programming of the memory cells in layer 2 of stack 400, Fig. 7A , Figure 7B or Figure 7CThe voltage conditions shown in can be applied to the coarse programming of the memory cells in layer 1 of stack 400, and Fig. 9A , Fig. 9B or Fig. 9C The voltage conditions shown in can be applied to coarse programming of memory cells in stack 0 of stack 400 .

[0074] In some embodiments, for fine programming of memory cells in stack 400 coupled to a selected WLn, Figure 5A The voltage condition of the word line WLn+1 (e.g., the seventh word line) during the channel preparation period from t0 to t4 in the embodiment of the present invention may be the same as the voltage condition of the selected WLn during the channel preparation period, rather than the same as the voltage condition of the other WLs during the channel preparation period, thereby further reducing program disturbance during fine programming of the memory cells coupled to the selected WLn. WLn+1 is a word line coupled to a memory cell (e.g., the second memory cell) that has not been programmed, and is located immediately below the WLn selected for programming.

[0075] In some embodiments, Fig. 10A FIG. 4 shows a diagram of a memory cell in layer 2 of stack 400 during fine programming according to some aspects of the present disclosure. Figure 4 An example of the voltages of components in stack 400 . Fig. 10A The example in FIG. 4 is directed to fine programming of memory cells in stack 2 of stack 400 after coarse programming of memory cells in stack 2. In addition to WLn+1, Fig. 10A The voltage conditions of most of the components of the stack 400 shown in FIG. 4 (eg, selected WLn, WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of FIG. Figure 5A The corresponding voltage conditions in are equivalent. Fig. 10A As shown in , the voltage condition of the word line WLn+1 during the channel preparation period is the same as the voltage condition of the selected WLn during the channel preparation period, rather than the same as the voltage condition of other WLs during the channel preparation period, so that the memory cells coupled to WLn+1 are turned on during the channel preparation period, thereby further reducing program interference during fine programming of the memory cells coupled to the selected WLn.

[0076] Fig. 10B According to some aspects of the present disclosure, Figure 4 During fine programming of the memory cells in stack 2 Figure 4 Another example of the voltages of the components in the stack 400. In addition to WLn+1, Fig. 10BThe voltage conditions of most of the components of the stack 400 shown in FIG. 4 (eg, selected WLn, WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of FIG. Figure 5B The corresponding voltage conditions in are equivalent. Fig. 10B As shown in , the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of the selected WLn during the channel preparation period, rather than the same as the voltage condition of other WLs during the channel preparation period, thereby further reducing program disturbance during fine programming of memory cells coupled to the selected WLn.

[0077] Fig. 10C According to some aspects of the present disclosure, Figure 4 During fine programming of the memory cells in stack 2 Figure 4 Another example of the voltages of components in the stack 400. In addition to WLn+1, Fig. 10C The voltage conditions of most of the components of the stack 400 shown in FIG. 4 (eg, selected WLn, WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of FIG. Figure 5C The corresponding voltage conditions in are equivalent. Fig. 10C As shown in , the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of the selected WLn during the channel preparation period, rather than the same as the voltage condition of other WLs during the channel preparation period, thereby further reducing program disturbance during fine programming of memory cells coupled to the selected WLn.

[0078] Fig.11A FIG. 4 shows a memory cell in layer 1 of stack 400 during fine programming according to some aspects of the present disclosure. Figure 4 Example of voltages of components in stack 400. In addition to WLn+1, Fig.11A The voltage conditions of most of the components of the stack 400 shown in FIG. 4 (eg, selected WLn, WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of FIG. Fig. 7A The corresponding voltage conditions in are equivalent. Fig.11A As shown in , the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of the selected WLn during the channel preparation period, rather than the same as the voltage condition of other WLs during the channel preparation period, thereby further reducing program disturbance during fine programming of memory cells coupled to the selected WLn.

[0079] Fig. 11BAccording to some aspects of the present disclosure, Figure 4 During fine programming of the memory cells in stack 1 Figure 4 Another example of the voltages of the components in the stack 400. In addition to WLn+1, Fig. 11B The voltage conditions of most of the components of the stack 400 shown in FIG. 4 (eg, selected WLn, WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of FIG. Figure 7B The corresponding voltage conditions in are equivalent. Fig. 11B As shown in , the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of the selected WLn during the channel preparation period, rather than the same as the voltage condition of other WLs during the channel preparation period, thereby further reducing program disturbance during fine programming of memory cells coupled to the selected WLn.

[0080] Fig. 11C According to some aspects of the present disclosure, Figure 4 During fine programming of the memory cells in stack 1 Figure 4 Another example of the voltages of the components in the stack 400. In addition to WLn+1, Fig. 11C The voltage conditions of most of the components of the stack 400 shown in FIG. 4 (eg, selected WLn, WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of FIG. Figure 7C The corresponding voltage conditions in are equivalent. Fig. 11C As shown in , the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of the selected WLn during the channel preparation period, rather than the same as the voltage condition of other WLs during the channel preparation period, thereby further reducing program disturbance during fine programming of memory cells coupled to the selected WLn.

[0081] Fig. 12A FIG. 4 shows a memory cell in layer 0 of stack 400 during fine programming according to some aspects of the present disclosure. Figure 4 Example of voltages of components in stack 400. In addition to WLn+1, Fig. 12A The voltage conditions of most of the components of the stack 400 shown in FIG. 4 (eg, selected WLn, WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of FIG. Fig. 9A The corresponding voltage conditions in are equivalent. Fig. 12AAs shown in , the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of the selected WLn during the channel preparation period, rather than the same as the voltage condition of other WLs during the channel preparation period, thereby further reducing program disturbance during fine programming of memory cells coupled to the selected WLn.

[0082] Fig. 12B According to some aspects of the present disclosure, Figure 4 During fine programming of the memory cells in stack 2 Figure 4 Another example of the voltages of the components in the stack 400. In addition to WLn+1, Fig. 12B The voltage conditions of most of the components of the stack 400 shown in FIG. 4 (eg, selected WLn, WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of FIG. Fig. 9B The corresponding voltage conditions in are equivalent. Fig. 12B As shown in , the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of the selected WLn during the channel preparation period, rather than the same as the voltage condition of other WLs during the channel preparation period, thereby further reducing program disturbance during fine programming of memory cells coupled to the selected WLn.

[0083] Fig. 12C According to some aspects of the present disclosure, Figure 4 During fine programming of the memory cells in stack 2 Figure 4 Another example of the voltages of the components in the stack 400. In addition to WLn+1, Fig. 12C The voltage conditions of most of the components of the stack 400 shown in FIG. 4 (eg, selected WLn, WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of FIG. Fig. 9C The corresponding voltage conditions in are equivalent. Fig. 12C As shown in , the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of the selected WLn during the channel preparation period, rather than the same as the voltage condition of other WLs during the channel preparation period, thereby further reducing program disturbance during fine programming of memory cells coupled to the selected WLn.

[0084] As mentioned above, FIG. 5A to FIG. 5C , FIG. 7A to FIG. 7C as well as FIG. 9A to FIG. 12C The diagram shows the memory cells in the stack 400 being programmed from the top to the bottom of the stack 400. Figure 4When programming the memory cells in the stack 400 from the bottom to the top, with some exceptions, the same voltage conditions as in the stack 400 may also be used. FIG. 5A to FIG. 5C , FIG. 7A to FIG. 7C as well as FIG. 9A to FIG. 12C The voltage conditions of the components of the stack 400 are illustrated in a similar manner as in FIG. Figure 2 The order of the process of programming the memory cells in the memory cell stack from the bottom to the top of the memory cell stack is from the memory cells coupled to the word lines close to the substrate 202 to the memory cells coupled to the word lines farther from the substrate 202.

[0085] More specifically, when programming the memory cells in the stack 400 from the bottom to the top of the stack 400, FIG. 5A to FIG. 5C , FIG. 7A to FIG. 7C as well as FIG. 9A to FIG. 12C The voltage condition of the BSG in each of the stack 400 may be applied to the TSG in the stack 400, FIG. 5A to FIG. 5C , FIG. 7A to FIG. 7C as well as FIG. 9A to FIG. 12C The voltage condition of ACS in each of the above may be applied to the bit line (BL) of the stack 400 and FIG. 5A to FIG. 5C , FIG. 7A to FIG. 7C as well as FIG. 9A to FIG. 12C The voltage condition of the BTM DMY in each of the TOP DMYs may be applied to the TOP DMYs of the stack 400. TSG represents a transistor coupled to one or more select gate transistors (eg, Figure 1 BL represents one or more select gate lines (eg, DSG line 113) of the DSG 112 in the stack 400. BL represents a bit line in the stack 400, for example, Figure 1 TOP DMY represents the topmost dummy word line in stack 2 of stack 400.

[0086] For example, Fig.13 According to some aspects of the present disclosure Figure 4 0. An exemplary memory cell stack 400 in FIG. 4 wherein during a process of programming memory cells in the stack 400 from the bottom to the top of the stack 400, Stack 0 has the memory cells selected for programming.

[0087] Fig.14A FIG. 2 shows a memory cell in stack 0 during programming according to some aspects of the present disclosure. Fig.13 Example of voltages of components in the stack 400. In addition to TSG, BL and TOP DMY, Fig.13 The voltage conditions of most components of the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WLs, IDPDMY stack 0 and IDPDMY stack 1) are the same as Figure 5A The corresponding voltage conditions in are equivalent. In some embodiments, selected WLn represents the word line selected for programming operations of memory cells in stack 0. Selected WLn can be Figure 1 118 in FIG. WLn-1 through WLn-x represent word lines coupled to Fig.13 The word line of the memory cell in stack 0 of WLn-1 that has been programmed during programming from the bottom to the top of the stack 400. An exemplary range of x in WLn-x may be 3 to 10. Each of WLn-1 to WLn-x may also be Figure 1 For example, the word line 118 in FIG. Fig.13 As for the voltage conditions of TSG, BL and TOP DMY of the stack 400, since the memory cells in the stack 0 are selected to be programmed during the process of programming the memory cells in the stack 400 from the bottom to the top of the stack 400, Figure 5A The voltage condition of the BSG can be applied to Fig.13 The TSG of the stack 400, Figure 5A The voltage conditions of the ACS can be applied to Fig.13 The BL of the stack 400, and Figure 5A The voltage condition of BTM DMY can be applied to Fig.13 TOP DMY of the stack 400 in.

[0088] Fig. 14B FIG. 2 shows a memory cell in stack 0 during programming according to some aspects of the present disclosure. Fig.13 Another example of the voltage of the components in the stack 400. In addition to TSG, BL and TOP DMY, Fig.13 The voltage conditions of most components of the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WLs, IDPDMY stack 0 and IDPDMY stack 1) are the same as Figure 5B More specifically, since the memory cells in stack 0 are selected for programming during the process of programming the memory cells in stack 400 from the bottom to the top, Figure 5B The voltage condition of the BSG can be applied to Fig.13 The TSG of the stack 400, Figure 5B The voltage conditions of the ACS can be applied to Fig.13 The BL of the stack 400, and Figure 5B The voltage condition of BTM DMY can be applied to Fig.13 TOP DMY of the stack 400 in.

[0089] Fig. 14CFIG. 2 shows a memory cell in stack 0 during programming according to some aspects of the present disclosure. Fig.13 Another example of the voltage of the components in the stack 400. In addition to TSG, BL and TOP DMY, Fig.13 The voltage conditions of most components of the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WLs, IDPDMY stack 0 and IDPDMY stack 1) are the same as Figure 5C More specifically, since the memory cells in stack 0 are selected for programming during the process of programming the memory cells in stack 400 from the bottom to the top, Figure 5C The voltage condition of the BSG can be applied to Fig.13 The TSG of the stack 400, Figure 5C The voltage conditions of the ACS can be applied to Fig.13 The BL of the stack 400, and Figure 5C The voltage condition of BTM DMY can be applied to Fig.13 TOP DMY of the stack 400 in.

[0090] As another example, Fig.15 According to some aspects of the present disclosure Figure 4 0046] An exemplary memory cell stack 400 in FIG. 1, wherein during a process of programming memory cells in the stack 400 from the bottom to the top of the stack 400, stack 1 has a memory cell selected for programming.

[0091] Fig.16A 1 shows a memory cell in stack 1 during programming according to some aspects of the present disclosure. Fig.15 Example of voltages of components in the stack 400. In addition to TSG, BL and TOP DMY, Fig.15 The voltage conditions of most components of the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WLs, and IDPDMY stack 1) are similar to Fig. 7A More specifically, since the memory cells in stack 1 are selected for programming during the process of programming the memory cells in stack 400 from the bottom to the top, Fig. 7A The voltage condition of the BSG can be applied to Fig.15 The TSG of the stack 400, Fig. 7A The voltage conditions of the ACS can be applied to Fig.15 The BL of the stack 400, and Fig. 7A The voltage condition of BTM DMY can be applied to Fig.15TOPDMY of the stack 400 in.

[0092] Fig. 16B 1 shows a memory cell in stack 1 during programming according to some aspects of the present disclosure. Fig.15 Another example of the voltage of the components in the stack 400. In addition to TSG, BL and TOP DMY, Fig.15 The voltage conditions of most components of the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WLs, and IDPDMY stack 1) are similar to Figure 7B More specifically, since the memory cells in stack 1 are selected for programming during the process of programming the memory cells in stack 400 from the bottom to the top, Figure 7B The voltage condition of the BSG can be applied to Fig.15 The TSG of the stack 400, Figure 7B The voltage conditions of the ACS can be applied to Fig.15 The BL of the stack 400, and Figure 7B The voltage condition of BTM DMY can be applied to Fig.15 TOPDMY of the stack 400 in.

[0093] Fig. 16C 1 shows a memory cell in stack 1 during programming according to some aspects of the present disclosure. Fig.15 Another example of the voltage of the components in the stack 400. In addition to TSG, BL and TOP DMY, Fig.15 The voltage conditions of most components of the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WLs, and IDPDMY stack 1) are similar to Figure 7C More specifically, since the memory cells in stack 1 are selected for programming during the process of programming the memory cells in stack 400 from the bottom to the top, Figure 7C The voltage condition of the BSG can be applied to Fig.15 The TSG of the stack 400, Figure 7C The voltage conditions of the ACS can be applied to Fig.15 The BL of the stack 400, and Figure 7C The voltage condition of BTM DMY can be applied to Fig.15 TOPDMY of the stack 400 in.

[0094] Fig.17An example of a flow chart of a method for reducing program disturb in a memory device according to some aspects of the present disclosure is shown. At 1702, peripheral circuitry of a memory device applies a first voltage to a first word line coupled to a first memory cell in a memory cell array at a first time and during a channel preparation period of a program operation of the first memory cell.

[0095] At 1704, the peripheral circuit applies a second voltage to the first word line at a second time after the first time and during the channel preparation period, wherein the second voltage is lower than the first voltage.

[0096] At 1706, the peripheral circuit applies a program voltage to the first word line after the channel preparation period and during a program operation of the first memory cell.

[0097] Fig.18 A block diagram of an exemplary system 1800 having a memory device according to some aspects of the present disclosure is shown. System 1800 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other electronic device having a storage component located therein. Fig.18 As shown in , system 1800 may include a host 1808 and a memory system 1802, the memory system 1802 having one or more memory devices 1804 and a memory controller 1806. The host 1808 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system on a chip (SoC), such as an application processor (AP). The host 1808 may be configured to send or receive data to or from the memory device 1804.

[0098] The memory device 1804 may be any memory device disclosed in the present disclosure. According to some embodiments, the memory controller 1806 is coupled to the memory device 1804 and the host 1808 and is configured to control the memory device 1804. The memory controller 1806 may manage data stored in the memory device 1804 and communicate with the host 1808. In some embodiments, the memory controller 1806 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 1806 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smart phones, tablet computers, laptop computers, etc. and an enterprise storage array. The memory controller 1806 may be configured to control the operation of the memory device 1804, such as read, erase, and program operations. The memory controller 1806 may also be configured to manage various functions related to data stored in or to be stored in the memory device 1804, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 1806 is further configured to process error correction codes (ECC) related to data read from or written to the memory device 1804. Any other suitable functions may also be performed by the memory controller 1806, such as formatting the memory device 1804.

[0099] The memory controller 1806 may communicate with an external device (e.g., the host 1808) according to a specific communication protocol. For example, the memory controller 1806 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0100] The memory controller 1806 and the one or more memory devices 1804 may be integrated into various types of storage devices, for example, included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 1802 may be implemented and packaged into different types of final electronic products. Fig.19AIn one example shown in FIG. 1 , the memory controller 1806 and the single memory device 1804 may be integrated into a memory card 1902. The memory card 1902 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1902 may further include a processor that connects the memory card 1902 to a host (e.g., Fig.18 The memory card connector 1904 is coupled to the host 1808 in FIG. Fig.19B In another example shown, the memory controller 1806 and the plurality of memory devices 1804 may be integrated into the SSD 1906. The SSD 1906 may further include a processor that interfaces the SSD 1906 with a host (e.g., Fig.18 In some implementations, the storage capacity and / or operating speed of SSD 1906 is higher than the storage capacity and / or operating speed of memory card 1902.

[0101] Certain aspects of the subject matter described herein may be implemented as a memory device. The memory device includes a memory cell array and a peripheral circuit. The memory cell array includes memory cells. The peripheral circuit is coupled to the memory cell array and is configured to perform operations, wherein, to perform the operations, the peripheral circuit is configured to apply a first voltage to a first word line coupled to the first memory cell at a first time and during a channel preparation period of a programming operation of a first memory cell in the memory cell array, apply a second voltage to the first word line at a second time after the first time and during the channel preparation period, wherein the second voltage is lower than the first voltage, and apply a programming voltage to the first word line after the channel preparation period and during a programming operation of the first memory cell.

[0102] The memory device may include one or more of the following features.

[0103] In some embodiments, the first voltage is lower than the programming voltage.

[0104] In some embodiments, the peripheral circuit is further configured to apply a third voltage to the first word line before the first time, wherein the third voltage is lower than the first voltage.

[0105] In some embodiments, the third voltage is lower than or equal to the second voltage.

[0106] In some embodiments, the peripheral circuit is further configured to: apply a first voltage to a second word line coupled to one or more memory cells in the memory cell array at a first time, wherein each of the one or more memory cells is a programmed memory cell; and apply a fourth voltage to the second word line at a second time.

[0107] In some embodiments, the first voltage is lower than a pass voltage to be applied to the second word line after the second time.

[0108] In some embodiments, the fourth voltage is lower than or equal to the second voltage.

[0109] In some embodiments, the peripheral circuit is further configured to apply a fifth voltage to the third word line before applying the pass voltage to the third word line, wherein the third word line is coupled to one or more memory cells in the memory cell array and each of the one or more memory cells is an unprogrammed memory cell.

[0110] In some embodiments, the fifth voltage is lower than the pass voltage.

[0111] In some embodiments, the peripheral circuit is further configured to: apply a sixth voltage to a fourth word line coupled to a memory cell adjacent to a select gate transistor at a first time, wherein the select gate transistor is coupled to a source line of a memory cell array, the sixth voltage is higher than the third voltage and the fourth word line is a first pseudo word line; and apply a third voltage to the fourth word line at a third time after the second time.

[0112] In some embodiments, the peripheral circuit is further configured to: apply a seventh voltage to a select gate line coupled to the select gate transistor at a first time, wherein the seventh voltage is higher than the third voltage; and apply the third voltage to the select gate line at a third time.

[0113] In some implementations, the peripheral circuit is further configured to apply an eighth voltage to a source line of the memory cell array at the first time.

[0114] In some implementations, the eighth voltage is equal to the third voltage.

[0115] In some embodiments, the memory cell array includes a first stack of memory cells and a second stack of memory cells, the first stack is adjacent to the second stack, the first memory cell is located in the first stack, and the peripheral circuit is further configured to apply a sixth voltage to a fifth word line coupled to a memory cell in the first stack that is closest to the second stack at a first time, wherein the fifth word line is a second dummy word line.

[0116] In some implementations, the peripheral circuit is further configured to apply the sixth voltage to a sixth word line coupled to a memory cell in the second stack that is closest to the first stack at the first time, wherein the sixth word line is a third dummy word line.

[0117] In some implementations, the first memory cell is a multi-level cell, and the programming operation of the first memory cell is a coarse programming operation.

[0118] In some embodiments, the first memory cell is a multi-level cell, the programming operation of the first memory cell is a fine programming operation, and the peripheral circuit is further configured to apply a first voltage to a seventh word line coupled to a second memory cell in the memory cell array at a first time, wherein the seventh word line is adjacent to the first word line; and apply a second voltage to the seventh word line at a second time.

[0119] Certain aspects of the subject matter described herein may be implemented as a memory system. The memory system includes a memory device and a controller. The memory device includes a memory cell array and a peripheral circuit. The memory cell array includes memory cells. The peripheral circuit is coupled to the memory cell array and is configured to perform operations, wherein, in order to perform these operations, the peripheral circuit is configured to apply a first voltage to a first word line coupled to the first memory cell at a first time and during a channel preparation period of a programming operation of a first memory cell in the memory cell array, apply a second voltage to the first word line at a second time after the first time and during the channel preparation period, wherein the second voltage is lower than the first voltage, and apply a programming voltage to the first word line after the channel preparation period and during the programming operation of the first memory cell.

[0120] Certain aspects of the subject matter described herein can be implemented as a method. The method includes: applying a first voltage to a first word line coupled to a first memory cell at a first time and during a channel preparation period of a programming operation of a first memory cell in a memory cell array; applying a second voltage to the first word line at a second time after the first time and during the channel preparation period, wherein the second voltage is lower than the first voltage; and applying a programming voltage to the first word line after the channel preparation period and during the programming operation of the first memory cell.

[0121] The method may include one or more of the following features.

[0122] In some embodiments, the first voltage is lower than a programming voltage.

[0123] In some embodiments, the method further includes applying a third voltage to the first word line before the first time, wherein the third voltage is lower than the first voltage.

[0124] In some embodiments, the third voltage is lower than or equal to the second voltage.

[0125] In some embodiments, the method further includes: applying a first voltage to a second word line coupled to one or more memory cells in the memory cell array at a first time, wherein each of the one or more memory cells is a programmed memory cell; and applying a fourth voltage to the second word line at a second time.

[0126] In some embodiments, the first voltage is lower than a pass voltage to be applied to the second word line after the second time.

[0127] In some embodiments, the fourth voltage is lower than or equal to the second voltage.

[0128] In some embodiments, the method further includes: applying a sixth voltage to a fourth word line coupled to a memory cell adjacent to a select gate transistor at a first time, wherein the select gate transistor is coupled to a source line of a memory cell array, the sixth voltage is higher than the third voltage and the fourth word line is a first pseudo word line; and applying a third voltage to the fourth word line at a third time after the second time.

[0129] In some embodiments, the memory cell array includes a first stack of memory cells and a second stack of memory cells, the first stack is adjacent to the second stack, the first memory cell is located in the first stack, and the method further includes applying a sixth voltage to a fifth word line coupled to a memory cell in the first stack that is closest to the second stack at a first time, wherein the fifth word line is a second dummy word line.

[0130] In some implementations, the method further includes applying the sixth voltage to a sixth word line coupled to a memory cell in the second stack that is closest to the first stack at a first time, wherein the sixth word line is a third dummy word line.

[0131] In some implementations, the first memory cell is a multi-level cell, and the programming operation of the first memory cell is a coarse programming operation.

[0132] In some embodiments, the first memory cell is a multi-level cell, the programming operation of the first memory cell is a fine programming operation, and the method further includes: applying a first voltage to a seventh word line coupled to a second memory cell in the memory cell array at a first time, wherein the seventh word line is adjacent to the first word line; and applying a second voltage to the seventh word line at a second time.

[0133] Although this specification contains many specific implementation details, these should not be understood as limitations on the scope of the content claimed for protection, but should be understood as descriptions of features unique to specific embodiments. Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any sub-combination. In addition, although the features described above may be described as working in certain combinations and even initially claimed for protection, one or more features from the combination claimed for protection may be removed from the combination in some cases, and the combination claimed for protection may involve sub-combinations or variations of sub-combinations.

[0134] As used in this disclosure, indefinite or definite articles are used to include one or more than one, unless the context clearly indicates otherwise. The word "or" is used to represent a non-exclusive "or" unless otherwise specified. The expression "at least one of A and B" has the same meaning as "A, B, or A and B". In addition, the words or terms used in this disclosure, which are not otherwise defined, are used for descriptive purposes only and not for limitation. Any use of section headings is intended to assist in reading this document and should not be construed as limiting; information related to a section heading may appear within or outside that particular section.

[0135] As used herein, the word "about" or "approximately" can allow a value or range to vary to a certain degree, for example, within 10%, within 5%, or within 1% of the stated value or range limit.

[0136] As used in this disclosure, the term "substantially" means a majority, a majority, or at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0137] Values ​​expressed in range format should be interpreted in a flexible manner to include not only the values ​​explicitly cited as range limits, but also all individual values ​​or subranges encompassed within the range, as if each value and subrange were explicitly cited. For example, the range "0.1% to about 5%" or "0.1% to 5%" should be interpreted to include about 0.1% to about 5% and individual values ​​(e.g., 1%, 2%, 3% and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the indicated range. The expression "X to Y" has the same meaning as "approximately X to approximately Y" unless otherwise indicated. Similarly, the expression "X, Y, or Z" has the same meaning as "approximately X, approximately Y, or approximately Z" unless otherwise indicated.

[0138] Specific embodiments of the subject matter have been described. Other embodiments, as well as modifications and permutations of the described embodiments, are within the scope of the following claims and will be apparent to those skilled in the art. Although operations are depicted in a particular order in the drawings or claims, it is not required that such operations be performed in the particular order shown or in a sequential order, nor is it required that all of the illustrated operations be performed (some operations may be shown as optional), in some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and may be performed where deemed appropriate.

[0139] Furthermore, the division or integration of the various system modules and components in the aforementioned embodiments is not required in all embodiments, and the described components and systems are generally integrated together or packaged into multiple products.

[0140] Accordingly, the exemplary embodiments described above do not limit or restrict the present disclosure. Other changes, substitutions and modifications are also possible without departing from the essence and scope of the present disclosure.

Claims

1. A memory device, comprising: a memory cell array comprising memory cells; as well as A peripheral circuit coupled to the memory cell array and configured to perform operations comprising: applying a first voltage to a first word line coupled to a first memory cell in the memory cell array at a first time and during a channel preparation period of a programming operation of the first memory cell; applying a second voltage to the first word line at a second time after the first time and during the channel preparation period, wherein the second voltage is lower than the first voltage; and A program voltage is applied to the first word line after the channel preparation period and during the program operation of the first memory cell.

2. The memory device according to claim 1, wherein: The first voltage is lower than the programming voltage.

3. The memory device according to claim 1 or 2, wherein: The operations further include: A third voltage is applied to the first word line before the first time, wherein the third voltage is lower than the first voltage.

4. The memory device according to claim 3, wherein: The third voltage is lower than or equal to the second voltage.

5. The memory device according to any one of claims 1 to 4, wherein: The operations further include: applying the first voltage to a second word line coupled to one or more memory cells in the memory cell array at the first time, wherein each of the one or more memory cells is a programmed memory cell; and A fourth voltage is applied to the second word line at the second time.

6. The memory device according to claim 5, wherein: The first voltage is lower than a pass voltage to be applied to the second word line after the second time.

7. The memory device according to claim 5 or 6, wherein: The fourth voltage is lower than or equal to the second voltage.

8. The memory device according to any one of claims 1 to 7, wherein: The operations further include: A fifth voltage is applied to a third word line before a pass voltage is applied to the third word line, wherein the third word line is coupled to one or more memory cells in the memory cell array and each of the one or more memory cells is an unprogrammed memory cell.

9. The memory device according to claim 8, wherein: The fifth voltage is lower than the pass voltage.

10. The memory device according to claim 3 or 4, wherein: The operations further include: applying a sixth voltage to a fourth word line coupled to a memory cell adjacent to a select gate transistor coupled to a source line of the memory cell array at the first time, wherein the select gate transistor is coupled to a source line of the memory cell array, the sixth voltage is higher than the third voltage, and the fourth word line is a first dummy word line; and The third voltage is applied to the fourth word line at a third time after the second time.

11. The memory device according to claim 10, wherein: The operations further include: applying a seventh voltage to a select gate line coupled to the select gate transistor at the first time, wherein the seventh voltage is higher than the third voltage; and The third voltage is applied to the select gate line at the third time.

12. The memory device according to claim 10 or 11, wherein: The operations further include: An eighth voltage is applied to the source line of the memory cell array at the first time.

13. The memory device according to claim 12, wherein: The eighth voltage is equal to the third voltage.

14. The memory device according to any one of claims 10 to 13, wherein: The memory cell array includes a first stack of memory cells and a second stack of memory cells, the first stack being adjacent to the second stack, the first memory cell being located in the first stack, and the operations further include: A sixth voltage is applied to a fifth word line coupled to a memory cell in the first stack that is closest to the second stack at the first time, wherein the fifth word line is a second dummy word line.

15. The memory device of claim 14, wherein: The operations further include: The sixth voltage is applied to a sixth word line coupled to a memory cell in the second stack that is closest to the first stack at the first time, wherein the sixth word line is a third dummy word line.

16. The memory device according to any one of claims 1 to 15, wherein: The first memory cell is a multi-level cell, and the programming operation of the first memory cell is a coarse programming operation.

17. The memory device according to any one of claims 1 to 7 or 10 to 15, wherein: The first memory cell is a multi-level cell, the programming operation of the first memory cell is a fine programming operation, and the operation further comprises: applying the first voltage to a seventh word line coupled to a second memory cell in the memory cell array at the first time, wherein the seventh word line is adjacent to the first word line; and The second voltage is applied to the seventh word line at the second time.

18. A memory system comprising: A memory device comprising: a memory cell array comprising memory cells; and A peripheral circuit coupled to the memory cell array and configured to perform operations comprising: applying a first voltage to a first word line coupled to a first memory cell in the memory cell array at a first time and during a channel preparation period of a programming operation of the first memory cell; applying a second voltage to the first word line at a second time after the first time and during the channel preparation period, wherein the second voltage is lower than the first voltage; and applying a program voltage to the first word line after the channel preparation period and during a program operation of the first memory cell; and A controller is coupled to the memory device and is configured to send a signal to the memory device to initiate the programming operation.

19. A method comprising: applying a first voltage to a first word line coupled to a first memory cell in a memory cell array at a first time and during a channel preparation period of a programming operation of the first memory cell; applying a second voltage to the first word line at a second time after the first time and during the channel preparation period, wherein the second voltage is lower than the first voltage; as well as A program voltage is applied to the first word line after the channel preparation period and during the program operation of the first memory cell.

20. The method according to claim 19, wherein: The first voltage is lower than the programming voltage.

21. The method according to claim 19 or 20, further comprising: A third voltage is applied to the first word line before the first time, wherein the third voltage is lower than the first voltage.

22. The method according to claim 21, wherein: The third voltage is lower than or equal to the second voltage.

23. The method according to any one of claims 19 to 22, further comprising: applying the first voltage to a second word line coupled to one or more memory cells in the memory cell array at the first time, wherein each of the one or more memory cells is a programmed memory cell; and A fourth voltage is applied to the second word line at the second time.

24. The method according to claim 23, wherein: The first voltage is lower than a pass voltage to be applied to the second word line after the second time.

25. The method according to claim 23 or 24, wherein: The fourth voltage is lower than or equal to the second voltage.

26. The method according to claim 21 or 22, further comprising: applying a sixth voltage to a fourth word line coupled to a memory cell adjacent to a select gate transistor coupled to a source line of the memory cell array at the first time, wherein the sixth voltage is higher than the third voltage and the fourth word line is a first dummy word line; and A third voltage is applied to the fourth word line at a third time after the second time.

27. The method according to claim 26, wherein: The memory cell array includes a first stack of memory cells and a second stack of memory cells, the first stack being adjacent to the second stack, the first memory cell being located in the first stack, and the method further comprising: The sixth voltage is applied to a fifth word line coupled to a memory cell in the first stack that is closest to the second stack at the first time, wherein the fifth word line is a second dummy word line.

28. The method of claim 27, further comprising: The sixth voltage is applied to a sixth word line coupled to a memory cell in the second stack that is closest to the first stack at the first time, wherein the sixth word line is a third dummy word line.

29. The method according to any one of claims 19 to 28, wherein: The first memory cell is a multi-level cell, and the programming operation of the first memory cell is a coarse programming operation.

30. The method according to any one of claims 19 to 28, wherein: The first memory cell is a multi-level cell, the programming operation of the first memory cell is a fine programming operation, and the method further comprises: applying the first voltage to a seventh word line coupled to a second memory cell in the memory cell array at the first time, wherein the seventh word line is adjacent to the first word line; and The second voltage is applied to the seventh word line at the second time.

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