Shifting register, driving method thereof and gate driving circuit

Abstract

The invention provides a shift register, a driving method thereof and a gate driving circuit, relates to the technical field of display, and aims to solve the problem of Mura risk caused by difference between pixel light-emitting time and charging time due to slow reset speed of a gate driving signal output end of the shift register. The shift register comprises a coupling node, a control node, a first output node, a first output circuit and a first coupling control circuit, the first output circuit is used for controlling the connection or disconnection of the electric connection between the first first level signal input end and the gate driving signal output end under the control of the potential of the first output node; the first coupling control circuit is used for controlling the connection or disconnection of the electric connection between the coupling node and the clock signal input end under the control of the potential of the control node; the potential of the first output node is controlled according to the potential of the coupling node.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register and a driving method thereof, and a gate driving circuit. Background Art

[0002] In order to reduce the driving power consumption of display products, low-frequency or variable-frequency driving methods are generally used to drive display products. When using the above driving method, the pixel circuit in the display product requires a relatively high retention capability, and LTPO technology is generally used, that is, replacing the leakage-sensitive switching transistor in the pixel circuit with an oxide transistor. However, when driving the pixel driving circuit of the above structure, the gate drive signal output end of the shift register resets slowly, resulting in differences in the pixel light emission time and charging time, bringing the risk of Mura. Summary of the invention

[0003] The object of the present invention is to provide a shift register and a driving method thereof, and a gate driving circuit, which are used to improve the problem of Mura risk caused by the difference in pixel light emitting time and charging time due to the slow reset speed of the gate driving signal output end of the shift register.

[0004] In order to achieve the above object, the present invention provides the following technical solutions:

[0005] A first aspect of the present invention provides a shift register, comprising: a coupling node, a control node, a first output node, a first output circuit and a first coupling control circuit;

[0006] The first output circuit is coupled to the first output node, the first first level signal input terminal and the gate drive signal output terminal of the shift register respectively; and is used to control the conduction or disconnection of the electrical connection between the first first level signal input terminal and the gate drive signal output terminal under the control of the potential of the first output node;

[0007] The first coupling control circuit is coupled to the coupling node, the control node, the first output node and the clock signal input terminal respectively; the first coupling control circuit is used to control the conduction or disconnection of the electrical connection between the coupling node and the clock signal input terminal under the control of the potential of the control node; and is also used to control the potential of the first output node according to the potential of the coupling node.

[0008] Optionally, the control node is directly coupled to the first output node; the first coupling control circuit includes a first control subcircuit and a first coupling subcircuit;

[0009] The first control subcircuit is coupled to the first output node, the coupling node and the clock signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the coupling node and the clock signal input terminal under the control of the potential of the first output node;

[0010] The first coupling subcircuit is coupled to the coupling node and the first output node respectively, and is used to control the potential of the first output node according to the potential of the coupling node.

[0011] Optionally, the first control subcircuit includes a fourth transistor, and the first coupling subcircuit includes a third capacitor;

[0012] The gate of the fourth transistor is coupled to the first output node, the first electrode of the fourth transistor is coupled to the clock signal input terminal, and the second electrode of the fourth transistor is coupled to the coupling node;

[0013] A first plate of the third capacitor is coupled to the coupling node, and a second plate of the third capacitor is coupled to the first output node.

[0014] Optionally, the first coupling control circuit includes a second control subcircuit, a third control subcircuit and a second coupling subcircuit;

[0015] The second control subcircuit is coupled to the control node, the coupling node and the clock signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the coupling node and the clock signal input terminal under the control of the potential of the control node;

[0016] The third control subcircuit is coupled to the control node and the first output node respectively, and is used to control the conduction or disconnection of the electrical connection between the control node and the first output node under the control of the potential of the control node;

[0017] The second coupling subcircuit is coupled to the coupling node and the control node respectively, and is used to control the potential of the control node according to the potential of the coupling node.

[0018] Optionally, the second control subcircuit includes a fourth transistor, a gate of the fourth transistor is coupled to the control node, a first electrode of the fourth transistor is coupled to the clock signal input terminal, and a second electrode of the fourth transistor is coupled to the coupling node;

[0019] The third control subcircuit includes a sixteenth transistor, a gate of the sixteenth transistor is coupled to the control node, a first electrode of the sixteenth transistor is coupled to the control node, and a second electrode of the sixteenth transistor is coupled to the first output node;

[0020] The second coupling subcircuit includes a third capacitor, a first plate of the third capacitor is coupled to the coupling node, and a second plate of the third capacitor is coupled to the control node.

[0021] Optionally, the shift register further includes: a first input circuit, a first transmission circuit, a second input circuit, a second transmission circuit, a first pull-down node, and a second pull-down node;

[0022] The first input circuit is coupled to the clock signal input terminal, the input signal terminal, and the first pull-down node respectively, and is used to control the conduction or disconnection of the electrical connection between the input signal terminal and the first pull-down node under the control of the clock signal input to the clock signal input terminal;

[0023] The first transmission circuit is coupled to the second first-level signal input terminal, the first pull-down node and the first output node respectively, and is used to open or close the electrical connection between the first pull-down node and the first output node under the control of the first-level signal inputted from the second first-level signal input terminal;

[0024] The second input circuit is coupled to the clock signal input terminal, the input signal terminal, and the second pull-down node respectively, and is used to control the conduction or disconnection of the electrical connection between the input signal terminal and the second pull-down node under the control of the clock signal input to the clock signal input terminal;

[0025] The second transmission circuit is coupled to the second first-level signal input terminal, the second pull-down node and the control node respectively, and is used to turn on or off the electrical connection between the second pull-down node and the control node under the control of the first-level signal input to the second first-level signal input terminal.

[0026] Optionally, the first input circuit includes a first transistor, a gate of the first transistor is coupled to the clock signal input terminal, a first electrode of the first transistor is coupled to the input signal terminal, and a second electrode of the first transistor is coupled to the first pull-down node;

[0027] The first transmission circuit includes a twelfth transistor, a gate of the twelfth transistor is coupled to the second first level signal input terminal, a first electrode of the twelfth transistor is coupled to the first pull-down node, and a second electrode of the twelfth transistor is coupled to the first output node;

[0028] The second input circuit comprises a fourteenth transistor, a gate of the fourteenth transistor is coupled to the clock signal input terminal, a first electrode of the fourteenth transistor is coupled to the input signal terminal, and a second electrode of the fourteenth transistor is coupled to the second pull-down node;

[0029] The second transmission circuit includes a fifteenth transistor, a gate of the fifteenth transistor is coupled to the second first-level signal input terminal, a first electrode of the fifteenth transistor is coupled to the second pull-down node, and a second electrode of the fifteenth transistor is coupled to the control node.

[0030] Optionally, the shift register further includes a second output node, a second output circuit and a second coupling control circuit;

[0031] The second output circuit is coupled to the second output node, the first second level signal input terminal and the gate drive signal output terminal of the shift register respectively; and is used to control the conduction or disconnection of the electrical connection between the first second level signal input terminal and the gate drive signal output terminal under the control of the potential of the second output node;

[0032] The second coupling control circuit is coupled to the second output node, the second second-level signal input terminal and the coupling node respectively, and is used to control the conduction or disconnection of the electrical connection between the second second-level signal input terminal and the coupling node under the control of the potential of the second output node.

[0033] Optionally, the second coupling control circuit includes a fifth transistor, a gate of the fifth transistor is coupled to the second output node, a first electrode of the fifth transistor is coupled to the second second-level signal input terminal, and a second electrode of the fifth transistor is coupled to the coupling node;

[0034] The second output circuit includes a ninth transistor, a gate of the ninth transistor is coupled to the second output node, a first electrode of the ninth transistor is coupled to the first second level signal input terminal, and a second electrode of the ninth transistor is coupled to the gate drive signal output terminal.

[0035] Optionally, the shift register further includes a first input circuit, a first pull-down node and a first output node control circuit;

[0036] The first input circuit is coupled to the clock signal input terminal, the input signal terminal and the first pull-down node respectively, and is used to control the conduction or disconnection of the electrical connection between the input signal terminal and the first pull-down node under the control of the clock signal input to the clock signal input terminal;

[0037] The first output node control circuit is coupled to the first pull-down node, the second second-level signal input terminal and the second output node respectively, and is used to control the conduction or disconnection of the electrical connection between the second second-level signal input terminal and the second output node under the control of the potential of the first pull-down node.

[0038] Optionally, the first input circuit includes a first transistor, a gate of the first transistor is coupled to the clock signal input terminal, a first electrode of the first transistor is coupled to the input signal terminal, and a second electrode of the first transistor is coupled to the first pull-down node;

[0039] The first output node control circuit includes an eighth transistor, a gate of the eighth transistor is coupled to the first pull-down node, a first electrode of the eighth transistor is coupled to the second second-level signal input terminal, and a second electrode of the eighth transistor is coupled to the second output node.

[0040] Optionally, the shift register also includes a first output node control circuit, which is respectively coupled to the input signal terminal, the second second-level signal input terminal and the second output node, and is used to control the conduction or disconnection of the electrical connection between the second second-level signal input terminal and the second output node under the control of the signal input at the input signal terminal.

[0041] Optionally, the first output node control circuit includes an eighth transistor, a gate of the eighth transistor is coupled to the input signal terminal, a first electrode of the eighth transistor is coupled to the second second-level signal input terminal, and a second electrode of the eighth transistor is coupled to the second output node.

[0042] Optionally, the shift register further includes: a first input circuit, a first transmission circuit and a first pull-down node;

[0043] The first input circuit is coupled to the clock signal input terminal, the input signal terminal, and the first pull-down node respectively, and is used to control the conduction or disconnection of the electrical connection between the input signal terminal and the first pull-down node under the control of the clock signal input to the clock signal input terminal;

[0044] The first transmission circuit is coupled to the second first-level signal input terminal, the first pull-down node and the first output node respectively, and is used to open or close the electrical connection between the first pull-down node and the first output node under the control of the first-level signal inputted from the second first-level signal input terminal;

[0045] The clock signal input terminal coupled to the first coupling control circuit and the clock signal input terminal coupled to the first input circuit input the same clock signal.

[0046] Optionally, the shift register further includes: a first input circuit, a first transmission circuit and a first pull-down node;

[0047] The first input circuit is coupled to the clock signal input terminal, the input signal terminal, and the first pull-down node respectively, and is used to control the conduction or disconnection of the electrical connection between the input signal terminal and the first pull-down node under the control of the clock signal input to the clock signal input terminal;

[0048] The first transmission circuit is coupled to the second first-level signal input terminal, the first pull-down node and the first output node respectively, and is used to open or close the electrical connection between the first pull-down node and the first output node under the control of the first-level signal inputted from the second first-level signal input terminal;

[0049] The clock signal input to the clock signal input terminal coupled to the first coupling control circuit has a preset delay relative to the clock signal input to the clock signal input terminal coupled to the first input circuit.

[0050] Optionally, the first input circuit includes a first transistor, a gate of the first transistor is coupled to the clock signal input terminal, a first electrode of the first transistor is coupled to the input signal terminal, and a second electrode of the first transistor is coupled to the first pull-down node;

[0051] The first transmission circuit includes a twelfth transistor, a gate of the twelfth transistor is coupled to the second first-level signal input terminal, a first electrode of the twelfth transistor is coupled to the first pull-down node, and a second electrode of the twelfth transistor is coupled to the first output node.

[0052] Optionally, the shift register further includes: a first pull-up node, a second pull-up node, a third pull-up node, a first pull-up node control circuit, a second pull-up node control circuit, a third pull-up node control circuit, and a second output node control circuit;

[0053] The first pull-up node control circuit is coupled to the clock signal input terminal, the second first-level signal input terminal, the first pull-up node and the first pull-down node respectively; and is used to control the conduction or disconnection of the electrical connection between the second first-level signal input terminal and the first pull-up node under the control of the clock signal input terminal, and is also used to control the conduction or disconnection of the electrical connection between the clock signal input terminal and the first pull-up node under the control of the potential of the first pull-down node;

[0054] The second pull-up node control circuit is coupled to the second first level signal input terminal, the first pull-up node and the second pull-up node respectively, and is used to control the conduction or disconnection of the electrical connection between the first pull-up node and the second pull-up node under the control of the first level signal inputted from the second first level signal input terminal;

[0055] The third pull-up node control circuit is coupled to the second pull-up node, the third pull-up node and the inverted clock signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the inverted clock signal input terminal and the third pull-up node under the control of the potential of the second pull-up node, and is also used to control the potential of the third pull-up node under the control of the potential of the second pull-up node;

[0056] The second output node control circuit is coupled to the inverted clock signal input terminal, the third pull-up node and the second output node respectively, and is used to control the conduction or disconnection of the electrical connection between the third pull-up node and the second output node under the control of the inverted clock signal input to the inverted clock signal input terminal.

[0057] Optionally, the first pull-up node control circuit includes a second transistor and a third transistor, the gate of the second transistor is coupled to the first pull-down node, the first electrode of the second transistor is coupled to the clock signal input terminal, and the second electrode of the second transistor is coupled to the first pull-up node; the gate of the third transistor is coupled to the clock signal input terminal, the first electrode of the third transistor is coupled to the second first-level signal input terminal, and the second electrode of the third transistor is coupled to the first pull-up node;

[0058] The second pull-up node control circuit includes an eleventh transistor, a gate of the eleventh transistor is coupled to the second first level signal input terminal, a first electrode of the eleventh transistor is coupled to the first pull-up node, and a second electrode of the eleventh transistor is coupled to the second pull-up node;

[0059] The third pull-up node control circuit includes a sixth transistor and a first capacitor, the gate of the sixth transistor is coupled to the second pull-up node, the first electrode of the sixth transistor is coupled to the inverted clock signal input terminal, and the second electrode of the sixth transistor is coupled to the third pull-up node; the first plate of the first capacitor is coupled to the second pull-up node, and the second plate of the first capacitor is coupled to the third pull-up node;

[0060] The second output node control circuit includes a seventh transistor, a gate of the seventh transistor is coupled to the inverted clock signal input terminal, a first electrode of the seventh transistor is coupled to the third pull-up node, and a second electrode of the seventh transistor is coupled to the second output node.

[0061] Optionally, the shift register also includes a reset control circuit, which is coupled to the reset signal input terminal, the second second-level signal input terminal and the first pull-down node, respectively, and is used to control the conduction or disconnection of the electrical connection between the second second-level signal input terminal and the first pull-down node under the control of the reset signal input terminal.

[0062] Optionally, the reset control circuit includes a thirteenth transistor, a gate of the thirteenth transistor is coupled to the reset signal input terminal, a first electrode of the thirteenth transistor is coupled to the second second-level signal input terminal, and a second electrode of the thirteenth transistor is coupled to the first pull-down node.

[0063] Optionally, the first output circuit includes a tenth transistor, the gate of the tenth transistor is coupled to the first output node, the first electrode of the tenth transistor is coupled to the first first-level signal input terminal, and the second electrode of the tenth transistor is coupled to the gate drive signal output terminal of the shift register.

[0064] Optionally, a voltage value of the second level signal inputted by the second second level signal input terminal is greater than or equal to a voltage value of the second level signal inputted by the first second level signal input terminal; a voltage value of the first level signal inputted by the second first level signal input terminal is less than or equal to a voltage value of the first level signal inputted by the first first level signal input terminal;

[0065] The high level value of the clock signal input to the clock signal input terminal is the same as the voltage value of the second level signal input to the second second level signal input terminal, and the low level value of the clock signal input to the clock signal input terminal is the same as the voltage value of the first level signal input to the second first level signal input terminal.

[0066] Based on the technical solution of the above-mentioned shift register, a second aspect of the present invention provides a gate driving circuit, comprising a plurality of the above-mentioned shift registers connected in cascade.

[0067] Optionally, the gate drive circuit includes a first clock signal line, a second clock signal line, a first inverted clock signal line, and a second inverted clock signal line; a first clock signal transmitted by the first clock signal line is opposite in phase to a first inverted clock signal transmitted by the first inverted clock signal line; a second clock signal transmitted by the second clock signal line is opposite in phase to a second inverted clock signal transmitted by the second inverted clock signal line; and there is a preset delay between the second clock signal and the first clock signal;

[0068] In the odd-numbered shift register, the clock signal input terminal coupled to the first coupling control circuit is coupled to the first clock signal line or the second clock signal line;

[0069] In the even-numbered shift register, the clock signal input terminal coupled to the first coupling control circuit is coupled to the first inverted clock signal line or the second inverted clock signal line.

[0070] Optionally, in the odd-numbered shift register, the clock signal input terminal coupled to the first input circuit is coupled to the first clock signal line or the second clock signal line, the clock signal input terminal coupled to the third transistor in the first pull-up node control circuit is coupled to the first clock signal line or the second clock signal line, the clock signal input terminal coupled to the second transistor in the first pull-up node control circuit is coupled to the first clock signal line or the second clock signal line, the inverted clock signal input terminal coupled to the third pull-up node control circuit is coupled to the first inverted clock signal line or the second inverted clock signal line, and the inverted clock signal input terminal coupled to the second output node control circuit is coupled to the first inverted clock signal line or the second inverted clock signal line;

[0071] In the even-numbered shift register, the clock signal input terminal coupled by the first input circuit is coupled to the first inverted clock signal line or the second inverted clock signal line, the clock signal input terminal coupled by the third transistor in the first pull-up node control circuit is coupled to the first inverted clock signal line or the second inverted clock signal line, the clock signal input terminal coupled by the second transistor in the first pull-up node control circuit is coupled to the first inverted clock signal line or the second inverted clock signal line, the inverted clock signal input terminal coupled by the third pull-up node control circuit is coupled to the first clock signal line or the second clock signal line, and the inverted clock signal input terminal coupled by the second output node control circuit is coupled to the first clock signal line or the second clock signal line.

[0072] Based on the technical solution of the above shift register, the third aspect of the present invention provides a driving method of a shift register, which is used to drive the above shift register; the driving method comprises:

[0073] The first output circuit controls the electrical connection between the first first level signal input terminal and the gate drive signal output terminal to be turned on or off under the control of the potential of the first output node;

[0074] The first coupling control circuit controls the electrical connection between the coupling node and the clock signal input terminal to be turned on or off under the control of the potential of the control node; and is also used to control the potential of the first output node according to the potential of the coupling node.

[0075] Optionally, the control node is directly coupled to the first output node; the first coupling control circuit includes a first control subcircuit and a first coupling subcircuit;

[0076] The first control subcircuit controls the conduction or disconnection of the electrical connection between the coupling node and the clock signal input terminal under the control of the potential of the first output node;

[0077] The first coupling subcircuit controls the potential of the first output node according to the potential of the coupling node.

[0078] Optionally, the first coupling control circuit includes a second control subcircuit, a third control subcircuit and a second coupling subcircuit;

[0079] The second control subcircuit controls the conduction or disconnection of the electrical connection between the coupling node and the clock signal input terminal under the control of the potential of the control node;

[0080] The third control subcircuit controls the conduction or disconnection of the electrical connection between the control node and the first output node under the control of the potential of the control node;

[0081] The second coupling sub-circuit controls the potential of the control node according to the potential of the coupling node.

[0082] In the technical solution provided by the present invention, the first coupling control circuit can control the electrical connection between the coupling node and the clock signal input terminal to be turned on or off, so that the potential of the coupling node can be the same as the potential of the clock signal input by the clock signal input terminal; at the same time, the first coupling control circuit can control the potential of the first output node according to the potential of the coupling node; in this way, when resetting the gate drive signal output terminal, the clock signal input terminal can be controlled to input a signal with a suitable potential to control the coupling node to have a suitable potential, thereby controlling the potential of the first output node to be quickly pulled down, eliminating the step formed in the process of the potential of the first output node being pulled down, greatly shortening the reset time of the gate drive signal output terminal, realizing the rapid reset of the gate drive signal output terminal, enhancing the driving capability of the shift register, ensuring the pixel light emission time and charging time, and avoiding the Mura problem caused by the difference in pixel charging time or light emission time. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0084] Figure 1 A first structural schematic diagram of a shift register provided by an embodiment of the present invention;

[0085] Figure 2A second structural schematic diagram of a shift register provided by an embodiment of the present invention;

[0086] Figure 3 A third structural diagram of a shift register provided by an embodiment of the present invention;

[0087] Figure 4 A fourth structural diagram of a shift register provided by an embodiment of the present invention;

[0088] Figure 5 A fifth structural diagram of a shift register provided by an embodiment of the present invention;

[0089] Figure 6 A sixth structural diagram of a shift register provided by an embodiment of the present invention;

[0090] Figure 7 A seventh structural diagram of a shift register provided by an embodiment of the present invention;

[0091] Figure 8 An eighth structural diagram of a shift register provided by an embodiment of the present invention;

[0092] Fig. 9 A first circuit schematic diagram of a shift register provided by an embodiment of the present invention;

[0093] Fig.10 for Fig. 9 Corresponding working timing diagram;

[0094] Fig.11 A second circuit schematic diagram of a shift register provided by an embodiment of the present invention;

[0095] Fig.12 A third circuit schematic diagram of a shift register provided by an embodiment of the present invention;

[0096] Fig.13 A ninth structural diagram of a shift register provided by an embodiment of the present invention;

[0097] Fig.14 A tenth structural diagram of a shift register provided by an embodiment of the present invention;

[0098] Fig.15 An eleventh structural diagram of a shift register provided by an embodiment of the present invention;

[0099] Fig.16 A twelfth structural schematic diagram of a shift register provided by an embodiment of the present invention;

[0100] Fig.17 A thirteenth structural schematic diagram of a shift register provided by an embodiment of the present invention;

[0101] Fig.18 A fourteenth structural schematic diagram of a shift register provided by an embodiment of the present invention;

[0102] Fig.19 A fifteenth structural schematic diagram of a shift register provided by an embodiment of the present invention;

[0103] Fig. 20 A fourth circuit schematic diagram of a shift register provided by an embodiment of the present invention;

[0104] Fig.21 A fifth circuit schematic diagram of a shift register provided by an embodiment of the present invention;

[0105] Fig. 22 A sixth circuit schematic diagram of a shift register provided by an embodiment of the present invention;

[0106] Fig.23 To adopt Fig.11 A timing diagram of a signal output from a gate drive signal output terminal of a shift register when the circuit structure is as follows;

[0107] Fig.24 To adopt Fig.21 A timing diagram of a signal output from a gate drive signal output terminal of a shift register when the circuit structure is as follows;

[0108] Fig.25 A leakage current curve diagram of a ninth transistor in a shift register provided by an embodiment of the present invention;

[0109] Fig.26 A driving current curve diagram of the tenth transistor in the shift register provided by an embodiment of the present invention;

[0110] Fig. 27 A schematic diagram of cascading multiple shift registers provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0111] In order to further illustrate the shift register and its driving method and gate driving circuit provided by the embodiments of the present invention, a detailed description is given below in conjunction with the accompanying drawings.

[0112] See also Figure 1 and Fig. 9 , an embodiment of the present invention provides a shift register, comprising: a coupling node PD_c, a control node K1, a first output node PD_out, a first output circuit 10 and a first coupling control circuit 11;

[0113] The first output circuit 10 is coupled to the first output node PD_out, the first first level signal input terminal VGL1 and the gate drive signal output terminal Eout of the shift register respectively; and is used to control the conduction or disconnection of the electrical connection between the first first level signal input terminal VGL1 and the gate drive signal output terminal Eout under the control of the potential of the first output node PD_out;

[0114] The first coupling control circuit 11 is coupled to the coupling node PD_c, the control node K1, the first output node PD_out and the clock signal input terminal (the clock signal input terminal is used to input the first clock signal CK1 or the second clock signal CK2, and there is a preset delay between the second clock signal CK2 and the first clock signal CK1) respectively; the first coupling control circuit 11 is used to control the conduction or disconnection of the electrical connection between the coupling node PD_c and the clock signal input terminal under the control of the potential of the control node K1; and is also used to control the potential of the first output node PD_out according to the potential of the coupling node PD_c.

[0115] Exemplarily, the first output circuit 10 includes a tenth transistor T10, a gate of the tenth transistor T10 is coupled to the first output node PD_out, a first electrode of the tenth transistor T10 is coupled to the first first-level signal input terminal VGL1, and a second electrode of the tenth transistor T10 is coupled to the gate drive signal output terminal Eout of the shift register.

[0116] Exemplarily, the first level signal inputted by the first first level signal input terminal VGL1 includes a low level signal, but is not limited thereto. The gate driving signal output terminal Eout is coupled to a corresponding driven pixel circuit.

[0117] Exemplarily, the potential of the control node K1 is associated with the potential of the first output node PD_out, and the potential of the first output node PD_out can follow the change of the potential of the control node K1.

[0118] Exemplarily, when the first coupling control circuit 11 controls the electrical connection between the coupling node PD_c and the clock signal input terminal under the control of the potential of the control node K1, the potential of the coupling node PD_c is the same as the potential of the clock signal input to the clock signal input terminal, and the first coupling control circuit 11 controls the potential of the first output node PD_out according to the potential of the coupling node PD_c, so that the potential of the first output node PD_out can change with the change of the potential of the coupling node PD_c, thereby realizing the adjustment of the potential of the first output node PD_out.

[0119] Exemplarily, the shift register may be used in an EM GOA (light emission control shift register), an oxide transistor, and a GOA circuit (gate drive circuit) controlled by a low brush switch.

[0120] According to the specific structure of the above-mentioned shift register, in the shift register provided by the embodiment of the present invention, the first coupling control circuit 11 can control the electrical connection between the coupling node PD_c and the clock signal input terminal to be turned on or off, so that the potential of the coupling node PD_c can be the same as the potential of the clock signal input by the clock signal input terminal; at the same time, the first coupling control circuit 11 can control the potential of the first output node PD_out according to the potential of the coupling node PD_c; in this way, when resetting the gate drive signal output terminal Eout, the clock signal input terminal can be controlled to input a signal with a suitable potential to control the coupling node to have a suitable potential, thereby controlling the potential of the first output node PD_out to be quickly pulled down, eliminating the step formed in the process of the potential of the first output node PD_out being pulled down, greatly shortening the reset time of the gate drive signal output terminal Eout, realizing the rapid reset of the gate drive signal output terminal Eout, enhancing the driving capability of the shift register, ensuring the pixel light emission time and charging time, and avoiding the Mura problem caused by the difference in pixel charging time or light emission time.

[0121] like Figure 2 , Figure 3 and Fig. 9 As shown, in some embodiments, the control node K1 is directly coupled to the first output node PD_out; the first coupling control circuit 11 includes a first control subcircuit 110 and a first coupling subcircuit 111;

[0122] The first control subcircuit 110 is coupled to the first output node PD_out, the coupling node PD_c and the clock signal input terminal respectively, and is used to control the electrical connection between the coupling node PD_c and the clock signal input terminal to be turned on or off under the control of the potential of the first output node PD_out;

[0123] The first coupling sub-circuit 111 is coupled to the coupling node PD_c and the first output node PD_out, respectively, and is used to control the potential of the first output node PD_out according to the potential of the coupling node PD_c.

[0124] Exemplarily, the first control subcircuit 110 includes a fourth transistor T4, and the first coupling subcircuit 111 includes a third capacitor C3; the gate of the fourth transistor T4 is coupled to the first output node PD_out, the first electrode of the fourth transistor T4 is coupled to the clock signal input terminal, and the second electrode of the fourth transistor T4 is coupled to the coupling node PD_c; the first plate of the third capacitor C3 is coupled to the coupling node PD_c, and the second plate of the third capacitor C3 is coupled to the first output node PD_out.

[0125] Setting the first coupling control circuit 11 to adopt the above structure can not only achieve the beneficial effects of quickly resetting the gate drive signal output terminal Eout and enhancing the driving capability of the shift register, but also help simplify the circuit structure of the shift register.

[0126] In more detail, compared with the prior art, when the first coupling control circuit 11 is configured to adopt the above structure, under the same load condition, the reset time of the gate drive signal output terminal Eout is greatly reduced through simulation. Fig.23 As shown, the reset time is reduced from 5.83 μs (solid line) to 0.32 μs (dashed line).

[0127] like Fig.13 and Fig. 20 As shown, in some embodiments, the first coupling control circuit 11 includes a second control subcircuit 112, a third control subcircuit 113 and a second coupling subcircuit 114;

[0128] The second control subcircuit 112 is coupled to the control node K1, the coupling node PD_c and the clock signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the coupling node PD_c and the clock signal input terminal under the control of the potential of the control node K1;

[0129] The third control subcircuit 113 is coupled to the control node K1 and the first output node PD_out respectively, and is used to control the conduction or disconnection of the electrical connection between the control node K1 and the first output node PD_out under the control of the potential of the control node K1;

[0130] The second coupling sub-circuit 114 is coupled to the coupling node PD_c and the control node K1 respectively, and is used to control the potential of the control node K1 according to the potential of the coupling node PD_c.

[0131] Exemplarily, the second control subcircuit 112 includes a fourth transistor T4, a gate of the fourth transistor T4 is coupled to the control node K1, a first electrode of the fourth transistor T4 is coupled to the clock signal input terminal, and a second electrode of the fourth transistor T4 is coupled to the coupling node PD_c;

[0132] The third control subcircuit 113 includes a sixteenth transistor T16, a gate of the sixteenth transistor T16 is coupled to the control node K1, a first electrode of the sixteenth transistor T16 is coupled to the control node K1, and a second electrode of the sixteenth transistor T16 is coupled to the first output node PD_out. The sixteenth transistor T16 is coupled in the above manner to form a diode structure.

[0133] The second coupling sub-circuit 114 includes a third capacitor C3 , a first plate of the third capacitor C3 is coupled to the coupling node PD_c, and a second plate of the third capacitor C3 is coupled to the control node K1 .

[0134] When the first coupling control circuit 11 is configured to adopt the above structure, the sixteenth transistor T16 forms a structure with a diode function, and the coupling node PD_c and the first output node PD_out are indirectly coupled through the diode structure, which is conducive to better improving the working stability of the first output node PD_out and reducing the adverse interference of the first output node PD_out. At the same time, the first coupling control circuit 11 adopts the above structure, which can achieve the beneficial effects of quickly resetting the gate drive signal output terminal Eout and enhancing the driving ability of the shift register.

[0135] In more detail, compared with the prior art, when the first coupling control circuit 11 is configured to adopt the above structure, under the same load condition, the reset time of the gate drive signal output terminal Eout is greatly reduced through simulation. Fig.24 As shown, the reset time is reduced from 1.07 μs (solid line) to 0.45 μs (dashed line).

[0136] like Fig.14 As shown, in some embodiments, the shift register further includes: a first input circuit 12, a first transmission circuit 13, a second input circuit 14, a second transmission circuit 15, a first pull-down node PD_in1 and a second pull-down node PD_in2;

[0137] The first input circuit 12 is coupled to the clock signal input terminal, the input signal terminal ESTV, and the first pull-down node PD_in1 respectively, and is used to control the conduction or disconnection of the electrical connection between the input signal terminal ESTV and the first pull-down node PD_in1 under the control of the clock signal inputted from the clock signal input terminal;

[0138] The first transmission circuit 13 is respectively coupled to the second first level signal input terminal VGL2, the first pull-down node PD_in1 and the first output node PD_out, and is used to open or close the electrical connection between the first pull-down node PD_in1 and the first output node PD_out under the control of the first level signal input by the second first level signal input terminal VGL2;

[0139] The second input circuit 14 is coupled to the clock signal input terminal, the input signal terminal ESTV, and the second pull-down node PD_in2 respectively, and is used to control the conduction or disconnection of the electrical connection between the input signal terminal ESTV and the second pull-down node PD_in2 under the control of the clock signal inputted from the clock signal input terminal;

[0140] The second transmission circuit 15 is coupled to the second first-level signal input terminal VGL2, the second pull-down node PD_in2 and the control node K1, respectively, and is used to turn on or off the electrical connection between the second pull-down node PD_in2 and the control node K1 under the control of the first-level signal input to the second first-level signal input terminal VGL2.

[0141] like Fig. 20 As shown, illustratively, the first input circuit 12 includes a first transistor T1, a gate of the first transistor T1 is coupled to the clock signal input terminal, a first electrode of the first transistor T1 is coupled to the input signal terminal ESTV, and a second electrode of the first transistor T1 is coupled to the first pull-down node PD_in1;

[0142] The first transmission circuit 13 includes a twelfth transistor T12, a gate of the twelfth transistor T12 is coupled to the second first level signal input terminal VGL2, a first electrode of the twelfth transistor T12 is coupled to the first pull-down node PD_in1, and a second electrode of the twelfth transistor T12 is coupled to the first output node PD_out;

[0143] The second input circuit 14 includes a fourteenth transistor T14, a gate of the fourteenth transistor T14 is coupled to the clock signal input terminal, a first electrode of the fourteenth transistor T14 is coupled to the input signal terminal ESTV, and a second electrode of the fourteenth transistor T14 is coupled to the second pull-down node PD_in2;

[0144] The second transmission circuit 15 includes a fifteenth transistor T15, a gate of the fifteenth transistor T15 is coupled to the second first level signal input terminal VGL2, a first electrode of the fifteenth transistor T15 is coupled to the second pull-down node PD_in2, and a second electrode of the fifteenth transistor T15 is coupled to the control node K1.

[0145] Exemplarily, the clock signal input terminal simultaneously controls the on or off of the first transistor T1 and the fourteenth transistor T14, and the second first level signal input terminal VGL2 simultaneously controls the on or off of the twelfth transistor T12 and the fifteenth transistor T15.

[0146] The above-mentioned setting method enables the second input circuit 14 and the second transmission circuit 15 to form a supplementary branch, so that there are two branches between the input signal terminal ESTV and the first output node PD_out. This is not only conducive to improving the stability of signal transmission between the input signal terminal ESTV and the first output node PD_out, but also provides conditions for realizing indirect coupling between the control node K1 and the first output node PD_out.

[0147] like Figure 4 , Fig.15 , Fig. 9 and Fig. 20 As shown, in some embodiments, the shift register further includes a second output node PU_out, a second output circuit 16 and a second coupling control circuit 17;

[0148] The second output circuit 16 is coupled to the second output node PU_out, the first second level signal input terminal VGH1 and the gate drive signal output terminal Eout of the shift register respectively; and is used to control the conduction or disconnection of the electrical connection between the first second level signal input terminal VGH1 and the gate drive signal output terminal Eout under the control of the potential of the second output node PU_out;

[0149] The second coupling control circuit 17 is coupled to the second output node PU_out, the second second-level signal input terminal VGH2 and the coupling node PD_c, respectively, and is used to control the conduction or disconnection of the electrical connection between the second second-level signal input terminal VGH2 and the coupling node PD_c under the control of the potential of the second output node PU_out.

[0150] Exemplarily, the second coupling control circuit 17 includes a fifth transistor T5, a gate of the fifth transistor T5 is coupled to the second output node PU_out, a first electrode of the fifth transistor T5 is coupled to the second second level signal input terminal VGH2, and a second electrode of the fifth transistor T5 is coupled to the coupling node PD_c;

[0151] The second output circuit 16 includes a ninth transistor T9, a gate of the ninth transistor T9 is coupled to the second output node PU_out, a first electrode of the ninth transistor T9 is coupled to the first second level signal input terminal VGH1, and a second electrode of the ninth transistor T9 is coupled to the gate drive signal output terminal Eout.

[0152] Exemplarily, the second output circuit 16 further includes a second capacitor C2, a first plate of the second capacitor C2 is coupled to the second output node PU_out, and a second plate of the second capacitor C2 is coupled to the first second level signal input terminal VGH1.

[0153] Exemplarily, the second level signal inputted by the second second level signal input terminal VGH2 includes a high level signal, but is not limited thereto.

[0154] When the second coupling control circuit 17 controls the electrical connection between the second second-level signal input terminal VGH2 and the coupling node PD_c under the control of the potential of the second output node PU_out, the coupling node PD_c has the same potential as the second level signal input by the second level signal input terminal, so that the first coupling control circuit 11 can couple and control the potential of the first output node PD_out according to the potential of the second level signal, thereby controlling the working state of the first output circuit 10.

[0155] The second coupling control circuit 17 and the first coupling control circuit 11 together form a coupling voltage structure, which can control the coupling node PD_c to have a corresponding potential in different time periods, and then control the first output node PD_out to have a corresponding potential through the coupling effect of the first coupling control circuit 11. This structure can achieve the potential of the first output node PD_out to be pulled up when the gate drive signal output terminal Eout is not reset, and control the tenth transistor T10 in the first output circuit 10 to be turned off, and can achieve the potential of the first output node PD_out to be quickly pulled down when the gate drive signal output terminal Eout is reset, and control the tenth transistor T10 in the first output circuit 10 to be turned on, so as to achieve the rapid reset of the gate drive signal output terminal Eout, enhance the driving ability of the shift register and other beneficial effects.

[0156] The first first-level signal input terminal VGL1 and the second first-level signal input terminal VGL2 coupled to the shift register both input low-level signals, and the level value of the first-level signal input to the second first-level signal input terminal VGL2 is less than or equal to the level value of the first-level signal input to the first first-level signal input terminal VGL1. For example, the voltage difference between the level value of the first-level signal input to the second first-level signal input terminal VGL2 and the level value of the first-level signal input to the first first-level signal input terminal VGL1 is approximately the threshold voltage of the tenth transistor T10.

[0157] The first second-level signal input terminal VGH1 and the second second-level signal input terminal VGH2 coupled to the shift register both input a high-level signal, and the level value of the second-level signal input to the second second-level signal input terminal VGH2 is greater than or equal to the level value of the second-level signal input to the first second-level signal input terminal VGH1. For example, the voltage difference between the level value of the second-level signal input to the second second-level signal input terminal VGH2 and the level value of the second-level signal input to the first second-level signal input terminal VGH1 is approximately the threshold voltage of the ninth transistor T9.

[0158] The high level of the clock signal inputted by the clock signal input terminal coupled to the above shift register is the same as the second level signal inputted by the second second level signal input terminal VGH2, and the low level of the clock signal inputted by the clock signal input terminal coupled to the above shift register is the same as the first level signal inputted by the second first level signal input terminal VGL2. The above shift register adopts two first level signal input terminals and two second level signal input terminals to realize power supply, which can better meet the power supply demand of the shift register, improve the overall working performance of the shift register, and ensure the stability of the gate drive signal outputted by the shift register. At the same time, it is helpful to reduce the output reset attenuation problem caused by the threshold voltage drop of the transistor, thereby ensuring the rapid reset of the gate drive signal output terminal and enhancing the driving capability of the shift register.

[0159] like Figure 5 and Fig.16 As shown, in some embodiments, the shift register further includes a first input circuit 12, a first pull-down node PD_in1 and a first output node control circuit 18;

[0160] The first input circuit 12 is coupled to the clock signal input terminal, the input signal terminal ESTV and the first pull-down node PD_in1 respectively, and is used to control the conduction or disconnection of the electrical connection between the input signal terminal ESTV and the first pull-down node PD_in1 under the control of the clock signal inputted from the clock signal input terminal;

[0161] The first output node control circuit 18 is coupled to the first pull-down node PD_in1, the second second-level signal input terminal VGH2 and the second output node PU_out, respectively, and is used to control the conduction or disconnection of the electrical connection between the second second-level signal input terminal VGH2 and the second output node PU_out under the control of the potential of the first pull-down node PD_in1.

[0162] like Fig. 9 and Fig. 20 As shown, illustratively, the first input circuit 12 includes a first transistor T1, a gate of the first transistor T1 is coupled to the clock signal input terminal, a first electrode of the first transistor T1 is coupled to the input signal terminal ESTV, and a second electrode of the first transistor T1 is coupled to the first pull-down node PD_in1;

[0163] The first output node control circuit 18 includes an eighth transistor T8, a gate of the eighth transistor T8 is coupled to the first pull-down node PD_in1, a first electrode of the eighth transistor T8 is coupled to the second second-level signal input terminal VGH2, and a second electrode of the eighth transistor T8 is coupled to the second output node PU_out.

[0164] The shift register is configured as described above to include the first output node control circuit 18, so that the first output node control circuit 18 can control the electrical connection between the second second-level signal input terminal VGH2 and the second output node PU_out to be turned on or off under the control of the potential of the first pull-down node PD_in1, thereby controlling the potential of the second output node PU_out. In more detail, when the potential of the first pull-down node PD_in1 is at a low level, the potential of the first output node PD_out is at a low level, and the tenth transistor T10 is controlled to be turned on; at the same time, the first pull-down node PD_in1 controls the eighth transistor T8 to be turned on, and controls the potential of the second output node PU_out to be the same as the potential of the second-level signal input by the second second-level signal input terminal VGH2, thereby controlling the ninth transistor T9 to be turned off, and ensuring the normal output of the gate drive signal output terminal Eout.

[0165] like Figure 6 and Fig.17 As shown, in some embodiments, the shift register also includes a first output node control circuit 18, which is respectively coupled to the input signal terminal ESTV, the second second-level signal input terminal VGH2 and the second output node PU_out, and is used to control the conduction or disconnection of the electrical connection between the second second-level signal input terminal VGH2 and the second output node PU_out under the control of the signal input at the input signal terminal ESTV.

[0166] Exemplarily, the first output node control circuit 18 includes an eighth transistor T8, a gate of the eighth transistor T8 is coupled to the input signal terminal ESTV, a first electrode of the eighth transistor T8 is coupled to the second second-level signal input terminal VGH2, and a second electrode of the eighth transistor T8 is coupled to the second output node PU_out.

[0167] The above-mentioned setting of the shift register includes the first output node control circuit 18, so that the first output node control circuit 18 can control the conduction or disconnection of the electrical connection between the second second-level signal input terminal VGH2 and the second output node PU_out under the control of the potential of the input signal terminal ESTV, thereby controlling the potential of the second output node PU_out.

[0168] In more detail, when the potential of the input signal terminal ESTV is at a low level, the eighth transistor T8 is controlled to be turned on, and the potential of the second output node PU_out is controlled to be the same as the potential of the second level signal input by the second second level signal input terminal VGH2, thereby controlling the ninth transistor T9 to be turned off. Then, when the potential of the first pull-down node PD_in1 is at a low level, the potential of the first output node PD_out is at a low level, and the tenth transistor T10 is controlled to be turned on, thereby ensuring the normal output of the gate drive signal output terminal Eout.

[0169] By controlling the first output node control circuit 18 through the input signal terminal ESTV, the second output node PU_out can be pulled up in advance, the ninth transistor T9 is turned off first, and then the tenth transistor T10 is turned on. This method effectively avoids direct conduction between the first second level signal input terminal VGH1 coupled to the ninth transistor T9 and the first first level signal input terminal VGL1 coupled to the tenth transistor T10, which can greatly reduce the power consumption of the shift register.

[0170] Specific as Fig.25 and Fig.26 When the input signal terminal ESTV is used to control the first output node control circuit 18, when the gate drive signal output terminal Eout is reset, the current of the driving transistor (ie, the ninth transistor T9 and the tenth transistor T10) is significantly reduced.

[0171] like Fig.25 As shown, the solid line represents the leakage current of the ninth transistor T9 when the gate drive signal output terminal Eout is reset when the first pull-down node PD_in1 is used to control the first output node control circuit 18, and the dotted line represents the leakage current of the ninth transistor T9 when the gate drive signal output terminal Eout is reset when the input signal terminal ESTV is used to control the first output node control circuit 18. It can be seen that when the gate drive signal output terminal Eout is reset when the input signal terminal ESTV is used to control the first output node control circuit 18, the leakage current of the ninth transistor T9 is almost eliminated. It should be noted that Fig.25 The position of the dotted line in the middle represents 100nA, which is close to 0A. Therefore, the position of the dotted line can be understood as the leakage current is almost eliminated, while the position of the solid line has a larger leakage current. The magnitude of the leakage current can also be viewed by the integral area. Taking the horizontal line where 100nA is located as the baseline, the dotted line overlaps with the baseline, and the integral area is 0. The area enclosed between the solid line and the baseline is the integral area. The larger the integral area, the larger the leakage current. The larger the leakage current, the larger the corresponding power consumption. Therefore, when the input signal terminal ESTV is used to control the first output node control circuit 18, the power consumption of the shift register can be better reduced.

[0172] like Fig.26 As shown, the solid line curve represents the driving current of the tenth transistor T10 when the gate drive signal output terminal Eout is reset when the first pull-down node PD_in1 is used to control the first output node control circuit 18, and the dotted line curve represents the driving current of the tenth transistor T10 when the gate drive signal output terminal Eout is reset when the input signal terminal ESTV is used to control the first output node control circuit 18. It can be seen that when the input signal terminal ESTV is used to control the first output node control circuit 18, when the gate drive signal output terminal Eout is reset, the driving current integral area of ​​the tenth transistor T10 is significantly reduced. It should be noted that Fig.26 The driving current integral area in is the area formed by the solid curve, the dotted curve and the horizontal dotted line respectively. It can be seen that the current integral area formed by the dotted curve is smaller than the current integral area formed by the solid curve. When the driving conditions are met, reducing the driving current can better reduce the power consumption of the shift register. Therefore, when the input signal terminal ESTV is used to control the first output node control circuit 18, the power consumption of the shift register can be better reduced.

[0173] like Fig.12 and Fig. 22 As shown, in some embodiments, the shift register further includes: a first input circuit 12, a first transmission circuit 13 and a first pull-down node PD_in1;

[0174] The first input circuit 12 is coupled to the clock signal input terminal, the input signal terminal ESTV, and the first pull-down node PD_in1 respectively, and is used to control the conduction or disconnection of the electrical connection between the input signal terminal ESTV and the first pull-down node PD_in1 under the control of the clock signal inputted from the clock signal input terminal;

[0175] The first transmission circuit 13 is respectively coupled to the second first level signal input terminal VGL2, the first pull-down node PD_in1 and the first output node PD_out, and is used to open or close the electrical connection between the first pull-down node PD_in1 and the first output node PD_out under the control of the first level signal input by the second first level signal input terminal VGL2;

[0176] The clock signal input terminal coupled to the first coupling control circuit 11 and the clock signal input terminal coupled to the first input circuit 12 are input with the same clock signal.

[0177] The above-mentioned setting method enables the clock signal input terminal coupled to the first coupling control circuit 11 and the clock signal input terminal coupled to the first input circuit 12 to be connected to the same clock signal line, which is beneficial to reduce the number of signal lines that need to be coupled to the shift register. When the shift register is applied to display products, it is beneficial to achieve a narrow border for the display product.

[0178] The above-mentioned setting couples the first transmission circuit 13 with the second first-level signal input terminal VGL2. Since the first-level signal inputted by the second first-level signal input terminal VGL2 has a more negative voltage value, the twelfth transistor T12 included in the first transmission circuit 13 can be turned on more thoroughly, which is beneficial to better reduce the voltage drop between the first pull-down node PD_in1 and the first output node PD_out.

[0179] like Fig.11 and Fig.21 As shown, in some embodiments, the shift register further includes: a first input circuit 12, a first transmission circuit 13 and a first pull-down node PD_in1;

[0180] The first input circuit 12 is coupled to the clock signal input terminal, the input signal terminal ESTV, and the first pull-down node PD_in1 respectively, and is used to control the conduction or disconnection of the electrical connection between the input signal terminal ESTV and the first pull-down node PD_in1 under the control of the clock signal inputted from the clock signal input terminal;

[0181] The first transmission circuit 13 is respectively coupled to the second first level signal input terminal VGL2, the first pull-down node PD_in1 and the first output node PD_out, and is used to open or close the electrical connection between the first pull-down node PD_in1 and the first output node PD_out under the control of the first level signal input by the second first level signal input terminal VGL2;

[0182] The clock signal input to the clock signal input terminal coupled to the first coupling control circuit 11 has a preset delay relative to the clock signal input to the clock signal input terminal coupled to the first input circuit 12 .

[0183] Exemplarily, the first input circuit 12 includes a first transistor T1, a gate of the first transistor T1 is coupled to the clock signal input terminal, a first electrode of the first transistor T1 is coupled to the input signal terminal ESTV, and a second electrode of the first transistor T1 is coupled to the first pull-down node PD_in1;

[0184] The first transmission circuit 13 includes a twelfth transistor T12, a gate of the twelfth transistor T12 is coupled to the second first level signal input terminal VGL2, a first electrode of the twelfth transistor T12 is coupled to the first pull-down node PD_in1, and a second electrode of the twelfth transistor T12 is coupled to the first output node PD_out.

[0185] In more detail, when the gate drive signal output terminal Eout is reset, the first transistor T1 and the twelfth transistor T12 are controlled to be turned on, so as to pull down the first pull-down node PD_in1 and the first output node PD_out, and turn on the tenth transistor T10. However, in the reset process, the threshold voltages of the first transistor T1, the twelfth transistor T12 and the tenth transistor T10 are usually attenuated, and the gate drive signal output terminal Eout cannot be quickly pulled down to the first level signal input by the first first level signal input terminal VGL1. The above setting is that the clock signal input to the clock signal input terminal coupled to the first coupling control circuit 11 has a preset delay relative to the clock signal input to the clock signal input terminal coupled to the first input circuit 12, so as to pull down the potential of the coupling node PD_c through the slightly delayed clock signal, further pull down the potential of the first output node PD_out, and make the tenth transistor T10 fully turned on, so as to quickly reset the gate drive signal output terminal Eout to the first level signal.

[0186] It is worth noting that the clock signal input to the clock signal input terminal coupled to the first coupling control circuit 11 has a phase difference with the clock signal input to the clock signal input terminal coupled to the first input circuit 12. The phase difference is determined by the internal node capacitance of the shift register and the load of the gate line coupled to the shift register. The phase difference can generally be set within the range of 0 to 2 μs.

[0187] like Figure 7 , Fig.11 , Fig.18 and Fig.21 As shown, in some embodiments, the shift register further includes: a first pull-up node PU_in, a second pull-up node PU_c, a third pull-up node PU_c2, a first pull-up node control circuit 19, a second pull-up node control circuit 20, a third pull-up node control circuit 21, and a second output node control circuit 22;

[0188] The first pull-up node control circuit 19 is coupled to the clock signal input terminal, the second first level signal input terminal VGL2, the first pull-up node PU_in and the first pull-down node PD_in1 respectively; it is used to control the conduction or disconnection of the electrical connection between the second first level signal input terminal VGL2 and the first pull-up node PU_in under the control of the clock signal input terminal, and is also used to control the conduction or disconnection of the electrical connection between the clock signal input terminal and the first pull-up node PU_in under the control of the potential of the first pull-down node PD_in1;

[0189] The second pull-up node control circuit 20 is coupled to the second first level signal input terminal VGL2, the first pull-up node PU_in and the second pull-up node PU_c, respectively, and is used to control the conduction or disconnection of the electrical connection between the first pull-up node PU_in and the second pull-up node PU_c under the control of the first level signal input by the second first level signal input terminal VGL2;

[0190] The third pull-up node control circuit 21 is coupled to the second pull-up node PU_c, the third pull-up node PU_c2 and the inverted clock signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the inverted clock signal input terminal and the third pull-up node PU_c2 under the control of the potential of the second pull-up node PU_c, and is also used to control the potential of the third pull-up node PU_c2 under the control of the potential of the second pull-up node PU_c;

[0191] The second output node control circuit 22 is respectively coupled to the inverted clock signal input terminal, the third pull-up node PU_c2 and the second output node PU_out, and is used to control the conduction or disconnection of the electrical connection between the third pull-up node PU_c2 and the second output node PU_out under the control of the inverted clock signal input to the inverted clock signal input terminal.

[0192] It should be noted that the clock signal input to the clock signal input terminal and the inverted clock signal input to the inverted clock signal input terminal can have completely opposite phases; for example: when the clock signal input to the clock signal input terminal is at a high level, the inverted clock signal input to the inverted clock signal input terminal is at a low level; when the clock signal input to the clock signal input terminal is at a low level, the inverted clock signal input to the inverted clock signal input terminal is at a high level.

[0193] The clock signal input to the clock signal input terminal and the inverted clock signal input to the inverted clock signal input terminal may also have opposite phases; for example: during a period when the clock signal input to the clock signal input terminal is at a high level, the inverted clock signal input to the inverted clock signal input terminal is at a high level, a low level, and a high level in sequence; during a period when the inverted clock signal input to the inverted clock signal input terminal is at a high level, the clock signal input to the clock signal input terminal is at a high level, a low level, and a high level in sequence.

[0194] Exemplarily, the first pull-up node control circuit 19 includes a second transistor T2 and a third transistor T3, the gate of the second transistor T2 is coupled to the first pull-down node PD_in1, the first electrode of the second transistor T2 is coupled to the clock signal input terminal, and the second electrode of the second transistor T2 is coupled to the first pull-up node PU_in; the gate of the third transistor T3 is coupled to the clock signal input terminal, the first electrode of the third transistor T3 is coupled to the second first level signal input terminal VGL2, and the second electrode of the third transistor T3 is coupled to the first pull-up node PU_in;

[0195] The second pull-up node control circuit 20 includes an eleventh transistor T11, a gate of the eleventh transistor T11 is coupled to the second first level signal input terminal VGL2, a first electrode of the eleventh transistor T11 is coupled to the first pull-up node PU_in, and a second electrode of the eleventh transistor T11 is coupled to the second pull-up node PU_c;

[0196] The third pull-up node control circuit 21 includes a sixth transistor T6 and a first capacitor C1, the gate of the sixth transistor T6 is coupled to the second pull-up node PU_c, the first electrode of the sixth transistor T6 is coupled to the inverted clock signal input terminal, and the second electrode of the sixth transistor T6 is coupled to the third pull-up node PU_c2; the first electrode plate of the first capacitor C1 is coupled to the second pull-up node PU_c, and the second electrode plate of the first capacitor C1 is coupled to the third pull-up node PU_c2;

[0197] The second output node control circuit 22 includes a seventh transistor T7, a gate of the seventh transistor T7 is coupled to the inverted clock signal input terminal, a first electrode of the seventh transistor T7 is coupled to the third pull-up node PU_c2, and a second electrode of the seventh transistor T7 is coupled to the second output node PU_out.

[0198] like Figure 8 , Fig. 9 , Fig.11 , Fig.12 , Fig.19 , Fig. 20 , Fig.21 and Fig. 22 As shown, in some embodiments, the shift register also includes a reset control circuit 23, and the reset control circuit 23 is coupled to the reset signal input terminal, the second second-level signal input terminal VGH2 and the first pull-down node PD_in1 respectively, and is used to control the conduction or disconnection of the electrical connection between the second second-level signal input terminal VGH2 and the first pull-down node PD_in1 under the control of the reset signal input terminal.

[0199] Exemplarily, the reset control circuit 23 includes a thirteenth transistor T13, a gate of the thirteenth transistor T13 is coupled to the reset signal input terminal, a first electrode of the thirteenth transistor T13 is coupled to the second second-level signal input terminal VGH2, and a second electrode of the thirteenth transistor T13 is coupled to the first pull-down node PD_in1.

[0200] Exemplarily, when the shift register is applied to a gate driving circuit, the gate driving circuit further includes a reset signal line, and the reset signal input terminals coupled to the shift registers included in the gate driving circuit are all coupled to the reset signal line.

[0201] The shift register is configured as described above to include a reset control circuit 23 , and the first pull-down node PD_in1 can be reset by the reset control circuit 23 .

[0202] It should be noted that the types of transistors included in the shift register are various. Exemplarily, the transistors include N-type transistors or P-type transistors, but are not limited thereto.

[0203] In some embodiments, the voltage value of the second level signal inputted by the second second level signal input terminal VGH2 is greater than or equal to the voltage value of the second level signal inputted by the first second level signal input terminal VGH1; the voltage value of the first level signal inputted by the second first level signal input terminal VGL2 is less than or equal to the voltage value of the first level signal inputted by the first first level signal input terminal VGL1;

[0204] The high level value of the clock signal input to the clock signal input terminal is the same as the voltage value of the second level signal input to the second second level signal input terminal VGH2, and the low level value of the clock signal input to the clock signal input terminal is the same as the voltage value of the first level signal input to the second first level signal input terminal VGL2.

[0205] An embodiment of the present invention further provides a gate driving circuit, comprising a plurality of cascaded shift registers.

[0206] The gate drive circuit is applied to a display device, which may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board, a backplane, etc.

[0207] In the shift register provided in the above embodiment, the first coupling control circuit 11 can control the electrical connection between the coupling node PD_c and the clock signal input terminal to be turned on or off, so that the potential of the coupling node PD_c can be the same as the potential of the clock signal input by the clock signal input terminal; at the same time, the first coupling control circuit 11 can control the potential of the first output node PD_out according to the potential of the coupling node PD_c; in this way, when resetting the gate drive signal output terminal Eout, the clock signal input terminal can be controlled to input a signal with a suitable potential to control the coupling node to have a suitable potential, thereby controlling the potential of the first output node PD_out to be quickly lowered, eliminating the step formed in the process of lowering the potential of the first output node PD_out, greatly shortening the reset time of the gate drive signal output terminal Eout, realizing the rapid reset of the gate drive signal output terminal Eout, enhancing the driving capability of the shift register, ensuring the pixel light emission time and charging time, and avoiding the Mura problem caused by the difference in pixel charging time or light emission time.

[0208] The gate driving circuit provided in the embodiment of the present invention also has the above-mentioned beneficial effects when including the above-mentioned shift register, which will not be described in detail here.

[0209] like Fig.11 and Fig.21As shown, in some embodiments, the gate drive circuit includes a first clock signal line CK1', a second clock signal line CK2', a first inverted clock signal line CB1' and a second inverted clock signal line CB2'; the first clock signal CK1 transmitted by the first clock signal line CK1' is opposite in phase to the first inverted clock signal CB1 transmitted by the first inverted clock signal line CB1'; the second clock signal CK2 transmitted by the second clock signal line CK2' is opposite in phase to the second inverted clock signal CB2 transmitted by the second inverted clock signal line CB2'; there is a preset delay between the second clock signal and the first clock signal; it should be noted that the first clock signal CK1 is opposite in phase to the first inverted clock signal CB1, which may refer to the first clock signal CK1 and the first inverted clock signal CB1 being completely opposite in phase; it may also refer to the first clock signal CK1 and the first inverted clock signal CB1 being partially opposite in phase, such as: during the period when the first clock signal CK1 is at a high level, the first inverted clock signal CB1 is sequentially at a high level, a low level and a high level; during the period when the first inverted clock signal CB1 is at a high level, the first clock signal CK1 is sequentially at a high level, a low level and a high level. The second clock signal CK2 and the second inverted clock signal CB2 are in opposite phases, as described above, and will not be repeated here.

[0210] In the odd-numbered shift register, the clock signal input terminal coupled to the first coupling control circuit 11 is coupled to the first clock signal line CK1' or the second clock signal line CK2';

[0211] In the even-numbered shift register, the clock signal input terminal coupled to the first coupling control circuit 11 is coupled to the first inverted clock signal line CB1 ′ or the second inverted clock signal line CB2 ′.

[0212] In some embodiments, in the odd-numbered shift register, the clock signal input terminal coupled to the first input circuit 12 is coupled to the first clock signal line CK1' or the second clock signal line CK2', the clock signal input terminal coupled to the third transistor T3 in the first pull-up node control circuit 19 is coupled to the first clock signal line CK1' or the second clock signal line CK2', the clock signal input terminal coupled to the second transistor T2 in the first pull-up node control circuit 19 is coupled to the first clock signal line CK1' or the second clock signal line CK2', the inverted clock signal input terminal coupled to the third pull-up node control circuit 21 is coupled to the first inverted clock signal line CB1' or the second inverted clock signal line CB2', and the inverted clock signal input terminal coupled to the second output node control circuit 22 is coupled to the first inverted clock signal line CB1' or the second inverted clock signal line CB2';

[0213] In the even-numbered shift register, the clock signal input terminal coupled to the first input circuit 12 is coupled to the first inverted clock signal line CB1' or the second inverted clock signal line CB2', the clock signal input terminal coupled to the third transistor T3 in the first pull-up node control circuit 19 is coupled to the first inverted clock signal line CB1' or the second inverted clock signal line CB2', the clock signal input terminal coupled to the second transistor T2 in the first pull-up node control circuit 19 is coupled to the first inverted clock signal line CB1' or the second inverted clock signal line CB2', the inverted clock signal input terminal coupled to the third pull-up node control circuit 21 is coupled to the first clock signal line CK1' or the second clock signal line CK2', and the inverted clock signal input terminal coupled to the second output node control circuit 22 is coupled to the first clock signal line CK1' or the second clock signal line CK2'.

[0214] like Fig. 27 As shown, the following specific embodiments are given:

[0215] In the odd-numbered shift register, the clock signal input terminal coupled to the first input circuit 12 is coupled to the first clock signal line CK1', the clock signal input terminal coupled to the third transistor T3 in the first pull-up node control circuit 19 is coupled to the second clock signal line CK2', the clock signal input terminal coupled to the second transistor T2 in the first pull-up node control circuit 19 is coupled to the first clock signal line CK1', the inverted clock signal input terminal coupled to the third pull-up node control circuit 21 is coupled to the first inverted clock signal line CB1', and the inverted clock signal input terminal coupled to the second output node control circuit 22 is coupled to the first inverted clock signal line CB1'; the clock signal input terminal coupled to the first coupling control circuit 11 is coupled to the second clock signal line CK2';

[0216] In the even-numbered shift register, the clock signal input terminal coupled to the first input circuit 12 is coupled to the first inverted clock signal line CB1', the clock signal input terminal coupled to the third transistor T3 in the first pull-up node control circuit 19 is coupled to the second inverted clock signal line CB2', the clock signal input terminal coupled to the second transistor T2 in the first pull-up node control circuit 19 is coupled to the first inverted clock signal line CB1', the inverted clock signal input terminal coupled to the third pull-up node control circuit 21 is coupled to the first clock signal line CK1', and the inverted clock signal input terminal coupled to the second output node control circuit 22 is coupled to the first clock signal line CK1'; the clock signal input terminal coupled to the first coupling control circuit 11 is coupled to the second inverted clock signal line CB2'.

[0217] It should be noted that Fig. 27The frame start signal line ESTV' is also illustrated. The input signal terminal ESTV of the first shift register unit GOA1 is coupled to the frame start signal line ESTV'; the input signal terminal ESTV of the second shift register unit GOA2 is coupled to the gate drive signal output terminal Eout1 of the first shift register unit GOA1; the input signal terminal ESTV of the third shift register unit GOA3 is coupled to the gate drive signal output terminal Eout2 of the second shift register unit GOA2; the input signal terminal ESTV of the fourth shift register unit GOA4 is coupled to the gate drive signal output terminal Eout3 of the third shift register unit GOA3; the gate drive signal output terminal Eout4 of the fourth shift register unit GOA4 is used to connect the input signal terminal of the next stage shift register unit.

[0218] In more detail, Fig. 9 and Fig.10 As shown, the working process of the shift register is described in detail below.

[0219] In the first time period P1: the first transistor T1 is turned on, the second transistor T2 is turned off, the third transistor T3 is turned on, the fourth transistor T4 is turned off, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, the seventh transistor T7 is turned off, the eighth transistor T8 is turned off, the ninth transistor T9 is turned off, the tenth transistor T10 is turned off, the eleventh transistor T11 and the twelfth transistor T12 are turned on; the potential of the first pull-down node PD_in1 is high, the potential of the first output node PD_out is high, the potential of the first pull-up node PU_in is low, the potential of the second pull-up node PU_c is low, the potential of the second output node PU_out is high, and the gate drive signal output terminal Eout keeps outputting a low level signal.

[0220] In the second period P2: the first transistor T1 is turned off, the second transistor T2 is turned off, the third transistor T3 is turned off, the fourth transistor T4 is turned off, the fifth transistor T5 is turned on, the sixth transistor T6 is turned on, the seventh transistor T7 is turned on, the eighth transistor T8 is turned off, the ninth transistor T9 is turned on, the tenth transistor T10 is turned off, the eleventh transistor T11 and the twelfth transistor T12 are turned on; the potential of the first pull-down node PD_in1 is high, the potential of the first output node PD_out is high, the potential of the first pull-up node PU_in is low, the potential of the second pull-up node PU_c is low, the potential of the second output node PU_out is low, and the gate drive signal output terminal Eout outputs a high level signal.

[0221] In the third time period P3: the first transistor T1 is turned on, the second transistor T2 is turned off, the third transistor T3 is turned on, the fourth transistor T4 is turned off, the fifth transistor T5 is turned on, the sixth transistor T6 is turned on, the seventh transistor T7 is turned off, the eighth transistor T8 is turned off, the ninth transistor T9 is turned on, the tenth transistor T10 is turned off, the eleventh transistor T11 and the twelfth transistor T12 are turned on; the potential of the first pull-down node PD_in1 is high, the potential of the first output node PD_out is high, the potential of the first pull-up node PU_in is low, the potential of the second pull-up node PU_c is low, the potential of the second output node PU_out is low, and the gate drive signal output terminal Eout outputs a high level signal.

[0222] In the fourth time period P4: the first transistor T1 is turned off, the second transistor T2 is turned off, the third transistor T3 is turned off, the fourth transistor T4 is turned off, the fifth transistor T5 is turned on, the sixth transistor T6 is turned on, the seventh transistor T7 is turned on, the eighth transistor T8 is turned off, the ninth transistor T9 is turned on, the tenth transistor T10 is turned off, the eleventh transistor T11 and the twelfth transistor T12 are turned on; the potential of the first pull-down node PD_in1 is high, the potential of the first output node PD_out is high, the potential of the first pull-up node PU_in is low, the potential of the second pull-up node PU_c is low, the potential of the second output node PU_out is low, and the gate drive signal output terminal Eout outputs a high level signal.

[0223] In the fifth time period P5: the first transistor T1 is turned on, the second transistor T2 is turned off, the third transistor T3 is turned on, the fourth transistor T4 is turned off, the fifth transistor T5 is turned on, the sixth transistor T6 is turned on, the seventh transistor T7 is turned off, the eighth transistor T8 is turned off, the ninth transistor T9 is turned on, the tenth transistor T10 is turned off, the eleventh transistor T11 and the twelfth transistor T12 are turned on; the potential of the first pull-down node PD_in1 is high, the potential of the first output node PD_out is high, the potential of the first pull-up node PU_in is low, the potential of the second pull-up node PU_c is low, the potential of the second output node PU_out is low, and the gate drive signal output terminal Eout outputs a high level signal.

[0224] In the sixth time period P6: the first transistor T1 is turned off, the second transistor T2 is turned off, the third transistor T3 is turned off, the fourth transistor T4 is turned off, the fifth transistor T5 is turned on, the sixth transistor T6 is turned on, the seventh transistor T7 is turned on, the eighth transistor T8 is turned off, the ninth transistor T9 is turned on, the tenth transistor T10 is turned off, the eleventh transistor T11 and the twelfth transistor T12 are turned on; the potential of the first pull-down node PD_in1 is high, the potential of the first output node PD_out is high, the potential of the first pull-up node PU_in is low, the potential of the second pull-up node PU_c is low, the potential of the second output node PU_out is low, and the gate drive signal output terminal Eout outputs a high level signal.

[0225] In the seventh time period P7, the first transistor T1 is turned on, the second transistor T2 is turned on, the third transistor T3 is turned on, the fourth transistor T4 is turned on, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, the seventh transistor T7 is turned off, the eighth transistor T8 is turned on, the ninth transistor T9 is turned off, the tenth transistor T10 is turned on, and the eleventh transistor T11 and the twelfth transistor T12 are turned on; the potential of the first pull-down node PD_in1 is a low level, due to the coupling effect of the fourth transistor T4 and the third capacitor C3, the potential of the first output node PD_out is quickly pulled down to a low level, the potential of the first pull-up node PU_in is a low level, the potential of the second pull-up node PU_c is a low level, the potential of the second output node PU_out is a high level, and the gate drive signal output terminal Eout outputs a low level signal.

[0226] It should be noted that when the potential of the first output node PD_out is at a high level and the fourth transistor T4 is turned off, the third capacitor C3 can maintain the potential of the first output node PD_out, so that the tenth transistor T10 remains turned off.

[0227] The embodiment of the present invention further provides a shift register driving method, which is used to drive the shift register provided by the above embodiment; the driving method comprises:

[0228] The first output circuit 10 controls the electrical connection between the first first level signal input terminal VGL1 and the gate drive signal output terminal Eout to be turned on or off under the control of the potential of the first output node PD_out;

[0229] The first coupling control circuit 11 controls the electrical connection between the coupling node PD_c and the clock signal input terminal under the control of the potential of the control node K1, and is also used to control the potential of the first output node PD_out according to the potential of the coupling node PD_c.

[0230] When the driving method provided by the embodiment of the present invention is used to drive the shift register, the first coupling control circuit 11 can control the electrical connection between the coupling node PD_c and the clock signal input terminal to be turned on or off, so that the potential of the coupling node PD_c can be the same as the potential of the clock signal input by the clock signal input terminal; at the same time, the first coupling control circuit 11 can control the potential of the first output node PD_out according to the potential of the coupling node PD_c; in this way, when resetting the gate drive signal output terminal Eout, the clock signal input terminal can be controlled to input a signal with a suitable potential to control the coupling node to have a suitable potential, thereby controlling the potential of the first output node PD_out to be quickly lowered, eliminating the step formed in the process of lowering the potential of the first output node PD_out, greatly shortening the reset time of the gate drive signal output terminal Eout, realizing the rapid reset of the gate drive signal output terminal Eout, enhancing the driving capability of the shift register, ensuring the pixel light emission time and charging time, and avoiding the Mura problem caused by the difference in pixel charging time or light emission time.

[0231] In some embodiments, the control node K1 is directly coupled to the first output node PD_out; the first coupling control circuit 11 includes a first control subcircuit 110 and a first coupling subcircuit 111;

[0232] The first control subcircuit 110 controls the electrical connection between the coupling node PD_c and the clock signal input terminal to be turned on or off under the control of the potential of the first output node PD_out;

[0233] The first coupling sub-circuit 111 controls the potential of the first output node PD_out according to the potential of the coupling node PD_c.

[0234] Using the driving method provided in the above embodiment to drive the above shift register can not only achieve the beneficial effects of quickly resetting the gate drive signal output terminal Eout and enhancing the driving capability of the shift register, but also help simplify the circuit structure of the shift register.

[0235] In some embodiments, the first coupling control circuit 11 includes a second control subcircuit 112 , a third control subcircuit 113 , and a second coupling subcircuit 114 ;

[0236] The second control subcircuit 112 controls the conduction or disconnection of the electrical connection between the coupling node PD_c and the clock signal input terminal under the control of the potential of the control node K1;

[0237] The third control subcircuit 113 controls the electrical connection between the control node K1 and the first output node PD_out to be turned on or off under the control of the potential of the control node K1;

[0238] The second coupling sub-circuit 114 controls the potential of the control node K1 according to the potential of the coupling node PD_c.

[0239] The driving method provided by the above embodiment is used to drive the above shift register, which is beneficial to better improve the working stability of the first output node PD_out and reduce the adverse interference of the first output node PD_out. At the same time, it can achieve the beneficial effects of quickly resetting the gate drive signal output terminal Eout and enhancing the driving ability of the shift register.

[0240] It should be noted that the "same layer" in the embodiment of the present invention may refer to a film layer on the same structural layer. Or, for example, a film layer on the same layer may be a film layer for forming a specific pattern formed by the same film forming process, and then the film layer is patterned by the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0241] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the sequence of the steps. For ordinary technicians in this field, without paying creative work, changes to the sequence of the steps are also within the protection scope of the present invention.

[0242] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0243] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0244] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0245] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0246] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A shift register, characterized in that: include: a coupling node, a control node, a first output node, a first output circuit, and a first coupling control circuit; The first output circuit is coupled to the first output node, the first first level signal input terminal and the gate drive signal output terminal of the shift register respectively; and is used to control the conduction or disconnection of the electrical connection between the first first level signal input terminal and the gate drive signal output terminal under the control of the potential of the first output node; The first coupling control circuit is coupled to the coupling node, the control node, the first output node and the clock signal input terminal respectively; the first coupling control circuit is used to control the conduction or disconnection of the electrical connection between the coupling node and the clock signal input terminal under the control of the potential of the control node; The device is further configured to control the potential of the first output node according to the potential of the coupling node.

2. The shift register according to claim 1, characterized in that: The control node is directly coupled to the first output node; the first coupling control circuit includes a first control subcircuit and a first coupling subcircuit; The first control subcircuit is coupled to the first output node, the coupling node and the clock signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the coupling node and the clock signal input terminal under the control of the potential of the first output node; The first coupling subcircuit is coupled to the coupling node and the first output node respectively, and is used to control the potential of the first output node according to the potential of the coupling node.

3. The shift register according to claim 2, characterized in that: The first control subcircuit includes a fourth transistor, and the first coupling subcircuit includes a third capacitor; The gate of the fourth transistor is coupled to the first output node, the first electrode of the fourth transistor is coupled to the clock signal input terminal, and the second electrode of the fourth transistor is coupled to the coupling node; A first plate of the third capacitor is coupled to the coupling node, and a second plate of the third capacitor is coupled to the first output node.

4. The shift register according to claim 1, wherein: The first coupling control circuit includes a second control subcircuit, a third control subcircuit and a second coupling subcircuit; The second control subcircuit is coupled to the control node, the coupling node and the clock signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the coupling node and the clock signal input terminal under the control of the potential of the control node; The third control subcircuit is coupled to the control node and the first output node respectively, and is used to control the conduction or disconnection of the electrical connection between the control node and the first output node under the control of the potential of the control node; The second coupling subcircuit is coupled to the coupling node and the control node respectively, and is used to control the potential of the control node according to the potential of the coupling node.

5. The shift register according to claim 4, characterized in that: The second control subcircuit comprises a fourth transistor, a gate of the fourth transistor is coupled to the control node, a first electrode of the fourth transistor is coupled to the clock signal input terminal, and a second electrode of the fourth transistor is coupled to the coupling node; The third control subcircuit includes a sixteenth transistor, a gate of the sixteenth transistor is coupled to the control node, a first electrode of the sixteenth transistor is coupled to the control node, and a second electrode of the sixteenth transistor is coupled to the first output node; The second coupling subcircuit includes a third capacitor, a first plate of the third capacitor is coupled to the coupling node, and a second plate of the third capacitor is coupled to the control node.

6. The shift register according to claim 4, characterized in that: The shift register further includes: a first input circuit, a first transmission circuit, a second input circuit, a second transmission circuit, a first pull-down node, and a second pull-down node; The first input circuit is coupled to the clock signal input terminal, the input signal terminal, and the first pull-down node respectively, and is used to control the conduction or disconnection of the electrical connection between the input signal terminal and the first pull-down node under the control of the clock signal input to the clock signal input terminal; The first transmission circuit is coupled to the second first-level signal input terminal, the first pull-down node and the first output node respectively, and is used to open or close the electrical connection between the first pull-down node and the first output node under the control of the first-level signal inputted from the second first-level signal input terminal; The second input circuit is coupled to the clock signal input terminal, the input signal terminal, and the second pull-down node respectively, and is used to control the conduction or disconnection of the electrical connection between the input signal terminal and the second pull-down node under the control of the clock signal input to the clock signal input terminal; The second transmission circuit is coupled to the second first-level signal input terminal, the second pull-down node and the control node respectively, and is used to turn on or off the electrical connection between the second pull-down node and the control node under the control of the first-level signal input to the second first-level signal input terminal.

7. The shift register according to claim 6, characterized in that: The first input circuit comprises a first transistor, a gate of the first transistor is coupled to the clock signal input terminal, a first electrode of the first transistor is coupled to the input signal terminal, and a second electrode of the first transistor is coupled to the first pull-down node; The first transmission circuit includes a twelfth transistor, a gate of the twelfth transistor is coupled to the second first level signal input terminal, a first electrode of the twelfth transistor is coupled to the first pull-down node, and a second electrode of the twelfth transistor is coupled to the first output node; The second input circuit comprises a fourteenth transistor, a gate of the fourteenth transistor is coupled to the clock signal input terminal, a first electrode of the fourteenth transistor is coupled to the input signal terminal, and a second electrode of the fourteenth transistor is coupled to the second pull-down node; The second transmission circuit includes a fifteenth transistor, a gate of the fifteenth transistor is coupled to the second first-level signal input terminal, a first electrode of the fifteenth transistor is coupled to the second pull-down node, and a second electrode of the fifteenth transistor is coupled to the control node.

8. The shift register according to any one of claims 1 to 7, characterized in that: The shift register further includes a second output node, a second output circuit, and a second coupling control circuit; The second output circuit is coupled to the second output node, the first second level signal input terminal and the gate drive signal output terminal of the shift register respectively; and is used to control the conduction or disconnection of the electrical connection between the first second level signal input terminal and the gate drive signal output terminal under the control of the potential of the second output node; The second coupling control circuit is coupled to the second output node, the second second-level signal input terminal and the coupling node respectively, and is used to control the conduction or disconnection of the electrical connection between the second second-level signal input terminal and the coupling node under the control of the potential of the second output node.

9. The shift register according to claim 8, characterized in that: The second coupling control circuit comprises a fifth transistor, a gate of the fifth transistor is coupled to the second output node, a first electrode of the fifth transistor is coupled to the second second-level signal input terminal, and a second electrode of the fifth transistor is coupled to the coupling node; The second output circuit includes a ninth transistor, a gate of the ninth transistor is coupled to the second output node, a first electrode of the ninth transistor is coupled to the first second level signal input terminal, and a second electrode of the ninth transistor is coupled to the gate drive signal output terminal.

10. The shift register according to any one of claims 1 to 5, characterized in that: The shift register further includes a first input circuit, a first pull-down node and a first output node control circuit; The first input circuit is coupled to the clock signal input terminal, the input signal terminal and the first pull-down node respectively, and is used to control the conduction or disconnection of the electrical connection between the input signal terminal and the first pull-down node under the control of the clock signal input to the clock signal input terminal; The first output node control circuit is coupled to the first pull-down node, the second second-level signal input terminal and the second output node respectively, and is used to control the conduction or disconnection of the electrical connection between the second second-level signal input terminal and the second output node under the control of the potential of the first pull-down node.

11. The shift register according to claim 10, characterized in that: The first input circuit comprises a first transistor, a gate of the first transistor is coupled to the clock signal input terminal, a first electrode of the first transistor is coupled to the input signal terminal, and a second electrode of the first transistor is coupled to the first pull-down node; The first output node control circuit includes an eighth transistor, a gate of the eighth transistor is coupled to the first pull-down node, a first electrode of the eighth transistor is coupled to the second second-level signal input terminal, and a second electrode of the eighth transistor is coupled to the second output node.

12. The shift register according to any one of claims 1 to 7, characterized in that: The shift register also includes a first output node control circuit, which is coupled to the input signal terminal, the second second-level signal input terminal and the second output node respectively, and is used to control the conduction or disconnection of the electrical connection between the second second-level signal input terminal and the second output node under the control of the signal input from the input signal terminal.

13. The shift register according to claim 12, characterized in that: The first output node control circuit includes an eighth transistor, a gate of the eighth transistor is coupled to the input signal terminal, a first electrode of the eighth transistor is coupled to the second second-level signal input terminal, and a second electrode of the eighth transistor is coupled to the second output node.

14. The shift register according to claim 1, characterized in that: The shift register further includes: a first input circuit, a first transmission circuit and a first pull-down node; The first input circuit is coupled to the clock signal input terminal, the input signal terminal, and the first pull-down node respectively, and is used to control the conduction or disconnection of the electrical connection between the input signal terminal and the first pull-down node under the control of the clock signal input to the clock signal input terminal; The first transmission circuit is coupled to the second first-level signal input terminal, the first pull-down node and the first output node respectively, and is used to open or close the electrical connection between the first pull-down node and the first output node under the control of the first-level signal inputted from the second first-level signal input terminal; The clock signal input terminal coupled to the first coupling control circuit and the clock signal input terminal coupled to the first input circuit input the same clock signal.

15. The shift register according to claim 1, characterized in that: The shift register further includes: a first input circuit, a first transmission circuit and a first pull-down node; The first input circuit is coupled to the clock signal input terminal, the input signal terminal, and the first pull-down node respectively, and is used to control the conduction or disconnection of the electrical connection between the input signal terminal and the first pull-down node under the control of the clock signal input to the clock signal input terminal; The first transmission circuit is coupled to the second first-level signal input terminal, the first pull-down node and the first output node respectively, and is used to open or close the electrical connection between the first pull-down node and the first output node under the control of the first-level signal inputted from the second first-level signal input terminal; The clock signal input to the clock signal input terminal coupled to the first coupling control circuit has a preset delay relative to the clock signal input to the clock signal input terminal coupled to the first input circuit.

16. The shift register according to claim 14 or 15, characterized in that: The first input circuit comprises a first transistor, a gate of the first transistor is coupled to the clock signal input terminal, a first electrode of the first transistor is coupled to the input signal terminal, and a second electrode of the first transistor is coupled to the first pull-down node; The first transmission circuit includes a twelfth transistor, a gate of the twelfth transistor is coupled to the second first-level signal input terminal, a first electrode of the twelfth transistor is coupled to the first pull-down node, and a second electrode of the twelfth transistor is coupled to the first output node.

17. The shift register according to any one of claims 1 to 7, characterized in that: The shift register further includes: a first pull-up node, a second pull-up node, a third pull-up node, a first pull-up node control circuit, a second pull-up node control circuit, a third pull-up node control circuit, and a second output node control circuit; The first pull-up node control circuit is coupled to the clock signal input terminal, the second first level signal input terminal, the first pull-up node and the first pull-down node respectively; and is used to control the conduction or disconnection of the electrical connection between the second first level signal input terminal and the first pull-up node under the control of the clock signal input terminal, and is also used to control the conduction or disconnection of the electrical connection between the clock signal input terminal and the first pull-up node under the control of the potential of the first pull-down node; The second pull-up node control circuit is coupled to the second first level signal input terminal, the first pull-up node and the second pull-up node respectively, and is used to control the conduction or disconnection of the electrical connection between the first pull-up node and the second pull-up node under the control of the first level signal inputted from the second first level signal input terminal; The third pull-up node control circuit is coupled to the second pull-up node, the third pull-up node and the inverted clock signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the inverted clock signal input terminal and the third pull-up node under the control of the potential of the second pull-up node, and is also used to control the potential of the third pull-up node under the control of the potential of the second pull-up node; The second output node control circuit is coupled to the inverted clock signal input terminal, the third pull-up node and the second output node respectively, and is used to control the conduction or disconnection of the electrical connection between the third pull-up node and the second output node under the control of the inverted clock signal input to the inverted clock signal input terminal.

18. The shift register according to claim 17, characterized in that: The first pull-up node control circuit includes a second transistor and a third transistor, the gate of the second transistor is coupled to the first pull-down node, the first electrode of the second transistor is coupled to the clock signal input terminal, and the second electrode of the second transistor is coupled to the first pull-up node; the gate of the third transistor is coupled to the clock signal input terminal, the first electrode of the third transistor is coupled to the second first-level signal input terminal, and the second electrode of the third transistor is coupled to the first pull-up node; The second pull-up node control circuit includes an eleventh transistor, a gate of the eleventh transistor is coupled to the second first level signal input terminal, a first electrode of the eleventh transistor is coupled to the first pull-up node, and a second electrode of the eleventh transistor is coupled to the second pull-up node; The third pull-up node control circuit includes a sixth transistor and a first capacitor, the gate of the sixth transistor is coupled to the second pull-up node, the first electrode of the sixth transistor is coupled to the inverted clock signal input terminal, and the second electrode of the sixth transistor is coupled to the third pull-up node; the first plate of the first capacitor is coupled to the second pull-up node, and the second plate of the first capacitor is coupled to the third pull-up node; The second output node control circuit includes a seventh transistor, a gate of the seventh transistor is coupled to the inverted clock signal input terminal, a first electrode of the seventh transistor is coupled to the third pull-up node, and a second electrode of the seventh transistor is coupled to the second output node.

19. The shift register according to any one of claims 1 to 7, characterized in that: The shift register also includes a reset control circuit, which is coupled to a reset signal input terminal, a second second-level signal input terminal and a first pull-down node respectively, and is used to control the conduction or disconnection of the electrical connection between the second second-level signal input terminal and the first pull-down node under the control of a reset signal input to the reset signal input terminal.

20. The shift register according to claim 19, characterized in that: The reset control circuit includes a thirteenth transistor, a gate of the thirteenth transistor is coupled to the reset signal input terminal, a first electrode of the thirteenth transistor is coupled to the second second-level signal input terminal, and a second electrode of the thirteenth transistor is coupled to the first pull-down node.

21. The shift register according to claim 1, characterized in that: The first output circuit includes a tenth transistor, a gate of the tenth transistor is coupled to the first output node, a first electrode of the tenth transistor is coupled to the first first-level signal input terminal, and a second electrode of the tenth transistor is coupled to the gate drive signal output terminal of the shift register.

22. The shift register according to claim 8, characterized in that: The voltage value of the second level signal inputted by the second second level signal input terminal is greater than or equal to the voltage value of the second level signal inputted by the first second level signal input terminal; The voltage value of the first level signal inputted by the second first level signal input terminal is less than or equal to the voltage value of the first level signal inputted by the first first level signal input terminal; The high level value of the clock signal input to the clock signal input terminal is the same as the voltage value of the second level signal input to the second second level signal input terminal, and the low level value of the clock signal input to the clock signal input terminal is the same as the voltage value of the first level signal input to the second first level signal input terminal.

23. A shift register driving method, characterized in that: Used to drive the shift register according to any one of claims 1 to 22; the driving method comprises: The first output circuit controls the electrical connection between the first first level signal input terminal and the gate drive signal output terminal to be turned on or off under the control of the potential of the first output node; The first coupling control circuit controls the electrical connection between the coupling node and the clock signal input terminal to be turned on or off under the control of the potential of the control node; and is also used to control the potential of the first output node according to the potential of the coupling node.

24. The driving method of the shift register according to claim 23, characterized in that: The control node is directly coupled to the first output node; the first coupling control circuit includes a first control subcircuit and a first coupling subcircuit; The first control subcircuit controls the conduction or disconnection of the electrical connection between the coupling node and the clock signal input terminal under the control of the potential of the first output node; The first coupling subcircuit controls the potential of the first output node according to the potential of the coupling node.

25. The driving method of the shift register according to claim 23, characterized in that: The first coupling control circuit includes a second control subcircuit, a third control subcircuit and a second coupling subcircuit; The second control subcircuit controls the conduction or disconnection of the electrical connection between the coupling node and the clock signal input terminal under the control of the potential of the control node; The third control subcircuit controls the conduction or disconnection of the electrical connection between the control node and the first output node under the control of the potential of the control node; The second coupling sub-circuit controls the potential of the control node according to the potential of the coupling node.

26. A gate drive circuit, characterized in that: The invention comprises a plurality of shift registers according to any one of claims 1 to 22 connected in cascade.

27. The gate driving circuit according to claim 26, characterized in that: The gate drive circuit includes a first clock signal line, a second clock signal line, a first inverted clock signal line, and a second inverted clock signal line; The first clock signal transmitted by the first clock signal line is in opposite phase to the first inverted clock signal transmitted by the first inverted clock signal line; The second clock signal transmitted by the second clock signal line is in opposite phase to the second inverted clock signal transmitted by the second inverted clock signal line; there is a preset delay between the second clock signal and the first clock signal; In the odd-numbered shift register, the clock signal input terminal coupled to the first coupling control circuit is coupled to the first clock signal line or the second clock signal line; In the even-numbered shift register, the clock signal input terminal coupled to the first coupling control circuit is coupled to the first inverted clock signal line or the second inverted clock signal line.

28. The gate driving circuit according to claim 27, characterized in that: In the odd-numbered shift register, a clock signal input terminal coupled to the first input circuit is coupled to the first clock signal line or the second clock signal line, a clock signal input terminal coupled to the third transistor in the first pull-up node control circuit is coupled to the first clock signal line or the second clock signal line, a clock signal input terminal coupled to the second transistor in the first pull-up node control circuit is coupled to the first clock signal line or the second clock signal line, an inverted clock signal input terminal coupled to the third pull-up node control circuit is coupled to the first inverted clock signal line or the second inverted clock signal line, and an inverted clock signal input terminal coupled to the second output node control circuit is coupled to the first inverted clock signal line or the second inverted clock signal line; In the even-numbered shift register, the clock signal input terminal coupled by the first input circuit is coupled to the first inverted clock signal line or the second inverted clock signal line, the clock signal input terminal coupled by the third transistor in the first pull-up node control circuit is coupled to the first inverted clock signal line or the second inverted clock signal line, the clock signal input terminal coupled by the second transistor in the first pull-up node control circuit is coupled to the first inverted clock signal line or the second inverted clock signal line, the inverted clock signal input terminal coupled by the third pull-up node control circuit is coupled to the first clock signal line or the second clock signal line, and the inverted clock signal input terminal coupled by the second output node control circuit is coupled to the first clock signal line or the second clock signal line.

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