Method of manufacturing a semiconductor structure

Abstract

The application provides a manufacturing method of a semiconductor structure. The manufacturing method comprises: providing a lead frame, the lead frame comprising a plurality of pins, a plurality of first connecting portions and a second connecting portion; the pins are connected with adjacent second connecting portions through the first connecting portions; the pins comprise opposite first surfaces and second surfaces; forming a plastic package structure comprising the lead frame, a chip and a plastic package layer, the chip faces the first surfaces, the plastic package layer encapsulates the chip and the lead frame, and the second surfaces are exposed from the plastic package layer; forming a groove between the second connecting portion and the pin connected therewith, at least part of the side of each pin facing the first connecting portion connected therewith is exposed by the groove, and at least part of the surface of the second connecting portion facing away from the chip is covered by the plastic package layer; forming a solder layer on the exposed surface of the lead frame; cutting the obtained structure along a cutting path, and removing the second connecting portion; the orthogonal projection of the cutting path on the plane where the first surfaces are located falls within the orthogonal projection of the groove on the plane.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a manufacturing method of semiconductor structure. BACKGROUND

[0002] A chip packaging technology can include the following processes: firstly, a lead frame is attached to a carrier plate, the lead frame includes a frame, a connecting part in the frame, and a plurality of pins, the pins are connected to the connecting part, and the connecting part is connected to the frame; then, a chip is attached to the lead frame, and the pins are electrically connected to the solder pads of the chip; then, a plastic encapsulation layer is formed; then, cutting is performed to form a groove exposing the side surface of the pins; then, a tin plating layer is formed on the exposed surface of the lead frame by electroplating process; finally, the connecting part and the frame are removed by cutting process.

[0003] In the above chip packaging technology, during the cutting process of removing the connecting part, tin whiskers are generated on the tin plating layer formed on the surface of the connecting part, and the tin whiskers will fall between the adjacent pins after falling off, which will cause short circuit of the adjacent pins and affect the yield of the product. SUMMARY

[0004] Embodiments of the present application provide a manufacturing method of semiconductor structure. The manufacturing method of semiconductor structure includes:

[0005] A lead frame is provided, the lead frame includes a plurality of pins, a plurality of first connecting parts, and a second connecting part; the pins are connected to adjacent second connecting parts through the first connecting parts; the pins include opposite first surfaces and second surfaces;

[0006] A plastic encapsulation structure is formed, the plastic encapsulation structure includes the lead frame, a chip, and a plastic encapsulation layer, the chip faces the first surfaces, the plastic encapsulation layer encapsulates the chip and the lead frame, and the second surfaces are exposed from the plastic encapsulation layer;

[0007] A groove is formed between the second connecting part and the pins connected thereto, at least part of the side surface of each pin facing the first connecting part connected thereto is exposed by the groove, at least part of the surface of the second connecting part facing away from the chip is covered by the plastic encapsulation layer, and the length of the area of the surface of the second connecting part facing away from the chip covered by the plastic encapsulation layer is equal to the length of the second connecting part;

[0008] A solder layer is formed on the exposed surface of the lead frame;

[0009] The obtained structure is cut along a cutting path to remove the second connecting part, and at least one semiconductor structure is obtained, the semiconductor structure includes at least one chip; the orthogonal projection of the cutting path on the plane where the first surfaces are located falls within the orthogonal projection of the groove on the plane.

[0010] In one embodiment, the second connecting part comprises a first portion and a second portion extending along a length direction, the first portion is located at a side of the second portion facing the first connecting part, and the thickness of the first portion is less than the thickness of the second portion; after the groove is formed between the second connecting part and the lead connected thereto, the surface of the first portion facing away from the chip is covered by the plastic encapsulation layer.

[0011] In one embodiment, the thickness of the second portion is equal to the thickness of the lead; after the groove is formed between the second connecting part and the lead connected thereto, the surface of the second portion facing away from the chip is exposed to the plastic encapsulation layer.

[0012] In one embodiment, two sides of at least one second connecting part are connected to the first connecting part respectively, and the second connecting part comprises two first portions located at opposite sides of the second portion.

[0013] In one embodiment, the two first portions of the second connecting part have the same width.

[0014] In one embodiment, the thickness of each region of the second connecting part is less than the thickness of the lead, and after the groove is formed between the second connecting part and the lead connected thereto, the surface of the second connecting part facing away from the chip is entirely covered by the plastic encapsulation layer.

[0015] In one embodiment, the cutting width when the structure obtained by cutting along the cutting path is cut is less than the width of the groove.

[0016] In one embodiment, at least one side of the surface of the first connecting part facing away from the second surface is provided with a recess, and the orthogonal projection of the recess on the plane where the first surface is located overlaps with the orthogonal projection of the cutting path on the plane.

[0017] In one embodiment, after the groove is formed between the second connecting part and the lead connected thereto, the size of the portion of the lead exposed on the side facing the first connecting part connected thereto in the thickness direction of the lead is greater than or equal to half of the thickness of the lead.

[0018] In one embodiment, the lead frame comprises a plurality of second connecting parts, and the plurality of second connecting parts are electrically connected.

[0019] The main technical effects achieved by the embodiments of the present application are as follows:

[0020] The manufacturing method of the semiconductor structure provided by the embodiment of the present application can form the solder layer on the exposed side of the pin, so as to meet the requirement of welding the side of the pin. After forming the groove, at least part of the surface of the second connecting part away from the chip is covered by the plastic sealing layer, so that the part of the surface of the second connecting part away from the chip covered by the plastic sealing layer does not form the solder layer. The solder layer is located in a smaller area of the surface of the second connecting part away from the chip, so as to reduce the probability of cutting the part of the solder layer located in the surface of the second connecting part away from the chip due to cutting error, reduce the risk of generating the wire drawing caused by cutting the solder layer, and further improve the problem of short circuit of the semiconductor structure caused by the wire drawing falling between the two adjacent first connecting parts after the wire drawing falls off, so as to improve the product yield of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a flowchart of the manufacturing method of the semiconductor structure provided by an example embodiment of the present application;

[0022] Figure 2 is a partial top view of a lead frame provided by an example embodiment of the present application;

[0023] Figure 3 is a sectional view of the lead frame shown in Figure 2 along AA;

[0024] Figure 4 is a partial top view of a lead frame provided by another example embodiment of the present application;

[0025] Figure 5 is a sectional view of the lead frame shown in Figure 4 along CC;

[0026] Figure 6 is a sectional view of the lead frame shown in Figure 2 along BB, and Figure 3 a sectional view of the lead frame shown in

[0027] Figure 7 is a partial sectional view of a semiconductor package structure provided by an example embodiment of the present application;

[0028] Figure 8 is a partial sectional view of a semiconductor package structure provided by another example embodiment of the present application;

[0029] Figure 9 is a partial sectional view of a first intermediate structure provided by an example embodiment of the present application;

[0030] Figure 10 is a sectional view of the first intermediate structure shown in Figure 9a perspective view of a first intermediate structure shown;

[0031] Figure 11 a partial cross-sectional view of a first intermediate structure according to another example embodiment of the present application;

[0032] Figure 12 a partial cross-sectional view of a second intermediate structure according to an example embodiment of the present application;

[0033] Figure 13 a partial cross-sectional view of a second intermediate structure according to another example embodiment of the present application;

[0034] Figure 14 a cross-sectional view of a semiconductor structure according to an example embodiment of the present application. DETAILED DESCRIPTION

[0035] Reference will now be made to specific embodiments of the application, examples of which are illustrated in the accompanying drawings. Understanding that the following

[0036] The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in this application, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0037] It should be understood that although the terms first, second, third, etc. can be used herein to describe various information, these terms are not intended to denote a particular order or hierarchy among the information. These terms are used merely for the sake of description and are not intended to convey any meaning beyond the scope of the application. The word "if' as used herein means "when" or "upon" or "in response to the

[0038] Some embodiments of the present application will now be described in detail in connection with the accompanying drawings. The following description is merely exemplary in nature and is not intended to limit the application since modifications can be made by those skilled in the art with the benefit of the teachings herein. The description of the exemplary embodiments is intended to be illustrative, and not to limit the scope of the application. Many changes, modifications, variations, and other uses of the present application will become apparent to those skilled in the art after studying the present description, which is illustrative only and does not limit the scope of the application. As used herein, "exemplary" or "illustrative" means "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" or "illustrative" is not necessarily to be construed as preferred or advantageous over other implementations. The following detailed description is exemplary in nature and is intended to provide a thorough and complete disclosure of the embodiments of the application. Such a disclosure is not intended to be limiting, but rather exemplary of the embodiments of the application. Numerous modifications and variations within the scope of the present application are possible in light of the above teachings. It is, therefore, to be understood that within the scope of the

[0039] The present embodiments provide a method for manufacturing a semiconductor structure. As shown in FIG. 1, the method includes the following steps. Figure 1As shown, the manufacturing method of the semiconductor structure comprises steps 110-150.

[0040] In step 110, a lead frame is provided, which comprises a plurality of pins, a plurality of first connecting portions and a second connecting portion; the pins are connected to adjacent second connecting portions through the first connecting portions; the pins comprise opposite first surfaces and second surfaces.

[0041] In step 120, a plastic encapsulation structure is formed, which comprises the lead frame, a chip and a plastic encapsulation layer; the chip faces the first surfaces; the plastic encapsulation layer encapsulates the chip and the lead frame; the second surfaces are exposed from the plastic encapsulation layer.

[0042] In step 130, a groove is formed between the second connecting portion and the pins connected thereto; at least part of the side surface of each pin facing the first connecting portion connected thereto is exposed by the groove; at least part of the surface of the second connecting portion facing away from the chip is covered by the plastic encapsulation layer; and the length of the area of the surface of the second connecting portion facing away from the chip covered by the plastic encapsulation layer is equal to the length of the second connecting portion.

[0043] In step 140, a solder layer is formed on the exposed surface of the lead frame.

[0044] In step 150, the obtained structure is cut along a cutting path to remove the second connecting portion, thereby obtaining at least one semiconductor structure comprising at least one chip; the orthogonal projection of the cutting path on the plane where the first surfaces are located falls within the orthogonal projection of the groove on the plane.

[0045] The manufacturing method of the semiconductor structure provided by the embodiments of the present application can expose at least part of the side surface of the pin after forming the groove between the second connecting portion and the adjacent pin, and then form a solder layer on the exposed side surface of the pin, thereby meeting the requirement of soldering the side surface of the pin; since at least part of the surface of the second connecting portion facing away from the chip is covered by the plastic encapsulation layer after forming the groove, the part of the surface of the second connecting portion facing away from the chip covered by the plastic encapsulation layer will not form a solder layer, thereby reducing the probability of cutting into the part of the surface of the second connecting portion facing away from the chip where the solder layer is located due to cutting errors, reducing the risk of generating a wire caused by cutting into the solder layer, and further improving the problem of short circuit of the semiconductor structure caused by the wire falling between the adjacent two first connecting portions after the wire falls off, thereby improving the product yield of the semiconductor structure.

[0046] The manufacturing method of the semiconductor structure provided by the embodiments of the present application will be described in detail below.

[0047] In step 110, a lead frame is provided, the lead frame comprising a plurality of leads, a plurality of first connecting portions, and a second connecting portion; the leads are connected to adjacent second connecting portions through the first connecting portions; the leads comprise opposite first surfaces and second surfaces.

[0048] As shown in Figures 2 to 5 , the lead frame comprises leads 10, first connecting portions 20, and a second connecting portion 30, one end of the first connecting portion 20 is connected to the lead 10, and the other end is connected to the second connecting portion 30. The same second connecting portion 30 can be connected to a plurality of leads 10, and the plurality of leads 10 connected to the same second connecting portion 30 and located on the same side of the second connecting portion 30 are arranged in the length direction of the second connecting portion 30.

[0049] The "length" mentioned in the embodiments of the present application refers to the size of the X direction in Figure 2 and Figure 4 , the "width" refers to the size of the Y direction in Figure 2 and Figure 4 , and the "thickness" refers to the size of the Z direction in Figure 3 and Figure 5 .

[0050] In one embodiment, the lead frame comprises a plurality of second connecting portions, and the plurality of second connecting portions are electrically connected. In some embodiments, part of the plurality of second connecting portions extend in the transverse direction, and the rest of the second connecting portions extend in the longitudinal direction, and the second connecting portions extending in the transverse direction are connected to the second connecting portions extending in the longitudinal direction.

[0051] In one embodiment, as shown in Figure 3 and Figure 5 , the first connecting portion 20 comprises a first sub-connecting portion 21 and a second sub-connecting portion 22 connected to the first sub-connecting portion 21, the maximum thickness of the first sub-connecting portion 21 can be the same as the thickness of the lead 10, and greater than the thickness of the second sub-connecting portion 22. The surface on the same side of the first sub-connecting portion 21 and the second surface 12 of the lead 10 is flush with the second surface 12, and the surface on the same side of the first sub-connecting portion 21 and the first surface 13 of the lead 10 is flush with the first surface 13. The surface on the same side of the second sub-connecting portion 22 and the first surface 13 of the lead 10 is flush with the first surface 13, and the surface of the second sub-connecting portion 22 facing away from the first surface 13 is lower than the second surface 12. The first sub-connecting portion 21 is connected to the lead 10, and the second sub-connecting portion 22 is connected to the second connecting portion 30.

[0052] In one embodiment, as shown in Figure 2 and Figure 3As shown, the second connecting portion 30 includes a first portion 31 and a second portion 32 extending along the length direction, and the length of the first portion 31 and the length of the second portion 32 are both equal to the length of the second connecting portion 30. The thickness of the first portion 31 is less than the thickness of the second portion 32, and the thickness of the second portion 32 is equal to the thickness of the pin 10. The surface of the second portion 32 on the same side as the second surface 12 is flush with the second surface 12, and the surface of the second portion 32 on the same side as the first surface 13 is flush with the first surface 13. The surface of the first portion 31 on the same side as the first surface 13 is flush with the first surface 13, and the surface of the first portion 31 away from the first surface 13 is lower than the second surface 12. By setting the thickness of the second portion 32 to be greater than the thickness of the first portion 31, and the surface of the second portion 32 on the same side as the second surface 12 to be flush, it is possible to reduce the possibility of wire drawing in the subsequent cutting process while ensuring the strength of the lead frame.

[0053] In another embodiment, as shown in Figure 5 the thickness of each region of the second connecting portion 30 is less than the thickness of the pin 10, and the thickness of the second connecting portion 30 is uniform. The thickness of the second connecting portion 30 can be the same as the thickness of the second sub-connecting portion 22. The surface of the second connecting portion 30 on the same side as the first surface 13 is flush with the first surface 13, and the surfaces of the second connecting portion 30 away from the second surface 12 are flush and lower than the second surface 12.

[0054] In one embodiment, as shown in Figure 6 the first connecting portion 20 is provided with a recess 211 on at least one side of the surface away from the second surface 12. The orthogonal projection of the recess 211 on the plane of the first surface 13 overlaps with the orthogonal projection of the cutting path on the plane. In this way, the cutting stress can be reduced and the cutting difficulty can be reduced when the obtained structure is cut in step 150. Furthermore, compared with the scheme in which the recess is provided on the surface of the first connecting portion 20 away from the first surface, the surface area of the first connecting portion 20 away from the first surface 13 can be larger, and thus the surface area of the first connecting portion away from the first surface 13 in the final obtained semiconductor structure can be larger, which helps to increase the soldering area of the semiconductor structure and other structures such as a circuit board. In some embodiments, the recess 211 can be located in the first sub-connecting portion 21. Figure 6 In the embodiment shown, the opposite sides of the surface of the first connecting portion 20 away from the second surface 12 are respectively provided with recesses 211, so as to more effectively reduce the cutting difficulty. In other embodiments, only one side of the surface of the first connecting portion 20 away from the second surface 12 can be provided with a recess 211.

[0055] In step 120, a plastic package structure is formed, which includes the lead frame, the chip and the plastic layer, the chip faces the first surface, the plastic layer encapsulates the chip and the lead frame, and the second surface of the lead frame is exposed by the plastic layer.

[0056] The semiconductor package structure obtained by step 120 can be as shown in Figure 7 or Figure 8 The semiconductor package structure obtained by step 120 can be as shown in Figure 7 and Figure 8 The plastic layer and the surface of the lead frame on the same side of the second surface can be flush with each other. The semiconductor package structure can include a plurality of chips 50, the chips 50 are located on one side of the lead frame, and the chips 50 face the first surface of the lead frame; the plastic layer 80 encapsulates the chips 50 and the lead frame, and the second surface of the lead frame is exposed by the plastic layer 80.

[0057] In one embodiment, as shown in Figure 7 and Figure 8 The lead frame can further include a base island 40, and the chip 50 is attached to the base island 40 through an adhesive layer 60. The chip 50 can include a chip front surface and a chip back surface opposite to the chip front surface, and the chip back surface is attached to the base island 40 through the adhesive layer 60. The adhesive layer 60 can be, for example, a tin paste or a silver paste. In other embodiments, the material of the adhesive layer 60 can be a resin-based adhesive or other non-conductive adhesive. The chip front surface can be provided with a solder pad, and the solder pad can be electrically connected to the lead frame 10 through a bonding wire 70, so that the lead frame 10 can lead out the solder pad of the chip 50.

[0058] In one embodiment, when the structure of the lead frame is as shown in Figure 3 , the semiconductor package structure can be as shown in Figure 7 The surface of the second part 32 away from the chip 50 is exposed by the plastic layer 80, the surface of the first sub-connection part 21 away from the chip 50 is exposed by the plastic layer 80, and the surface of the second sub-connection part 22 away from the chip 50 and the surface of the first part 31 away from the chip 50 are covered by the plastic layer 80; the space between the first sub-connection part 21 and the second connection part 30 of the lead frame is filled by the plastic layer 80.

[0059] In another embodiment, when the structure of the lead frame is as shown in Figure 5 , the semiconductor package structure can be as shown in Figure 8 The surface of the first sub-connection part 21 away from the chip 50 is exposed by the plastic layer 80, the surface of the second sub-connection part 22 away from the chip 50 and the surface of the second connection part 30 away from the chip 50 are all covered by the plastic layer 80; the space between the two first sub-connection parts 21 of the lead frame is filled by the plastic layer 80.

[0060] In step 130, a groove is formed between the second connecting portion and the pins connected thereto, at least part of the side of each pin facing the first connecting portion connected thereto is exposed by the groove, at least part of the surface of the second connecting portion facing away from the chip is covered by the plastic encapsulation layer, and the length of the area of the surface of the second connecting portion facing away from the chip covered by the plastic encapsulation layer is equal to the length of the second connecting portion.

[0061] In one embodiment, a cutting process can be used to form the groove 101 between the second connecting portion 30 and the pins 10 connected thereto. The width of the cutting knife used in cutting is large, and during the cutting process, the second connecting portion 30 is pressed by the cutting knife, which causes the width of the second connecting portion 30 to increase. If the surface of the second connecting portion 30 facing away from the chip is completely exposed after step 130, the width of the part of the solder layer formed on the second connecting portion 30 is large, and during cutting in step 150, the solder layer on the surface of the second connecting portion 30 is easily cut, which causes wire drawing.

[0062] In one embodiment, when the semiconductor package structure is as shown in Figure 7 , the first intermediate structure as shown in Figure 9 and Figure 10 can be obtained by step 130. As shown in Figure 9 and Figure 10 , part of the side 11 of the pin 10 facing the second connecting portion 30 is exposed from the plastic encapsulation layer 80, and the first part 31 of the surface of the second connecting portion 30 facing away from the chip 50 is covered by the plastic encapsulation layer 80. Part of the first connecting portion 20 is removed when the groove 101 is formed, and after the groove 101 is formed, the surface of the first connecting portion 20 facing away from the chip 50 is flush and exposed from the plastic encapsulation layer 80. Since the first part 31 of the second connecting portion 30 facing away from the chip 50 is covered by the plastic encapsulation layer 80, the surface of the first part 31 facing away from the chip 50 is not formed with a solder layer in subsequent steps, which reduces the width of the solder layer formed on the surface of the second connecting portion 30 facing away from the chip 50, and further reduces the risk of cutting the solder layer on the surface of the second connecting portion 30 due to cutting errors and the increase in the width of the second connecting portion 30 when the groove is formed by the cutting process in step 150, thereby improving the yield of the semiconductor structure.

[0063] Further, as shown in Figure 9 and Figure 10 , the second part 32 of the surface of the second connecting portion 30 facing away from the chip 50 is exposed from the plastic encapsulation layer 80. When the thickness of the second part 32 is equal to the thickness of the pin 10, the second part 32 of the surface of the second connecting portion 30 facing away from the chip 50 is exposed from the plastic encapsulation layer 80.

[0064] Further, as shown in Figure 9 , the second part 32 of the surface of the second connecting portion 30 facing away from the chip 50 is exposed from the plastic encapsulation layer 80. When the thickness of the second part 32 is equal to the thickness of the pin 10, the second part 32 of the surface of the second connecting portion 30 facing away from the chip 50 is exposed from the plastic encapsulation layer 80.Figure 10 As shown, two sides of the second connecting part 30 are connected with the first connecting part 20 respectively; the second connecting part 30 comprises two first parts 31, and the two first parts 31 are located at opposite sides of the second part 32. When cutting is performed in the subsequent step 150, cutting needs to be performed at the grooves 101 at the two sides of the second connecting part 30 respectively. By arranging the first part 31 at the opposite sides of the second part 32 respectively, the distance between the pin located at the two sides of the second part 32 and the second part 32 can be made larger, and cutting to the part of the solder layer located on the surface of the second part 32 can be avoided when cutting is performed at the grooves 101 at the two sides of the second connecting part 30.

[0065] Further, the widths of the two first parts 31 of the second connecting part 30 are the same. By such arrangement, the width of one of the first parts 31 is not made smaller, so that the distance between the pin of the first part 31 and the second part 32 is not made smaller and the cutting to the part of the solder layer located on the surface of the second part 32 can be effectively avoided.

[0066] In another embodiment, the semiconductor package structure is as shown in Figure 8 and the first intermediate structure as shown in Figure 11 is obtained. As shown in Figure 11 , a part of the side surface 11 of the pin 10 facing the second connecting part 30 is exposed from the plastic encapsulation layer 80, and the surface of the second connecting part 30 away from the chip 50 is entirely covered by the plastic encapsulation layer 80. The part of the first connecting part 20 is removed when the groove 101 is formed, and the surface of the first connecting part 20 away from the chip 50 can be flush with and exposed from the plastic encapsulation layer 80 after the groove 101 is formed. Since the surface of the second connecting part 30 away from the chip 50 is entirely covered by the plastic encapsulation layer 80, no solder layer is formed on the surface of the second connecting part 30 away from the chip 50 in the subsequent steps, so that even if the second connecting part 30 is cut due to cutting error in the step 150, the solder layer is not pulled out, thereby helping to improve the yield of the semiconductor structure.

[0067] In one embodiment, after the step of forming the groove between the second connecting part and the pin connected therewith, the size of the part of the side surface of the pin 10 facing the first connecting part 20 connected therewith in the thickness direction of the pin 10 is greater than or equal to half of the thickness of the pin 10. By such arrangement, the size of the solder layer formed on the side surface of the semiconductor structure obtained finally in the thickness direction of the pin 10 is greater than or equal to half of the thickness of the pin 10, which helps to ensure the welding effect of the side surface of the semiconductor structure and other structures such as a circuit board. The size of the part of the side surface of the pin 10 facing the first connecting part 20 connected therewith in the thickness direction of the pin 10 is the same as the depth of the groove 101.

[0068] In one embodiment, the extending direction of the groove 101 is the same as that of the second connecting part 30, and the length of the groove 101 is the same as that of the second connecting part 30.

[0069] In one embodiment, when the opposite sides of the second connecting part 30 are respectively connected with the pins 10, the opposite sides of the second connecting part 30 are respectively formed with the grooves 101.

[0070] In step 140, a solder layer is formed on the exposed surface of the lead frame.

[0071] In one embodiment, the solder layer can be formed on the exposed surface of the lead frame by electroplating process. The exposed surface of the lead frame includes the surface of the pin 10 facing away from the chip 50, the part of the side surface of the pin 10 exposed by the groove 101, the exposed surface of the first connecting part 20, and the exposed surface of the second connecting part 30. Since the second connecting parts of the lead frame are electrically connected, and each pin is connected with the first connecting part and the second connecting part respectively, each structure of the lead frame is electrically connected, and the exposed surface of the lead frame can be simultaneously formed with the solder layer when electroplating is performed.

[0072] In one embodiment, the material of the solder layer is tin.

[0073] In one embodiment, the first intermediate structure is as shown in FIG. 4A, and the second intermediate structure obtained by step 140 is as shown in FIG. 4B. Figure 9 Figure 12 In one embodiment, the first intermediate structure is as shown in FIG. 4A, and the second intermediate structure obtained by step 140 is as shown in FIG. 4B. Figure 12 As shown in FIG. 4B, the solder layer 90 is partially located on the surface of the pin 10 facing away from the chip 50, partially on the part of the side surface 11 of the pin 10 exposed by the groove 101, partially on the surface of the second part 32 facing away from the chip 50, and partially on the surface of the first connecting part 20 facing away from the chip 50.

[0074] In another embodiment, the first intermediate structure is as shown in FIG. 5A, and the second intermediate structure obtained by step 150 is as shown in FIG. 5B. Figure 11 Figure 13 In another embodiment, the first intermediate structure is as shown in FIG. 5A, and the second intermediate structure obtained by step 150 is as shown in FIG. 5B. Figure 13 As shown in FIG. 5B, the solder layer 90 is partially located on the surface of the pin 10 facing away from the chip 50, partially on the part of the side surface 11 of the pin 10 exposed by the groove 101, partially on the surface of the first connecting part 20 facing away from the chip 50, and the surface of the second connecting part 30 facing away from the chip 50 is not formed with the solder layer 90.

[0075] In step 150, the obtained structure is cut along the cutting path to remove the second connecting part, and at least one semiconductor structure is obtained, which includes at least one chip; the orthogonal projection of the cutting path on the plane where the first surface is located falls within the orthogonal projection of the groove on the plane.​​

[0076] In one embodiment, the cutting width when cutting the structure obtained along the cutting path is less than the width of the groove. Since the orthogonal projection of the cutting path on the plane where the first surface is located falls within the orthogonal projection of the groove on the plane, by setting the cutting width when cutting the structure obtained along the cutting path to be less than the width of the groove, when the solder layer is formed on the surface of the second connecting portion 30 facing away from the chip 50, even if there is a cutting error, the solder layer can be effectively avoided from being cut when cutting the solder layer on the surface of the second connecting portion 30, and the occurrence of the solder layer being pulled out can be effectively prevented.

[0077] In one embodiment, the width of the groove 101 is in the range of 0.3mm to 1.0mm, and the cutting width when cutting the structure obtained along the cutting path is in the range of 0.2mm to 0.35mm. In some embodiments, the width of the groove 101 is 0.5mm, and the cutting width when cutting the structure obtained along the cutting path is 0.25mm.

[0078] In one embodiment, the semiconductor structure can include the portion where the first connecting portion 20 is connected to the pin 10, as shown in FIG. 10. In other embodiments, when the cutting precision is relatively high, the semiconductor structure can not include the portion where the first connecting portion 20 is connected to the pin. Figure 14

[0079] It is noted that the dimensions of the layers and regions are exaggerated in the drawings for clarity. Also, it is to be understood that when a layer or element is referred to as being "on" another layer or element, it can be directly on the other element or intervening layers can also be present. Furthermore, it is to be understood that when a layer or element is referred to as being "beneath" another layer or element, it can be directly beneath the other element, or intervening layers or elements can also be present. In addition, it is to be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer or element between the two layers or elements or one or more intervening layers or elements can also be present. Like reference numerals refer to like elements throughout.

[0080] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0081] ​It is to be understood that the application is not limited to the precise construction already described above and shown in the drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application should only be limited by the claims appended hereto.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, The manufacturing method comprises: providing a lead frame comprising a plurality of pins, a plurality of first connecting portions and a second connecting portion; the pins are connected to adjacent second connecting portions through the first connecting portions; the pins comprise opposite first surfaces and second surfaces; forming a plastic encapsulation structure comprising the lead frame, a chip and a plastic encapsulation layer, the chip faces the first surfaces, the plastic encapsulation layer encapsulates the chip and the lead frame, and the second surfaces are exposed from the plastic encapsulation layer; forming a groove between the second connecting portion and the pins connected thereto, at least part of the side of each pin facing the first connecting portion connected thereto is exposed by the groove, at least part of the surface of the second connecting portion facing away from the chip is covered by the plastic encapsulation layer, and the length of the area of the surface of the second connecting portion facing away from the chip covered by the plastic encapsulation layer is equal to the length of the second connecting portion; forming a solder layer on the exposed surface of the lead frame; cutting the obtained structure along a cutting path to remove the second connecting portion and obtain at least one semiconductor structure comprising at least one chip; the orthogonal projection of the cutting path on the plane where the first surfaces are located falls within the orthogonal projection of the groove on the plane.

2. The method of manufacturing a semiconductor structure according to claim 1, wherein The second connecting portion comprises a first part and a second part extending along the length direction, the first part is located on the side of the second part facing the first connecting portion, and the thickness of the first part is smaller than the thickness of the second part; after the groove is formed between the second connecting portion and the pins connected thereto, the surface of the first part facing away from the chip is covered by the plastic encapsulation layer.

3. The method of manufacturing a semiconductor structure according to claim 2, wherein The thickness of the second part is equal to the thickness of the pin; after the groove is formed between the second connecting portion and the pins connected thereto, the surface of the second part facing away from the chip is exposed from the plastic encapsulation layer.

4. The method of manufacturing a semiconductor structure according to claim 2, wherein Both sides of at least one second connecting portion are connected to the first connecting portions, respectively, the second connecting portion comprises two first parts, and the two first parts are located on opposite sides of the second part.

5. The method of manufacturing a semiconductor structure according to claim 4, wherein The widths of the two first parts of the second connecting portion are the same.

6. The method of manufacturing a semiconductor structure according to claim 1, wherein The thickness of each area of the second connecting portion is smaller than the thickness of the pin; after the groove is formed between the second connecting portion and the pins connected thereto, the surface of the second connecting portion facing away from the chip is entirely covered by the plastic encapsulation layer.

7. The method of manufacturing a semiconductor structure according to claim 1, wherein The cutting width when the obtained structure is cut along the cutting path is smaller than the width of the groove.

8. The method of manufacturing a semiconductor structure according to claim 1, wherein At least one side of the surface of the first connecting portion facing away from the second surface is provided with a recess, and the orthogonal projection of the recess on the plane where the first surfaces are located overlaps with the orthogonal projection of the cutting path on the plane.

9. The method of manufacturing a semiconductor structure according to claim 1, wherein After the groove is formed between the second connecting portion and the pins connected thereto, the size of the part of the pin facing the first connecting portion connected thereto and exposed in the thickness direction of the pin is greater than or equal to half of the thickness of the pin.

10. The method of manufacturing a semiconductor structure according to claim 1, wherein The lead frame comprises a plurality of second connecting portions, and the plurality of second connecting portions are electrically connected.

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