Semiconductor device manufacturing method and integrated circuit structure

Abstract

One aspect of the disclosure relates to a method of semiconductor device fabrication. The method comprises the following steps: forming a transistor on a semiconductor substrate; forming a first metal layer and an overlying second metal layer over the transistor; depositing a heat dissipation layer above the overlying second metal layer; and annealing the heat dissipation layer to a temperature above the threshold temperature. The deposition of the heat dissipation layer is performed below the threshold temperature. During the annealing, the first metal layer and the overlying second metal layer are maintained below a threshold temperature. One aspect of the embodiments of the present application also relates to an integrated circuit structure.

Description

Technical Field

[0001] Embodiments of the present application relate to a method for manufacturing a semiconductor device and an integrated circuit structure. Background Art

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices that can support more and more complex and advanced functions at the same time. In order to meet these needs, there is a continuous trend in the integrated circuit (IC) industry towards manufacturing low-cost, high-performance, and low-power ICs. So far, these goals have been achieved to a large extent by reducing the IC size (e.g., minimum feature size), thereby improving production efficiency and reducing related costs. However, this scaling also increases the complexity of the IC manufacturing process. Therefore, the continued progress of achieving IC devices and their performance requires similar progress in IC manufacturing processes and technologies.

[0003] As technology advances, there has been an increased focus on dissipating the heat generated by semiconductor devices such as transistors, as higher temperatures may degrade device performance. The situation is further complicated in semiconductor devices including multi-die configurations such as stacked die configurations, which further restrict the heat dissipation path. Thus, while existing semiconductor device structures are generally adequate for their intended purposes, they are not completely satisfactory in every aspect. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising: forming a transistor on a semiconductor substrate; forming a first metal layer and an overlying second metal layer above the transistor; depositing a heat dissipation layer above the overlying second metal layer, wherein the deposition of the heat dissipation layer is performed below a threshold temperature; and annealing the heat dissipation layer to a temperature above the threshold temperature, wherein during the annealing, the first metal layer and the overlying second metal layer are maintained below the threshold temperature.

[0005] According to another aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising: forming a transistor device on a substrate; forming a multi-layer interconnect (MLI) above the transistor device; depositing a thermally conductive material on the MLI; after the deposition of the thermally conductive material, performing a heat treatment on the thermally conductive material to improve the thermal conductivity of the thermally conductive material; and planarizing the thermally conductive material.

[0006] According to another aspect of an embodiment of the present application, an integrated circuit structure is provided, including: a transistor device formed on a substrate, the transistor device having a source / drain (S / D) region and a gate structure; a multi-layer interconnect (MLI) structure located above the transistor device, wherein the MLI structure includes metal lines and metal vias embedded in an inter-metal dielectric (IMD) layer; and a heat dissipation layer disposed above at least a portion of the MLI structure, wherein a top portion of the heat dissipation layer has a larger grain size than a bottom portion of the heat dissipation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion. It should also be emphasized that the accompanying drawings illustrate only typical embodiments of the present disclosure and, therefore, should not be considered limiting in scope, as the present disclosure may be equally well applied to other embodiments. In addition, the drawings may implicitly describe features that are not explicitly described in the detailed description.

[0008] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F ,and Figure 1G shows cross-sectional views of semiconductor device structures at different stages of fabrication on which a heat dissipation layer is formed according to some aspects of the present disclosure;

[0009] Figure 2A , Figure 2B , Figure 2C ,and Figure 2D Graphs showing the relationship between temperature, grain size, crystallization ratio, and crystal orientation consistency and the height of a heat sink layer above a semiconductor device structure according to some aspects of the present disclosure are shown respectively;

[0010] Figure 3 A flow chart showing an embodiment of a method for manufacturing a semiconductor device having a heat dissipation layer according to aspects of the present disclosure;

[0011] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 ,and Fig.11 According to some aspects of the present disclosure Figure 3 A cross-sectional view of a semiconductor structure corresponding to transitional manufacturing steps of the method. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] For ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0014] In addition, when "about", "approximately", etc. are used to describe a number or a range of numbers, the term is intended to cover numbers within a reasonable range that take into account variations inherently caused during manufacturing as understood by a person of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing a component (which has features associated with the number), the number or range of numbers covers a reasonable range that includes the described number, for example, within + / -10% of the described number. For example, a material layer having a thickness of "about 5nm" can cover a range of sizes from 4.5nm to 5.5nm, where a person of ordinary skill in the art knows that the manufacturing tolerance associated with the deposited material layer is + / -10%. In addition, the disclosed dimensions of different features can implicitly disclose the size ratios between the different features. Further, the present disclosure may repeat reference numbers and / or letters in various examples. The repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] The present disclosure relates to semiconductor structures, such as integrated circuit (IC) structures that include one or more dies to form semiconductor structures. These structures may be referred to as 3D ICs because they integrate ICs in part by stacking dies in a vertical direction. The components of the stacked structure may be connected physically and / or by electrical connections. 3D ICs provide form factor advantages as well as power and performance advantages, including by virtue of the interconnect lengths between stacked devices. One application of a 3D IC structure is a vertically stacked processor and one or more memory chips. However, semiconductor structures including 3D ICs may encounter challenges with heat dissipation within the structure.

[0016] Therefore, some embodiments described herein provide semiconductor structures including thermal dissipation layers (also referred to as heat spreading layers) to provide heat dissipation paths. In some embodiments, thermally conductive materials are implemented as heat spreading layers to provide high thermal conductivity in 3D ICs. In the context of the present disclosure, the terms "conductive" and "conductivity" specifically refer to "electrically conductive" and "electrical conductivity", respectively, to distinguish them from the terms "thermal conductive" and "thermal conductivity". The thermally conductive material used herein is defined as a material having a thermal conductivity of not less than 10 W / m·K (watts per meter Kelvin). In some embodiments, the thermally conductive material may include boron nitride (BN) (e.g., hexagonal BN (h-BN) or cubic BN (c-BN)), aluminum nitride (AlN), graphene, carbon, diamond, diamond-like carbon, benzoic acid (BA), transition metal dichalcogenides (TMD) (e.g., MoS2, MoSe2, WS2, or WSe2), etc. Thus, the present disclosure provides benefits for structures and methods that allow high thermal conductivity between layers of a semiconductor structure (e.g., between dies) for thermal management.

[0017] In the following description, front-end-of-line (FEOL) generally refers to the portion of the circuit where functional devices such as logic and memory devices are formed. FEOL components include transistors and their components, such as source / drain components, channel regions, gate structures. Device-level contacts or metal components extend to the terminals of the transistors. Back-end-of-line (BEOL) in the present disclosure generally refers to components formed after the FEOL components, including multi-layer interconnects (MLI). MLI provides multiple metal lines (also called interconnect lines) and inserted vias, which provide electrical connections including to FEOL components. Metal lines provide horizontal wiring, and vias provide vertical wiring to connect metal lines in different metal layers. Any number of metal layers can be used, including, for example, an exemplary MLI can include five (5) or more vertically stacked metal lines, generally referred to as M1, M2, M3, M4, M5, etc. The MLI includes a dielectric or insulating material surrounding the metal lines and vias to provide suitable structural support. The dielectric or insulating material can be referred to as an intermetallic dielectric (IMD), as discussed below.

[0018] Figure 1A A cross-sectional view of a portion of a semiconductor structure 100 according to an embodiment of the present disclosure is shown. The semiconductor structure 100 may be part of an integrated circuit (IC) device and may include a plurality of device components (not shown).

[0019] As will be further described below for various embodiments, the semiconductor structure 100 is formed on a semiconductor structure that has been subjected to a FEOL process. Such a FEOL process can form various transistors on a substrate to serve different functions. For example, these different transistors can form a central processing unit (CPU), a graphics processing unit (GPU), an access transistor for a memory device, an image signal processing (ISP) circuit, and / or other suitable circuits. The transistor can be a planar transistor or a multi-gate transistor. A planar device refers to a device having a gate structure bonded to a planar surface of a semiconductor active region. A multi-gate device generally refers to a device having a gate structure or a portion thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications. FinFETs have an elevated channel surrounded by a gate on more than one side (e.g., a gate surrounds the top and sidewalls of a "fin" of a semiconductor material extending from a substrate). The gate structure of the GAA transistor can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Since its gate structure surrounds the channel region, the GAA transistor can also be called a surround gate transistor (SGT) or a multi-bridge channel (MBC) transistor. The channel region of the GAA transistor can be formed by nanowires, nanosheets, or other nanostructures, and therefore, the GAA transistor can also be called a nanowire transistor or a nanosheet transistor. The transistors mentioned generally herein, as well as each configuration discussed, are applicable to the embodiments of this article.

[0020] The semiconductor structure 100 includes a multi-layer interconnect (MLI) structure that includes multiple metal layers and is part of the BEOL as discussed above. One metal layer 102 of the MLI is shown. In some embodiments, the metal layer 102 is the top or uppermost metal layer of the MLI. In some embodiments, the metal layer 102 is an intermediate metal layer of the MLI, for example, a metal layer that is at M3 or above M3 but below the uppermost metal layer of the MLI. In some embodiments, the semiconductor structure 100 is formed on a semiconductor substrate including silicon (Si). Alternatively or in addition, the substrate includes another elemental semiconductor, such as germanium (Ge); a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In some embodiments, the substrate includes one or more III-V materials, one or more II-IV materials, or a combination thereof. In some embodiments, the substrate is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. The semiconductor-on-insulator substrate can be manufactured by separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0021] The MLI of the semiconductor structure 100 includes a plurality of metal lines or layers in the MLI, for example, the MLI may generally include about five (5) to about twenty (20) metal layers (or metallization layers). Each metal layer of the MLI includes a plurality of vias and metal lines embedded in a dielectric or insulating layer, which dielectric or insulating layer may also be referred to herein as an intermetallic dielectric (IMD) layer. The vias and metal lines may be formed of titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), or aluminum (Al). In one embodiment, they are formed of copper (Cu). The IMD layer may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), or doped silicate glass such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. In one embodiment, the IMD layer includes silicon oxide.

[0022] Figure 1AShown in the figure is a metal layer 102. In one embodiment, the metallization layer 102 is the top metal layer of the MLI of the semiconductor structure 100. In one embodiment, the metal layer 102 is the top metal layer of the tube core (e.g., the bottom tube core) of the semiconductor structure 100. In one embodiment, the metal layer 102 is an intermediate metal layer of the MLI of the semiconductor structure 100, for example, a metal layer that is located at M4 or above M4 but below the top metal layer of the MLI. The metal layer 102 may include metal lines and / or vias formed of copper (Cu), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al), or a combination thereof. The metal layer 102 includes an IMD surrounding the metal lines and / or vias. The IMD may be formed of silicon oxycarbide, silicon oxide, amorphous boron nitride (a-BN), SiCOH, SiCNH, PSG, BSG, BPSG, FSG, TEOS oxide, HSQ, MSQ, etc. The IMD may also be a low-k (LK) dielectric layer having a dielectric constant value less than about 3.9, or an extremely low-k (ELK) dielectric layer having a dielectric constant value less than about 3.0.

[0023] In the semiconductor structure 100, on the metal layer 102 is a heat dissipation layer 104. The heat dissipation layer 104 is made of a thermally conductive material such as boron nitride (BN), aluminum nitride (AlN), graphene, carbon, diamond, diamond-like carbon, benzoic acid (BA), transition metal dichalcogenides (TMD) (e.g., MoS2, MoSe2, WS2, or WSe2), etc. The heat dissipation layer 104 may have a thickness between about 0.1 micrometers (μm) and 10 μm. The heat dissipation layer 104 may be deposited at a temperature less than or equal to about 400 degrees Celsius. Exemplary deposition methods include chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition ALD. It is not trivial or arbitrary that the temperature during the deposition process is less than or equal to about 400 degrees Celsius. This is because if the temperature exceeds 400 degrees Celsius, the high temperature may damage the BEOL features, especially the dielectric materials used in the IMD of the MLI. However, thermally conductive materials typically need to be deposited in a high temperature environment, typically in excess of 400 degrees Celsius, to ensure crystal quality and thereby achieve high thermal conductivity. Low temperature deposition processes typically result in the resulting heat sink layer suffering from low crystal quality and, therefore, low thermal conductivity. As discussed in further detail below, the present disclosure also applies a post-deposition thermal treatment to the heat sink layer 104 to implement a local annealing process. The annealing process is "local" because the high temperature region exceeding 400 degrees Celsius is confined to the heat sink layer 104 and does not cause the temperature in the underlying MLI to rise to above 400 degrees Celsius.

[0024] Figure 1BA semiconductor structure 100 is shown having a capping layer 106 deposited on a heat sink layer 104. The capping layer 106 may be composed of a material such as Ti, Al, Ni, silicon glass, Cr, Al2O3, SiO2, carbon, or a metal. The heat sink layer 104 may have a thickness between about 0.01 micrometers (μm) and 1 μm. The capping layer 106 serves two main functions. First, it acts as a light absorbing layer, which increases the light absorption rate when a pulsed laser is used in a post-deposition thermal treatment. Second, it serves as a thin protective layer to prevent oxidation of the heat sink layer 104 during the post-deposition thermal treatment. In some other embodiments, the deposition of the capping layer 106 may be skipped so that the post-deposition thermal treatment may be applied directly to the heat sink layer 104 without passing through the capping layer 106.

[0025] Figure 1C A semiconductor structure 100 receiving a post-deposition heat treatment is shown. In the illustrated embodiment, a pulsed laser 108 is applied to transfer transient heat to the semiconductor structure 100. This transient heat treatment is also referred to as a post-deposition laser annealing process. In one embodiment, the pulsed laser 108 is applied in a scanning mode. In one example, the pulsed laser 108 is scanned to the semiconductor structure 100 through an exemplary path 110. In the laser scanning path, the laser beam is scanned parallelly over the semiconductor structure 100 line by line. The laser beam has an energy density that is unevenly distributed, such as a Gaussian distribution. Adjacent scan lines have a certain overlap to more uniformly heat the heat dissipation layer 104. In one embodiment, the laser source for the laser annealing process includes a pulsed solid-state laser source. For example, the pulsed solid-state laser source can have a short wavelength of about 355nm, 405nm, 532nm, 633nm, or other suitable wavelengths. For ultraviolet and visible wavelengths, the input power density can be in the range of about 10W / m to about 500W / m, and for the microwave range, it can be as high as 10000W / m depending on the wavelength, repetition range, material, and structure. The laser source may have a pulse rate between about 10 kHz and about 300 kHz. The laser pulse may have a duration between about 10 ns and about 10 us and a scan rate between about 1 cm / s and about 10 cm / s. During the post-deposition laser annealing process, the semiconductor structure 100 may be in a vacuum environment, or in an inert gas environment such as argon or nitrogen. In some other embodiments, the semiconductor structure 100 may be an environment filled with air or H2. The semiconductor structure 100 may be placed on a temperature-controlled holder or stage, wherein the stage temperature is set between about -60 degrees Celsius and about 375 degrees Celsius.

[0026] Figure 2A1 shows the temperature gradient inside the semiconductor structure 100. The height H0 marks the top surface of the metal layer 102, and the height H1 marks the top surface of the heat dissipation layer 104. That is, the heat dissipation layer 104 extends between the marks H0 and H1. The temperature t1 at the interface between the metal layer 102 and the heat dissipation layer 104 is controlled at about 400 degrees Celsius, so that the temperature inside the metal layer 102 is well maintained below 400 degrees Celsius, while the temperature inside the heat dissipation layer 104 is generally above 400 degrees Celsius. In some embodiments, the temperature t2 at the top surface of the heat dissipation layer 104 can reach above 800 degrees Celsius.

[0027] The transient thermal treatment improves the thermal conductivity of the heat dissipation layer 104. In one aspect, the transient treatment improves thermal conductivity by improving thermal coupling at grain boundaries and / or by treating dangling bonds and defects. In another aspect, the transient thermal treatment improves thermal conductivity by inducing melting or amorphous to crystalline transition or phase change in the thin film material. In one example, the thermally conductive material deposited during the low temperature deposition process is amorphous boron nitride (a-BN), and is converted from (h-BN), cubic form (c-BN), or a combination of hexagonal and cubic forms to hexagonal, which has higher thermal conductivity. In another aspect, the transient thermal treatment improves thermal conductivity by improving crystallinity and directional alignment. Further, the top surface of the semiconductor structure 100 can be pre-patterned before depositing the thermally conductive material to induce preferential crystal orientation during transient laser heating. Pre-patterning improves the surface roughness of the top surface of the semiconductor structure 100.

[0028] Figure 2B , Figure 2C ,and Figure 2D The grain size gradient, crystallization rate gradient, and crystal orientation consistency gradient in the heat dissipation layer 104 are shown respectively. In each figure, the initial values ​​of the grain size (G0), crystallization rate (C0), and crystal orientation consistency (O0) of the heat dissipation layer 104 before transient heat treatment are also added as a reference. Figure 2B , Figure 2C ,and Figure 2D As shown in FIG. 1 , the transient heat treatment increases the grain size, crystallinity, and crystal orientation consistency within the heat dissipation layer 104, each of which contributes to improving thermal conductivity. In addition, each curve shows a gradient climbing up to the top surface of the heat dissipation layer 104, so that the top of the heat dissipation layer 104 has a higher grain size, crystallinity, and crystal orientation consistency than the bottom thereof. This is because the top of the heat dissipation layer 104 receives a higher temperature than the bottom thereof (e.g., Figure 2A The effectiveness of the transient heat treatment can be monitored by Raman spectroscopy and / or X-ray diffraction (XRD) spectroscopy.

[0029] Reference now Figure 1D . Figure 1DFIG. 1 shows the semiconductor structure 100 after removing the capping layer 106 . Figure 1A Compared with transient heat treatment, Figure 1D The grain size in the heat dissipation layer 104 shown in the figure is enlarged. The capping layer 106 can be removed in an etching process such as a wet etching process or a dry etching process. In one example, a process gas containing fluorine and carbon is used to implement the removal of the capping layer 106. For example, the process gas used for etching includes a gas containing fluorine and carbon, such as C4F8, CH2F2, and / or CF4, and a carrier gas, such as N2. In one example of the etching process, the flow rate of C4F8 is in a range between about 0 sccm and about 50 sccm, the flow rate of CF4 is in a range between about 0 sccm and about 300 sccm (and at least one of C4F8 has a non-zero flow rate), and the flow rate of N2 is in a range between about 0 sccm and about 200 sccm. According to an alternative embodiment, the process gas used for etching includes CH2F2, and a carrier gas such as N2. In an example of an etching process, a flow rate of CH 2 F 2 is in a range between about 10 sccm and about 200 sccm, and a flow rate of N 2 is in a range between about 50 sccm and about 100 sccm.

[0030] Can be repeated as Figure 1A-Figure 1D The formation process of the heat dissipation layer 104 shown in , to grow a stacked second heat dissipation layer or even more heat dissipation layers, to further grow the thickness of the entire heat dissipation layer. Figure 1E An exemplary final structure is shown in FIG. 1 , in which a second heat dissipation layer 104 ′ is formed. In each sub-heat dissipation layer, as shown in FIG. Figure 2B-Figure 2D The gradient shown in FIG. 1 is repeated in a discontinuous manner at the interface between two adjacent sub-heat sink layers, which, as explained above, is mainly due to the temperature gradient during the transient thermal treatment. In addition, the interface between adjacent sub-heat sink layers is identifiable.

[0031] In some embodiments, Figure 1D The heat dissipation layer 104 shown in FIG. 1 may be used as a seed layer for further growing a thicker heat dissipation layer in a low temperature deposition process below 400 degrees Celsius. Figure 1FAn exemplary final structure is shown in FIG. 1 , in which a thicker heat dissipation layer 104" is formed. In some embodiments, the low temperature deposition process can be a PVD or CVD process. One benefit of such a process is that only one transient thermal treatment needs to be performed during the formation of the seed layer 104, and further growth of a thicker heat dissipation layer 104" does not require further transient thermal treatment. In one example, the seed layer 104 has a thickness between about 10 nm and about 300 nm, while the thicker heat dissipation layer 104" has a thickness greater than about 500 nm. Since the thicker heat dissipation layer 104" extends the lattice of the seed layer 104, it can also inherit and continue the grain size ( Figure 2B G2 in), crystallization rate ( Figure 2C C2 in), and crystal orientation consistency ( Figure 2D In addition, the interface between the seed layer 104 and the thicker heat sink layer 104" may not be discernible.

[0032] Figure 1G An embodiment of a semiconductor structure 100 is shown, which has a dielectric or insulating layer 112 adjacent to a heat sink layer 104. Further, the insulating layer 112 can surround the heat sink layer 104 so that the heat sink layer 104 is in the form of an island. If it is considered that the thermally conductive material selected for the heat sink layer 104 is not sufficient to provide a strong bond or seal, the insulating layer 112 is used to facilitate the bond or seal. The insulating layer 112 and the heat sink layer 104 have different compositions. The insulating layer 112 may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), or doped silicate glass such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass, boron-doped silicate glass (BSG), and / or other suitable dielectric materials.

[0033] Reference now Figure 3 , a method 200 for forming a semiconductor structure 300 or a portion thereof is shown. In some embodiments, the fabrication of the semiconductor structure 300 may be substantially similar to the above with respect to Figure 1A-1G The fabrication of the semiconductor structure 100 is discussed. The blocks of the method 200 are exemplary only, and additional steps may be implemented and / or steps may be omitted. Figure 4-Figure 11 Portions of an exemplary semiconductor structure corresponding to transitional fabrication steps of method 200 are shown.

[0034] In one embodiment of method 200, in block 202, a semiconductor device such as a transistor is formed on a substrate. The device may be part of an IC. Figure 4In an example, a substrate 302 having one or more transistors 304 is provided, and the transistor 304 includes a source / drain region 306 and a gate structure 308 disposed thereon. As discussed above, the transistor 304 can be a planar transistor or a multi-gate transistor. The substrate can be substantially similar to as discussed above. For example, in one embodiment, the semiconductor substrate 302 includes silicon (Si). Alternatively or in addition, the substrate 302 includes another elemental semiconductor, such as: germanium (Ge); a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In some embodiments, the substrate 302 includes one or more III-V materials, one or more II-IV materials, or a combination thereof. In some embodiments, the substrate 302 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate.

[0035] The source / drain region 306 may be a doped region and / or epitaxial growth region defining a source / source component associated with a gate structure 308 of a semiconductor device. The source / drain region 306 may be deposited using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. When the source / drain region 306 is n-type, it may include silicon (Si) doped with an n-type dopant such as phosphorus (P) or arsenic (As). When the source / drain region 306 is p-type, it may include silicon germanium (SiGe) doped with a p-type dopant such as boron (B) or boron difluoride (BF2). In some embodiments, the source / drain region 306 may include multiple layers, such as layers with different dopant concentrations.

[0036] The gate structure 308 includes an interface layer, a gate dielectric layer, and a gate electrode. The interface layer of the gate structure 308 may include a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may be formed on the interface layer. The gate dielectric layer may include a high-k dielectric material, such as hafnium oxide. Alternatively, the gate dielectric layer of the gate structure 308 may include other high-K dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium oxide silicon (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. The gate electrode layer of the gate structure 308 may include a single layer structure, or alternatively a multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to improve device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy, or various combinations of metal silicides. For example, the gate electrode layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (Ta AlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials, or combinations thereof.

[0037] A dielectric layer 310, also referred to as an interlayer dielectric (ILD) layer, may be formed on the substrate 302 and adjacent to the gate structure 308. The ILD layer 310 may be deposited using PECVD, FCVD, spin coating, or a suitable deposition technique. In some embodiments, after forming the ILD layer 310, the structure may be annealed to improve the integrity of the ILD layer 310. Although not explicitly shown in the figures, it is understood that a contact etch stop layer (CESL) may be deposited prior to depositing the ILD layer 310, such that the CESL is disposed between the ILD layer 310 and the source / drain features. The CESL may include silicon nitride or silicon oxynitride and may be deposited using CVD, ALD, or a suitable method.

[0038] The contact structure 311 extends through the ILD layer 310 to the source / drain region 306 and the gate structure 308. The contact structure 311 may be referred to as a mid-end-of-line (MEOL) structure. As an example, the contact structure 311 may include ruthenium (Ru), cobalt (Co), nickel (Ni), tungsten (W), copper (Cu), or other metals. In some embodiments, the contact structure 311 may include a barrier layer to interface with the ILD layer 310. Such a barrier layer may include a metal nitride, such as titanium nitride, tantalum nitride, tungsten nitride, cobalt nitride, or nickel nitride. In addition, in order to reduce contact resistance, a silicide component may be used as part of the contact structure 311 and interface with transistor components such as the gate structure 308. The silicide component may include titanium silicide. The contact structure 311 may be deposited using CVD, PVD, or a suitable method.

[0039] The method 200 then proceeds to block 204 where a multi-layer interconnect (MLI) is formed over the device. Figure 4, MLI 312 is provided with a metal layer including a metal line 312A and a via 312B formed above substrate 302. Although six (6) metal layers are shown for ease of reference, any number of metal layers may be provided. A dielectric layer 312C is interposed between metal lines 312A and vias 312B. Metal lines 312A and vias 312B may include copper (Cu). Other components include those discussed above, titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al), or combinations thereof. Dielectric layer 312C may be deposited using PECVD, FCVD, spin coating, or a suitable deposition technique. The dielectric layer 312C may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), or doped silicate glass such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass, boron-doped silicate glass (BSG), and / or other suitable dielectric materials. In one embodiment, the dielectric layer 312C includes silicon oxide. Each MLI 312 component may include a multilayer structure. As discussed in the following embodiments, one or more layers of the dielectric layer 312C may include a thermally conductive material component. In some embodiments, at least the first dielectric layer 312C is an oxide-based layer (e.g., adjacent to ILD 310), and at least one dielectric layer 312C above the first dielectric layer 312C (e.g., at or above M4) is a thermally conductive material component.

[0040] The method 200 then proceeds to block 206 where a heat sink layer is formed over and / or within the multi-layer interconnects. Figure 5 In the example of FIG. 3 , a heat dissipation layer 314 is formed over the MLI 312. The heat dissipation layer 314 may be substantially similar to the above-described heat dissipation layer 314. Figure 1A-1G The heat dissipation layer 104 discussed. In some embodiments, the heat dissipation layer 314 is a single layer structure, e.g. Figure 1D In some embodiments, the heat dissipation layer 314 includes two or more sub-layers, such as Figure 1E In some embodiments, the heat dissipation layer 314 includes a thinner seed layer and a thicker heat dissipation layer, for example Figure 1F In some embodiments, the heat dissipation layer 314 includes a thermally conductive material in the form of islands surrounded by other dielectric layers, such as Figure 1G . The heat sink layer 314 may have a thickness between about 0.5 micrometers (μm) and 10 μm. The heat sink layer may be initially deposited at a temperature less than or equal to about 400 degrees Celsius and then activated in a transient thermal process. Exemplary deposition methods include CVD, PVD, or ALD. Substantially similar to Figure 1B and Figure 1CA sacrificial capping layer of capping layer 106 shown in FIG. 1 may optionally be deposited on heat spreader layer 314 prior to transient thermal treatment and subsequently removed after transient thermal treatment. In some embodiments, transient thermal treatment may increase the thermal conductivity of heat spreader layer 314 by three to ten times.

[0041] In one embodiment, method 200 proceeds to block 208 where planarization is performed on heat sink layer 314. In some embodiments, planarization may include a chemical mechanical planarization (CMP) process or ion milling. In one embodiment, the surface of heat sink layer 314 has a root mean square (RMS) roughness between 5 nm and 100 nm before the planarization process or the ion milling process, and has an RMS of less than about 1 nm after planarization.

[0042] In other examples, materials suitable for heat sink layer 314 (e.g., boron nitride or diamond-like carbon) may also be used as one or more IMD layers 312C within MLI 312, e.g. Figure 6 As shown in . In some embodiments, the dielectric layers corresponding to metal layer four (M4) and above include a heat dissipation layer 314 as an intermetallic dielectric. That is, the lower dielectric layer IMD layer 312C of MLI 312 may include a dielectric material different from the upper dielectric layer 312C of MLI 312. In one embodiment, the upper dielectric layer 312C of MLI 312 includes a thermally conductive material, such as boron nitride or diamond-like carbon, and the lower dielectric layer 312C of MLI 312 includes silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), or doped silicate glass such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. One or more. In other embodiments, each IMD layer of MLI 312 includes a thermally conductive material (e.g., boron nitride or diamond-like carbon). As Figure 6 As shown in FIG. 3 , metal lines 312A and vias 312B are formed in heat dissipation layer 314. Figure 6 As shown in the semiconductor structure 300 of FIG. 1 , in some embodiments, another heat dissipation layer 314 ′ is formed above the MLI 312 . The upper heat dissipation layer 314 ′ can be thicker than the heat dissipation layer provided within the MLI 312 .

[0043] In one embodiment of the method 200, the method proceeds to block 210 where additional interconnect features are formed in the heat spreader layer 314. Figure 7, forming a via 316 extending through the heat spreader layer 314. The via 316 interfaces with the uppermost metallization layer (e.g., metal line 312A) of the MLI 312 to provide an electrical connection. The via 316 may be formed by appropriate photolithography and etching processes to form an opening in the heat spreader layer 314, and then by depositing one or more conductive materials into the opening to form the via 316. Exemplary compositions include copper (Cu), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al), tantalum (Ta), or combinations thereof.

[0044] In some embodiments, the method 200 continues to block 212 to treat the surface of the heat dissipation layer 314. The treatment may include preparing the surface for bonding with another layer or component. In some embodiments, a surface treatment or activation process, such as a cleaning process and / or a plasma treatment, is performed on the heat dissipation layer 314. In some embodiments, block 212 is omitted.

[0045] In some embodiments, method 200 continues to block 214, where additional layers or components are formed on the structure. The additional layers or components may include other semiconductor structures, such as other dies, heat sinks, packaging components such as input / output terminals (e.g., balls, bumps, pillars), substrates such as semiconductor substrates or plug-in substrates, carrier substrates, and / or various other components including those implementing a 3D IC structure.

[0046] Reference now Figure 8-Figure 11 , shows a semiconductor structure that may be formed using one or more aspects at block 214 of method 200. Any aspect of any of the exemplary devices may be used in conjunction with other embodiments.

[0047] refer to Figure 8 , a semiconductor structure 800 is shown, which includes a semiconductor substrate 302, a semiconductor device 304, an MLI 312, and a heat dissipation layer 314, which can be substantially similar to that discussed above. The aspects of the method 200 discussed above can be used to manufacture the semiconductor structure 800. As shown in the semiconductor structure 800, a conductive component 802 is disposed above the heat dissipation layer 314 and is connected to the through hole 316. The conductive component 802 can be an interconnect such as a C4 bump interconnect, a column (e.g., a copper column), a C3 ball, a solder ball, and / or other conductive components. In some embodiments, the conductive component is connected to another semiconductor structure, such as another die, a plug-in substrate, operable to be connected to a printed circuit board, and / or other packaging structure. A passivation member or bottom filling material (not shown) can be formed above the heat dissipation layer 314 and adjacent to the conductive component 802.

[0048] refer to Fig. 9 , a semiconductor structure 900 is shown having a second die 300' disposed above the heat spreader 314 of the semiconductor structure 300. The semiconductor structure 300 may be substantially similar to the method 200 and Figure 5-Figure 7 As discussed. In one embodiment, the second die 300' can be substantially similar to the first semiconductor structure 300. In some embodiments, the first semiconductor structure 300 and the second die 300' can include different ICs. The heat dissipation layer 314 also serves as a bonding layer. The through-hole 316 provides an electrical connection for signals and / or power between the semiconductor structure 300 and the second die 300'.

[0049] refer to Fig.10 , a semiconductor structure 1000 is shown having a second die 300' disposed above a heat spreader 314 of a semiconductor structure 300. The semiconductor structure 300 may be substantially similar to the method 200 and Figure 5-Figure 7As discussed. In one embodiment, the second die 300' may be substantially similar to the first semiconductor structure 300. In some embodiments, the first semiconductor structure 300 and the second die 300' may include different ICs. The heat dissipation layer 314 also serves as a bonding layer. The through-hole 316 provides an electrical connection for signals and / or power between the semiconductor structure 300 and the second die 300'. Above the second die 300' including its heat dissipation layer 314 is an additional component 1002. In one embodiment, the additional component 1002 is another die, such as another die substantially similar to the semiconductor structure 300 and / or die 300'. In one embodiment, the additional component 1002 is another IC device, which includes a die having different functions and / or footprints compared to the semiconductor structure 300 and / or die 300'. In one embodiment, the additional component 1002 is a carrier substrate, such as a glass substrate. In one embodiment, the additional component 1002 is another substrate. In some embodiments, the component 1002 includes a silicon (Si) substrate. Alternatively or additionally, component 1002 includes another elemental semiconductor, such as germanium (Ge); a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In some embodiments, component 1002 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. The semiconductor-on-insulator substrate can be fabricated by separation by injection of oxygen (SIMOX), wafer bonding, and / or other suitable methods. In one embodiment, component 1002 is a heat sink. The heat sink can include a thermally conductive plate (e.g., copper or aluminum), a coolant in a pipe, and / or other configurations.

[0050] refer to Fig.11 , a semiconductor structure 1100 is shown having a second die 300' disposed above a heat spreader 314 of a semiconductor structure 300. The semiconductor structure 300 may be substantially similar to that described above with respect to methods 200 and Figure 5-Figure 7 In particular, in the illustrated embodiment, the first semiconductor structure 300 includes a semiconductor structure such as Figure 6314 ′ is an upper dielectric layer of MLI 312 composed of a thermally conductive material as shown in . In one embodiment, the second die 300 ′ can be substantially similar to the first semiconductor structure 300. In one embodiment, the second die 300 ′ can be substantially similar to the first semiconductor structure 300. In some embodiments, the first semiconductor structure 300 and the second die 300 ′ can include different ICs. The heat dissipation layer 314 ′ also serves as a bonding layer. The through hole 316 provides an electrical connection for signals and / or power between the semiconductor structure 300 and the second die 300 ′.

[0051] Thus, structures and methods are provided that allow stacked components such as in 3D IC configurations to have a heat sink layer within the stack. Although not limiting, the present disclosure provides advantages for IC semiconductor structures having a heat sink layer compatible with low temperature BEOL processes. Further, the proposed heat sink layer can also be used as a bonding layer.

[0052] One aspect of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes: forming a transistor on a semiconductor substrate; forming a first metal layer and an overlying second metal layer above the transistor; depositing a heat dissipation layer above the overlying second metal layer; and annealing the heat dissipation layer to a temperature above a threshold temperature. The deposition of the heat dissipation layer is performed below the threshold temperature. During the annealing, the first metal layer and the overlying second metal layer are maintained below the threshold temperature. In some embodiments, the annealing includes a transient heat treatment. In some embodiments, the annealing includes applying a pulsed laser to locally heat the heat dissipation layer. In some embodiments, the threshold temperature is about 400 degrees Celsius. In some embodiments, the annealing increases the thermal conductivity of the heat dissipation layer. In some embodiments, the method further includes: depositing a capping layer above the heat dissipation layer before annealing, and removing the capping layer after annealing. In some embodiments, the capping layer includes at least one of Ti, Al, Ni, silicon glass, Cr, Al2O3, SiO2, carbon, or a metal. In some embodiments, the heat dissipation layer includes at least one of boron nitride, aluminum nitride, graphene, carbon, diamond, diamond-like carbon, benzoic acid, or a transition metal disulfide. In some embodiments, the method further comprises: forming a via extending through the heat dissipation layer. In some embodiments, the method further comprises: stacking a die on top of the heat dissipation layer. The via provides an electrical connection between the transistor and the die.

[0053] Another aspect of the present disclosure relates to a method. The method includes: forming a transistor device on a substrate; forming a multi-layer interconnect (MLI) above the transistor device; depositing a thermally conductive material on the MLI; after the deposition of the thermally conductive material, heat treating the thermally conductive material to increase the thermal conductivity of the thermally conductive material; and flattening the thermally conductive material. In some embodiments, the heat treatment includes applying a pulsed laser. In some embodiments, during the heat treatment, the temperature within the MLI is maintained below about 400 degrees Celsius. In some embodiments, the heat treatment enlarges the grain size of the thermally conductive material. In some embodiments, the heat treatment converts the thermally conductive material from an amorphous state to a crystalline state. In some embodiments, the heat treatment improves the crystal orientation consistency within the thermally conductive material. In some embodiments, the method also includes: depositing a capping layer above the thermally conductive material before the heat treatment, and removing the capping layer after the heat treatment.

[0054] Another aspect of the present disclosure relates to a method of forming an integrated circuit (IC) structure. The IC structure includes: a transistor device formed on a substrate, the transistor device having a source / drain (S / D) region and a gate structure; a multi-layer interconnect (MLI) structure located above the transistor device, the MLI structure including metal lines and metal vias embedded in an inter-metal dielectric (IMD) layer; and a heat dissipation layer disposed above at least a portion of the MLI structure. The top of the heat dissipation layer has a larger grain size than the bottom of the heat dissipation layer. In some embodiments, the heat dissipation layer includes a through-via electrically connected to the MLI structure. In some embodiments, the IC structure also includes: a die bonded to the heat dissipation layer. The through-via provides an electrical connection between the MLI structure and the die.

[0055] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a transistor on a semiconductor substrate; forming a first metal layer and an overlying second metal layer above the transistor; depositing a heat sink layer over the overlying second metal layer, wherein the depositing of the heat sink layer is performed below a threshold temperature; and The heat spreader layer is annealed to a temperature above the threshold temperature, wherein the first metal layer and the overlying second metal layer remain below the threshold temperature during the annealing.

2. The method according to claim 1, wherein: The annealing includes a transient heat treatment.

3. The method according to claim 1, wherein: The annealing includes applying a pulsed laser to locally heat the heat dissipation layer.

4. The method according to claim 1, wherein: The threshold temperature is approximately 400 degrees Celsius.

5. The method according to claim 1, wherein: The annealing improves the thermal conductivity of the heat dissipation layer.

6. The method according to claim 1, further comprising: Before the annealing, depositing a capping layer over the heat dissipation layer; as well as After the annealing, the capping layer is removed.

7. A method for manufacturing a semiconductor device, comprising: forming a transistor device on a substrate; forming multiple layers of interconnects over the transistor device; depositing a thermally conductive material on the MLI; After the depositing of the thermally conductive material, heat treating the thermally conductive material to increase the thermal conductivity of the thermally conductive material; as well as The thermally conductive material is planarized.

8. The method according to claim 7, wherein: The heat treatment enlarges the grain size of the thermally conductive material.

9. The method according to claim 7, wherein: The heat treatment transforms the thermally conductive material from an amorphous state to a crystalline state.

10. An integrated circuit structure comprising: A transistor device is formed on a substrate, wherein the transistor device has a source / drain region and a gate structure; a multi-layer interconnect structure located above the transistor device, wherein the multi-layer interconnect structure includes metal lines and metal vias embedded in an inter-metal dielectric layer; and A heat dissipation layer is disposed above at least a portion of the multi-layer interconnect structure, wherein a top portion of the heat dissipation layer has a larger grain size than a bottom portion of the heat dissipation layer.

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