Embedded packaging structure, power supply device and electronic equipment

Abstract

The embodiment of the invention discloses an embedded packaging structure, a power supply device and electronic equipment. The embedded packaging structure comprises at least three layers of embedded frames which are sequentially overlapped, and chips, inductance elements and a plurality of electronic elements which are embedded in the embedded frames, at least one electronic element in the plurality of electronic elements is a capacitor element or a resistor element; the inductance element is embedded in the middle layer embedded frame of the at least three layers of embedded frames, and the thickness of the middle layer embedded frame is larger than or equal to that of the inductance element. The inductance element is embedded in the middle-layer embedded frame in the multi-layer embedded frame, so that the influence possibly caused by dimensional tolerance of devices such as the inductance element can be avoided, and the product yield can be ensured; and the processing of each layer of packaging module and the overlapping assembly of the modules can be completed in a substrate factory, so that the industrial chain can be further optimized. In addition, a fully embedded structure is realized by stacking multiple layers of embedded frames, the area occupied by the device on the board is remarkably reduced, and the risk of device exposure is reasonably controlled.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of electronic component packaging, and in particular to an embedded packaging structure, a power supply device, and an electronic device. Background Art

[0002] Embedded component packaging (ECP) technology is used to embed electronic components into the substrate, which can shorten the connection path between components, reduce transmission loss, improve product integration, and reduce module size. With the development of electronic products, the power of electronic components has increased accordingly, and the corresponding ECP device heat dissipation problem has become increasingly prominent.

[0003] Take the power module as an example. A typical power module structure using ECP technology has chips, inductors, capacitors and resistors that are packaged in ECP respectively, and the inductor ECP, capacitors and resistors ECP are stacked with the chip ECP to form a vertical current-carrying power module. The inductor is located in the middle layer of the stacked structure. Limited by the thickness tolerance of the inductor, the power module structure cannot overcome the influence of the inductor thickness tolerance and cannot ensure that each inductor is reliably connected after stacking. Summary of the invention

[0004] The embodiments of the present application provide an embedded packaging structure, a power supply device and an electronic device, which can effectively improve the product yield through structural optimization of the embedded packaging structure.

[0005] The first aspect of the embodiment of the present application provides an embedded packaging structure, which includes at least three layers of embedded frames stacked in sequence, and chips, inductors and multiple electronic components embedded in the at least three layers of embedded frames; at least one of the multiple electronic components is a capacitor or a resistor; wherein the inductor is embedded in the middle layer of the embedded frame in the at least three layers of embedded frames, and the thickness of the middle layer of the embedded frame is greater than or equal to the thickness of the inductor. In this way, the inductor is completely embedded in the middle layer of the embedded frame in the multi-layer embedded frame, and the inductor and other devices are completely embedded in the embedded frame through the substrate processing process. Since the thickness of each layer of the embedded frame is controllable, the connection reliability of the part of the inductor that may be affected by the size tolerance of the part of the inductor can be avoided, thereby effectively avoiding the influence of the height tolerance of the inductor on the stacking assembly relationship, and providing technical guarantee for the reasonable control of the product yield. At the same time, since the thickness of each layer of the embedded frame is controllable, the product thickness of the embedded packaging structure formed by stacking can also be guaranteed, so as to better meet various practical application scenarios. For example, taking the scenario where it needs to be bonded to a thermally conductive structure, by reasonably controlling the product thickness, the embedded packaging structure can be reliably bonded to the thermally conductive structure to meet the product's heat dissipation requirements, which can further ensure the safe use and performance of the inner-layer devices.

[0006] In practical applications of the present application, multiple electronic components can be embedded in different embedding frame layers, for example but not limited to, embedded independently of chips and inductor components. In addition, the embedded packaging structure provided by the present application solution, all electronic components including chips can be packaged based on ECP technology, and the processing of each layer of ECP packaging modules and the stacking and assembly of modules can be completed in the substrate factory, which can further optimize the industrial chain and reduce manufacturing costs. In addition, by stacking multiple layers of embedded frames to achieve a fully embedded structure, on the one hand, the product structure is highly integrated, which significantly reduces the area occupied by the device on the board; on the other hand, it can reduce the risk of device exposure and make the wiring in the board more flexible.

[0007] Based on the first aspect, the embodiment of the present application also provides a first implementation method of the first aspect: wherein the connection between two adjacent layers of embedded frames is electrically connected using conductive paste. Compared with the implementation method of the traditional vertical power supply module layer by layer using soldering to achieve the corresponding conductive relationship, this implementation method uses conductive paste to achieve electrical connection, which can avoid the high temperature of reflow during the processing of each layer structure, as well as the influence of the high temperature of reflow between the superimposed modules, so as to ensure the safe use and performance of the inner layer devices; in addition, based on the embedded packaging structure, the frequency of high temperature reflow affecting chips and other devices is effectively reduced, which provides the possibility of arranging the reflow process for the subsequent product process, and is conducive to improving the processing technology of the entire product module.

[0008] Exemplarily, the conductive paste may be composed of conductive particles (such as but not limited to silver or copper) and an adhesive, wherein the conductive particles provide conductivity and the adhesive is used to adhere the conductive particles to the connecting surfaces of two adjacent embedded frames to achieve Z-direction conduction interconnection between the two adjacent embedded frames.

[0009] Based on the first implementation of the first aspect, the embodiment of the present application further provides a second implementation of the first aspect: a slot is provided on the embedded frame, the slot passes through the inductor element or electronic element to be electrically connected, and the slot is filled with a conductive material to form a corresponding connection portion. Exemplarily, the slot can be a through slot or a through hole.

[0010] Taking the connection area of ​​the inductor element as an example, the slot can be opened using the existing hole-forming process, and the cross-section is an inverted trapezoid with a larger top and a smaller bottom. Compared with the blind hole array connection structure, the connection portion can increase the flow area of ​​the inductor by about 400%; at the same time, it can completely avoid the situation where the bottom of the blind hole array does not penetrate the substrate, resulting in no effective electrical connection. For example, for application scenarios with relatively small inductor height tolerances, the slot setting can ensure that the thicker conductor layer is penetrated to form an effective electrical connection. Overall, it can effectively overcome the possible impact of the inductor height tolerance.

[0011] In practical applications, the slot can be filled entirely with copper or other conductive materials to form the connection portion. Alternatively, the slot can be filled with different conductive materials to form the connection portion. For example, but not limited to, the periphery and bottom of the slot can be filled with copper to form the peripheral conductor of the connection portion, and the middle of the slot can be filled with other conductive materials to form the middle conductor. For example, a copper-containing material can be filled in the middle of the slot, or a silver-containing material can be filled in the middle of the slot. Alternatively, the periphery and bottom of the slot can also be filled with copper to form the connection portion.

[0012] In other practical applications, the relative position of the slot relative to the inductor element or other elements to be electrically connected can be determined as needed. For example, the slot can be opened relative to the terminal pad of the inductor element; or, the slot can also be opened relative to the terminal body of the inductor element, and the slot aperture is larger than the size of the terminal body to cover the entire end face of the terminal body to achieve a larger inductor flow area; or, the slot can also be opened relative to part of the terminal body of the inductor element.

[0013] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, the embodiment of the present application also provides a third implementation of the first aspect: at least three layers of embedded frames are electrically connected by mechanical through holes. In this way, the use of mechanical through holes to achieve conduction can also significantly reduce the number of high-temperature reflow times of chips and other devices, and ensure the safe use and performance of the inner layer devices.

[0014] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, the embodiment of the present application also provides a fourth implementation of the first aspect: the periphery of the embedded packaging structure includes a connecting side portion formed by a sidewall copper deposition process, and the connecting side portion is electrically connected to at least the top embedded frame and the bottom embedded frame in at least three layers of embedded frames. Similarly, based on the connecting side portion, the number of high-temperature reflow times of components such as chips can be significantly reduced, ensuring the safe use and performance of the inner layer components.

[0015] For example, the connecting side portion may be a through hole formed based on a sidewall copper deposition process, which has a good moisture-proof effect, can further dissipate heat efficiently, and can shield signal interference.

[0016] In the specific implementation, after each layer of embedded frame is pressed and formed, a thin copper layer can be deposited on the edge of the board by chemical method or electroplating method to achieve electrical connection between layers; then, the copper layer on the non-circuit parts of the board surface on both sides of the substrate is etched away, and then the board surface on both sides of the substrate is coated with a green oil layer, gold-plated fingers and other board-making processes are completed.

[0017] In a specific application, the communicating side portion may also be connected to the middle embedded frame or the interconnection line layer between adjacent embedded frames through the board edge.

[0018] Based on the first aspect, or the first implementation manner of the first aspect, or the second implementation manner of the first aspect, or the third implementation manner of the first aspect, or the fourth implementation manner of the first aspect, the embodiment of the present application also provides a fifth implementation manner of the first aspect: an interconnection circuit layer is arranged between two adjacent layers of embedded frames.

[0019] Exemplarily, the interconnection circuit layer is integrally formed with one of two adjacent embedded frames.

[0020] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, or the fourth implementation of the first aspect, or the fifth implementation of the first aspect, the embodiment of the present application further provides a sixth implementation of the first aspect: the top of the top embedded frame in at least three layers of embedded frames is arranged with an interconnection circuit layer, or the bottom of the bottom embedded frame in at least three layers of embedded frames is arranged with an interconnection circuit layer. In this way, the actual circuits can be flexibly arranged according to the actual application scenario.

[0021] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, or the fourth implementation of the first aspect, or the fifth implementation of the first aspect, or the sixth implementation of the first aspect, the embodiment of the present application also provides a seventh implementation of the first aspect: the intermediate layer embedded frame of the embedded inductor element is an inductor embedded frame, the embedded frame of the embedded chip is a chip embedded frame, and the chip embedded frame is adjacent to the inductor embedded frame. Such a setting can simplify the interlayer line layout, reasonably control the line insertion loss, and reduce the process difficulty and cost.

[0022] In practical applications, the chip embedding frame may include a metal mold layer, which is connected to the back of the chip to quickly conduct heat from the chip and improve the heat dissipation capacity. Exemplarily, the metal mold layer is a copper block or a thick copper layer.

[0023] Exemplarily, the chip embedding frame may be provided in at least two layers, and the at least two layers of chip embedding frames are provided on the same side of the inductor embedding frame, or are provided on both sides of the inductor embedding frame.

[0024] In other exemplary embodiments, the embedded packaging structure may include a first embedded frame, a second embedded frame and a third embedded frame stacked in sequence, the first embedded frame is a chip embedded frame, the second embedded frame is an inductor embedded frame, and at least part of the multiple electronic components are embedded in the third embedded frame.

[0025] Based on the seventh implementation of the first aspect, the embodiment of the present application further provides an eighth implementation of the first aspect: at least one of the multiple electronic components is embedded in the chip embedding frame. Alternatively, at least one of the multiple electronic components is embedded in the inductor embedding frame. In this way, on the one hand, it is conducive to the inter-layer layout of the lines, making the routing layout more flexible; on the other hand, it can reduce the device layout density of other embedded layers, which can reduce the formation of parasitic inductance to a certain extent.

[0026] The second aspect of the embodiment of the present application provides a power supply device, which includes a chip, an inductor element and multiple electronic components, and the chip, the inductor element and the multiple electronic components are packaged using the embedded packaging structure as described above. Based on the embedded packaging structure, the product yield can be effectively improved, and a good technical guarantee is provided for realizing a power supply device with a large current capacity, which meets the trend requirements of high-density layout design.

[0027] A second aspect of an embodiment of the present application provides an electronic device, which includes a circuit board and a power supply device. The power supply device is arranged on the circuit board, and the power supply device adopts the power supply device described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0029] Figure 2 A schematic diagram of a buried packaging structure provided in an embodiment of the present application;

[0030] Figure 3 for Figure 2 A schematic diagram of a superimposed relationship of the embedded frame layer shown in ;

[0031] Figure 4 A schematic diagram of another embedded packaging structure provided in an embodiment of the present application;

[0032] Figure 5 A schematic diagram of the structure of another embedded packaging structure provided in an embodiment of the present application;

[0033] Figure 6 A schematic diagram of another embedded packaging structure provided in an embodiment of the present application;

[0034] Figure 7 A schematic diagram of the structure of another embedded packaging structure provided in an embodiment of the present application;

[0035] Figure 8 The figure shows schematic diagrams of connecting parts of four different structural forms provided in the embodiments of the present application;

[0036] Fig. 9 The figure shows a schematic diagram of the relationship between three different slot opening positions provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The embodiment of the present application provides an embedded packaging structure, which can reasonably control the product yield through structural optimization.

[0038] See also Figure 1 , which is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0039] like Figure 1 As shown, the electronic device includes a housing 100, a mainboard 200 and a power supply device 300 disposed in the housing 100, and the power supply device 300 is electrically connected to the mainboard 200 for supplying power to the mainboard and the power devices on the mainboard. In a specific implementation, the electronic device can be a smart phone, a smart TV, a smart TV set-top box, a personal computer (PC), a wearable device, a smart broadband, etc. The embodiments of the present application are not limited. It should be understood that the other main functional components of the electronic device can be implemented using existing technologies, so they will not be repeated herein.

[0040] A typical power supply device, whose chip, inductor, capacitor and resistor are respectively packaged using ECP technology, and the inductor ECP, capacitor and resistor ECP are stacked with the chip ECP to form a vertical current-passing power module. Among them, the inductor is located in the middle layer of the stacked structure. Due to the thickness tolerance of the inductor processing, the power module structure cannot overcome the influence of the inductor thickness tolerance.

[0041] Based on this, an embodiment of the present application provides an embedded packaging structure, which includes at least three layers of embedded frames stacked in sequence, and chips, inductance elements and multiple electronic components embedded in the at least three layers of embedded frames, at least one of the multiple electronic components is a capacitor element or a resistor element; wherein the inductance element is embedded in a middle layer of the at least three layers of embedded frames, and the thickness of the middle layer of the embedded frame is greater than or equal to the thickness of the inductance element. Here, the embedded frame is a semi-finished embedded substrate that is not covered with a solder mask layer (green oil layer); in addition, the overall structure of the inductor element has an irregular outer contour shape, and the "thickness" of the inductor element refers to the maximum structural dimension of the inductor element in the thickness direction of the embedded frame, so that the inductor element is completely embedded in the intermediate layer embedded frame; for example but not limited to, for an implementation method of realizing electrical connection through the terminal body of the inductor element, the thickness of the inductor element can be the maximum structural dimension formed based on the outer end of the terminal body; for an implementation method of realizing electrical connection through the terminal pad of the inductor element, the thickness of the inductor element can be the maximum structural dimension formed based on the outer end of the terminal pad.

[0042] In this way, the inductor element is embedded in the middle layer embedded frame of the multi-layer embedded frame, and the inductor element and other devices are completely embedded in the embedded frame through the substrate processing technology. Based on the structural characteristics of the embedded frame, the inter-layer electrical connection is realized, which can avoid the existence of dimensional tolerance affecting the connection reliability of some inductors, and can effectively avoid the influence of high temperature of reflow between the stacked modules, and ensure the safe use and performance of the inner layer devices; at the same time, the thickness of each layer of the embedded frame is controllable (for example, the thickness of the middle layer embedded frame is set to a thickness greater than the maximum tolerance of the inductor element to eliminate the tolerance influence of the inductor element), which can ensure the product thickness of the embedded packaging structure formed by the stacking. Taking the scenario where it needs to be bonded with the heat conductive structure as an example, by reasonably controlling the product thickness, the embedded packaging structure can be reliably bonded with the heat conductive structure to meet the heat dissipation requirements of the product, and the safe use and performance of the inner layer devices can be further guaranteed. On the whole, it can avoid the influence of the height tolerance of the inductor element on the stacking assembly relationship, and provide technical guarantee for the reasonable control of product yield.

[0043] In addition, the embedded packaging structure provided by the present application solution, all electronic components including chips are packaged based on ECP technology, and the processing of each layer of ECP packaging modules and the stacking and assembly of modules can be completed in the substrate factory, which can further optimize the industrial chain and reduce manufacturing costs. In addition, by stacking multiple layers of embedded frames to achieve a fully embedded structure, on the one hand, the high integration of the product structure significantly reduces the area occupied by the device on the board; on the other hand, it can reduce the risk of device exposure and make the wiring in the board more flexible.

[0044] In order to better understand the technical solution and technical effect of the present application, without losing generality, the following will describe in detail the specific embodiments with reference to the accompanying drawings and using the power module as the main body. Figure 2 , which is a structural schematic diagram of an embedded packaging structure provided in an embodiment of the present application.

[0045] like Figure 2 As shown, the embedded packaging structure includes three layers of embedded frames stacked in sequence: a first embedded frame 11, a second embedded frame 12 and a third embedded frame 13, the second embedded frame 12 is an intermediate embedded frame, and the first embedded frame 11 and the second embedded frame 12 are respectively located on both sides of the second embedded frame 12. Each electronic component is embedded in the three embedded frames, which are then stacked to form a power module 300.

[0046] In this embodiment, two inductance elements L are embedded in the second embedding frame 12. In a specific implementation, the thickness of the second embedding frame 12 may be greater than the thickness of the inductance element L, or may be equal to the thickness of the inductance element L, so that the inductance element L is completely embedded in the second embedding frame 12. For ease of description, the second embedding frame 12 in which the inductance element is embedded may be defined as an inductance embedding frame. It should be understood that Figure 2 The cross-sectional diagram shown is illustrated by taking two inductance elements L as an example. In other possible implementations, the number of inductance elements L to be set can be determined according to the needs of the actual application scenario, and is not limited to the two shown in the diagram.

[0047] The chip IC is embedded in the first embedding frame 11. For ease of description, the first embedding frame 11 in which the chip is embedded can be defined as a chip embedding frame; multiple capacitor elements C and resistor elements R are embedded in the third embedding frame 13. It can also be understood that Figure 2 Two chip ICs are used as an example for corresponding illustration, and the number of chip ICs arranged in the first embedding frame 11 can be determined according to actual needs.

[0048] Furthermore, the number of capacitor elements C and resistor elements R embedded in the third embedding frame 13, and the relative position relationship of the plurality of capacitor elements C and resistor elements R in the third embedding frame 13 layer can be determined according to the design requirements of the actual product. This embodiment of the present application is not limited.

[0049] Please also see Figure 2 and Figure 3 ,in, Figure 3 for Figure 2 A schematic diagram of the overlapping relationship of the embedded frame layer is shown in FIG.

[0050] like Figure 3 After the three layers of embedded frames are formed, they can be stacked in sequence and formed into a complete substrate through a pressing process; then, the copper layer of the non-circuit parts of the board surface on both sides of the substrate is etched away, and further Figure 2 As shown, the board-forming processes such as coating the green oil layer 31 on both sides of the substrate and plating the gold fingers 32 are completed, and finally the power module 300 is manufactured.

[0051] Therefore, the processing of the embedded packaging structure can be completed in the substrate factory, the industrial chain is relatively simple, and it is convenient to reasonably control the product quality.

[0052] Optionally, the capacitor element C and the resistor element R may be selectively embedded in the first embedding frame 11. For example, but not limited to, the capacitor element C is embedded between two chip ICs as shown in the figure. In a specific implementation, the resistor element R may also be embedded in the first embedding frame 11. In this way, on the one hand, it is convenient to arrange the lines between the layers, making the routing arrangement more flexible; on the other hand, it can reduce the device arrangement density of other embedded layers, and can reduce the formation of parasitic inductance to a certain extent.

[0053] In other specific implementations, the capacitor element C and the resistor element R may also be selectively embedded in the second embedding frame 12 .

[0054] In this embodiment, a conductive paste 41 is used between two adjacent embedded frames to achieve Z-direction interconnection. The "Z-direction" here refers to the conduction between the substrate layers in the direction intersecting with the board surface. The conductive paste can be composed of conductive particles (for example but not limited to silver or copper) and an adhesive. The conductive particles provide conductivity, and the adhesive is used to adhere the conductive particles to the connection surface of the two adjacent embedded frames. In a specific implementation, the conductive paste is applied to the "connection area" of the connection surface. The "connection area" can also be defined as a connection part. The corresponding connection area can be reserved in the design or added during the manufacturing process. The adhesive is cured through a pressing process to form a reliable electrical connection.

[0055] As shown in the figure, the two inductance elements L located in the second embedded frame 12 have their terminal top pads electrically connected to the capacitor element C located in the third embedded frame 13 through the conductive paste 41, and their terminal bottom pads electrically connected to the chip IC and other electronic components located in the first embedded frame 11 through the conductive paste 41.

[0056] Compared with the traditional vertical power supply module layer by layer using soldering to achieve the corresponding conductive relationship, this implementation uses conductive paste to achieve electrical connection, which can avoid the high temperature of reflow during the processing of each layer structure, as well as the influence of high temperature reflow between stacked modules, so as to ensure the safe use and performance of the inner layer devices; in addition, based on the embedded packaging structure, the frequency of high-temperature reflow affecting chips and other devices is effectively reduced, which creates the possibility of arranging the reflow process for the subsequent product processes, and is conducive to improving the processing technology of the entire product module.

[0057] Of course, in a specific implementation, the interconnection circuit layer 21 can be arranged between two adjacent embedded frames as needed, and the interconnection circuit layer 21 can also be arranged on the top layer (top of the third embedded frame 13) and the bottom layer (bottom of the first embedded frame 11) of the embedded packaging structure to establish a corresponding circuit conduction relationship and realize the function of the power module 300. It should be understood that the specific interface connection relationship and the arrangement relationship of the interconnection circuit layer can be constructed based on the power circuit of the power module, and the specific functions of the power circuit can be realized by using existing technologies, which will not be repeated here.

[0058] For the interconnection circuit layer, it can be configured independently and stacked with each layer of embedded frames to form a substrate; it can also be integrated on the embedded frame, or formed as a whole with the adjacent embedded frames. For example, the interconnection circuit layer 21 located on the top of the third embedded frame 13 is integrated on the third embedded frame 13, or it can be configured independently and then stacked with each layer of embedded frames to form a substrate.

[0059] In addition, for the interconnection circuit layer between two adjacent embedded frames, Figure 2 As shown, they are respectively integrated and configured on two adjacent embedded frames; in other possible implementations, they can also be integrated and configured on one side of the embedded frame, for example, the interconnection line layer 21 located between the second embedded frame 12 and the third embedded frame 13 can be integrated and configured on the second embedded frame 12, or can also be integrated and configured on the third embedded frame 13. This embodiment of the application is not limited.

[0060] For the first embedded frame 11 of the core embedded chip IC, a resin frame can be used, such as but not limited to glass fiber reinforced epoxy resin, which has good insulation performance, mechanical strength and thermal stability; a metal frame can also be used, such as but not limited to an aluminum frame or a copper frame, which is conducive to heat dissipation and reducing component temperature.

[0061] In addition, the chip IC embedded in the first embedding frame 11 can be interconnected on both sides. Specifically, the routing can be realized based on the inner layer of the first embedding frame 11. At the same time, a copper block or a thick copper layer can be connected to the back of the chip IC for heat dissipation to quickly conduct the heat generated by the chip IC and improve the heat dissipation performance. In a specific implementation, the copper block or thick copper layer used as the heat dissipation structure can be other forms of metal mold layers 111 set in the first embedding frame 11, as long as the heat of the chip IC can be quickly conducted out. This is not limited to the embodiments of the present application.

[0062] In a possible specific implementation, the chip IC can be arranged with the welding surface (ie, I / O interface) facing one side of the middle embedded frame, or with the welding surface facing away from the middle embedded frame (not shown in the figure). This application embodiment is not limited.

[0063] The foregoing Figure 2 In the described implementation, conductive paste is used to achieve Z-direction conduction between two adjacent embedded frames. In other specific implementations, mechanical through holes can also be used to achieve conduction interconnection between embedded frames of different layers. Figure 4 , which is a schematic diagram of another embedded packaging structure provided by an embodiment of the present application. Figure 2 The differences and connections between the described embodiments, and the components or structures with the same functions are indicated in the figures with the same symbols.

[0064] The embedded packaging structure provided in this embodiment is used to form a power module 300a.

[0065] like Figure 4 As shown, the first embedded frame 11, the second embedded frame 12 and the third embedded frame 13 are connected to each other through three mechanical through holes. The first embedded frame 11 and the third embedded frame 13 are connected to each other through the first mechanical through hole 421, and the first embedded frame 11 and the second embedded frame 12 are connected to each other through the second mechanical through hole 422 and the third mechanical through hole 423.

[0066] In this way, the present embodiment uses mechanical through holes to achieve conduction, which can also significantly reduce the number of high-temperature reflow times of chips and other devices, and can ensure the safe use and performance of inner layer devices.

[0067] Understandably, Figure 4 The cross-sectional diagram shown in the figure uses three mechanical vias as an example for illustration. In other possible implementations, the number of mechanical vias can be determined according to the needs of the actual application scenario to achieve interlayer conduction under the corresponding circuit relationship. In other words, the specific number of mechanical vias used to achieve Z-conductivity interconnection is not limited to the three shown in the figure.

[0068] The foregoing Figure 2 The described embodiment uses Z-direction conductive paste to realize the conductive interconnection between two adjacent embedded frames. Figure 4 In the described implementation, mechanical vias are used to achieve conductive interconnection between different layers of embedded frames. In other specific implementations, a Z-direction conductive paste and mechanical vias may also be used in combination. Figure 5 , which is a schematic diagram of another embedded packaging structure provided by the embodiment of the present application. Figure 2 and Figure 4 The differences and connections between the described embodiments, and the components or structures with the same functions are indicated in the figures with the same symbols.

[0069] The embedded packaging structure provided in this embodiment is used to form a power module 300b.

[0070] Among them, conductive paste 41 is used between two adjacent embedded frames to achieve Z-direction conduction interconnection. As shown in the figure, the two inductance elements L located in the second embedded frame 12 have their terminal top pads electrically connected to the capacitance element C located in the third embedded frame 13 through the conductive paste 41, and their terminal bottom pads are electrically connected to the chip IC and other electronic components located in the first embedded frame 11 through the conductive paste 41.

[0071] At the same time, the first embedded frame 11 and the third embedded frame 13 shown in the figure are connected to each other through the fourth mechanical through hole 424 and the fifth mechanical through hole 425 respectively.

[0072] In this way, this embodiment uses a combination of conductive paste and mechanical through holes to achieve conduction, which can also significantly reduce the number of high-temperature reflow times of chips and other devices, and ensure the safe use and performance of inner layer devices.

[0073] It should be noted that the specific connection points of the conductive paste and the specific connection relationship of the mechanical through holes are not limited to the exemplary embodiments shown in the figure. In other specific implementations, they can be determined according to the overall design requirements of the actual product, and the embodiments of this application are not limited thereto.

[0074] In addition, in other possible implementations, the Z-direction conductive interconnection of each layer of the embedded frame of the embedded packaging structure can also be achieved through the sidewall copper deposition process. Figure 6 , which is a schematic diagram of another embedded packaging structure provided by an embodiment of the present application. Figure 2 , Figure 4 and Figure 5 The differences and connections between the described embodiments, and the components or structures with the same functions are indicated in the figures with the same symbols.

[0075] The embedded packaging structure provided in this embodiment is used to form a power module 300c.

[0076] Figure 6 The first embedded frame 11, the second embedded frame 12 and the third embedded frame 13 shown in the figure are stacked in sequence to form the embedded packaging structure. Among them, the connecting side portion 43 is formed on the periphery of the embedded packaging structure by the side wall copper plating process, and the connecting side portion 43 is electrically connected to the third embedded frame 13 located at the top layer and the first embedded frame 11 located at the bottom layer, respectively, to achieve conductive interconnection. In this way, the present embodiment uses the connecting side portion 43 to achieve the conduction between the upper and lower layers, which can also significantly reduce the number of high-temperature reflow times of chips and other devices, and can ensure the safe use and performance of the inner layer devices.

[0077] In other possible implementations, the connecting side portion used to establish the above conductive interconnection can also be formed into a through hole based on the sidewall copper deposition process, which has a good moisture-proof effect. At the same time, it can further dissipate heat efficiently and shield signal interference.

[0078] In a specific implementation, after each layer of embedded frame is pressed and formed, a thin copper layer can be deposited on the edge of the board by a chemical method or an electroplating method to achieve electrical connection between the top interconnection circuit layer 21 and the bottom interconnection circuit layer 21; then, the copper layer on the non-circuit portion of the board surface on both sides of the substrate is etched away, and then the board forming processes such as coating the board surface on both sides of the substrate with a green oil layer 31 and gold-plating fingers 32 are completed, and finally the power module 300c is obtained.

[0079] As shown in the figure, the connecting side portion 43 can be connected to the interconnection line layer 21 located at the top of the third embedded frame 13 and the interconnection line layer 21 located at the bottom of the first embedded frame 11. In other possible implementations, the connecting side portion 43 can also be connected to the interconnection line layer between the intermediate embedded frame or the adjacent embedded frames through the board edge (not shown in the figure), and establish electrical connections between different layers, which can also reduce the impact of high-temperature reflow, as long as good signal integrity and electrical performance are obtained. This embodiment of the application is not limited.

[0080] It should be noted that the aforementioned embodiments all use three-layer embedded frames for three-dimensional stacking after embedding. In other specific implementations, four-layer or other multiple-layer embedded frames are formed according to the circuit design of different power modules. After the electronic components are embedded in the corresponding embedded frames respectively, the multi-layer embedded frames are pressed in turn to form a corresponding embedded packaging structure, which is not limited to the embodiments of the present application.

[0081] See also Figure 7 , which is a schematic diagram of another embedded packaging structure provided in the embodiment of the present application. Figure 2 , Figure 4 , Figure 5 and Figure 6 The differences and connections between the described embodiments, and the components or structures with the same functions are indicated in the figures with the same symbols.

[0082] The embedded packaging structure provided in this embodiment is used to form a power module 300d.

[0083] The embedded packaging structure includes four layers and embedded frames: a first embedded frame 11, a second embedded frame 12, a third embedded frame 13 and a fourth embedded frame 14. Figure 2 In the described embodiment, the fourth embedded frame 14 in this embodiment is overlapped adjacent to the first embedded frame 11 .

[0084] The inductor element L is embedded in the second embedding frame 12. The chip IC is embedded in the first embedding frame 11 and the fourth embedding frame 14, respectively, to form two chip embedding frames, both of which are located on the same side of the second embedding frame 12 shown in the figure. Here, the two chip embedding frames are arranged adjacent to the inductor embedding frame, which can simplify the interlayer line layout, reasonably control the line insertion loss, and reduce the process difficulty and cost; multiple capacitor elements C and resistor elements R are embedded in the third embedding frame 13. It can also be understood that Figure 7 The setting quantity of related components is only an example. In a specific implementation, the setting quantity of each component can be determined according to actual needs.

[0085] Among them, conductive paste 41 is used between two adjacent embedded frames to achieve Z-direction conduction interconnection. As shown in the figure, the two inductance elements L located in the second embedded frame 12 have their terminal top pads electrically connected to the capacitance element C located in the third embedded frame 13 through the conductive paste 41, and their terminal bottom pads are electrically connected to the chip IC and other electronic components located in the first embedded frame 11 through the conductive paste 41.

[0086] As shown in the figure, in the first embedded frame 11, the second embedded frame 12 and the third embedded frame 13, the conductive paste 41 is used between the adjacent two layers of embedded frames to achieve Z-direction conduction interconnection, and the two inductance elements L located in the second embedded frame 12 have their terminal top pads electrically connected to the capacitance element C located in the third embedded frame 13 through the conductive paste 41, and their terminal bottom pads are electrically connected to the chip IC and other electronic components located in the first embedded frame 11 through the conductive paste 41. The fourth embedded frame 14 and the first embedded frame 11 can achieve Z-direction conduction interconnection through the interconnection line layer 21.

[0087] In other possible implementations, the fourth embedded frame 14 and the first embedded frame 11 can be overlapped on both sides of the second embedded frame 12 (not shown in the figure), and the two chip embedded frames are also arranged adjacent to the inductor embedded frame, effectively simplifying the interlayer circuit layout.

[0088] In addition, a blind hole array structure can be used to connect the embedded frame and the inductor element L. As described above, the inductor processing technology has certain limitations, especially the height tolerance of the inductor is about ±100um. For example, when the inductor element L is embedded in the embedded frame, there will be a height difference of 200um between the largest and smallest inductors. At this time, the diameter difference of the bottom of the hole drilled by Laser is large, the process is difficult, and it will affect the electrical connection area between the embedded frame and the inductor element L side or the capacitor element C side, thereby affecting the product performance.

[0089] Optionally, a through slot or through hole can be opened at the connection position of the embedded frame, and a connection portion can be formed based on the through slot or through hole (slot hole). Taking the connection position of the inductor element L as an example, the connection can be made at the connection position of the inductor element L terminal on the second embedded frame 12 through the connection portion.

[0090] Specifically, see Figure 8 , which shows schematic diagrams of connecting parts of four different structural forms. For ease of description, the insulating substrate around the slot hole is not shown in the figure.

[0091] Figure 8 As shown in Figure (a), the slot 51 can be formed by using an existing hole forming process, and the cross section is an inverted trapezoidal shape with a larger top and a smaller bottom. In this embodiment, the slot 51 is completely filled with copper to form a connecting portion 52a.

[0092] The connection portion 52a is connected between the terminal pad L1 of the inductor element and the interconnected conductor layer 21, which is equivalent to forming a large-sized boss structure at the position connected to the inductor element L. Compared with the blind hole array connection structure, the connection portion 52a can increase the flow area of ​​the inductor by about 400%; at the same time, it can completely avoid the situation where the bottom of the blind hole array does not penetrate the substrate, resulting in no effective electrical connection. For example, for application scenarios with relatively small inductor height tolerance, the setting of the slot can ensure that the thicker conductor layer is penetrated to form an effective electrical connection. Overall, it can effectively overcome the possible impact of the inductor height tolerance.

[0093] Figure 8 As shown in FIG. 5( b ), the slot 51 may be filled with different conductive materials to form a connecting portion 52 b .

[0094] The surroundings and bottom of the slot 51 can be filled with copper to form the outer conductor 52b1 of the connecting portion 52b, where the copper refers to a single material copper that is not a copper alloy. The middle of the slot 51 can be filled with other conductive materials to form a middle conductor 52b2; for example, but not limited to, the middle conductor 52b2 can be formed by filling the middle of the slot 51 with a copper-containing material; or, the middle conductor 52b2 can be filled with other metal materials (for example, but not limited to silver, etc.). Similarly, the connecting portion 52b is connected between the terminal pad L1 of the inductor element and the interconnect conductor layer 21, and the flow area of ​​the inductor is increased through the connecting portion 52b.

[0095] Figure 8 As shown in the middle (c) figure, the surroundings and bottom of the slot 51 are filled with copper to form a connecting portion 52c, which is connected between the terminal pad L1 of the inductor element and the interconnection conductor layer 21, thereby increasing the flow area of ​​the inductor.

[0096] Figure 8 As shown in FIG. 5( d ), the groove 51 may be filled with other conductive materials other than copper to form a connecting portion 52 d .

[0097] For example, but not limited to, the connection portion 52d can be formed by filling the middle of the slot 51 with a material containing copper; or, the connection portion 52d can be formed by filling a material containing other metals (such as but not limited to silver, etc.). The connection portion 52d is connected between the terminal pad L1 of the inductor element and the interconnection conductor layer 21, and the flow area of ​​the inductor is increased through the connection portion 52d.

[0098] In addition, the relative position of the through slot or through hole (slot hole 51) with respect to the inductor element L can be determined as required, as long as a connection portion is formed with respect to the inductor element L and the corresponding conduction relationship requirements are met. Fig. 9 , which shows a schematic diagram of the relative position relationship between three different slots (equivalent to connecting parts) and the inductor element L.

[0099] Fig. 9 As shown in the middle figure (a), the slot hole 51a is opened opposite to the terminal pad L1 of the inductor element L, and the connection portion 52 formed by the slot hole 51a is electrically connected to the terminal pad L1.

[0100] Fig. 9 As shown in the middle (b), the slot 51b is opened opposite to the terminal body L2 of the inductor element L. The slot 51b has a diameter larger than the terminal body L2 so as to cover the entire end surface of the terminal body L2. The connection portion 52 formed by the slot 51b is electrically connected to the end surface of the terminal body L2.

[0101] Fig. 9As shown in Figure (c), the slot 51c is opened opposite to a portion of the terminal body L2 of the inductor element L, that is, the slot 51c does not cover the entire end surface of the terminal body L2. The connection portion 52 formed by the slot 51c is electrically connected to a portion of the end surface of the terminal body L2. Of course, Fig. 9 The slot shown in Figure (b) is arranged opposite to the terminal body L2 and is opened in a manner that completely covers the end surface of the terminal body L2. Fig. 9 The connection portion formed by the slot hole shown in the figure has a larger inductor flow area based on the terminal body L2.

[0102] Optionally, the connection portion formed based on the slot can also be applied to the connection area of ​​other electronic components to be electrically connected to form a corresponding connection portion.

[0103] In a specific implementation, the opening and filling of the slots can be realized by ordinary technicians in the field based on the existing technology, which will not be described in detail here.

[0104] The implementation scheme of the embedded packaging structure described in the above embodiments can be widely applied to the packaging structure of different functional modules. In practical applications, in the scenario of power module architecture, the above technical advantages are particularly significant.

[0105] It should be noted that the directional words "bottom", "end" and "side" used in this article are defined based on the state of the embedded packaging structure shown in the figure. The embedded packaging structure assembled and applied in the actual scene is not limited to the state shown in the figure. For example, in the use state, the mainboard of the electronic device extends vertically, or the extension direction of the mainboard of the electronic device forms a certain angle with the vertical. It should be understood that the use of the above directional words does not constitute a substantial limitation on the embedded packaging structure described in this application.

[0106] In addition, the ordinal numbers "first", "second", "third" and "fourth" used in this document are only used to describe the same functional components or structures in the technical solution. It is understood that the use of the above ordinal numbers does not constitute an understanding of the technical solution for protection of this application.

[0107] The above are only preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An embedded packaging structure, characterized in that: The invention comprises at least three layers of embedded frames stacked in sequence, and chips, inductance elements and a plurality of electronic elements embedded in the at least three layers of embedded frames; at least one of the plurality of electronic elements is a capacitor element or a resistor element; The inductor element is embedded in a middle embedded frame of the at least three embedded frames, and the thickness of the middle embedded frame is greater than or equal to the thickness of the inductor element.

2. The embedded packaging structure according to claim 1, characterized in that: The connecting parts between two adjacent layers of the embedded frames are electrically connected by using conductive paste.

3. The embedded packaging structure according to claim 2, characterized in that: The embedding frame is provided with a slot hole, the slot hole penetrates to the inductor element or the electronic element to be electrically connected, and the slot hole is filled with a conductive material to form the corresponding connecting portion.

4. The embedded packaging structure according to any one of claims 1 to 3, characterized in that: The at least three layers of embedded frames are electrically connected by mechanical through holes.

5. The embedded packaging structure according to any one of claims 1 to 4, characterized in that: The periphery of the embedded packaging structure includes a connecting side portion formed by a sidewall copper deposition process, and the connecting side portion is electrically connected to at least a top embedded frame and a bottom embedded frame of the at least three layers of embedded frames.

6. The embedded packaging structure according to claim 5, characterized in that: The communicating side portion is a through hole.

7. The embedded packaging structure according to any one of claims 1 to 6, characterized in that: An interconnection circuit layer is arranged between two adjacent layers of the embedded frames.

8. The embedded packaging structure according to claim 7, characterized in that: The interconnection circuit layer is integrally formed with one of the two adjacent embedded frames.

9. The embedded packaging structure according to any one of claims 1 to 8, characterized in that: An interconnection circuit layer is arranged on the top of a top embedded frame among the at least three embedded frames, or an interconnection circuit layer is arranged on the bottom of a bottom embedded frame among the at least three embedded frames.

10. The embedded packaging structure according to any one of claims 1 to 9, characterized in that: The intermediate layer embedding frame embedding the inductor element is an inductor embedding frame, and the embedding frame embedding the chip is a chip embedding frame. The chip embedding frame is arranged adjacent to the inductor embedding frame.

11. The embedded packaging structure according to claim 10, characterized in that: The chip embedding frame comprises a metal mold layer, and the metal mold layer is connected to the back side of the chip.

12. The embedded packaging structure according to claim 10 or 11, characterized in that: At least one of the plurality of electronic components is embedded in the chip embedding frame.

13. The embedded packaging structure according to any one of claims 10 to 12, characterized in that: At least one of the plurality of electronic components is embedded in the inductor embedding frame.

14. The embedded packaging structure according to any one of claims 10 to 13, characterized in that: The chip embedding frame is provided with at least two layers, and the at least two layers of chip embedding frames are provided on the same side of the inductor embedding frame, or on both sides of the inductor embedding frame.

15. The embedded packaging structure according to any one of claims 10 to 13, characterized in that: The embedded packaging structure includes a first embedded frame, a second embedded frame and a third embedded frame stacked in sequence, the first embedded frame is the chip embedded frame, the second embedded frame is the inductor embedded frame, and at least part of the multiple electronic components are embedded in the third embedded frame.

16. A power supply device, characterized in that: The invention comprises a chip, an inductor element and a plurality of electronic elements, wherein the chip, the inductor element and the plurality of electronic elements are packaged by adopting the embedded packaging structure according to any one of claims 1 to 15.

17. An electronic device, characterized in that: It comprises a circuit board and a power supply device, wherein the power supply device is arranged on the circuit board, and the power supply device adopts the power supply device according to claim 16.

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