A packaging substrate and a chip packaging structure

Abstract

This application discloses a packaging substrate and a chip packaging structure. The ground layer includes a first region metal layer and a second region metal layer. The second region metal layer is located within a hollow area of ​​the first region metal layer and has an insulating gap with it. The packaging substrate also includes multiple conductive structures that are vertically connected to different conductive layers. Each conductive structure includes a first conductive structure for grounding and a second conductive structure for connecting to a power source. In the ground layer, the first conductive structures are all electrically connected to the first region metal layer, and the second region metal layer is electrically connected to multiple second conductive structures extending to the ground layer. Among the multiple second conductive structures connected to the second region metal layer, the spacing between at least two second conductive structures is greater than the lateral dimension of the second conductive structure. This application's packaging substrate can improve the power integrity of the chip packaging structure.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and more specifically, to a packaging substrate and a chip packaging structure. Background Technology

[0002] With the continuous development of science and technology, more and more electronic devices are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable tool for people today.

[0003] The core component that enables various functions of electronic devices is the chip. To protect the chip and facilitate its connection to external circuits, it needs to be encapsulated and protected using a packaging substrate. The packaging substrate consists of a stacked structure formed by multiple conductive layers layered sequentially, with insulating layers between adjacent conductive layers. When using existing packaging substrates to protect chips, the power integrity of the chip packaging structure is relatively poor. Summary of the Invention

[0004] In view of this, this application provides a packaging substrate and a chip packaging structure, as follows:

[0005] This application provides a packaging substrate, which includes a plurality of stacked conductive layers and an insulating layer between adjacent conductive layers. At least one of the plurality of conductive layers is a ground layer. The ground layer includes a first region metal layer and a second region metal layer. The second region metal layer is located in the internal cutout of the first region metal layer and has an insulating gap with the first region metal layer.

[0006] The packaging substrate further includes multiple conductive structures that are longitudinally electrically connected to different conductive layers; the conductive structures include: a first conductive structure for grounding; and a second conductive structure for connecting to a power source.

[0007] In the grounding layer, the first conductive structures are all electrically connected to the first region metal layer, and the second region metal layer is electrically connected to a plurality of second conductive structures extending to the grounding layer; among the plurality of second conductive structures connected to the second region metal layer, the spacing between at least two second conductive structures is greater than the lateral dimension of the second conductive structure.

[0008] Preferably, in the above-mentioned packaging substrate, the plurality of conductive layers are sequentially arranged in the stacking direction as a first conductive layer to an Nth conductive layer, where N is a positive integer greater than 2; the Nth conductive layer includes a capacitor welding area for welding capacitors; at least the Nth conductive layer is the ground layer;

[0009] The Nth conductive layer includes a first capacitor pad and a second capacitor pad located within the capacitor soldering area. The first capacitor pad is used to connect the positive terminal pin of the capacitor, and the second capacitor pad is used to connect the negative terminal pin of the capacitor. Within a preset range from the capacitor soldering area, there is a second conductive structure, and the second region metal layer connects the second conductive structure and the first capacitor pad.

[0010] Preferably, in the above-described packaging substrate, a single capacitor soldering area has two first capacitor pads and two second capacitor pads;

[0011] The two second capacitor pads are respectively located on both sides of the line connecting the two first capacitor pads.

[0012] Preferably, in the above-described packaging substrate, for the Nth conductive layer, the second region metal layer has an intersecting first sub-region and a second sub-region;

[0013] At least one of the second conductive structures is connected to each of the two ends of the first sub-region located on both sides of the intersection region;

[0014] The second sub-region is connected to at least one of the second conductive structures at each of its two ends on both sides of the intersection region;

[0015] The capacitor is fixedly connected at the intersection.

[0016] Preferably, in the above-described packaging substrate, two second conductive structures with a spacing of less than a set threshold are electrically connected based on the second region metal layer on the same ground layer.

[0017] Preferably, in the above-mentioned packaging substrate, in the same ground layer, two second conductive structures with a spacing greater than a set threshold are connected based on the second region metal layer, and there is no first conductive structure on the connection path of the second conductive structures.

[0018] Preferably, in the above-mentioned packaging substrate, the set threshold is less than or equal to the lateral dimension of the second conductive structure.

[0019] This application also provides a chip packaging structure, including:

[0020] A packaging substrate; the packaging substrate includes a plurality of stacked conductive layers, with an insulating layer between adjacent conductive layers, wherein at least one of the plurality of conductive layers includes a ground layer, the ground layer including a first region metal layer and a second region metal layer, the second region metal layer being located in an internal cutout of the first region metal layer and having an insulating gap between the second region metal layer and the first region metal layer; the packaging substrate also includes a plurality of conductive structures that are longitudinally electrically connected to different conductive layers; the conductive structures include: a first conductive structure for grounding; a second conductive structure for connecting to a power source; wherein, in the ground layer, the first conductive structures are all electrically connected to the first region metal layer, and the second region metal layer is electrically connected to a plurality of second conductive structures extending to the ground layer; among the plurality of second conductive structures connected to the second region metal layer, the spacing between at least two second conductive structures is greater than the lateral dimension of the second conductive structure;

[0021] A chip fixed to one side surface of the packaging substrate, wherein the first region metal layer and the second region metal layer are electrically connected to the power module inside the chip.

[0022] Preferably, in the above chip packaging structure, the plurality of conductive layers are sequentially arranged in the stacking direction as a first conductive layer to an Nth conductive layer, where N is a positive integer greater than 2, and at least the Nth conductive layer is the ground layer; the first conductive layer is soldered to fix the chip.

[0023] The chip packaging structure also includes a capacitor fixed on the Nth conductive layer, having a positive terminal and a negative terminal, which are electrically connected to the second region metal layer and the first region metal layer of the Nth conductive layer, respectively.

[0024] Preferably, in the above chip packaging structure, the Nth conductive layer includes a first capacitor pad and a second capacitor pad located in the capacitor bonding area;

[0025] The first capacitor pad is used to connect the positive terminal of the capacitor, and the second capacitor pad is used to connect the negative terminal of the capacitor; within a preset range from the capacitor soldering area, there is a second conductive structure, and the metal layer of the second area connects the second conductive structure and the first capacitor pad.

[0026] As described above, the packaging substrate and chip packaging structure provided in this application include a ground layer comprising a first region metal layer and a second region metal layer. The second region metal layer is located within a hollow area of ​​the first region metal layer and has an insulating gap with it. The packaging substrate also includes multiple conductive structures that are vertically electrically connected to different conductive layers. Each conductive structure includes a first conductive structure for grounding and a second conductive structure for connecting to a power source. In the ground layer, the first conductive structures are all electrically connected to the first region metal layer, and the second region metal layer is electrically connected to multiple second conductive structures extending to the ground layer. Among the multiple second conductive structures connected to the second region metal layer, the spacing between at least two second conductive structures is greater than the lateral dimension of the second conductive structure. The packaging substrate of this application can improve the power integrity of the chip packaging structure. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0028] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0029] Figure 1 A cross-sectional view of a packaging substrate provided in an embodiment of this application;

[0030] Figure 2 for Figure 1 Top view of the ground layer in the package substrate shown;

[0031] Figure 3 A top view of the Nth conductive layer provided in an embodiment of this application;

[0032] Figure 4 A schematic diagram illustrating the principle of reducing loop inductance based on back-mounted capacitors in an embodiment of this application;

[0033] Figure 5 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0034] Figure 6A PDN impedance curve for a chip packaging structure provided in this application embodiment;

[0035] Figure 7 A simulation system architecture diagram for chip packaging structure is provided in the embodiments of this application;

[0036] Figure 8 The time-domain simulation waveform diagram of a chip packaging structure provided in this application embodiment is shown. Detailed Implementation

[0037] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0038] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] refer to Figure 1 and Figure 2 As shown, Figure 1 This is a cross-sectional view of a packaging substrate provided in an embodiment of this application. Figure 2 for Figure 1 The diagram shows a top view of the grounding layer in the packaging substrate. The packaging substrate includes several stacked conductive layers 11, with an insulating layer 12 between adjacent conductive layers 11. At least one of the conductive layers 11 serves as a grounding layer 110. The grounding layer 110 includes a first region metal layer 21 and a second region metal layer 22. The second region metal layer 22 is located in the internal cutout of the first region metal layer 21 and has an insulating gap with the first region metal layer 21. The packaging substrate also includes multiple conductive structures 13 that are longitudinally electrically connected to different conductive layers 11. The conductive structures 13 include: a first conductive structure 131 for grounding; and a second conductive structure 132 for connecting to a power source.

[0040] In the grounding layer 110, the first conductive structures 131 are all electrically connected to the first region metal layer 21, and the second region metal layer 22 is electrically connected to a plurality of second conductive structures 132 extending to the grounding layer 110; among the plurality of second conductive structures 132 connected to the second region metal layer 22, the spacing between at least two second conductive structures 132 is greater than the lateral dimension of the second conductive structure 132.

[0041] In this embodiment, multiple second conductive structures 132 are connected through a second region metal layer 22 in the ground layer 110, thereby strengthening the power connection, reducing the loop inductance value, improving power integrity, and optimizing the product performance of the chip packaging structure.

[0042] exist Figure 1 In the illustrated embodiment, the bottommost conductive layer 11 is used as the ground layer 110 as an example for explanation. Depending on the chip packaging structure requirements, one or more conductive layers 11 in the packaging substrate can be designated as ground layers 110; this embodiment does not limit this. When there are multiple ground layers 110, the conductive layer pattern structure of each ground layer 110 can be the same or different depending on the requirements; this embodiment does not limit this. In the accompanying drawings of this embodiment, the area of ​​the packaging substrate shown is mainly the area of ​​the packaging substrate used to connect the power module of the chip.

[0043] As the functionality and complexity of SOCs (System-on-a-Chip) increase, the requirements for high-speed signal lines and power supplies become increasingly stringent. From a power supply perspective, adding a certain number of passive components to the side of the packaging substrate away from the chip can help improve the stability of the power distribution network (PDN). When using the packaging substrate provided in this application to package and protect the chip, the chip and passive components can be respectively bound to opposite sides of the packaging substrate, thereby reducing the size of the chip package structure. The passive components include capacitors.

[0044] refer to Figure 3 As shown, Figure 3 This is a top view of an Nth conductive layer provided in an embodiment of this application. In this configuration, a plurality of conductive layers 11 are arranged sequentially in the stacking direction as the first conductive layer to the Nth conductive layer, where N is a positive integer greater than 2. The Nth conductive layer includes a capacitor welding region 23, which is used for welding capacitors. In this configuration, at least the Nth conductive layer is a ground layer 110.

[0045] exist Figure 3 In the illustrated configuration, the Nth conductive layer includes a first capacitor pad 31 and a second capacitor pad 32 located within the capacitor soldering area 23. The first capacitor pad 31 is used to connect the positive terminal of the capacitor, and the second capacitor pad 32 is used to connect the negative terminal of the capacitor. Within a preset range from the capacitor soldering area 23, there is a second conductive structure 132, and a second region metal layer 22 connects the second conductive structure 132 and the first capacitor pad 31. In this configuration, multiple second conductive structures 132 are connected through the second region metal layer 22 and then connected to the first capacitor pad 31 in the Nth conductive layer, thereby strengthening the power supply connection and achieving the effect of strengthening the capacitor, which can effectively reduce the loop inductance value.

[0046] In this embodiment, the first conductive structure 131 and the second conductive structure 132 can be conductive vias that pass through multiple conductive layers 11. The conductive vias can be designed based on the circuit layout, with different conductive layers 11 connected through one or more conductive vias. The conductive vias can extend from any conductive layer 11 to another conductive layer 11, and are not limited to this type of design. Figure 1 In the configuration shown, the conductive hole extends from the first conductive layer to the Nth conductive layer.

[0047] In the Nth conductive layer, the first region metal layer 21 connects all the first conductive structures 131 extending to the Nth conductive layer and connects the second capacitor pad 32 to ensure the integrity of the ground plane and compensate for the grounding effect of the capacitor.

[0048] In conventional packaging substrates, taking N=10 as an example, when the 10th conductive layer serves as the ground plane and four capacitors are soldered and fixed, the two positive leads of the four corner capacitors are connected to separate capacitor positive pads. The conductive vias extending to the 10th conductive layer are distributed across multiple separate metal layer regions, resulting in poor power plane integrity. It is necessary to connect all positive leads to a metal layer above the 10th conductive layer that serves as the power plane. For example, taking the 8th layer as the power plane, the two capacitor positive pads on the 10th conductive layer connecting the same capacitor need to extend to the power plane of the 8th conductive layer through conductive vias, utilizing the higher power integrity of the 8th conductive layer for series connection. While this method can improve product performance to some extent by connecting capacitors on the Nth conductive layer, the excessively strong ground metal layer connection in the Nth conductive layer can lead to insufficient power connection and fewer current paths at the power supply end. To solve these problems, a more robust power plane can be used... Figure 3 As shown.

[0049] like Figure 3 As shown, a single capacitor soldering area 23 has two first capacitor pads 31 and two second capacitor pads 32; wherein the two second capacitor pads 32 are respectively disposed on both sides of the connection between the two first capacitor pads 31. Thus, a four-pin capacitor with two positive leads and two negative leads can be connected in the capacitor soldering area 23 via the two first capacitor pads 31 and the two second capacitor pads 32 in the Nth conductive layer. Furthermore, the two first capacitor pads 31 are connected to the second region metal layer 22 based on the Nth conductive layer, so that the two positive leads of the four-pin capacitor are connected in the Nth conductive layer. This method utilizes the connection of the four-pin capacitor and the second conductive structure 132 within a preset range to the same second region metal layer, forming a larger area power plane to compensate for the integrity of the power plane, thereby strengthening the capacitor and reducing the loop inductance.

[0050] The two first capacitor pads 31 connected to the Nth conductive layer can be connected to the power plane in the ath conductive layer through the second conductive structure 132. Here, a is a positive integer greater than 1 and less than N. For example, when N=10, a can be 8. The values ​​of N and a are not limited in this embodiment; they can be set based on the design requirements of the packaging substrate.

[0051] refer to Figure 4 As shown, Figure 4 This is a schematic diagram of the principle of reducing loop inductance based on back-mounted capacitors provided in an embodiment of this application. The first conductive layer of the packaging substrate is used for soldering and fixing to the pins 41 of the chip, and the surface of the Nth conductive layer has solder balls 43 and capacitor pads for soldering back-mounted capacitors 42.

[0052] like Figure 4 As shown, on the upper and lower sides of the packaging substrate, not only can a loop path be formed with the upper chip through the back-mounted capacitor 41 as shown by the thin vertical solid line, but also a loop path can be formed with the upper chip through the second conductive structure 132 connected by the solder ball 43 as shown by the thick vertical solid line, and a loop path can be formed with the upper chip through the first conductive structure 131 connected by the solder ball 43 as shown by the dashed vertical line. By superimposing multiple loop paths, the loop inductance value is reduced.

[0053] In some embodiments of this application, for the Nth conductive layer, the second region metal layer 22 has intersecting first and second sub-regions, such as... Figure 2 Or Figure 3 As shown, the first sub-region and the second sub-region intersect in an X-shape; at least one second conductive structure 132 is connected to each of the two ends of the first sub-region located on both sides of the intersection; at least one second conductive structure 1321 is connected to each of the two ends of the second sub-region located on both sides of the intersection; wherein, the capacitor is fixedly connected at the intersection position, and the capacitor welding area 23 includes the intersection position.

[0054] On the same ground plane 110, two second conductive structures 132 with a spacing less than a set threshold are electrically connected based on a second region metal layer 22. This improves the integrity of the power plane.

[0055] The threshold value can be set based on requirements, such as setting it to be no greater than the lateral dimension of the second conductive structure 132. In this way, within the same ground layer 110, two second conductive structures 132 with a spacing smaller than the threshold value are connected through the second region metal layer 22, thereby improving the integrity of the power plane.

[0056] In some embodiments of this application, two second conductive structures 132 with a spacing greater than a set threshold are connected based on a second region metal layer 2 on the same ground layer 110, and there is no first conductive structure 131 on the connection path of the second conductive structures 132. In this way, in the same ground layer 110, two second conductive structures 132 with a spacing greater than the set threshold and no first conductive structure 131 between them can be connected through the second region metal layer 22, thereby improving the integrity of the power plane.

[0057] As mentioned above, a threshold is set to be less than or equal to the lateral dimension of the second conductive structure. In this way, within the same ground layer 110, there will be no obstruction from the first conductive structure 131 between two second conductive structures 132 with a spacing less than the set threshold, allowing them to be directly connected, thereby improving the integrity of the power plane.

[0058] Based on the above-described packaging substrate embodiments, another embodiment of this application provides a chip packaging structure, which can be as follows: Figure 5 As shown.

[0059] refer to Figure 5 As shown, Figure 5 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application, combined with... Figure 1 , Figure 3 and Figure 5 As shown, the chip packaging structure includes:

[0060] The packaging substrate 10 includes a plurality of stacked conductive layers 11, with an insulating layer 12 between adjacent conductive layers 11. At least one of the conductive layers 11 serves as a ground layer 110. The ground layer 110 includes a first region metal layer 21 and a second region metal layer 22. The second region metal layer 22 is located within a hollow area of ​​the first region metal layer 21 and has an insulating gap with the first region metal layer 21. The packaging substrate also includes a plurality of conductive structures 13 that longitudinally connect different conductive layers. Each conductive structure 13 includes: a first conductive structure 131 for grounding; and a second conductive structure 132 for connecting to a power source. In the ground layer 110, the first conductive structures 131 are all electrically connected to the first region metal layer 21, and the second region metal layer 22 is electrically connected to a plurality of second conductive structures 132 extending to the ground layer 110. Among the plurality of second conductive structures 132 connected to the second region metal layer 22, the spacing between at least two second conductive structures 132 is greater than the lateral dimension of the second conductive structure 132.

[0061] The chip 40, which is fixed to one side of the packaging substrate 10, has a first region metal layer 21 and a second region metal layer 22 that are electrically connected to the power module inside the chip 40.

[0062] The chip packaging structure provided in this application uses the packaging substrate 10 provided in the above embodiment, which can improve the power integrity in the ground layer 110 and improve product performance.

[0063] Optionally, the conductive layers 110 are arranged sequentially in the stacking direction as the first conductive layer to the Nth conductive layer, where N is a positive integer greater than 2, and at least the Nth conductive layer is a ground layer 110; the first conductive layer is used to weld and fix the chip 40; the chip package structure also includes a capacitor 42, which is fixed on the Nth conductive layer and has a positive terminal and a negative terminal, which are electrically connected to the second region metal layer 22 and the first region metal layer 21 of the Nth conductive layer, respectively.

[0064] One or more capacitors 42 can be soldered and fixed on the packaging substrate 10. The capacitors 42 are soldered and fixed on the Nth conductive layer and are back-mounted capacitors, which can reduce the circuit inductance.

[0065] Optionally, the Nth conductive layer includes a first capacitor pad 31 and a second capacitor pad 32 located within the capacitor soldering area 23; the first capacitor pad 31 is used to connect the positive terminal pin of the capacitor, and the second capacitor pad 32 is used to connect the negative terminal pin of the capacitor; within a preset range from the capacitor soldering area 23, there is a second conductive structure 132, and the second region metal layer 22 connects the second conductive structure 132 and the first capacitor pad 31.

[0066] As mentioned above, capacitor 42 can be a four-pin capacitor. Utilizing the characteristic relationship between the four-pin capacitor and the second conductive structure 132 within a preset range, the integrity of the power plane is compensated to enhance the capacitance and reduce the circuit inductance. The back-mounted capacitor disposed on the surface of the Nth conductive layer is not limited to a four-pin capacitor; it can also be a two-pin capacitor.

[0067] refer to Figure 6 As shown, Figure 6 This document presents a PDN impedance curve for a chip packaging structure according to an embodiment of this application. The horizontal axis represents impedance in Ω, and the vertical axis represents frequency in MHz. The dashed line represents the PDN impedance curve of a conventional chip packaging structure, while the solid line represents the PDN impedance curve of a chip packaging structure using the packaging substrate described in this embodiment.

[0068] in, Figure 6 The conventional chip packaging structure differs from the chip packaging structure of this application only in the pattern of the Nth conductive layer; the other structures are identical, facilitating mutual comparison and reference. Based on Figure 6It can be seen that for a chip packaging structure using a conventional packaging substrate, the impedance at the peak of the curve is 170 mohm and the loop inductance is 45.29 pH. For a chip packaging structure using the packaging substrate described in this application embodiment, the impedance at the peak of the curve is 153 mohm and the loop inductance is 26.79 pH. Compared to a conventional chip packaging structure, the chip packaging structure provided in this application embodiment reduces impedance and loop inductance.

[0069] refer to Figure 7 and Figure 8 As shown, Figure 7 This application provides a simulation system architecture diagram for chip packaging structures. Figure 8 The time-domain simulation waveform diagram of a chip packaging structure provided in this application embodiment is shown.

[0070] like Figure 7 As shown, the simulation system includes a circuit board 52, a power management chip 51 and a chip packaging structure disposed on the circuit board. The chip 54 is soldered onto the packaging substrate 53 to form a packaging structure, and then fixedly connected to the circuit board 52 by solder balls at the bottom of the packaging substrate.

[0071] in, Figure 8 The upper curve in the figure shows the time-domain simulation waveform of the chip package structure prepared using a conventional packaging substrate, while the lower curve shows the time-domain simulation waveform of the chip package structure prepared using the packaging substrate provided in the embodiments of this application.

[0072] in, Figure 8 The conventional chip packaging structure differs from the chip packaging structure of this application only in the pattern of the Nth conductive layer; the other structures are identical, facilitating mutual comparison. When high-inversion operations are performed within the chip, such as when connected to a high load, a large current is required, causing a voltage drop at the power output pins. Based on... Figure 8 As shown in the simulation waveform, the voltage drop point of the chip pins reveals that in a conventional chip package structure with four capacitors, the voltage drops from 950mV to 776mV at the voltage drop point, a drop of approximately 174mV. This indicates poor voltage stability and negatively impacts chip performance. The chip package structure provided in this embodiment, based on the aforementioned four-capacitor design, allows the voltage drop point to decrease from 950mV to 786mV, a drop of approximately 164mV. Compared to a conventional chip package structure, this represents a 10mV voltage increase at the voltage drop point, a 1.05% improvement. Furthermore, this design demonstrates better voltage stability compared to conventional chip packages, thus enhancing chip performance.

[0073] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0074] It should be noted that, in the description of this application, the drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for ease of understanding and description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0075] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the middle.

[0076] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0077] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A packaging substrate, characterized in that, The packaging substrate includes a plurality of stacked conductive layers, with an insulating layer between adjacent conductive layers. At least one of the plurality of conductive layers is included as a ground layer. The ground layer includes a first region metal layer and a second region metal layer. The second region metal layer is located in the internal cutout of the first region metal layer and has an insulating gap between it and the first region metal layer. The packaging substrate further includes multiple conductive structures that are longitudinally electrically connected to different conductive layers; the conductive structures include: a first conductive structure for grounding; and a second conductive structure for connecting to a power source. In the grounding layer, the first conductive structures are all electrically connected to the first region metal layer, and the second region metal layer is electrically connected to a plurality of second conductive structures extending to the grounding layer; among the plurality of second conductive structures connected to the second region metal layer, the spacing between at least two second conductive structures is greater than the lateral dimension of the second conductive structure. Wherein, the plurality of conductive layers are sequentially arranged in the stacking direction as the first conductive layer to the Nth conductive layer, where N is a positive integer greater than 2; the Nth conductive layer includes a capacitor welding area for welding capacitors; at least the Nth conductive layer is the ground layer; The Nth conductive layer includes a first capacitor pad and a second capacitor pad located within the capacitor soldering area. The first capacitor pad is used to connect the positive terminal pin of the capacitor, and the second capacitor pad is used to connect the negative terminal pin of the capacitor. Within a preset range from the capacitor soldering area, there is a second conductive structure, and the second region metal layer connects the second conductive structure and the first capacitor pad.

2. The packaging substrate according to claim 1, characterized in that, Each capacitor soldering area has two first capacitor pads and two second capacitor pads; The two second capacitor pads are respectively located on both sides of the line connecting the two first capacitor pads.

3. The packaging substrate according to claim 2, characterized in that, For the Nth conductive layer, the second region metal layer has an intersecting first sub-region and a second sub-region; At least one of the second conductive structures is connected to each of the two ends of the first sub-region located on both sides of the intersection region; The second sub-region is connected to at least one of the second conductive structures at each of its two ends on both sides of the intersection region; The capacitor is fixedly connected at the intersection.

4. The packaging substrate according to claim 1, characterized in that, On the same grounding layer, two second conductive structures with a spacing less than a set threshold are electrically connected based on the second region metal layer.

5. The packaging substrate according to claim 1, characterized in that, In the same grounding layer, two second conductive structures with a spacing greater than a set threshold are connected based on the second region metal layer, and there is no first conductive structure on the connection path of the second conductive structures.

6. The packaging substrate according to claim 4 or 5, characterized in that, The set threshold is less than or equal to the lateral dimension of the second conductive structure.

7. A chip packaging structure, characterized in that, include: Packaging substrate; The packaging substrate includes a plurality of stacked conductive layers, with an insulating layer between adjacent conductive layers. At least one of the conductive layers serves as a ground layer. The ground layer includes a first region metal layer and a second region metal layer. The second region metal layer is located within a cutout of the first region metal layer and has an insulating gap with it. The packaging substrate also includes a plurality of conductive structures that are longitudinally electrically connected to different conductive layers. Each conductive structure includes: a first conductive structure for grounding; and a second conductive structure for connecting to a power source. In the ground layer, the first conductive structures are all electrically connected to the first region metal layer, and the second region metal layer is electrically connected to a plurality of second conductive structures extending to the ground layer. Among the plurality of second conductive structures connected to the second region metal layer, the spacing between at least two second conductive structures is greater than the lateral dimension of the second conductive structure. A chip fixed to one side surface of the packaging substrate, wherein the first region metal layer and the second region metal layer are electrically connected to the power module inside the chip; Wherein, the plurality of conductive layers are sequentially arranged in the stacking direction as the first conductive layer to the Nth conductive layer, where N is a positive integer greater than 2; the Nth conductive layer includes a capacitor welding area for welding capacitors; at least the Nth conductive layer is the ground layer; The Nth conductive layer includes a first capacitor pad and a second capacitor pad located within the capacitor soldering area. The first capacitor pad is used to connect the positive terminal pin of the capacitor, and the second capacitor pad is used to connect the negative terminal pin of the capacitor. Within a preset range from the capacitor soldering area, there is a second conductive structure, and the second region metal layer connects the second conductive structure and the first capacitor pad.

8. The chip packaging structure according to claim 7, characterized in that, The chip is fixed by welding the first conductive layer; The chip packaging structure also includes a capacitor fixed on the Nth conductive layer, having a positive terminal and a negative terminal, which are electrically connected to the second region metal layer and the first region metal layer of the Nth conductive layer, respectively.

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