Semiconductor device, preparation method and electronic equipment

Abstract

The embodiment of the invention discloses a semiconductor device, a preparation method and electronic equipment, the semiconductor device comprises a dielectric layer, a device structure layer, a first insulating layer, a first connecting part, a second insulating layer and a second connecting part, a transistor is formed in the device structure layer, and the second connecting part is electrically connected with a second electrode in the transistor, so that the first connecting part is electrically connected with the second electrode. And signals are transmitted through the second connecting part. And filling the first opening through the first connecting part, electrically connecting the first connecting part with the first electrode, and supplying power through the first connecting part. The cross section area of the first opening in the first cross section is larger than the cross section area of the second opening in the first cross section, and the cross section area of the first opening in the first cross section represents the cross section area of the first connecting part at the first cross section; the resistance of the first connecting part can be reduced compared with the resistance of the bottom connecting part in the prior art, and the IR drop and the power consumption are reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method and an electronic device. Background Art

[0002] In a semiconductor device, generally, a bottom contact hole is provided at the bottom of the semiconductor device, a bottom connection portion is filled in the bottom contact hole, and a metal line in a backside power delivery network (BSPDN) is electrically connected to a source or drain in a transistor through the bottom connection portion, so that the power signal is delivered to the source or drain of the transistor by using the BSPDN to supply power to the transistor. However, as the size of semiconductor devices decreases, the size of transistors and metal lines decreases, which will increase the resistance of the bottom connection portion, thereby increasing the voltage drop (IR drop), and further increasing the power consumption of the semiconductor device. Summary of the invention

[0003] Embodiments of the present application provide a semiconductor device, a manufacturing method, and an electronic device for reducing the resistance of a bottom connection portion, reducing IR drop, and reducing power consumption of the semiconductor device.

[0004] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising: a dielectric layer, a device structure layer, a first insulating layer, a first connection portion, a second insulating layer and a second connection portion, wherein the dielectric layer is disposed on the device structure layer so that the dielectric layer and the device structure layer are stacked, and a first opening and a second opening penetrating the dielectric layer are disposed in the dielectric layer, and the bottoms of the first opening and the second opening both lead to the device structure layer. The first insulating layer covers the dielectric layer and covers and fills the second opening, and the first insulating layer is disposed around the first opening, that is, the first insulating layer does not fill the first opening, but exposes the first opening. In addition, at least one transistor is formed in the device structure layer, and the transistor includes a channel region, a first electrode and a second electrode, and the first electrode and the second electrode are distributed at both ends of the channel region, and the first electrode is exposed in the first opening.

[0005] In order to transmit a signal to the transistor, a first contact hole penetrating the second insulating layer is provided in the second insulating layer, the bottom of the first contact hole leads to the device structure layer and the second electrode is exposed in the first contact hole. The second connecting portion is filled in the first contact hole, and the second connecting portion is in contact with the second electrode through the first contact hole to achieve electrical connection between the second connecting portion and the second electrode, thereby transmitting a signal to the second electrode through the second connecting portion.

[0006] Furthermore, in order to supply power to the transistor, the first connection part is filled in the first opening, that is, the first connection part is arranged on the back side of the transistor, and the first connection part is contacted with the first electrode through the first opening to realize the electrical connection between the first connection part and the first electrode, thereby transmitting the power signal to the first electrode of the transistor through the first connection part to supply power to the transistor.

[0007] In addition, the first cross section is located between the upper surface and the lower surface of the dielectric layer, and the cross-sectional area of ​​the first opening in the first cross section is larger than the cross-sectional area of ​​the second opening in the first cross section, and the cross-sectional area of ​​the first opening in the first cross section is the same or gradually increases in the direction from the device structure layer to the dielectric layer. The cross-sectional area of ​​the cross section of the first opening in the first cross section represents the cross-sectional area of ​​the first connecting portion in the first cross section, and the cross-sectional area of ​​the first connecting portion in the first cross section can be larger than the cross-sectional area of ​​the second opening in the first cross section. However, the cross-sectional area of ​​the bottom connecting portion in the first cross section in the prior art is substantially the same as the cross-sectional area of ​​the second opening in the first cross section. Based on this, according to the resistance formula R=ρL / S (R represents the resistance value, ρ represents the resistivity of the material forming the resistor, L represents the length of the wire forming the resistor, and S represents the cross-sectional area of ​​the resistor), since the cross-sectional area of ​​the first connection part in the present application at the first cross-section is larger than the cross-sectional area of ​​the bottom connection part in the prior art at the first cross-section, the resistance of the first connection part in the present application is lower than the resistance of the bottom connection part in the prior art, thereby achieving the reduction of IR drop and power consumption of semiconductor devices.

[0008] In some examples, the cross section of the first opening in the first cross section has a first length along the first direction, and the cross section of the second opening in the first cross section has a second length along the first direction, and the first length is greater than the second length to achieve that the first area is greater than the second area. In addition, the first direction is parallel to the first cross section.

[0009] In some other examples, the first angle is made smaller than the second angle by making the cross section of the first opening in the first cross section and the side wall of the first opening in the first direction have a first angle, and making the cross section of the second opening in the first cross section and the side wall of the second opening in the first direction have a second angle. With this arrangement, the length of the first opening can be expanded in the first direction by tilting the side wall of the second opening in the first direction. Of course, the first angle can also be made substantially equal to the second angle, and with this arrangement, the side wall of the second opening in the first direction can be translated in the first direction, thereby expanding the length of the first opening in the first direction.

[0010] Furthermore, the cross section of the first opening in the first cross section has a third length along the second direction, and the cross section of the second opening in the first cross section has a fourth length along the second direction, and the third length is substantially equal to the fourth length. This arrangement is equivalent to extending the length of the first opening in the first direction without extending the length of the first opening in the second direction, thereby avoiding a short circuit between the first electrode and the channel.

[0011] In order to reduce the contact resistance, at least one interface layer is further provided in the semiconductor device, and the at least one interface layer is provided between the first connecting portion and the first electrode, so that the contact resistance between the first connecting portion and the first electrode is reduced by the interface layer.

[0012] The interface layer includes a low resistivity material. Exemplarily, the material of the interface layer is a semiconductor material. For example, the interface layer includes silicon, and the interface layer also has a high-activity dopant (wherein the dopant includes one or both of phosphorus and arsenic). Alternatively, the interface layer includes silicon and carbon, and the interface layer also has a high-activity dopant (wherein the dopant includes one or both of phosphorus and arsenic). Exemplarily, the concentration of the high-activity dopant is 4E20cm -3 or larger.

[0013] In order to further reduce the contact resistance, at least one interface layer is provided between the first connecting portion and the side wall of the first opening, that is, at least one interface layer is provided between the first connecting portion and the dielectric layer, and at least one interface layer is provided between the first connecting portion and the first insulating layer.

[0014] Furthermore, in order to transmit a signal to the first electrode, a second contact hole penetrating the second insulating layer is further provided in the second insulating layer, and the bottom of the second contact hole leads to the device structure layer, and the first electrode is exposed in the second contact hole. In addition, a third connection portion is further provided in the semiconductor device, and the third connection portion is filled in the second contact hole, so that the third connection portion contacts the first electrode through the second contact hole, so as to realize an electrical connection between the third connection portion and the first electrode, thereby transmitting a signal to the first electrode through the third connection portion.

[0015] In the transistor, the channel region includes: a first connection region, a second connection region, and an active region disposed between the first connection region and the second connection region, the first electrode contacts the first connection region, and the second electrode contacts the second connection region. The transistor also includes a gate, and the gate covers the active region through a gate insulating layer, so that the active region is controlled by the gate to realize conduction and disconnection between the first electrode and the second electrode. In addition, the second insulating layer is disposed on both sides of the gate.

[0016] Exemplarily, the channel includes a plurality of channel layers sequentially arranged along the stacking direction, and the plurality of channel layers are arranged at intervals from each other. By surrounding the active area of ​​each channel layer with a gate through a gate insulating layer, the transistor in the present application is formed as a gate all around field-effect transistor (GAAFET). Furthermore, the channel layer may be set as a nanosheet channel layer or a nanowire channel layer.

[0017] In addition, the transistor also includes an inner spacer, a gate spacer, and a gate barrier layer. Two inner spacers are respectively arranged between two adjacent channel layers, and the gate spacers are arranged on both sides of the gate, that is, each gate is respectively provided with a gate spacer on both sides. In addition, the surface of the gate barrier layer facing away from the dielectric layer can be roughly flush with the surface of the gate spacer facing away from the dielectric layer.

[0018] In order to further improve the performance of the transistor, the transistor further includes a bottom dielectric isolation (BDI), wherein the BDI is disposed between the channel region and the dielectric layer, and a gate is provided between the BDI and the channel region.

[0019] In addition, an interconnection layer and a carrier wafer are also provided on the side of the transistor away from the dielectric layer, wherein the interconnection layer has a first metal interconnection line and a second metal interconnection line, wherein the first metal interconnection line is respectively connected to the second connection part and the carrier wafer, and the second metal interconnection line is respectively connected to the third connection part and the carrier wafer. Due to the arrangement, the signal can be transmitted on the transmission path formed by the second electrode, the second connection part, the first metal interconnection line and the carrier wafer, and the signal can be transmitted on the transmission path formed by the first electrode, the third connection part, the second metal interconnection line and the carrier wafer.

[0020] In the second aspect, the embodiment of the present application further provides an electronic device, which includes a circuit board and a semiconductor device, and the semiconductor device is connected to the circuit board. The semiconductor device is a semiconductor device such as the first aspect or various embodiments of the first aspect. In addition, the principle of solving the problem by the electronic device is similar to that of the aforementioned semiconductor device, so the implementation of the electronic device can refer to the implementation of the aforementioned semiconductor device, and the repeated parts will not be repeated.

[0021] In a third aspect, an embodiment of the present application further provides a method for preparing a semiconductor device, comprising:

[0022] A device structure layer and a second insulating layer are formed on a semiconductor substrate; a dielectric layer is disposed on the device structure layer, a first opening and a second opening penetrating the dielectric layer are disposed in the dielectric layer, and the bottoms of the first opening and the second opening both lead to the device structure layer; at least one transistor is formed in the device structure layer, the transistor comprises a channel region, a first electrode and a second electrode, and the first electrode and the second electrode are distributed and disposed at both ends of the channel region; the first electrode is exposed in the first opening; a substrate fin is provided between the second electrode of the transistor and the semiconductor substrate, the substrate fin fills the second opening, a sacrificial connection portion is filled in the first opening, and the sacrificial connection portion contacts the first electrode through the first opening; a second insulating layer is disposed on a side of the device structure layer away from the dielectric layer, a first contact hole penetrating the second insulating layer is disposed in the second insulating layer, the bottom of the first contact hole leads to the device structure layer, and the second electrode is exposed in the first contact hole;

[0023] Depositing a second connecting portion so that the second connecting portion fills the first contact hole and the second connecting portion contacts the second electrode through the first contact hole;

[0024] After etching away the substrate fin to expose a portion of the region facing the dielectric layer, a first insulating layer is deposited on the dielectric layer away from the device structure layer, so that the first insulating layer covers and fills the second opening and bypasses the first opening, and the first insulating layer covers the surface of the dielectric layer away from the device structure layer;

[0025] Etching the sidewall of the first opening so that the cross-sectional area of ​​the first opening in the first cross-section is larger than the cross-sectional area of ​​the second opening in the first cross-section, and the first cross-section is located between the upper surface and the lower surface of the dielectric layer; and the cross-sectional area of ​​the first opening in the first cross-section is the same or gradually increases in a direction from the device structure layer to the dielectric layer;

[0026] The first connection portion is filled in the first opening, and the first connection portion is in contact with the first electrode through the first opening.

[0027] The implementation method of etching the sidewall of the first opening includes the following process: using an inclined etching process to etch the sidewall of the first opening in a first direction, wherein the first direction is parallel to the first cross section.

[0028] Exemplarily, the tilted etching process includes an angled reactive ion etching process.

[0029] The above-mentioned preparation method further comprises: after depositing the second connection part, forming an interconnection layer on the side of the semiconductor substrate having the transistor, and after bonding the side of the semiconductor substrate having the transistor to the carrier wafer, removing the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1A schematic diagram of the structure of an electronic device in an embodiment of the present application;

[0031] Figure 2a A schematic diagram of a top view of a semiconductor device in an embodiment of the present application;

[0032] Figure 2b for Figure 2a A schematic diagram of a cross-sectional structure along the AA' direction;

[0033] Figure 2c for Figure 2a A schematic diagram of a cross-sectional structure along the BB' direction;

[0034] Figure 2d for Figure 2a A schematic diagram of a cross-sectional structure along the CC' direction;

[0035] Figure 2e for Figure 2a A schematic diagram of a cross-sectional structure along the DD' direction;

[0036] Figure 3a for Figure 2a Another schematic diagram of a cross-sectional structure along the BB' direction;

[0037] Figure 3b for Figure 2a A schematic diagram of another cross-sectional structure along the CC' direction;

[0038] Figure 4a A schematic diagram of a top view of the structure of a semiconductor device in an embodiment of the present application during the preparation process;

[0039] Figure 4b for Figure 4a Schematic diagram of the cross-sectional structure along the AA' direction;

[0040] Figure 5a It is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0041] Figure 5b for Figure 5a Schematic diagram of the cross-sectional structure along the AA' direction;

[0042] Figure 5c for Figure 5a Schematic diagram of the cross-sectional structure along the BB' direction;

[0043] Figure 5d for Figure 5a Schematic diagram of the cross-sectional structure along the CC' direction;

[0044] Figure 6aIt is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0045] Figure 6b for Figure 6a Schematic diagram of the cross-sectional structure along the AA' direction;

[0046] Figure 6c for Figure 6a Schematic diagram of the cross-sectional structure along the BB' direction;

[0047] Figure 6d for Figure 6a Schematic diagram of the cross-sectional structure along the CC' direction;

[0048] Figure 7a It is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0049] Figure 7b for Figure 7a Schematic diagram of the cross-sectional structure along the AA' direction;

[0050] Figure 7c for Figure 7a Schematic diagram of the cross-sectional structure along the BB' direction;

[0051] Figure 7d for Figure 7a Schematic diagram of the cross-sectional structure along the CC' direction;

[0052] Figure 8a It is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0053] Figure 8b for Figure 8a Schematic diagram of the cross-sectional structure along the AA' direction;

[0054] Figure 8c for Figure 8a Schematic diagram of the cross-sectional structure along the BB' direction;

[0055] Figure 8d for Figure 8a Schematic diagram of the cross-sectional structure along the CC' direction;

[0056] Figure 8e for Figure 8a Schematic diagram of the cross-sectional structure along the DD' direction;

[0057] Figure 9a It is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0058] Figure 9b for Figure 9aSchematic diagram of the cross-sectional structure along the AA' direction;

[0059] Fig.9c for Figure 9a Schematic diagram of the cross-sectional structure along the BB' direction;

[0060] Figure 9d for Figure 9a Schematic diagram of the cross-sectional structure along the CC' direction;

[0061] Fig.9e for Figure 9a Schematic diagram of the cross-sectional structure along the DD' direction;

[0062] Fig.10a It is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0063] Fig.10b for Fig.10a Schematic diagram of the cross-sectional structure along the AA' direction;

[0064] Fig.10c for Fig.10a Schematic diagram of the cross-sectional structure along the BB' direction;

[0065] Fig.10d for Fig.10a Schematic diagram of the cross-sectional structure along the CC' direction;

[0066] Fig.10e for Fig.10a Schematic diagram of the cross-sectional structure along the DD' direction;

[0067] Fig.11a It is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0068] Fig.11b for Fig.11a Schematic diagram of the cross-sectional structure along the AA' direction;

[0069] Fig.11c for Fig.11a Schematic diagram of the cross-sectional structure along the BB' direction;

[0070] Fig.11d for Fig.11a Schematic diagram of the cross-sectional structure along the CC' direction;

[0071] Fig.11e for Fig.11a Schematic diagram of the cross-sectional structure along the DD' direction;

[0072] Fig.12a It is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0073] Figure 12b for Fig.12a Schematic diagram of the cross-sectional structure along the AA' direction;

[0074] Fig.12c for Fig.12a Schematic diagram of the cross-sectional structure along the BB' direction;

[0075] Fig.12d for Fig.12a Schematic diagram of the cross-sectional structure along the CC' direction;

[0076] Fig.12e for Fig.12a Schematic diagram of the cross-sectional structure along the DD' direction;

[0077] Fig.13a It is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0078] Fig.13b for Fig.13a Schematic diagram of the cross-sectional structure along the AA' direction;

[0079] Fig.13c for Fig.13a Schematic diagram of the cross-sectional structure along the BB' direction;

[0080] Fig.13d for Fig.13a Schematic diagram of the cross-sectional structure along the CC' direction;

[0081] Fig.13e for Fig.13a Schematic diagram of the cross-sectional structure along the DD' direction;

[0082] Fig.14a It is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0083] Fig.14b for Fig.14a Schematic diagram of the cross-sectional structure along the AA' direction;

[0084] Fig.14c for Fig.14a Schematic diagram of the cross-sectional structure along the BB' direction;

[0085] Fig.14d for Fig.14a Schematic diagram of the cross-sectional structure along the CC' direction;

[0086] Fig.14e for Fig.14a Schematic diagram of the cross-sectional structure along the DD' direction.

[0087] Reference numerals:

[0088] 100-housing; 200-circuit board; 300-semiconductor device; 410-dielectric layer; 500-device structure layer; 510-channel region; 521-first electrode; 522-second electrode; 531-gate; 532-gate insulating layer; 533-inner sidewall; 535-gate sidewall; 534-gate barrier layer; 550-bottom electrical isolation layer; 610-first insulating layer; 540-second insulating layer; 710-first connection portion; 720-second connection portion; 730-third connection portion; 810-interconnection layer; 820-carrier wafer; 711-interface layer; F1-first direction; F2-second direction; F3-stacking direction; B1-first connection area; B2-second connection area; B3-active area ; SD1-first surface; SD2-second surface; KK1-first opening; KK2-second opening, KK3-third opening; SC-first cross section; h11-first length; h12-second length; h21-third length; h22-fourth length; β1-first angle; β2-second angle; 20'-fin structure; 20-stacked film layer; 23-substrate fin; 30-initial bottom electrical isolation layer; 21a / 21b / 21c-sacrificial layer; 22a / 22b / 22c / 511-channel layer; 41-dummy gate structure; 710'-sacrificial connection; 10-semiconductor substrate; 11-first semiconductor layer; 12-etching stop layer; 13-second semiconductor layer; 11'-retained substrate. DETAILED DESCRIPTION

[0089] In the description of the present application, "at least one" means one or more, wherein "a plurality" means two or more. In view of this, "a plurality" may also be understood as "at least two" in the embodiments of the present application. "And / or" describes the association relationship of the associated objects, indicating that there may be three relationships, for example, A and / or B, which may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship. In addition, it should be understood that in the description of the present application, words such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, the example embodiments can be implemented in a variety of forms and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present application more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. In addition, the same reference numerals in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. The words expressing position and direction described in this application are all explained by taking the drawings as examples, but they can be changed as needed, and the changes are all included in the protection scope of this application. The drawings of this application are only used to illustrate the relative position relationship and do not represent the true proportion.

[0090] In order to facilitate the understanding of the semiconductor device, preparation method and electronic device provided in the embodiment of the present application, the application scenario is first introduced below. The semiconductor device provided in the embodiment of the present application can be widely used in various electronic devices, including various terminal devices and electronic devices. For example, terminal devices include but are not limited to smart phones, smart TVs, smart TV set-top boxes, smart watches, personal computers (personal computers, PCs), wearable devices, smart broadband and other devices. Electronic devices include but are not limited to wireless networks, fixed networks, servers and other communication equipment, as well as device modules, memory and other devices, which are not listed one by one here.

[0091] Figure 1 Schematic diagram of a structure of an electronic device in an embodiment of the present application. Figure 1 The electronic device includes: a housing 100, a circuit board 200 disposed in the housing 100, and a semiconductor device 300 fixed on the circuit board 200. The semiconductor device 300 and the circuit board 200 can be connected by bonding, bonding, etc. to achieve electrical connection between the semiconductor device 300 and the circuit board 200, so that signals can be transmitted between the semiconductor device 300 and the circuit board 200.

[0092] Figure 2a is a schematic diagram of a top view of a semiconductor device in an embodiment of the present application, Figure 2b for Figure 2a A schematic diagram of a cross-sectional structure along the AA' direction, Figure 2c for Figure 2a A schematic diagram of a cross-sectional structure along the BB' direction, Figure 2d for Figure 2a A schematic diagram of a cross-sectional structure along the CC' direction, Figure 2e for Figure 2a A schematic diagram of a cross-sectional structure along the DD' direction. Figure 2a to Figure 2e , the semiconductor device includes: a dielectric layer 410, a device structure layer 500, a first insulating layer 610 and a second insulating layer 540. The dielectric layer 410 and the device structure layer 500 are stacked, the dielectric layer 410 has a first surface SD1 (i.e., an upper surface) and a second surface SD2 (i.e., a lower surface) along the stacking direction F3 of the dielectric layer 410 and the device structure layer 500, the device structure layer 500 is arranged on the first surface SD1 of the dielectric layer 410, the second insulating layer 540 is arranged on the side of the device structure layer 500 away from the dielectric layer 410, and the first insulating layer 610 is arranged on the second surface SD2 of the dielectric layer 410. Furthermore, the dielectric layer 410 includes a first opening KK1, a second opening KK2, and a third opening KK3 extending from its first surface SD1 to its second surface SD2, that is, the first opening KK1, the second opening KK2, and the third opening KK3 extend through the dielectric layer 410 in the stacking direction F3, respectively, and the bottoms of the first opening KK1, the second opening KK2, and the third opening KK3 all lead to the device structure layer 500. The first insulating layer 610 fills the second opening KK2 and the third opening KK3 and covers the second surface SD2 of the dielectric layer 410, and the first insulating layer 610 bypasses the first opening KK1. A first cross section SC is provided, which is perpendicular to the stacking direction F3, and the orthographic projection of the first insulating layer 610 on the first cross section SC does not overlap with the orthographic projection of the first opening KK1 on the first cross section SC, so that the first insulating layer 610 does not fill the first opening KK1, but exposes the first opening KK1. Furthermore, the cross-sectional area of ​​the first opening KK1 at the first cross section is in the direction from the device structure layer 500 to the dielectric layer 410 (ie Figure 2d Furthermore, the cross-sectional area of ​​the second opening KK2 at the first cross section increases gradually in the direction from the device structure layer 500 to the dielectric layer 410 (i.e. Figure 2d In addition, the cross-sectional area of ​​the third opening KK3 at the first cross section increases gradually in the direction from the device structure layer 500 to the dielectric layer 410 (ie, Figure 2d Of course, the cross-sectional area of ​​the first opening KK1 at the first cross section increases in the direction from the device structure layer 500 to the dielectric layer 410 (i.e. Figure 2dFurthermore, the cross-sectional area of ​​the second opening KK2 in the first cross section is the same in the direction from the device structure layer 500 to the dielectric layer 410 (i.e. Figure 2d In addition, the cross-sectional area of ​​the third opening KK3 in the first cross section is the same in the direction from the device structure layer 500 to the dielectric layer 410 (i.e. Figure 2d The same refers to the same in terms of error tolerance.

[0093] Continue to refer to Figure 2a to Figure 2eOne or more transistors are formed in the device structure layer 500, and the transistors include a channel region 510, a first electrode 521, a second electrode 522, one or more gates 531, and a gate insulating layer 532, wherein the first electrode 521, the channel region 510, and the second electrode 522 are arranged along the second direction F2, the gate 531 extends along the first direction F1 and is arranged across the channel region 510, the first electrode 521 is arranged at a first end of the channel region 510 away from a side of the second end of the channel region 510 and contacts the first end of the channel region 510, so that the first electrode 521 is electrically connected to the channel region 510, and the second electrode 522 is arranged at a second end of the channel region 510 away from a side of the first end of the channel region 510 and contacts the second end of the channel region 510, so that the second electrode 522 is electrically connected to the channel region 510. Furthermore, the orthographic projection of the first electrode 521 on the first cross section SC and the orthographic projection of the first opening KK1 on the first cross section SC have an overlapping area, so that the first electrode 521 is exposed in the first opening KK1. The orthographic projection of the second electrode 522 on the first cross section SC and the orthographic projection of the second opening KK2 on the first cross section SC have an overlapping area, so that the second electrode 522 is exposed in the second opening KK2. The orthographic projection of the channel region 510 on the first cross section SC and the orthographic projection of the third opening KK3 on the first cross section SC have an overlapping area, and the orthographic projection of the first opening KK1 on the first cross section SC and the orthographic projection of the second opening KK2 on the first cross section SC do not overlap with the orthographic projection of the channel region 510 on the first cross section SC. In addition, the first opening KK1, the second opening KK2 and the third opening KK3 are respectively connected to each other in the second direction F2, that is, the side walls of the first opening KK1, the second opening KK2 and the third opening KK3 in the first direction F1 are all formed by the dielectric layer 410. Furthermore, since the first insulating layer 610 fills the second opening KK2 and the third opening KK3, not only the first insulating layer 610 contacts the surface of the second electrode 522 facing the dielectric layer 410 through the second opening KK2, and the first insulating layer 610 contacts the surface of the channel region 510 facing the dielectric layer 410 through the third opening KK3, but also the sidewall of the first opening KK1 in the second direction F2 is formed by the first insulating layer 610. In a specific implementation, the device structure layer can be formed on the semiconductor substrate, and then the semiconductor substrate is completely removed or a portion of the semiconductor substrate is removed during the preparation process. Alternatively, the device structure layer can also be formed in the semiconductor substrate, so that the semiconductor substrate is used as a part of the device structure layer.

[0094] Continue to refer to Figure 2a to Figure 2e, the channel region 510 includes a first connection region B1, a second connection region B2, and an active region B3 disposed between the first connection region B1 and the second connection region B2, the first electrode 521 contacts the first connection region B1, the second electrode 522 contacts the second connection region B2, and the gate 531 covers the active region B3 via a gate insulating layer 532. Further, the channel region 510 includes a plurality of channel layers 511 sequentially disposed along the stacking direction F3, and the plurality of channel layers 511 are disposed at intervals from each other, and the gate 531 surrounds the active region B3 of each channel layer 511 via a gate insulating layer 532, so that the transistor in the present application is formed as a GAAFET. Moreover, the above-mentioned channel layer 511 can be configured as a nanosheet channel layer or a nanowire channel layer. It is understandable that the first electrode 521 can be configured as the source of the transistor and the second electrode 522 can be configured as the drain of the transistor. Alternatively, the first electrode 521 can be configured as the drain of the transistor and the second electrode 522 can be configured as the source of the transistor.

[0095] In addition, the transistor further includes an inner spacer 533, a gate spacer 535, and a gate barrier layer 534. Two inner spacers 533 are respectively disposed between two adjacent channel layers 511, and the orthographic projection of one of the two inner spacers 533 on the first cross section SC overlaps (or coincides) with the orthographic projection of the first connection area B1 on the first cross section SC, and the orthographic projection of the other inner spacer 533 on the first cross section SC overlaps (or coincides) with the orthographic projection of the second connection area B2 on the first cross section SC. The gate spacers 535 are arranged on both sides of the gate 531, that is, each gate 531 is provided with a gate spacer 535 on both sides, and the orthographic projection of the gate spacer 535 on one side of the gate 531 on the first cross section SC has an overlapping area (or coincides) with the orthographic projection of the first connection area B1 on the first cross section SC, and the orthographic projection of the gate spacer 535 on the other side on the first cross section SC has an overlapping area (or coincides) with the orthographic projection of the second connection area B2 on the first cross section SC. In addition, the gate barrier layer 534 covers the gate 531, and the orthographic projection of the gate barrier layer 534 on the first cross section SC has an overlapping area (or coincides) with the orthographic projection of the gate 531 on the first cross section SC. In addition, the surface of the gate barrier layer 534 facing away from the dielectric layer 410 can be substantially flush with the surface of the gate spacer 535 facing away from the dielectric layer 410.

[0096] To further improve the performance of transistors, refer to Figure 2b and Figure 2cThe transistor further includes a bottom dielectric isolation layer (BDI) 550, which is disposed between the channel region 510 and the dielectric layer 410, and the orthographic projection of the BDI 550 on the first cross section SC and the orthographic projection of the channel region 510 on the first cross section SC have an overlapping region (or coincidence), and a gate 531 is provided between the BDI 550 and the channel region 510. In addition, when the BDI 550 is provided, the first insulating layer 610 contacts the surface of the BDI 550 facing the dielectric layer 410 through the third opening KK3.

[0097] Continue to refer to Figure 2a to Figure 2e , the second insulating layer 540 is arranged between adjacent gates 531, and a gate spacer 535 is also arranged between the second insulating layer 540 and the gate 531. In order to realize signal transmission to the second electrode 522, a first contact hole is also arranged in the second insulating layer 540 that penetrates the second insulating layer 540 along the stacking direction F3, and the orthographic projection of the first contact hole on the first cross section SC and the orthographic projection of at least a part of the surface of the second electrode 522 on the side away from the dielectric layer 410 on the first cross section SC have an overlapping area, so that at least a part of the surface of the second electrode 522 on the side away from the dielectric layer 410 is exposed through the first contact hole. Based on this, a second connecting portion 720 is also arranged in the semiconductor device, and the second connecting portion 720 fills the first contact hole, so that the second connecting portion 720 contacts the surface of the second electrode 522 on the side away from the dielectric layer 410 through the first contact hole, so as to realize electrical connection between the second connecting portion 720 and the second electrode 522. In this way, a signal can be transmitted to the second electrode 522 through the second connecting portion 720.

[0098] In order to achieve signal transmission to the first electrode 521, continue to refer to Figure 2c and Figure 2d In the second insulating layer 540, a second contact hole is further provided that penetrates the second insulating layer 540 along the stacking direction F3, and the orthographic projection of the second contact hole on the first cross section SC overlaps with the orthographic projection of at least a portion of the surface of the first electrode 521 on the side away from the dielectric layer 410 on the first cross section SC, so that the first electrode 521 is exposed in the second contact hole. Based on this, a third connecting portion 730 is further provided in the semiconductor device, and the third connecting portion 730 is filled in the second contact hole, so that the third connecting portion 730 contacts the first electrode 521 through the second contact hole, thereby realizing electrical connection between the third connecting portion 730 and the first electrode 521. With this arrangement, a signal can be transmitted to the first electrode 521 through the third connecting portion 730.

[0099] Continue to refer to Figure 2a to Figure 2eAn interconnection layer 810 and a carrier wafer 820 are also provided on the side of the device structure layer 500 away from the dielectric layer 410. The interconnection layer 810 has a first metal interconnection line and a second metal interconnection line. The first metal interconnection line is respectively connected to the second connection part 720 and the carrier wafer 820, and the second metal interconnection line is respectively connected to the third connection part 730 and the carrier wafer 820. Due to the arrangement, the signal can be transmitted on the transmission path formed by the second electrode 522, the second connection part 720, the first metal interconnection line and the carrier wafer 820, and the signal can be transmitted on the transmission path formed by the first electrode 521, the third connection part 730, the second metal interconnection line and the carrier wafer 820.

[0100] To supply power to the transistor, continue to refer to Figure 2a to Figure 2e , a conductive material is filled in the first opening KK1 to form a first connection portion 710 filled in the first opening KK1, which is equivalent to setting the first connection portion 710 at the bottom of the device structure layer 500 (i.e., the second surface SD2 of the dielectric layer 410), and making the first connection portion 710 contact the first electrode 521 through the first opening KK1 to achieve electrical connection between the first connection portion 710 and the first electrode 521, that is, the first connection portion 710 is equivalent to the bottom connection portion. In this way, after forming a BSPDN on the side of the dielectric layer 410 away from the device structure layer 500, the metal wire in the BSPDN is electrically connected to the first connection portion 710, so as to realize the use of the BSPDN to transmit the power signal to the first electrode 521 of the device structure layer 500, so as to supply power to the device structure layer 500. Furthermore, the first cross section SC is located between the first surface SD1 of the dielectric layer 410 and the second surface SD2 of the dielectric layer 410, and the cross-sectional area of ​​the first opening KK1 in the first cross section SC is the first area, which represents the cross-sectional area of ​​the first connection portion 710 at the first cross section SC. Also, the cross-sectional area of ​​the second opening KK2 in the first cross section SC is the second area, and the first area is made larger than the second area, so that the cross-sectional area of ​​the first connection portion 710 at the first cross section SC can be larger than the second area. However, the cross-sectional area of ​​the bottom connection portion in the prior art in the first cross section SC is substantially the same as the second area. Based on this, according to the resistance formula R=ρL / S, since the cross-sectional area of ​​the first connection portion 710 in the present application at the first cross section SC is larger than the cross-sectional area of ​​the bottom connection portion in the prior art at the first cross section SC, the resistance of the first connection portion 710 in the present application is reduced compared to the resistance of the bottom connection portion in the prior art, thereby being able to reduce IR drop and power consumption of semiconductor devices.

[0101] Continue to refer to Figure 2a to Figure 2e, the cross section of the first opening KK1 in the first cross section SC has a first length h11 along the first direction F1, and the cross section of the second opening KK2 in the first cross section SC has a second length h12 along the first direction F1, so that the first length h11 can be greater than the second length h12. Further, the cross section of the first opening KK1 in the first cross section SC has a third length h21 along the second direction F2, and the cross section of the second opening KK2 in the first cross section SC has a fourth length h22 along the second direction F2, so that the third length h21 and the fourth length h22 can be substantially equal. Thus, the first area can be made greater than the second area. It can be understood that in the present application, by making the third length h21 and the fourth length h22 substantially equal, the first length h11 is greater than the second length h12, which is equivalent to expanding the length of the first opening KK1 in the first direction, but not expanding the length of the first opening KK1 in the second direction, thereby avoiding a short circuit between the first electrode 521 and the channel region 510. In addition, the first direction F1 and the second direction F2 are respectively parallel to the first cross section SC, and the first direction F1 is perpendicular to the second direction F2.

[0102] Continue to refer to Figure 2d and Figure 2e , a first angle β1 is formed between the cross section of the first opening KK1 in the first cross section SC and the side wall of the first opening KK1 in the first direction F1, and a second angle β2 is formed between the cross section of the second opening KK2 in the first cross section SC and the side wall of the second opening KK2 in the first direction F1, so that the first angle β1 can be smaller than the second angle β2. With this arrangement, the length of the first opening KK1 can be extended in the first direction by tilting the side wall of the second opening KK2 in the first direction F1. Of course, the first angle β1 can also be made substantially equal to the second angle β2, so that the side wall of the second opening KK2 in the first direction F1 can be translated in the first direction F1, so that the length of the first opening KK1 can be extended in the first direction.

[0103] Reference Figure 2d and Figure 2e The cross-sectional shape of the first electrode 521 in the stacking direction F3 is a first shape, and the cross-sectional shape of the second electrode 522 in the stacking direction F3 is a second shape, and the first shape is different from the second shape. Of course, the first shape and the second shape can also be the same, which is not limited here.

[0104] Furthermore, in order to reduce the contact resistance, Figure 3a for Figure 2a Another cross-sectional structural diagram along the BB' direction, Figure 3b for Figure 2a Another cross-sectional structural diagram along the CC' direction, refer to Figure 3a and Figure 3b , an interface layer 711 is also provided in the semiconductor device, and the interface layer 711 can be provided between the first connection portion 710 and the first electrode 521, so that the contact resistance between the first connection portion 710 and the first electrode 521 is reduced by the interface layer 711. In addition, the interface layer 711 includes a low resistivity material. Exemplarily, the material of the interface layer 711 is a semiconductor material. For example, the interface layer 711 may include silicon or silicon and carbon with a high-activity dopant (the high-activity dopant is, for example, one or both of phosphorus and arsenic). In one embodiment, the active dopant concentration is 4E20cm -3 or greater. It is understandable that Figure 3a and Figure 3b One interface layer 711 is used as an example for illustration. In practical applications, two, three or more stacked interface layers 711 may be provided, which is not limited here.

[0105] To further reduce the contact resistance, refer to Figure 3a and Figure 3b The interface layer 711 is also disposed between the first connection portion 710 and the side wall of the first opening KK1 . That is, the interface layer 711 is also disposed between the first connection portion 710 and the dielectric layer 410 , and the interface layer 711 is also disposed between the first connection portion 710 and the first insulating layer 610 .

[0106] Understandably, in order to Figure 2a The positional relationship of the relevant film layers or structures is clearly described in Figure 2a Some film layers are hidden in the figure, for example, the first insulating layer 610 and other film layers are hidden. For the position relationship of the hidden film layers, please refer to Figure 2b to Figure 2d .

[0107] The present application also provides a method for preparing the semiconductor device, which may include the following contents:

[0108] Reference Figure 4a and Figure 4b , Figure 4a is a schematic diagram of a top view of the structure of a semiconductor device in an embodiment of the present application during the preparation process, Figure 4b for Figure 4aSchematic diagram of the cross-sectional structure along the AA' direction. Exemplarily, a semiconductor substrate 10 is provided, and the semiconductor substrate 10 includes a first semiconductor layer 11, an etch stop layer 12 (Etch stop layer, ESL) and a second semiconductor layer 13 which are stacked. The material of the first semiconductor layer 11 includes but is not limited to Si, Ge, etc., the material of the etch stop layer 12 includes but is not limited to SiGe, SiO2, etc., and the material of the second semiconductor layer 13 includes but is not limited to Si, Ge, etc. Exemplarily, the semiconductor substrate 10 can be set as a silicon-on-insulator (SOI) substrate, in which the bottom silicon layer in the SOI substrate serves as the second semiconductor layer 13, the buried oxide layer (such as SiO2) serves as the etch stop layer 12, and the top silicon layer serves as the first semiconductor layer 11. Afterwards, an initial BDI 30 is epitaxially grown on the first semiconductor layer 11 of the semiconductor substrate 10. Afterwards, sacrificial layers 21a, 21b, 21c and channel layers 22a, 22b, 22c are alternately epitaxially grown on the initial BDI 30 to form a stacked film layer 20. In addition, the present application does not limit the number of channel layers and sacrificial layers in the stacked film layer 20, for example, it can be 3 to 7 layers. Figure 4b Take three channel layers and three sacrificial layers as an example for illustration. In addition, the present application does not limit the materials of the sacrificial layer and the channel layer. Different types of sacrificial layer materials may be matched with different channel materials according to the requirements of etching selectivity. The sacrificial layer not only plays a certain supporting role for the channel layer, but also needs to be selectively etched and removed, that is, when etching and removing the sacrificial layer, the material of the sacrificial layer has high selectivity compared with the material of the channel layer. Moreover, the sacrificial layer sometimes needs to provide stress for the channel layer. For example, when the material of the channel layer is Si, the material of the corresponding sacrificial layer can be SiGe, and the material of the initial BDI 30 is SiC or SiGe with a different concentration from that of the sacrificial layer.

[0109] Reference Figure 5a to Figure 5d , Figure 5a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Figure 5b for Figure 5a Schematic diagram of the cross-sectional structure along the AA' direction, Figure 5c for Figure 5a Schematic diagram of the cross-sectional structure along the BB' direction, Figure 5d for Figure 5aSchematic diagram of the cross-sectional structure along the CC' direction. Exemplarily, the above-mentioned stacked film layer 20, the initial BDI 30 and the first semiconductor layer 11 are patterned, and shallow grooves are formed in the first semiconductor layer 11, as well as a plurality of fin structures 20' spaced apart from each other and limited by the shallow grooves. The plurality of fin structures 20' extend along the second direction F2 and are arranged along the first direction F1. In addition, the fin structure 20' includes: a substrate fin 23 and a device fin, the portion of the first semiconductor layer 11 limited by the shallow groove serves as the substrate fin 23, and the portion of the first semiconductor layer 11 between the plane where the bottom of the shallow groove is located and the ESL12 serves as the retained substrate 11'. In addition, the device fin includes: a patterned initial BDI30 and a stacked structure, the stacked structure includes alternating layers of sacrificial layers 21a~21c and channel layers 22a~22c. In addition, the channel layer in the stacked structure can be formed as a nanosheet channel layer (or a nanowire channel layer). Afterwards, in order to isolate adjacent fin structures 20', dielectric materials may be filled in the shallow trenches to form a shallow trench isolation (STI) structure, and the formed STI structure is the dielectric layer 410. Afterwards, a plurality of dummy gate structures 41 are formed that span the active regions B3 of each stacked structure and are spaced apart from each other, and the plurality of dummy gate structures 41 extend along the first direction F1 and are arranged along the second direction F2. Moreover, the same dummy gate structure 41 may span multiple fin structures 20'. In addition, for silicon-based devices, the dummy gate structure 41 may include a dummy gate electrode layer and a dummy gate oxide layer disposed between the dummy gate electrode layer and the stacked structure. Optionally, the material of the dummy gate electrode layer includes, but is not limited to, polysilicon. Afterwards, gate sidewalls 535 are formed on both sides of the dummy gate structure 41 along the second direction F2 to reduce the short channel effect. Furthermore, the gate spacer 535 covers the surface of the dummy gate structure 41 on the side away from the fin structure 20', and the area where the fin structure 20' is located between the gate spacers 535 of two adjacent dummy gate structures 41 is the source and drain region. Optionally, the dielectric material forming the STI structure includes but is not limited to one or more of SiO2, SiON, and SiNx. Furthermore, the material forming the gate spacer 535 includes but is not limited to one or more of SiNx and SiON. In addition, Figure 5a to Figure 5d In the figure, one fin structure 20 ′ and three dummy gate structures 41 are taken as an example for illustration.

[0110] Reference Figures 6a to 6d , Figure 6a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Figure 6b for Figure 6a Schematic diagram of the cross-sectional structure along the AA' direction, Figure 6c for Figure 6a Schematic diagram of the cross-sectional structure along the BB' direction, Figure 6d for Figure 6a Schematic diagram of the cross-sectional structure along the CC' direction. Exemplarily, the stacked structure and the initial BDI 30 in the source and drain regions are removed by etching, the dummy gate structure 41 and the stacked structure and the initial BDI 30 below the gate spacer 535 are retained, and the sides of the sacrificial layers 21a-21c and the channel layers 22a-22c below the gate spacer 535 are exposed, and the substrate fin 23 in the source and drain regions is exposed.

[0111] Reference Figures 7a to 7d , Figure 7a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Figure 7b for Figure 7a Schematic diagram of the cross-sectional structure along the AA' direction, Figure 7c for Figure 7a Schematic diagram of the cross-sectional structure along the BB' direction, Figure 7d for Figure 7a Schematic diagram of the cross-sectional structure along the CC' direction. Exemplarily, the initial BDI 30 is removed by isotropic etching, and the BDI film layer is deposited by a deposition process (such as atomic layer deposition). Afterwards, the BDI film layer is etched to retain the BDI film layer under the dummy gate structure 41 and the gate sidewall 535, and the BDI film layer in the remaining area is removed to form BDI550. Optionally, the material forming the BDI film layer includes but is not limited to one or more of SiO2, SiCN, SiON, and SiN. It is understandable that this step is an optional scheme, that is, this step may be performed or not, and is not limited here.

[0112] Reference Figures 8a to 8e , Figure 8a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Figure 8b for Figure 8a Schematic diagram of the cross-sectional structure along the AA' direction, Figure 8c for Figure 8a Schematic diagram of the cross-sectional structure along the BB' direction, Figure 8d for Figure 8a Schematic diagram of the cross-sectional structure along the CC' direction, Figure 8e for Figure 8aSchematic diagram of the cross-sectional structure along the DD' direction. Exemplarily, in the source and drain region where the backside contact hole (BSC) needs to be formed, the substrate fin 23 is etched to remove the substrate fin 23 in the region. Since the sidewall of the substrate fin 23 in the region is the dielectric layer 410, after the substrate fin 23 is removed, a first opening KK1 is formed in the dielectric layer 410. Of course, the first semiconductor layer 11 below the substrate fin 23 can be further etched a certain distance d1 to form a hole below the first opening KK1. Among them, since the first opening KK1 is formed by etching away the substrate fin 23, the cross-sectional area of ​​the first opening KK1 in the first cross section SC is SKK1', and SSK1' represents the cross-sectional area of ​​the substrate fin 23 in the first cross section SC. Further, the first length of the cross section of the first opening KK1 in the first cross section SC along the first direction F1 is h11', and h11' represents the length of the cross section of the substrate fin 23 in the first cross section SC along the first direction F1. The third length of the cross section of the first opening KK1 in the first cross section SC along the second direction F2 is h21, and h21 represents the length of the cross section of the substrate fin 23 in the first cross section SC along the second direction F2. Further, the first angle between the cross section of the first opening KK1 in the first cross section SC and the side wall of the first opening KK1 in the first direction F1 is β1', and β1' represents the angle between the cross section of the substrate fin 23 in the first cross section SC and the side wall of the first opening KK1 in the first direction F1 (the angle is usually 70 to 90 degrees).

[0113] Reference Figures 9a to 9d , Figure 9a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Figure 9b for Figure 9a Schematic diagram of the cross-sectional structure along the AA' direction, Fig.9c for Figure 9a Schematic diagram of the cross-sectional structure along the BB' direction, Figure 9d for Figure 9a Schematic diagram of the cross-sectional structure along the CC' direction, Fig.9e for Figure 9aSchematic diagram of the cross-sectional structure along the DD' direction. Exemplarily, a sacrificial connection film layer is deposited by a deposition process (such as atomic layer deposition), and the sacrificial connection film layer is etched to retain the sacrificial connection film layer in the first opening KK1 and the hole, and the sacrificial connection film layer in the remaining area is etched away, and the sidewalls of the sacrificial layers 21a~21c and the channel layers 22a~22c under the dummy gate structure 41 and the gate sidewall 535 are exposed, thereby forming a sacrificial connection 710' in the first opening KK1 and the hole. Optionally, the material forming the sacrificial connection film layer includes but is not limited to one or more of SiC, Si / Ge, SiN, and C. Thereafter, an inner sidewall 533 is formed under the gate sidewall 535. Thereafter, a first electrode 521 and a second electrode 522 connected to the channel layer are epitaxially formed in the source and drain regions on both sides of the dummy gate structure 41. Thereafter, a second insulating layer 540 is deposited on the first electrode 521 and the second electrode 522. Afterwards, the dummy gate structure 41 is etched away to form a gate opening. Afterwards, the sacrificial layer in the gate opening is etched away to release the active area of ​​the channel layer 22a-22c. A dielectric material with a high dielectric constant (e.g., a dielectric material with a dielectric constant greater than that of silicon oxide) is sampled to form a gate insulating layer 532 covering the active area B3. In the gate opening, a gate 531 is formed surrounding each active area. Exemplarily, the gate 531 is a metal gate 531, wherein the metal gate 531 is generally a multi-layer structure, which includes but is not limited to a combination of a work function metal (possibly multiple layers of work function metal), a liner layer, a wetting layer, an adhesion layer, a metal conductive layer or a metal silicide. For example, the metal gate 531 includes but is not limited to titanium (Ti), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), titanium aluminum (TiAl), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), tungsten (W), etc. Afterwards, a second contact hole is formed in the second insulating layer 540 on the first electrode 521 to expose a partial area or the entire area of ​​the surface of the first electrode 521 on the side away from the ESL12 through the second contact hole. In addition, a first contact hole is formed in the second insulating layer 540 on the second electrode 522 to expose a partial area or the entire area of ​​the surface of the second electrode 522 on the side away from the ESL12 through the first contact hole. Afterwards, a metal material is deposited, and a third connection portion 730 is filled in the second contact hole so that the third connection portion 730 contacts the first electrode 521 through the second contact hole, thereby realizing an electrical connection between the third connection portion 730 and the first electrode 521. In addition, a second connection portion 720 is filled in the first contact hole so that the second connection portion 720 contacts the second electrode 522 through the first contact hole, thereby realizing an electrical connection between the second connection portion 720 and the second electrode 522.

[0114] Reference Figures 10a to 10d , Fig.10a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Fig.10b for Fig.10a Schematic diagram of the cross-sectional structure along the AA' direction, Fig.10c for Fig.10a Schematic diagram of the cross-sectional structure along the BB' direction, Fig.10d for Fig.10a Schematic diagram of the cross-sectional structure along the CC' direction, Fig.10e for Fig.10a Schematic diagram of the cross-sectional structure along the DD' direction. Exemplarily, an interconnection layer 810 is formed on the side of the device structure layer 500 away from the ESL12, and a carrier wafer 820 is bonded to the side of the interconnection layer 810 away from the ESL12.

[0115] Reference Figures 11a to 11d , Fig.11a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Fig.11b for Fig.11a Schematic diagram of the cross-sectional structure along the AA' direction, Fig.11c for Fig.11a Schematic diagram of the cross-sectional structure along the BB' direction, Fig.11d for Fig.11a Schematic diagram of the cross-sectional structure along the CC' direction, Fig.11e for Fig.11a Schematic diagram of the cross-sectional structure along the DD' direction. Exemplarily, the semiconductor device is turned over, and the back side of the semiconductor substrate 10 is thinned by a thinning process to remove the second semiconductor layer 13, and the thinning stops at the interface between ESL12 and the second semiconductor layer 13. Then, ESL12 is etched away. Then, the retained substrate 11' is etched away to expose the sacrificial connection portion 710'. The retained substrate 11' may be completely etched away, or a portion of the retained substrate 11' may be removed, as long as the sacrificial connection portion 710' is exposed.

[0116] Reference Figures 12a to 12d , Fig.12a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Figure 12b for Fig.12a Schematic diagram of the cross-sectional structure along the AA' direction, Fig.12c for Fig.12a Schematic diagram of the cross-sectional structure along the BB' direction, Fig.12d for Fig.12a Schematic diagram of the cross-sectional structure along the CC' direction, Fig.12e for Fig.12aSchematic diagram of the cross-sectional structure along the DD' direction. Exemplarily, the substrate fin 23 on the side of the BDI220 away from the channel layer is etched away, and the substrate fin 23 on the side of the second electrode 522 away from the second connecting portion 720 is removed, and the second opening KK2 and the third opening KK3 are formed in the dielectric layer 410. Wherein, since the substrate fin 23 is etched away to form the second opening KK2, the cross-sectional area of ​​the second opening KK2 in the first cross-section SC is SKK2, and the second length of the cross section of the second opening KK2 in the first cross-section SC along the first direction F1 is h12, and the fourth length of the cross section of the second opening KK2 in the first cross-section SC along the second direction F2 is h22. Furthermore, the second angle between the cross section of the second opening KK2 in the first cross-section SC and the side wall of the first opening KK1 in the first direction F1 is β2. Furthermore, since the substrate fin is removed by etching, a third opening KK3 is formed, and the length of the cross section of the third opening KK3 in the first cross section SC along the first direction F1 is substantially the same as h12. Further, the angle between the cross section of the third opening KK3 in the first cross section SC and the side wall of the first opening KK1 in the first direction F1 is substantially the same as β2. Furthermore, since both the first opening KK1 and the second opening KK2 are formed by etching away the substrate fin, SKK2 is substantially the same as SKK1', h11' is substantially the same as h12, β1' is substantially the same as β2, and h22 is substantially the same as h21. Afterwards, a first insulating layer 610 is deposited on the side of the dielectric layer 410 away from the BDI550, and the first insulating layer 610 fills the second opening KK2 and the third opening KK3, and the first insulating layer 610 covers the surface of the dielectric layer 410 away from the BDI. Afterwards, the first insulating layer 610 is planarized by a chemical mechanical polishing (CMP) process to expose the surface of the sacrificial connection portion facing away from the BDI. It is understandable that the material of the first insulating layer 610 and the material of the dielectric layer 410 may be the same or different, which is not limited here.

[0117] Reference Figures 13a to 13d , Fig.13a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Fig.13b for Fig.13a Schematic diagram of the cross-sectional structure along the AA' direction, Fig.13c for Fig.13a Schematic diagram of the cross-sectional structure along the BB' direction, Fig.13d for Fig.13a Schematic diagram of the cross-sectional structure along the CC' direction, Fig.13e for Fig.13aSchematic diagram of the cross-sectional structure along the DD' direction. Exemplarily, the sacrificial connection portion 710' is etched away, and a partial area or the entire area of ​​the surface of the first electrode 521 facing the first insulating layer 610 is exposed through the first opening KK1. Among them, the first length h11 of the cross section of the first opening KK1 in the first cross section SC along the first direction F1 is h11'. The third length of the cross section of the first opening KK1 in the first cross section SC along the second direction F2 is h21. The first angle between the cross section of the first opening KK1 in the first cross section SC and the side wall of the first opening KK1 in the first direction F1 is β1'.

[0118] Reference Figures 14a to 14d , Fig.14a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Fig.14b for Fig.14a Schematic diagram of the cross-sectional structure along the AA' direction, Fig.14c for Fig.14a Schematic diagram of the cross-sectional structure along the BB' direction, Fig.14d for Fig.14a Schematic diagram of the cross-sectional structure along the CC' direction, Fig.14e for Fig.14a Schematic diagram of the cross-sectional structure along the DD' direction. Exemplarily, an inclined etching process such as an angled reactive ion etching process is used to etch the side wall of the first opening KK1 in the first direction F1, so that the first angle between the cross section of the first opening KK1 in the first cross section SC and the side wall of the first opening KK1 in the first direction F1 is β1, and the cross section of the first opening KK1 in the first cross section SC is increased from h11' to h11 along the first length h11 in the first direction F1, so that h11>h12. Moreover, h12 does not change, so that the cross-sectional area of ​​the first opening KK1 in the first cross section SC can be increased from SKK1' to SKK1. That is, SKK1>SKK2 is achieved. Furthermore, when an inclined etching process such as an angled reactive ion etching process is used to etch the sidewall of the first opening KK1 in the first direction F1, the sidewall of the first opening KK1 in the first direction F1 can be translated so that β1 is substantially the same as β1', and β1 is substantially the same as β2, or the sidewall of the first opening KK1 in the first direction F1 can be inclined so that β1<β1', and β1<β2. In this way, the length of the first opening KK1 is enlarged in the first direction, but the length of the first opening KK1 is not enlarged in the second direction, so that a short circuit between the first electrode 521 and the channel region 510 can be avoided.

[0119] Reference Figure 2a to Figure 2d, deposit a metal layer on the side of the first insulating layer 610 away from the dielectric layer 410, fill the first opening KK1 with the metal layer, and cover the surface of the first insulating layer 610 away from the BDI550. Then, planarize the metal layer by CMP process, remove the metal layer covering the surface of the first insulating layer 610 away from the BDI550, expose the first insulating layer 610, and form the first connecting portion 710 in the first opening KK1. Alternatively, refer to Figure 3a and Figure 3b , an interface layer is deposited on the side of the first insulating layer 610 away from the dielectric layer 410, and the interface layer covers the surface of the first electrode in the first opening KK1, and covers the sidewall of the first opening KK1. Then, a metal layer is deposited on the side of the first insulating layer 610 away from the dielectric layer 410, and the metal layer fills the first opening KK1, and the metal layer covers the surface of the first insulating layer 610 away from the BDI550. Then, the metal layer is planarized by a CMP process, and the metal layer covering the surface of the first insulating layer 610 away from the BDI550 is removed, exposing the first insulating layer 610, thereby forming a first connecting portion 710 in the first opening KK1.

[0120] The embodiment of the present application also provides an electronic device, which includes a circuit board (such as a printed circuit board) and any semiconductor device provided in the above embodiment of the present application, and the semiconductor device is connected to the circuit board. Since the principle of solving the problem by the electronic device is similar to that of the above semiconductor device, the implementation of the electronic device can refer to the implementation of the above semiconductor device, and the repeated parts will not be repeated.

[0121] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: dielectric layer; A device structure layer, wherein the dielectric layer is arranged on the device structure layer, a first opening and a second opening penetrating the dielectric layer are arranged in the dielectric layer, and the bottoms of the first opening and the second opening both lead to the device structure layer; at least one transistor is formed in the device structure layer, and the transistor includes a channel region, a first electrode and a second electrode, the first electrode and the second electrode are distributed and arranged at two ends of the channel region, and the first electrode is exposed in the first opening; a first insulating layer, covering the dielectric layer, the first insulating layer covering and filling the second opening, and the first insulating layer bypassing the first opening; a first connection portion filled in the first opening, and the first connection portion contacts the first electrode through the first opening, a cross-sectional area of ​​the first opening in a first cross-section is greater than a cross-sectional area of ​​the second opening in the first cross-section, the first cross-section is located between the upper surface and the lower surface of the dielectric layer; and a cross-sectional area of ​​the first opening in the first cross-section is the same or gradually increases in a direction from the device structure layer to the dielectric layer; A second insulating layer is arranged on a side of the device structure layer away from the dielectric layer, the second insulating layer is provided with a first contact hole penetrating the second insulating layer, the bottom of the first contact hole leads to the device structure layer, and the second electrode is exposed in the first contact hole; The second connection portion is filled in the first contact hole, and the second connection portion is in contact with the second electrode through the first contact hole.

2. The semiconductor device according to claim 1, wherein The cross section of the first opening in the first cross section has a first length along a first direction, the cross section of the second opening in the first cross section has a second length along the first direction, the first length is greater than the second length, and the first direction is parallel to the first cross section.

3. The semiconductor device according to claim 2, wherein: A first angle is formed between a cross section of the first opening in the first cross section and a side wall of the first opening in the first direction, a second angle is formed between a cross section of the second opening in the first cross section and a side wall of the second opening in the first direction, and the first angle is not greater than the second angle.

4. The semiconductor device according to claim 2 or 3, characterized in that The cross section of the first opening in the first cross section has a third length along the second direction, the cross section of the second opening in the first cross section has a fourth length along the second direction, the third length is equal to the fourth length, the second direction is parallel to the first cross section, and the second direction is perpendicular to the first direction.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The semiconductor device further includes: at least one interface layer, and the at least one interface layer is disposed between the first connection portion and the first electrode.

6. The semiconductor device according to claim 5, characterized in that The material of the interface layer is semiconductor material.

7. The semiconductor device according to claim 6, wherein: The interfacial layer includes silicon and a dopant; Alternatively, the interfacial layer comprises silicon, carbon and a dopant; The dopant includes one or both of phosphorus and arsenic.

8. The semiconductor device according to any one of claims 5 to 7, characterized in that: The at least one interface layer is also disposed between the first connecting portion and a sidewall of the first opening.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that: A second contact hole penetrating the second insulating layer is also provided in the second insulating layer, the bottom of the second contact hole leads to the device structure layer, and the first electrode is exposed in the second contact hole; The semiconductor device further includes a third connection portion filled in the second contact hole and contacting the first electrode through the second contact hole.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that: The channel region includes: a first connection region, a second connection region, and an active region disposed between the first connection region and the second connection region, the first electrode contacts the first connection region, and the second electrode contacts the second connection region; The transistor further includes a gate, the gate covers the active area via a gate insulating layer, and the second insulating layer is arranged on both sides of the gate.

11. The semiconductor device according to claim 10, wherein: The channel region includes: a plurality of channel layers which are stacked and spaced apart from each other; the gate surrounds an active region of each channel layer via the gate insulating layer.

12. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in any one of claims 1 to 11, wherein the semiconductor device is connected to the circuit board.

13. A method for preparing a semiconductor device, characterized in that: include: forming a dielectric layer, a device structure layer and a second insulating layer on a semiconductor substrate; The dielectric layer is arranged on the device structure layer, and a first opening and a second opening penetrating the dielectric layer are arranged in the dielectric layer, and the bottoms of the first opening and the second opening both lead to the device structure layer; At least one transistor is formed in the device structure layer, and the transistor includes a channel region, a first electrode and a second electrode, wherein the first electrode and the second electrode are disposed at two ends of the channel region; the first electrode is exposed in the first opening; A substrate fin is provided between the second electrode of the transistor and the semiconductor substrate, the substrate fin fills the second opening, a sacrificial connection portion is filled in the first opening, and the sacrificial connection portion contacts the first electrode through the first opening; A second insulating layer is arranged on a side of the device structure layer away from the dielectric layer, a first contact hole penetrating the second insulating layer is arranged in the second insulating layer, a bottom of the first contact hole leads to the device structure layer, and the second electrode is exposed in the first contact hole; Depositing a second connecting portion so that the second connecting portion fills the first contact hole and the second connecting portion contacts the second electrode through the first contact hole; After etching away the substrate fin to expose a portion of the channel region facing the dielectric layer, a first insulating layer is deposited on a side of the dielectric layer away from the device structure layer, so that the first insulating layer covers and fills the second opening and bypasses the first opening, and the first insulating layer covers a surface of the dielectric layer away from the device structure layer; Etching the sidewall of the first opening so that the cross-sectional area of ​​the first opening in a first cross-section is larger than the cross-sectional area of ​​the second opening in the first cross-section, the first cross-section is located between the upper surface and the lower surface of the dielectric layer; and the cross-sectional area of ​​the first opening in the first cross-section is the same or gradually increases in a direction from the device structure layer to the dielectric layer; A first connection portion is filled in the first opening, and the first connection portion is in contact with the first electrode through the first opening.

14. The preparation method according to claim 13, characterized in that: An inclined etching process is adopted to etch the sidewall of the first opening in a first direction, where the first direction is parallel to the first cross section.

15. The preparation method according to claim 14, characterized in that: The tilted etching process includes an angled reactive ion etching process.

16. The preparation method according to any one of claims 13 to 15, characterized in that: The preparation method further comprises: After depositing the second connecting portion, forming an interconnection layer on a side of the semiconductor substrate having the transistor; After bonding the semiconductor substrate with the transistor side to a carrier wafer, the semiconductor substrate is removed.

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