Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same may be provided herein. The semiconductor device may include a first structure including a first chip region and a first scribe region; a second structure disposed on the first structure; a first alignment key disposed in the first scribe region; at least one first bond pad disposed between the first alignment key and the first chip region, the first bond pad abutting an upper surface of the first structure; and a second bonding pad adjoining a lower surface of the second structure to contact the at least one first bonding pad.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a memory block having a three-dimensional (3D) structure and a method of manufacturing the same. Background Art

[0002] Through the semiconductor integration process, multiple chip regions can be formed on the semiconductor substrate. The multiple chip regions can be separated from each other by the scribe area. By separating the semiconductor chip regions from each other through a cutting process, the semiconductor chip region can be manufactured into multiple semiconductor chips.

[0003] As the improvement of the integration degree of a two-dimensional (2D) nonvolatile memory device in which memory cells are formed in a single layer on a substrate reaches its limit, a nonvolatile memory device having a 3D structure in which memory cells are vertically stacked on a substrate has been proposed, and a method of forming more circuits in a limited chip area has been proposed. For example, a wafer bonding method of combining a first wafer in which a peripheral circuit is formed with a second wafer in which a memory cell is formed has been proposed. Summary of the invention

[0004] Embodiments of the present disclosure may provide a semiconductor device. The semiconductor device may include: a first structure including a first chip region and a first scribe region; a second structure disposed on the first structure; a first alignment key disposed in the first scribe region; at least one first bonding pad disposed in the first scribe region, disposed between the first alignment key and the first chip region, the first bonding pad bordering an upper surface of the first structure; and at least one second bonding pad bordering a lower surface of the second structure to contact the at least one first bonding pad.

[0005] Embodiments of the present disclosure may provide a method for manufacturing a semiconductor device. The method may include the following steps: forming a first alignment key in a first scribe area of ​​a first structure defining a first scribe area and a first chip area; forming at least one first bonding pad disposed between the first alignment key and the first chip area, the at least one first bonding pad being adjacent to the upper surface of the first structure; forming at least one second bonding pad adjacent to the upper surface of the second structure, the at least one second bonding pad being formed in a second scribe area of ​​a second structure defining a second scribe area and a second chip area; and flipping the second structure so that the at least one second bonding pad is adjacent to the lower surface of the second structure, and stacking the second structure on the first structure so that the at least one second bonding pad of the flipped second structure contacts the at least one first bonding pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 2 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0008] FIG. 3A to FIG. 3C is a diagram illustrating an alignment key and a bonding pad according to an embodiment of the present disclosure.

[0009] FIG. 4A to FIG. 4E are diagrams showing bonding pads of various shapes according to an embodiment of the present disclosure.

[0010] FIG. 5A to FIG. 5H 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 6 is a diagram showing a memory card system to which the semiconductor device of the present disclosure is applied.

[0012] Figure 7 is a diagram showing a solid state drive (SSD) system to which the semiconductor device of the present disclosure is applied. DETAILED DESCRIPTION

[0013] The specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification or application are only for describing the embodiments of the present disclosure. The present disclosure can be implemented in many different forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0014] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can easily practice the technical spirit of the present disclosure.

[0015] Various embodiments of the present disclosure are directed to a semiconductor device and a method of manufacturing the semiconductor device, which can increase the bonding force of the semiconductor device manufactured by a wafer bonding method.

[0016] Figure 1 is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0017] The semiconductor device may include a structure STR. For example, the semiconductor device may include two structures STR. The structure STR may include a substrate (e.g., a silicon wafer, a SiGe wafer, an SOI wafer) and a material pattern formed on the substrate. In another embodiment, the structure STR may include a material pattern and may not include a substrate. The cross-sectional shape of the structure STR will be referred to later. Figure 2 describe.

[0018] Reference Figure 1The structure STR may include a chip area CHA and a scribe area SLA. The scribe area SLA may surround the chip area CHA.

[0019] The chip area CHA may be an area in which a semiconductor chip is formed. The chip area CHA may be arranged in an XY plane. A semiconductor chip may be formed by a semiconductor integration process performed on the chip area CHA. The semiconductor chips formed in a plurality of chip areas CHA may be substantially the same. After the semiconductor integration process is completed on the substrate, the structure STR may be separated into the chip areas CHA so that each chip area CHA may be separated into the shape of a semiconductor chip.

[0020] The scribe area SLA may be disposed outside the chip area CHA. For example, the scribe area SLA may be disposed between the chip areas CHA. After the semiconductor integration process is completed, the scribe area SLA may be cut off during the dicing process of separating the semiconductor chip. The individual chip areas CHA may be separated by cutting the structure STR along the scribe area SLA. The process for cutting the structure STR may include a sawing process using a blade, a laser process using a laser, an invisible dicing process, and the like. A chip protection member, an electrical test pattern, a process monitoring pattern, and an alignment key for protecting the chip area CHA may be disposed in the scribe area SLA.

[0021] The alignment key area AKA may be defined in the area of ​​the scribe line area SLA. The alignment key area AKA may be an area where an alignment key is formed. The alignment key will be referred to later. FIG. 3A to FIG. 3C describe.

[0022] although Figure 1 Six chip regions CHA are shown, but this is for convenience of illustration only and is not limited thereto. For example, the structure STR may include a varying number of chip regions CHA, including 7 or more. In addition, although Figure 1 The scribe lane area SLA is shown to include one alignment key area AKA, but is not limited thereto. The position and number of the alignment key areas AKA included in the scribe lane area SLA may be changed in various ways. In addition, the alignment key area AKA may be formed at any position around the chip area CHA, and at least two alignment key areas AKA may be disposed adjacent to any one chip area CHA.

[0023] Figure 2 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 2 It is along Figure 1 A cross-sectional view taken along line AA'.

[0024] Reference Figure 2, the semiconductor device may include a first structure STR1 and a second structure STR2, the second structure STR2 being disposed on the first structure STR1 in the Z direction. The second structure STR2 may be stacked on the first structure STR1. A lower surface of the second structure STR2 may contact an upper surface of the first structure STR1. The second structure STR2 may be coupled to the first structure STR1 by a wafer bonding method.

[0025] The first structure STR1 may include a first chip area CHA1 and a first scribing area SLA1. The second structure STR2 may include a second chip area CHA2 and a second scribing area SLA2. The second chip area CHA2 may overlap with the first chip area CHA1, and the second scribing area SLA2 may overlap with the first scribing area SLA1. Each of the first chip area CHA1 and the second chip area CHA2 may correspond to Figure 1 The chip area CHA, each of the first scribe lane area SLA1 and the second scribe lane area SLA2 may correspond to Figure 1 The SLA of the zoned area. Figure 2 The scribe lane regions (e.g., SLA1, SLA2) are shown to be arranged in the X direction relative to the chip regions (e.g., CHA1, CHA2), but this is only exemplary and not limited thereto. For example, the scribe lane regions (e.g., SLA1, SLA2) may be arranged in various directions relative to the chip regions (e.g., CHA1, CHA2), such as the Y direction, the opposite direction of the X direction, or the opposite direction of the Y direction.

[0026] The first structure STR1 may include a substrate SST. The substrate SST may extend from the first chip area CHA1 to the first scribe area SLA1. The substrate SST may extend in the X direction and the Y direction. For example, the substrate SST may be a silicon wafer, a SiGe wafer, or an SOI wafer.

[0027] The first structure STR1 may include a first material layer ML1 disposed on a substrate SST. The first material layer ML1 may be formed in a first scribe area SLA1 of the first structure STR1. The first material layer ML1 may be formed as an insulating layer (eg, an oxide layer).

[0028] In addition, the first structure STR1 may include a peripheral circuit. The first structure STR1 may include a third material layer ML3 disposed on the substrate SST, and may include at least one transistor TR, at least one first line L1, and at least one first plug P1 disposed inside the third material layer ML3. The third material layer ML3, at least one transistor TR, at least one first line L1, and at least one first plug P1 may be formed in a first chip area CHA1 of the first structure STR1. The third material layer ML3 may be formed as an insulating layer (e.g., an oxide layer), the at least one transistor TR may be formed of a semiconductor layer (e.g., doped silicon), and the at least one first line L1 and the at least one first plug P1 may be formed of a conductive layer (e.g., metal). Figure 2 The transistor TR, the first line L1 and the first plug P1 shown are only exemplary. The first structure STR1 may include Figure 2 The transistor TR, the first line L1 and the first plug P1 shown together form an additional component of the peripheral circuit.

[0029] The second structure STR2 may include a second material layer ML2 overlapping the first material layer ML1. The second material layer ML2 may be formed in the second scribe area SLA2 of the second structure STR2. The second material layer ML2 may be formed as a single layer or multiple layers. For example, the second material layer ML2 may be formed as an insulating layer (e.g., an oxide layer). In another embodiment, some regions of the second material layer ML2 may be formed as insulating layers, while other regions may be formed of multiple layers having different characteristics.

[0030] In addition, the second structure STR2 may include a conductive layer CD and an interlayer insulating layer IIL alternately stacked. The conductive layer CD and the interlayer insulating layer IIL may be formed in the second chip area CHA2 of the second structure STR2. The conductive layer CD and the interlayer insulating layer IIL may be stacked on each other in the Z direction. The conductive layer CD may be formed of at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polycrystalline silicon (poly-Si). The interlayer insulating layer IIL may be formed as an insulating layer (e.g., an oxide layer).

[0031] The second structure STR2 may include a cell plug CP within the alternately stacked conductive layers CD and the interlayer insulating layers IIL. The cell plug CP may be formed in the second chip area CHA2 of the second structure STR2. The cell plug CP may extend in the Z direction. The cell plug CP may penetrate the alternately stacked conductive layers CD and the interlayer insulating layers IIL. The cell plug CP may protrude further in the Z direction than the uppermost interlayer insulating layer IIL among the alternately stacked conductive layers CD and the interlayer insulating layers IIL. Although Figure 2, one cell plug CP is shown in the figure, but the second structure STR2 may include two or more cell plugs CP. Although not shown in the figure, the cell plug CP may include at least some of a blocking layer, a charge trapping layer formed along the inner wall of the blocking layer, a tunnel isolation layer formed along the inner wall of the charge trapping layer, a channel layer formed along the inner wall of the tunnel isolation layer, and a core column filling the inside of the channel layer.

[0032] The second structure STR2 may include a source layer SL on an alternately stacked conductive layer CD and an interlayer insulating layer IIL. The source layer SL may be formed on a second chip area CHA2 of the second structure STR2. The source layer SL may surround a portion of the cell plug CP that protrudes further than the interlayer insulating layer IIL in the Z direction. That is, the cell plug CP may protrude into the source layer SL. The source layer SL may be formed of doped silicon.

[0033] The second structure STR2 may include a fourth material layer ML4 under the alternately stacked conductive layers CD and the interlayer insulating layer IIL. The fourth material layer ML4 may overlap the third material layer ML3 of the first structure STR1. The fourth material layer ML4 may be formed as an insulating layer (eg, an oxide layer).

[0034] The second structure STR2 may include at least one second line L2 and at least one second plug P2 coupled to the cell plug CP. For example, the second line L2 may be a bit line. The at least one second line L2 and the at least one second plug P2 may be formed in the fourth material layer ML4. The second plug P2 may be electrically connected to the first plug P1. For example, the second plug P2 may directly contact the first plug P1, or the second plug may be indirectly coupled to the first plug through a separate path.

[0035] The second structure STR2 may not include a substrate. The second structure STR2 without a substrate will be referred to later. FIG. 5C to FIG. 5H describe.

[0036] Reference Figure 2 , the semiconductor device may include an alignment key AK. The alignment key AK may be disposed in a scribe area SLA of the semiconductor device. For example, the alignment key AK may be disposed in a scribe area SLA1 of the first structure STR1. The alignment key AK may be disposed in a first alignment key area AKA1 of the first scribe area SLA1. The alignment key AK may be adjacent to an upper surface of the first structure STR1. The alignment key AK may contact a second material layer ML2, and the second material layer ML2 is adjacent to a lower surface of the second structure STR2. The alignment key AK may be formed of a material different from that of the first material layer ML1. For example, the alignment key AK may include a metal material such as tungsten.

[0037] although Figure 2The alignment key AK is shown to be formed in the first scribe area SLA1 of the first structure STR1, but this is only exemplary and not limited thereto. For example, the alignment key AK may be formed in the second scribe area SLA2 instead of the first scribe area SLA1. In another embodiment, the first alignment key may be formed in the first scribe area SLA1, and the second alignment key may be formed in the second scribe area SLA2. Various embodiments of the alignment key AK formed in different positions will be referred to later. FIG. 3A to FIG. 3C describe.

[0038] The semiconductor device may include at least one first bonding pad BP1 disposed between the alignment key AK and the chip area CHA. The first bonding pad BP1 may be disposed in the first scribe area SLA1 of the first structure STR1. The first bonding pad BP1 may be disposed between the alignment key AK and the first chip area CHA1. The first bonding pad BP1 may be disposed in the first alignment key area AKA1 of the first scribe area SLA1. The first bonding pad BP1 may be spaced apart from the alignment key AK. The first bonding pad BP1 may be adjacent to the upper surface of the first structure STR1. The first structure STR1 may include one first bonding pad BP1 or two or more first bonding pads BP1. The first bonding pad BP1 may be formed of a material that is the same as or different from that of the alignment key AK. For example, the first bonding pad BP1 may be formed of a metal material such as copper (Cu).

[0039] The semiconductor device may include a second bonding pad BP2 contacting the first bonding pad BP1. The second bonding pad BP2 may be disposed in the second scribe area SLA2 of the second structure STR2. The second bonding pad BP2 may be disposed in the second alignment key area AKA2 of the second scribe area SLA2. The second bonding pad BP2 may be adjacent to the lower surface of the second structure STR2. The second bonding pad BP2 may overlap with the first bonding pad BP1. The second structure STR2 may include one second bonding pad BP2 or two or more second bonding pads BP2.

[0040] The second bonding pad BP2 may be formed of the same material as that of the first bonding pad BP1. For example, the second bonding pad BP2 may be formed of a metal material such as copper (Cu). Since the first bonding pad BP1 and the second bonding pad BP2 include the same material, the bonding force between the first bonding pad BP1 and the second bonding pad BP2 may be relatively high. For example, the bonding force between the first bonding pad BP1 and the second bonding pad BP2 including the same material may be higher than the bonding force between the alignment key AK and the second material layer ML2 including different materials. In another example, the bonding force between the first bonding pad BP1 and the second bonding pad BP2 formed of a metal material may be higher than the bonding force between the first material layer ML1 and the second material layer ML2 formed of an insulating layer.

[0041] The semiconductor device may include a third bonding pad BP3 disposed in a first chip area CHA1 of a first structure STR1. The third bonding pad BP3 may be adjacent to an upper surface of the first structure STR1. In addition, the semiconductor device may include a fourth bonding pad BP4 disposed in a second chip area CHA2 of a second structure STR2. The fourth bonding pad BP4 may be adjacent to a lower surface of the second structure STR2. The fourth bonding pad BP4 may contact the third bonding pad BP3.

[0042] The first bonding pad BP1 and the third bonding pad BP3 may be formed of the same material. For example, the first bonding pad BP1 and the third bonding pad BP3 may be formed at the same time. In addition, the second bonding pad BP2 and the fourth bonding pad BP4 may be formed of the same material. For example, the second bonding pad BP2 and the fourth bonding pad BP4 may be formed at the same time.

[0043] According to the present disclosure, since the semiconductor device includes the first bonding pads BP1 and the second bonding pads BP2 formed in the scribe areas SLA1 and SLA2 and the third bonding pads BP3 and the fourth bonding pads BP4 formed in the chip areas CHA1 and CHA2, the bonding force between the first structure STR1 and the second structure STR2 can be increased compared to the case where the first bonding pads BP1 and the second bonding pads BP2 are not included. Therefore, delamination occurring in the area where the alignment key AK is formed (e.g., the alignment key area AKA1 or AKA2) can be reduced.

[0044] FIG. 3A to FIG. 3C is a diagram illustrating an alignment key and a bonding pad according to an embodiment of the present disclosure. FIG. 3A to FIG. 3C Along the Figure 2 The cross section taken along the line BB' Figure 2 A diagram showing a cross section taken along line CC' and a state in which the cross section BB' and the cross section CC' are combined.

[0045] Reference Figure 3A , Figure 2 The alignment key AK may be bonding keys BK1 and BK2. The bonding keys BK1 and BK2 may be pattern structures formed to align the second structure STR2 on the first structure STR1. For example, in order to superimpose the second chip area CHA2 on the first chip area CHA1 and superimpose the second scribe area SLA2 on the first scribe area SLA1, the bonding keys BK1 and BK2 may be used.

[0046] When the alignment key AK is a bonding key BK1 or BK2, the first bonding key BK1 may be formed in a first alignment key area AKA1 of the first structure STR1, and the second bonding key BK2 may be formed in a second alignment key area AKA2 of the second structure STR2. The first bonding key BK1 may be adjacent to the upper surface of the first structure STR1, and the second bonding key BK2 may be adjacent to the lower surface of the second structure STR2. The first bonding key BK1 and the second bonding key BK2 may not overlap each other. For example, when the first structure STR1 and the second structure STR2 are connected to each other, the first bonding key BK1 and the second bonding key BK2 may be spaced apart from each other.

[0047] Reference Figure 3B and Figure 3C , Figure 2 The alignment key AK may be an overlay key OK. The overlay key OK may be a pattern structure formed in a photolithography step of a semiconductor integration process for alignment between a photomask and a first structure STR1 or between a photomask and a second structure STR2. For example, the overlay key OK may be used to form at least one of a cell plug, a contact plug, a bit line, and a slit insulating layer of a semiconductor chip. However, not limited thereto, the overlay key OK may be used to form various structures in a semiconductor chip.

[0048] When the alignment key AK is the superposition key OK, as Figure 3B As shown, the overlay key OK may be formed in the first alignment key area AKA1 of the first structure STR1, and the overlay key OK may not be formed in the second alignment key area AKA2 of the second structure STR2. Alternatively, when the alignment key AK is the overlay key OK, as shown in FIG. Figure 3C As shown, the superimposed key OK may not be formed in the first alignment key area AKA1 of the first structure STR1, and the superimposed key OK may be formed in the second alignment key area AKA2 of the second structure STR2. That is, the superimposed key OK may be formed in any one of the first alignment key area AKA1 and the second alignment key area AKA2 overlapping each other. For example, the superimposed key OK for forming the first structure STR1 (see Figure 3B ) and the superposition bond OK for forming the second structure STR2 (see Figure 3C) may be formed in a region where the second structure STR2 does not overlap with the first structure STR1 but is stacked thereon. Figure 3B The superimposed key OK may be adjacent to the upper surface of the first structure STR1. Figure 3C The superimposed key OK may be adjacent to the lower surface of the second structure STR2.

[0049] In the present disclosure, the alignment key (eg, Figure 3A The first bonding key BK1 and Figure 3B The superimposed key OK) may be referred to as a first alignment key. In addition, the alignment key (eg, Figure 3A The second bonding key BK2 and Figure 3C The superimposed key OK) may be referred to as the second alignment key. In the present disclosure, the cross-sectional shapes of the first alignment key and the second alignment key are not limited to FIG. 3A to FIG. 3C Those shown.

[0050] Reference FIG. 3A to FIG. 3C , at least one first bonding pad BP1 may be disposed at a first alignment key (eg, Figure 3A The first bonding key BK1 and Figure 3B The first bonding pad BP1 may be spaced apart from the first alignment key. The first bonding pad BP1 may be arranged in at least one direction relative to the first alignment key: the X direction, the Y direction, the opposite direction of the X direction, and the opposite direction of the Y direction. The first bonding pad BP1 may be adjacent to a boundary of the first alignment key area AKA1. The first bonding pad BP1 arranged in the first alignment key area AKA1 may be referred to as a first bonding pad group. The first bonding pad BP1 included in the first bonding pad group may surround the periphery of the first alignment key.

[0051] The second bonding pad BP2 may be formed at a position corresponding to the first bonding pad BP1. For example, while the second structure STR2 is stacked on the first structure STR1, the second bonding pad BP2 may be formed to overlap the first bonding pad BP1. At least one second bonding pad BP2 may be disposed at a second alignment key (e.g., Figure 3A The second bonding key BK2 and Figure 3CThe second bonding pad BP2 may be spaced apart from the second alignment key. The second bonding pad BP2 may be arranged in at least one direction relative to the second alignment key: the X direction, the Y direction, the opposite direction of the X direction, and the opposite direction of the Y direction. The second bonding pad BP2 may be adjacent to the boundary of the second alignment key area AKA2. The second bonding pad BP2 arranged in the second alignment key area AKA2 may be referred to as a second bonding pad group. The second bonding pad BP2 included in the second bonding pad group may be arranged along the boundary of the second alignment key.

[0052] According to the present disclosure, the bonding force between the first structure STR1 and the second structure STR2 may be increased by forming the first bonding pads BP1 and the second bonding pads BP2 in the first alignment key area AKA1 and the second alignment key area AKA2. Figure 2 and Figure 3A , since the first bonding key BK1 contacts the second material layer ML2, the second bonding key BK2 contacts the first material layer ML1, and the first bonding key BK1 and the second bonding key BK2 and the first material layer ML1 and the second material layer ML2 are formed of different materials, the bonding force at the heterojunction surface may be weak. In addition, referring to Figure 2 and Figure 3B , since the stacking bond OK contacts the second material layer ML2 and the stacking bond OK and the second material layer ML2 are formed of different materials, the bonding force at the heterojunction surface may be weak. In the present disclosure, the heterojunction surface may refer to an interface between material layers including different materials. However, since the semiconductor device of the present disclosure includes a first bonding pad BP1 and a second bonding pad BP2 formed of the same material (e.g., metal), the cross-sectional area of ​​the isojunction surface may increase, thereby increasing the bonding force between the first structure STR1 and the second structure STR2. In the present disclosure, the isojunction surface may refer to an interface between material layers including the same material.

[0053] According to the present disclosure, the dishing phenomenon occurring in the first alignment key area AKA1 and the second alignment key area AKA2 during the CMP process can be prevented or reduced by the first bonding pad BP1 and the second bonding pad BP2. That is, the step between the bonding surfaces of the first structure STR1 and the second structure STR2 can be removed or reduced by the first bonding pad BP1 and the second bonding pad BP2. Therefore, the first bonding pad BP1 and the second bonding pad BP2 can further increase the bonding force between the first structure STR1 and the second structure STR2.

[0054] Reference FIG. 3A to FIG. 3C, each of the first bonding pad BP1 and the second bonding pad BP2 may have a square cross-sectional shape. In addition, the first bonding pad BP1 and the second bonding pad BP2 may be aligned along the boundaries of the first alignment key area AKA1 and the second alignment key area AKA2, respectively. However, the cross-sectional shapes and arrangement methods of the first bonding pad BP1 and the second bonding pad BP2 are not limited to FIG. 3A to FIG. 3C Those shown. FIG. 4A to FIG. 4E Various embodiments of the cross-sectional shapes and arrangement methods of the first bonding pad BP1 and the second bonding pad BP2 are shown.

[0055] FIG. 4A to FIG. 4E are diagrams showing bonding pads of various shapes according to an embodiment of the present disclosure.

[0056] FIG. 4A to FIG. 4E The first alignment key AK1 and the first bonding pad BP1 formed in the first alignment key area AKA1 are shown. Since the second bonding pad BP2 of the second alignment key area AKA2 is formed to correspond to the first bonding pad BP1, FIG. 4A to FIG. 4E The second alignment key area AKA2 is omitted. FIG. 4A to FIG. 4E Show Figure 3B The superimposed key OK is used as an example of the first alignment key AK1, but it can be replaced by Figure 3A or Figure 3C Another alignment key is shown. FIG. 4A to FIG. 4E Various cross-sectional shapes and arrangement methods of the first bonding pad BP1 are described.

[0057] Reference Figure 4A , each first bonding pad BP1 may have a rectangular cross-section, wherein the length in the X direction is longer than the length in the Y direction. Figure 4A The X-direction length of each first bonding pad BP1 in FIG. 3A to FIG. 3C The X-direction lengths of the first bonding pads BP1 in the embodiment are the same. Figure 4A The Y-direction length of each first bonding pad BP1 in FIG. 3A to FIG. 3C 1 / 2 of the Y-direction length of each first bonding pad BP1. Figure 4A The number of the first bonding pads BP1 in may be FIG. 3A to FIG. 3C The number of the first bonding pads BP1 in FIG. Figure 4A The first bonding pads BP1 may be arranged in a row along boundaries (ie, left and right surfaces) of the first alignment key area AKA1 in the X direction, and may be doubly arranged along boundaries (ie, upper and lower surfaces) of the first alignment key area AKA1 in the Y direction.

[0058] Reference Figure 4B, some of the first bonding pads BP1 may have a rectangular cross-section whose length in the X direction is longer than that in the Y direction, and other first bonding pads BP1 may have a rectangular cross-section whose length in the Y direction is longer than that in the X direction. Figure 4B The length of the long side of each first bonding pad BP1 in FIG. 3A to FIG. 3C The length of the long side of each first bonding pad BP1 in Figure 4B The length of the short side of each first bonding pad BP1 in FIG. 3A to FIG. 3C The lengths of the short sides of the first bonding pads BP1 are the same. Figure 4B The number of the first bonding pads BP1 in the FIG. 3A to FIG. 3C In addition, Figure 4B The first bonding pads BP1 may be arranged in a row along a boundary of the first alignment key area AKA1.

[0059] Reference Figure 4C , some of the first bonding pads BP1 may have a rectangular cross-section whose length in the X direction is longer than that in the Y direction, and other first bonding pads BP1 may have a rectangular cross-section whose length in the Y direction is longer than that in the X direction. Figure 4C The length of the long side of each first bonding pad BP1 in FIG. 3A to FIG. 3C The length of the long side of each first bonding pad BP1 in Figure 4C The length of the short side of each first bonding pad BP1 in FIG. 3A to FIG. 3C The length of the short side of each first bonding pad BP1 in Figure 4C The number of the first bonding pads BP1 in may be Figure 4B The number of the first bonding pads BP1 in is approximately twice as large as that in FIG. Figure 4C The first bonding pads BP1 in FIG. 5 may be doubly arranged along a boundary of the first alignment key area AKA1 .

[0060] Reference Figure 4D , some of the first bonding pads BP1 may have a rectangular cross-section whose length in the X direction is longer than that in the Y direction, and other first bonding pads BP1 may have a rectangular cross-section whose length in the Y direction is longer than that in the X direction. Figure 4D The length of the long side of each first bonding pad BP1 in Figure 4B The length of the long side of each first bonding pad BP1 in Figure 4D The number of the first bonding pads BP1 in the Figure 4B In addition, Figure 4D The first bonding pads BP1 may be arranged along the boundaries of the first alignment key area AKA1 in various directions.

[0061] Reference Figure 4E , some of the first bonding pads BP1 may have a rectangular cross-section whose length in the X direction is longer than that in the Y direction, and other first bonding pads BP1 may have a rectangular cross-section whose length in the Y direction is longer than that in the X direction. Figure 4E The length of the long side of each first bonding pad BP1 in Figure 4D The lengths of the long sides of the first bonding pads BP1 are the same, Figure 4E The length of the short side of each first bonding pad BP1 in Figure 4D The length of the short side of each first bonding pad BP1 in Figure 4E The number of the first bonding pads BP1 in the Figure 4C In addition, Figure 4E The first bonding pads BP1 in FIG. 1 may be doubly arranged along the boundary of the first alignment key area AKA1 in various directions.

[0062] FIG. 4A to FIG. 4E The cross-sectional shape, number, and arrangement method of the first bonding pads BP1 shown are some of the various embodiments of the present disclosure, and in addition to FIG. 4A to FIG. 4E In addition to the illustrated embodiment, the first bonding pad BP1 may be formed in various ways.

[0063] FIG. 5A to FIG. 5H 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 5A to FIG. 5H Each can correspond to Figure 2 A cross section taken along line AA'.

[0064] Reference Figure 5A , the first structure STR1 may include a first scribe area SLA1 and a first chip area CHA1. The first structure STR1 may include a first substrate SST1. In the first scribe area SLA1 of the first structure STR1, a first material layer ML1 may be formed on the first substrate SST1. In the first chip area CHA1 of the first structure STR1, a third material layer ML3 may be formed on the first substrate SST1. The first material layer ML1 and the third material layer ML3 may be formed simultaneously, or may be formed by separate processes.

[0065] At least one transistor TR, at least one first line L1, and at least one first plug P1 may be formed in the first chip area CHA1 of the first structure STR1. At least one first line L1 and at least one first plug P1 may be formed in the third material layer ML3.

[0066] Reference Figure 5B, the first alignment key AK1 may be formed in the first scribe area SLA1 of the first structure STR1. For example, the first alignment key AK1 may be formed in the first alignment key area AKA1 of the first scribe area SLA1. The first alignment key AK1 may be Figure 3A The first bonding key BK1.

[0067] At least one first bonding pad BP1 may be formed between the first alignment key AK1 and the first chip area CHA1. The first bonding pad BP1 may be adjacent to the upper surface of the first structure STR1. The first bonding pad BP1 may be formed in the first scribe area SLA1 of the first structure STR1. For example, a portion of the upper surface of the first material layer ML1 may be etched to form a groove, and the inside of the groove may be filled with a metal layer to form the first bonding pad BP1. An anisotropic dry etching process may be performed to form a groove at a designated position on the first material layer ML1.

[0068] A third bonding pad BP3 may be formed in the first chip area CHA1 of the first structure STR1. The third bonding pad BP3 may be adjacent to the upper surface of the first structure STR1. For example, a portion of the upper surface of the third material layer ML3 may be etched to form a groove, and the inside of the groove may be filled with a metal layer to form the third bonding pad BP3.

[0069] In an embodiment, the first bonding pad BP1 and the third bonding pad BP3 may be formed at the same time. In an embodiment, the first bonding pad BP1 and the third bonding pad BP3 may be formed by different processes.

[0070] Reference Figure 5C , the second structure STR2 may include a second scribe line area SLA2 and a second chip area CHA2. Figure 5C In the second structure STR2, the second chip region CHA2 of the second structure STR2 may include a second substrate SST2. In the second chip region CHA2 of the second structure STR2, a conductive layer CD, an interlayer insulating layer IIL, and a cell plug CP may be formed on the second substrate SST2. For example, the interlayer insulating layer IIL and a sacrificial layer (not shown) may be alternately stacked on the second substrate SST2, the cell plug CP may be formed to penetrate the interlayer insulating layer IIL and the sacrificial layer, and the sacrificial layer may be replaced with the conductive layer CD. The cell plug CP may protrude into the second substrate SST2.

[0071] In the second scribe area SLA2 of the second structure STR2, a second material layer ML2a may be formed on the second substrate SST2. The second material layer ML2a may be formed as a single layer (e.g., an insulating layer) including alternately stacked interlayer insulating layers IIL and conductive layers CD, or alternately stacked interlayer insulating layers IIL and sacrificial layers.

[0072] Reference Figure 5D , a fourth material layer ML4 may be formed in the second chip area CHA2 of the second structure STR2. The fourth material layer ML4 may be formed on the alternately stacked conductive layers CD and the interlayer insulating layers IIL. In addition, at least one second wire L2 and at least one second plug P2 may be formed in the fourth material layer ML4. The second wire L2 may be electrically connected to the cell plug CP.

[0073] In addition, a second material layer ML2b may be formed in the second scribe line region SLA2 of the second structure STR2. Figure 5C A material layer identical to the fourth material layer ML4 is formed on the second material layer ML2a to form Figure 5D As another example, in Figure 5C A material layer different from the fourth material layer ML4 is formed on the second material layer ML2a, thereby forming Figure 5D The second material layer ML2b.

[0074] Reference Figure 5E , the second alignment key AK2 may be formed in the second scribe area SLA2 of the second structure STR2. For example, the second alignment key AK2 may be formed in the second alignment key area AKA2 of the second scribe area SLA2. The second alignment key AK2 may be Figure 3A The second bonding key BK2.

[0075] The second bonding pad BP2 may be formed in the second scribe lane area SLA2 of the second structure STR2. Figure 5E , at least one second bonding pad BP2 may be formed between the second alignment key AK2 and the second chip area CHA2. The second bonding pad BP2 may be adjacent to the upper surface of the second structure STR2. For example, a portion of the upper surface of the second material layer ML2b may be etched to form a groove, and the inside of the groove may be filled with a metal layer to form the second bonding pad BP2. An anisotropic dry etching process may be performed to form a groove at a designated position on the second material layer ML2b.

[0076] A fourth bonding pad BP4 may be formed in the second chip area CHA2 of the second structure STR2. The fourth bonding pad BP4 may be adjacent to the upper surface of the second structure STR2. For example, a portion of the upper surface of the fourth material layer ML4 may be etched to form a groove, and the inside of the groove may be filled with a metal layer to form the fourth bonding pad BP4.

[0077] In an embodiment, the second bonding pad BP2 and the fourth bonding pad BP4 may be formed at the same time. In another embodiment, the second bonding pad BP2 and the fourth bonding pad BP4 may be formed by different processes.

[0078] Reference Fig. 5F , the second structure STR2 may be flipped over so that the second bonding pad BP2 is adjacent to the lower surface of the second structure STR2. The flipped second structure STR2 may be stacked on the first structure STR1. For example, the second structure STR2 may be stacked on the first structure STR1 so that the second bonding pad BP2 contacts the first bonding pad BP1, respectively, and the fourth bonding pad BP4 contacts the third bonding pad BP3.

[0079] When the flipped second structure STR2 is stacked on the first structure STR1, the first bonding pads BP1 may overlap the second bonding pads BP2, respectively. In addition, when the flipped second structure STR2 is stacked on the first structure STR1, the fourth bonding pads BP4 may overlap the third bonding pads BP3.

[0080] In addition, when the reversed second structure STR2 is stacked on the first structure STR1, the second alignment key AK2 may not overlap the first alignment key AK1. The first alignment key AK1 may contact the second material layer ML2b, and the second alignment key AK2 may contact the first material layer ML1.

[0081] Reference Figure 5G , the second substrate SST2 of the second structure STR2 may be removed. After the second substrate SST2 is removed, a portion of the cell plug CP may be exposed. In addition, a portion of the exposed cell plug CP may be etched. For example, the blocking layer, the charge trapping layer, and the tunnel isolation layer of the exposed portion of the cell plug CP may be removed. Therefore, some areas of the channel layer of the cell plug CP may be exposed to the outside.

[0082] Reference Figure 5H , can be in the chip area CHA (for example, Figure 5E A source layer SL is formed in the second cell region CHA2 of the second structure STR2. The source layer SL may be formed to surround the exposed cell plug CP. For example, the source layer SL may contact the exposed channel layer.

[0083] In addition, in the second scribe area SLA2 (for example, Figure 5E The second material layer ML2c is formed in the second scribe line area SLA2 of the second structure STR2. Figure 5G A material layer of the same material as the source layer SL is formed on the second material layer ML2b to form Figure 5H In another embodiment, the second material layer ML2c may be Figure 5G A material layer different from the source layer SL is formed on the second material layer ML2b, thereby forming Figure 5H The second material layer ML2c.

[0084] Reference FIG. 5A to FIG. 5H ,although Figure 2 The alignment key AK is shown as Figure 3A The first bonding key BK1 and the second bonding key BK2 in FIG. 1 are for convenience of explanation only and are not limited thereto. For example, when Figure 2 The alignment key AK is Figure 3B When the overlay key is OK, you can FIG. 5A to FIG. 5H In another embodiment, when the second alignment key AK2 is omitted Figure 2 The alignment key AK is Figure 3C When the overlay key is OK, you can FIG. 5A to FIG. 5H The first alignment key AK1 is omitted.

[0085] According to the present disclosure, the first bonding pad BP1 may be simultaneously formed in the first scribe area SLA1 during the process of forming the third bonding pad BP3 in the first chip area CHA1. In addition, the second bonding pad BP2 may be simultaneously formed in the second scribe area SLA2 during the process of forming the fourth bonding pad BP4 in the second chip area CHA2. That is, the process of forming the first bonding pad BP1 and the second bonding pad BP2 does not increase the manufacturing time. Therefore, even if the first bonding pad BP1 and the second bonding pad BP2 are added in the present disclosure, the cost or time does not increase during the process of manufacturing the semiconductor device.

[0086] Figure 6 is a diagram showing a memory card system to which the semiconductor device of the present disclosure is applied.

[0087] Reference Figure 6 , the memory card system 3000 may include a controller 3100 , a memory device 3200 , and a connector 3300 .

[0088] The controller 3100 may be connected to the memory device 3200. The controller 3100 may access the memory device 3200. For example, the controller 3100 may control a program operation, a read operation, or an erase operation of the memory device 3200, or may control a background operation. The controller 3100 may provide an interface between the memory device 3200 and a host. The controller 3100 may run firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0089] The controller 3100 may communicate with an external device through the connector 3300. The controller 3100 may communicate with an external device (e.g., a host) based on a specific communication standard. For example, the controller 3100 may communicate with an external device through at least one of the following various communication standards: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Memory (UFS), WiFi, Bluetooth, High-Speed ​​Non-Volatile Memory (NVMe), etc. For example, the connector 3300 may be defined by at least one of the above communication standards.

[0090] The memory device 3200 may include a plurality of memory cells, and may correspond to a semiconductor device according to the present disclosure.

[0091] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to form a memory card such as a PC card (Personal Computer Memory Card International Association: PCMCIA), a Compact Flash card (CF), a Smart Media Card (SM, SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro, eMMC), an SD card (SD, miniSD, microSD, SDHC), or a Universal Flash Storage (UFS).

[0092] Figure 7 is a diagram showing a solid state drive (SSD) system to which the semiconductor device of the present disclosure is applied.

[0093] Reference Figure 7 , the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 through a signal connector 4001, and may receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0094] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. For example, the signal may indicate a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), WiFi, Bluetooth, Non-Volatile Memory Express (NVMe), etc.

[0095] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n may correspond to a semiconductor device according to the present disclosure. The plurality of memory devices 4221 to 422n may communicate with the controller 4210 through channels CH1 to CHn.

[0096] The auxiliary power supply 4230 may be connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may receive a power supply voltage from the host 4100 and may perform a charging operation. When power is not smoothly supplied from the host 4100, the auxiliary power supply 4230 may provide a power supply voltage for the SSD 4200. For example, the auxiliary power supply 4230 may be located inside the SSD 4200 or outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on a mainboard and may supply auxiliary power to the SSD 4200.

[0097] The buffer memory 4240 may operate as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or may temporarily store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, or LPDDR SDRAM, or may include a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, or PRAM.

[0098] According to the present disclosure, bonding force during wafer bonding may be increased by bonding pads formed in scribe line regions.

[0099] CROSS-REFERENCE TO RELATED APPLICATIONS

[0100] This application claims the priority of Korean Patent Application No. 10-2023-0114378 filed on August 30, 2023 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, comprising: A first structure, the first structure comprising a first chip region and a first scribe lane region; a second structure, the second structure being disposed on the first structure; A first alignment key, the first alignment key is arranged in the first scribe line area; at least one first bonding pad, the at least one first bonding pad being disposed in the first scribe lane region, disposed between the first alignment key and the first chip region, the first bonding pad being adjacent to an upper surface of the first structure; as well as At least one second bonding pad is adjacent to the lower surface of the second structure to contact the at least one first bonding pad.

2. The semiconductor device according to claim 1, in, The second structure includes a second chip region and a second scribe lane region, and Wherein, the at least one second bonding pad is arranged in the second scribe line region.

3. The semiconductor device according to claim 2, further comprising: A second alignment key is disposed in the second scribe line region and does not overlap with the first alignment key.

4. The semiconductor device according to claim 3, in, The first alignment key abuts an upper surface of the first structure, and Wherein, the second alignment key is adjacent to the lower surface of the second structure.

5. The semiconductor device according to claim 1, wherein The at least one first bonding pad is spaced apart from the first alignment key.

6. The semiconductor device according to claim 1, wherein The at least one first bonding pad is disposed in at least one direction relative to the first alignment key, the at least one direction comprising a first direction, a second direction crossing the first direction, a direction opposite to the first direction, or a direction opposite to the second direction.

7. The semiconductor device according to claim 1, in, The first alignment key is disposed in a first alignment key region of the first scribe lane region, and The at least one first bonding pad is adjacent to a boundary of the first alignment key area.

8. The semiconductor device according to claim 1, further comprising: a first bonding pad group, the first bonding pad group including the at least one first bonding pad; as well as A second bonding pad group includes the at least one second bonding pad.

9. The semiconductor device according to claim 8, wherein: The at least one first bonding pad group is disposed along a boundary of the first alignment key.

10. The semiconductor device according to claim 1, wherein The at least one first bonding pad and the at least one second bonding pad overlap each other.

11. The semiconductor device according to claim 1, wherein The at least one first bonding pad and the at least one second bonding pad include a same material.

12. The semiconductor device according to claim 1, wherein The at least one first bonding pad and the at least one second bonding pad include different materials.

13. The semiconductor device according to claim 1, wherein The first alignment key is a bonding key or an overlay key.

14. The semiconductor device according to claim 2, further comprising: a third bonding pad, the third bonding pad being disposed in the first chip region, the third bonding pad being adjacent to an upper surface of the first structure; as well as A fourth bonding pad is disposed in the second chip region, the fourth bonding pad being adjacent to a lower surface of the second structure to contact the third bonding pad.

15. The semiconductor device according to claim 14, wherein: The first to fourth bonding pads include the same material.

16. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a first alignment key in the first scribe lane region of a first structure defining a first scribe lane region and a first chip region; forming at least one first bonding pad disposed between the first alignment key and the first chip region, the at least one first bonding pad being adjacent to an upper surface of the first structure; forming at least one second bonding pad adjacent to an upper surface of the second structure, the at least one second bonding pad being formed in the second scribe area of ​​the second structure defining a second scribe area and a second chip area; as well as The second structure is flipped over so that the at least one second bonding pad abuts against a lower surface of the second structure, and the second structure is stacked on the first structure so that the at least one second bonding pad of the flipped second structure contacts the at least one first bonding pad.

17. The method according to claim 16, further comprising the steps of: Before forming the at least one second bonding pad, a second alignment key is formed in the second scribe lane region.

18. The method according to claim 17, wherein: When the second alignment key is formed, the second alignment key does not overlap with the first alignment key.

19. The method according to claim 16, further comprising the steps of: forming a third bonding pad in the first chip region adjacent to an upper surface of the first structure; as well as Before the second structure is flipped over, a fourth bonding pad is formed in the second chip region adjacent to the upper surface of the second structure.

20. The method according to claim 19, wherein: The step of forming the at least one first bonding pad and the step of forming the third bonding pad are performed simultaneously.

21. The method according to claim 19, wherein: The step of forming the at least one second bonding pad and the step of forming the fourth bonding pad are performed simultaneously.

22. The method according to claim 19, wherein: The step of laminating the second structure on the first structure comprises the following steps: The second structure is stacked on the first structure such that the fourth bonding pad of the flipped second structure contacts the third bonding pad of the first structure.

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