Semiconductor structure, manufacturing method thereof and semiconductor device

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof and a semiconductor device, and the semiconductor structure comprises an interposer which is internally provided with a hole groove and a groove which extend from the top surface of the interposer to the interior of the interposer; the capacitor is located in the hole groove and the groove, the capacitor comprises a first electrode layer, a capacitor dielectric layer and a second electrode layer which are stacked in sequence, the capacitor dielectric layer covers the surface of the first electrode layer, and the second electrode layer covers the surface of the capacitor dielectric layer; wherein the groove extends along a preset direction parallel to the top surface of the interposer and is communicated with a plurality of hole grooves which are arranged at intervals along the preset direction, the width size of the hole grooves is larger than that of the groove, and the direction of the width size is parallel to the top surface of the interposer and is perpendicular to the preset direction. The semiconductor structure has the advantages of large capacity, fast charging and discharging, and high integration level, and the arrangement mode of the semiconductor structure can well solve the stress problem.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof, and a semiconductor device. Background Art

[0002] In order to improve the integration of semiconductor structures, many chips can be stacked and welded together, such as 3-Dimensional Stack (3DS) memories such as High Bandwidth Memory (HBM). In this way, the original 2D layout can be expanded to 2.5D (between 2D and 3D packaging) or 3D, thereby greatly improving the density of the chip. In the field of advanced packaging technology, especially in 2.5D and 3D packaging technology, interposer packaging is widely used, that is, multiple chips (Die) are arranged on a substrate through an interposer device, and different chips can receive signals from other chips or transmit signals to other chips through the interposer device, thereby improving the overall signal density of the package and achieving the advantage of reducing the overall volume at the same time.

[0003] In order to maintain signal stability in interposer devices, a deep trench capacitor (DTC) structure is usually used to prevent signal lines from interfering with each other. However, the structural design of the deep trench capacitor structure in the prior art has obvious limitations, and the performance still needs to be further enhanced. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising: an interposer, wherein the interposer has holes and grooves extending from the top surface of the interposer toward the inside of the interposer; a capacitor located in the holes and grooves, wherein the capacitor comprises a first electrode layer, a capacitor dielectric layer and a second electrode layer stacked in sequence, wherein the capacitor dielectric layer covers the surface of the first electrode layer, and the second electrode layer covers the surface of the capacitor dielectric layer; wherein the grooves also extend along a preset direction parallel to the top surface of the interposer and connect a plurality of holes arranged at intervals along the preset direction, wherein the width dimension of the holes is greater than the width dimension of the grooves, and the direction of the width dimension is parallel to the top surface of the interposer and perpendicular to the preset direction.

[0005] In some embodiments, the semiconductor structure further includes: a lead-out contact layer located in the hole groove, covering a surface of the second electrode layer located in the hole groove and filling the hole groove.

[0006] In some embodiments, the material of the lead-out contact layer includes copper.

[0007] In some embodiments, the semiconductor structure further includes: a first contact and a second contact located above the capacitor, the first contact connected to the lead-out contact layer, and the second contact connected to the first electrode layer.

[0008] In some embodiments, the hole grooves and the lead-out contact layers, and the lead-out contact layers and the first contact members all correspond one to one.

[0009] In some embodiments, the intermediate layer includes a plurality of the grooves, and a plurality of the holes connected to adjacent grooves are arranged in a staggered manner along a direction perpendicular to the preset direction.

[0010] In some embodiments, the intermediate layer further includes a first region and a second region adjacent to each other, in the first region, the preset direction is a first direction, and in the second region, the preset direction is a second direction, and the first direction and the second direction are perpendicular to each other.

[0011] In some embodiments, in the first region, a plurality of the grooves extend along the first direction and are arranged at intervals along the second direction; and in the second region, a plurality of the grooves extend along the second direction and are arranged at intervals along the first direction.

[0012] In some embodiments, the semiconductor structure further includes: a bottom dielectric layer, covering at least the bottom and sidewalls of the hole and the groove, the bottom dielectric layer is located between the intermediate layer and the first electrode layer, and the first electrode layer covers the surface of the bottom dielectric layer.

[0013] According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing an interposer; forming holes and grooves in the interposer extending from the top surface of the interposer toward the inside of the interposer; forming a capacitor composed of a first electrode layer, a capacitor dielectric layer and a second electrode layer stacked in sequence in the holes and grooves, the capacitor dielectric layer covering the surface of the first electrode layer, and the second electrode layer covering the surface of the capacitor dielectric layer; wherein the grooves also extend along a preset direction parallel to the top surface of the interposer and connect a plurality of holes arranged at intervals along the preset direction, the width dimension of the holes is greater than the width dimension of the grooves, and the direction of the width dimension is parallel to the top surface of the interposer and perpendicular to the preset direction.

[0014] In some embodiments, the method for manufacturing the semiconductor structure further includes: forming a lead-out contact layer in the hole groove, covering a surface of the second electrode layer in the hole groove and filling the hole groove.

[0015] In some embodiments, the method for manufacturing the semiconductor structure also includes: forming a first contact and a second contact above the capacitor, the first contact connected to the lead-out contact layer, and the second contact connected to the first electrode layer; wherein the hole groove and the lead-out contact layer, and the lead-out contact layer and the first contact all correspond one-to-one.

[0016] In some embodiments, the intermediary layer also includes a first area and a second area that are adjacent to each other, in the first area, the preset direction is a first direction, and in the second area, the preset direction is a second direction, and the first direction and the second direction are perpendicular to each other; holes and grooves extending from the top surface of the intermediary layer toward the inside of the intermediary layer are formed in the intermediary layer, including: forming a plurality of grooves extending along the first direction and arranged at intervals along the second direction in the first area, forming a plurality of grooves extending along the second direction and arranged at intervals along the first direction in the second area, and a plurality of holes and grooves connected by adjacent grooves are staggered in a direction perpendicular to the preset direction.

[0017] In some embodiments, before forming the capacitor in the hole and the groove, the method for manufacturing the semiconductor structure also includes: forming a bottom dielectric layer in the hole and the groove, covering at least the bottom and side walls of the hole and the groove; the bottom dielectric layer is located between the intermediate layer and the first electrode layer formed subsequently, and the first electrode layer covers the surface of the bottom dielectric layer.

[0018] According to a third aspect of an embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor structure as described in any one of the aforementioned embodiments; a chip located on the semiconductor structure; wherein the chip and the semiconductor structure are electrically connected via solder ball bumps and / or solder pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram showing providing an intermediary layer according to an exemplary embodiment;

[0020] Figure 2 is a schematic diagram showing the formation of holes and grooves according to an exemplary embodiment;

[0021] Figure 3 is a schematic diagram showing the formation of holes and grooves according to another exemplary embodiment;

[0022] Figure 4 is a schematic diagram showing the formation of a bottom dielectric layer according to an exemplary embodiment;

[0023] Figure 5 is a schematic diagram showing the formation of a capacitor according to an exemplary embodiment;

[0024] Figure 6 is a schematic diagram showing the formation of a lead-out contact layer and first and second contacts according to an exemplary embodiment;

[0025] Figure 7 is a schematic diagram showing the formation of a lead-out contact layer and first and second contacts according to another exemplary embodiment;

[0026] Figure 8 is a schematic diagram showing an arrangement of a semiconductor structure according to an exemplary embodiment;

[0027] Fig. 9 is a schematic diagram of a semiconductor device according to an exemplary embodiment. DETAILED DESCRIPTION

[0028] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0029] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0030] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0031] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0032] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0033] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0034] In the related art, the DTC structure is basically a deep hole, and is usually made simultaneously by making a through silicon via (TSV) process in an interposer. The inventor of the present application found that with the development of 2.5D packaging technology, the device size is further miniaturized, the DTC structure capacitor area is reduced, and it is increasingly difficult to achieve an increase in capacitor density, accompanied by increasingly serious stress during the support process. It is becoming increasingly important to seek a new DTC structure design solution.

[0035] In view of the above technical problems, the present disclosure provides a semiconductor structure and a method for manufacturing the same, and a semiconductor device. Figures 1 to 9 A semiconductor structure, a method for preparing the semiconductor structure, and a semiconductor device exemplarily provided by the present disclosure are specifically introduced. Figures 1 to 7 is a schematic diagram of a method for preparing a semiconductor structure according to multiple exemplary embodiments of the present disclosure. Figure 8 FIG. 1 is a schematic diagram showing an arrangement of a semiconductor structure according to an exemplary embodiment of the present disclosure. Fig. 9 FIG. 1 is a schematic diagram of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0036] In an exemplary embodiment of the present disclosure, a semiconductor structure is provided, referring to Figure 6 or Figure 7 As shown, Figure 6 (a) or Figure 7 (a) is a top view showing the top surface of the interposer 1 in the reverse direction along the Z direction, Figure 6 (b) or Figure 7 (b) along Figure 6 (a) or Figure 7 (a) is a schematic cross-sectional view along the A-A' direction. Figure 6 (c) or Figure 7 (c) along Figure 6 (a) or Figure 7 (a) is a schematic cross-sectional view along the B-B' direction. Figure 6 (d) or Figure 7 (d) is along Figure 6 (a) or Figure 7 (a) is a schematic cross-sectional view along the C-C' direction. Figure 6 (e) or Figure 7 (e) is along Figure 6 (b) or Figure 7(b) is a cross-sectional schematic diagram along the D-D' direction. The semiconductor structure includes: an interposer 1, wherein the interposer 1 has a hole 21 and a groove 22 extending from the top surface of the interposer 1 toward the inside of the interposer 1; a capacitor 4, which is located in the hole 21 and the groove 22, and the capacitor 4 includes a first electrode layer 41, a capacitor dielectric layer 42 and a second electrode layer 43 stacked in sequence, wherein the capacitor dielectric layer 42 covers the surface of the first electrode layer 41, and the second electrode layer 43 covers the surface of the capacitor dielectric layer 42; wherein the groove 22 also extends along a preset direction parallel to the top surface of the interposer 1 and connects a plurality of hole grooves 21 arranged at intervals along the preset direction, and the width dimension of the hole groove 21 is greater than the width dimension of the groove 22, and the direction of the width dimension is parallel to the top surface of the interposer 1 and perpendicular to the preset direction. It should be noted that in an exemplary embodiment of the present disclosure, the preset direction is in the same direction or opposite direction to the X direction, and the direction of the width dimension is in the same direction or opposite direction to the Y direction. It should be noted that the X direction, the Y direction, and the Z direction in all the drawings of the specification in the present disclosure are perpendicular to each other.

[0037] In an exemplary embodiment of the present disclosure, the interposer 1 adopts a silicon interposer. The material of the silicon interposer can be at least one of the following materials: silicon, germanium, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI) and other semiconductor materials or a combination of III-V materials and organic materials.

[0038] The holes 21 and the grooves 22 are located in the interposer 1, extending from the top surface of the interposer 1 toward the inside of the interposer 1, that is, the openings of the holes 21 and the grooves 22 are on the top surface of the interposer 1, and the depth direction of the holes 21 and the grooves 22 is perpendicular to the plane where the top surface of the interposer 1 is located and is toward the inside of the interposer 1, which is opposite to the Z direction in the figure. On the plane parallel to the top surface of the interposer 1, the grooves 22 extend along a preset direction, and the holes 21 are arranged at intervals along the preset direction, which can be referred to Figure 6 As shown by the dotted line in (a) or 7(a), the groove 22 extends along the X direction or its reverse direction, and connects a plurality of holes 21 arranged at intervals along the X direction or its reverse direction. Figure 6As shown in (b) to 6(d) or 7(b) to 7(d), the cross-sectional schematic diagram of the hole 21 and / or groove 22 along the depth direction is rectangular, that is, the opening size of the hole 21 and / or groove 22 is substantially consistent with the bottom size. In other embodiments, the cross-sectional schematic diagram of the hole 21 and / or groove 22 is a trapezoid, for example, the opening size of the hole 21 and / or groove 22 is larger than the bottom size, or the bottom size of the hole 21 and / or groove 22 is larger than the opening size. In other embodiments, the bottom of the hole 21 and / or groove 22 is an arc-shaped concave toward the inside of the intermediary layer 1. In some embodiments, the width dimension of the hole 21 is larger than the width dimension of the groove 22, wherein the direction of the width dimension is parallel to the top surface of the intermediary layer 1 and perpendicular to the preset direction in the aforementioned embodiment, that is, the direction of the width dimension is in the same direction or opposite to the Y direction.

[0039] The capacitor 4 is located in the hole 21 and the groove 22, and includes a first electrode layer 41, a capacitor dielectric layer 42 and a second electrode layer 43 stacked in sequence, wherein the capacitor dielectric layer 42 covers the surface of the first electrode layer 41, and the second electrode layer 43 covers the surface of the capacitor dielectric layer 42. In some embodiments, specifically, as Figure 6 As shown in FIGS. 6(b) to 6(e) or 7(b) to 7(e), a plurality of slots 21 arranged in an interval along the X direction or in the reverse direction and connected by the same slot 22 and the capacitor 4 in the slot 22 are connected as a whole. In other embodiments, the capacitor 4 further includes one or more other electrode layers (not shown) in addition to the first electrode layer 41 and the second electrode layer 43, and adjacent electrode layers are separated by a capacitor dielectric layer 42 or an additional capacitor dielectric layer (not shown).

[0040] In some embodiments, the material of the first electrode layer 41 and / or the second electrode layer 43 may be a combination of at least one or more of doped silicon, titanium nitride (TiN), silicon-doped titanium nitride (TiSiN), titanium (Ti), tungsten (W), tungsten nitride (WN), and silicon-doped tungsten nitride (WSiN), and the material of the capacitor dielectric layer 42 may be a combination of at least one or more of silicon oxide (SiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), and lead titanate (PZT). In an exemplary embodiment of the present disclosure, the material of the first electrode layer 41 and / or the second electrode layer 43 is titanium nitride, and the material of the capacitor dielectric layer 42 is a high dielectric constant (high-K) material.

[0041] In some embodiments, the semiconductor structure further includes: an extraction contact layer 5, which is located in the hole groove 21, covers the surface of the second electrode layer 43 located in the hole groove 21 and fills the hole groove 21. Specifically, the extraction contact layer 5 is inserted into the hole groove 21 in a cylindrical shape, filling the remaining space in the hole groove 21 except the capacitor 4, and the extraction contact layer 5 is only located in the hole groove 21 and shares a central axis with the hole groove 21, and the hole groove 21 corresponds to the extraction contact layer 5 one by one. In some embodiments, the material of the extraction contact layer 5 can be a combination of one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), platinum (Pt), copper (Cu) and / or their nitrides. In an exemplary embodiment of the present disclosure, the material of the extraction contact layer 5 is copper.

[0042] In some embodiments, the semiconductor structure further includes: a first contact 61 and a second contact 62 located above the capacitor 4, the first contact 61 is connected to the lead contact layer 5, the second contact 62 is connected to the first electrode layer 41, and the lead contact layer 5 corresponds to the first contact 61. Specifically, the bottom of the first contact 61 is in direct contact with the top surface of the lead contact layer 5. In some embodiments, the first contact 61 can also directly contact a portion of the second electrode layer 43 adjacent to the lead contact layer 5; a window is formed on the surface of the capacitor 4, the window opens the second electrode layer 43 and the capacitor dielectric layer 42 to expose a portion of the top surface of the first electrode layer 41, and the second contact 62 is in direct contact with the first electrode layer 41 through the window. In some embodiments, as Figure 7 As shown in (a), the first contact member 61 and the second contact member 62 are arranged in a hexagonal close-packed manner to obtain a higher integration density under the premise of avoiding short circuit or interference between each other. In other embodiments, the second contact member 62 can also be located at other positions, and its number can also be reduced accordingly, but it is necessary to ensure that the first contact member 61 and the second contact member 62 have a certain spacing to avoid short circuit or interference between each other.

[0043] In some embodiments, the material of the first contact 61 and / or the second contact 62 may be tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), platinum (Pt), copper (Cu) and / or a combination of one or more of their nitrides. In an exemplary embodiment of the present disclosure, the material of the first contact 61 and the second contact 62 is tungsten.

[0044] In some embodiments, there is an interlayer dielectric layer 7 above the capacitor 4, and the interlayer dielectric layer 7 covers the top surface of the capacitor 4. The first contact 61 and the second contact 62 penetrate the interlayer dielectric layer 7 and are connected to the lead-out contact layer 5 and the first electrode layer 41 respectively. In some embodiments, the material of the interlayer dielectric layer 7 can be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In an exemplary embodiment of the present disclosure, the material of the interlayer dielectric layer 7 is silicon oxide.

[0045] In some embodiments, the semiconductor structure further includes: a bottom dielectric layer 3, the bottom dielectric layer is located below the capacitor 4, at least covers the bottom and sidewalls of the hole 21 and the groove 22, the bottom dielectric layer 3 is located between the intermediary layer 1 and the first electrode layer 41, and the first electrode layer 41 covers the surface of the bottom dielectric layer 3. The function of the bottom dielectric layer 3 is to prevent the intermediary layer 1 from interfering with the potential of the first electrode layer 41 and the impurities in the intermediary layer 1 from contaminating the material of the first electrode layer 41, thereby affecting the working performance of the capacitor 4. In some embodiments, the material of the bottom dielectric layer 3 can be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon, silicon carbonitride, and silicon oxynitride carbon. In an exemplary embodiment of the present disclosure, the material of the interlayer dielectric layer 3 is silicon oxide. In other embodiments, when the purity of the silicon-based material in the intermediary layer 1 is high, the semiconductor structure may not have the bottom dielectric layer 3, the first electrode layer 41 may directly contact the inner surface of the hole 21 and the groove 22 in the intermediary layer 1, and even the first electrode layer 41 may be directly formed by doping the inner surface of the hole 21 and the groove 22.

[0046] In some embodiments, the semiconductor structure includes a plurality of trenches 22, and the plurality of trenches 22 extending along the same preset direction are arranged parallel to each other and spaced apart from each other. Figure 7 As shown in (a) or 7(e), a plurality of grooves 22 extending along the X direction or in the opposite direction are arranged at intervals in the Y direction, and a plurality of holes 21 connected by adjacent grooves 22 are arranged in a staggered manner along the Y direction or in the opposite direction. In some embodiments, the spacing between adjacent grooves 22 is equal, and the spacing between adjacent holes 21 connected by the same groove 22 and the spacing between adjacent holes 21 connected by adjacent grooves 22 are equal, that is, the holes 21 are also arranged in a hexagonal close-packed manner.

[0047] In an exemplary embodiment of the present disclosure, referring to Figure 8As shown, the intermediary layer 1 also includes a first region 11 and a second region 12 that are adjacently arranged. In the first region 11, the preset direction is the first direction, that is, the same direction or the opposite direction to the X direction. In the second region 12, the preset direction is the second direction, that is, the same direction or the opposite direction to the Y direction. In some embodiments, the intermediary layer 1 also includes a third region 13 and a fourth region 14 that are adjacently arranged, wherein the third region 13 has the same preset direction as the second region 12, and the fourth region 14 has the same preset direction as the first region 11. The third region 13 is also adjacently arranged to the first region 11 in the Y direction, and the fourth region 14 is also adjacently arranged to the second region in the Y direction. In other embodiments, the intermediary layer 1 may include more regions, but the preset directions in the adjacently arranged regions must be perpendicular to each other. Regions with preset directions perpendicular to each other can effectively solve problems such as stress in the intermediary layer 1.

[0048] The semiconductor structure provided by the present disclosure has a groove in the intermediary layer connecting multiple holes and grooves, and the capacitor is located in the holes and grooves, which effectively increases the capacitor area and improves the capacitance, thereby improving the performance of the capacitor. A lead-out contact layer of a material with higher conductivity is also provided in the hole groove, and the lead-out contact layer is connected to the first contact piece in a one-to-one correspondence, which can meet the fast charging and discharging requirements of the capacitor. The holes and grooves connected by adjacent grooves extending in a preset direction are staggered in a direction perpendicular to the preset direction, which greatly improves the area utilization rate, thereby increasing the integration of the capacitor device. The preset directions of the groove extensions in adjacent areas of the intermediary layer are perpendicular to each other, which effectively solves the problems of stress in the intermediary layer. In summary, the semiconductor structure provided by the present disclosure has the advantages of large capacity, fast charging and discharging, and high integration, thereby greatly improving the device performance of the DTC structure, and its arrangement method also has a good improvement effect on the stress problem in the intermediary layer.

[0049] Based on the above semiconductor structure, the present disclosure also provides a method for preparing a semiconductor structure, including: providing an intermediate layer 1, such as Figure 1 As shown, Figure 1 (a) is a top view of the intermediate layer 1 in the opposite direction of the Z direction. Figure 1 (b) along Figure 1 (a) is a schematic cross-sectional view along the dotted line AA′, where the cross-section along the dotted line AA′ is perpendicular to the top surface of the interposer 1 .

[0050] In an exemplary embodiment of the present disclosure, the interposer 1 adopts a silicon interposer. The material of the silicon interposer can be at least one of the following materials: silicon, germanium, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI) and other semiconductor materials or a combination of III-V materials and organic materials.

[0051] Next, a hole 21 and a groove 22 extending from the top surface of the intermediary layer 1 toward the inside of the intermediary layer 1 are formed in the intermediary layer 1. Figure 2 or Figure 3 As shown, Figure 2 (a) / 3(a) is a top view toward the intermediate layer 1 in the opposite direction of the Z direction. Figure 2 (b) / 3(b) is along Figure 2 (a) / 3(a) is a schematic cross-sectional view of the dotted line A-A' in the direction of the interposer 1. The cross-sectional view along the dotted line A-A' is perpendicular to the top surface of the interposer 1. Specifically, holes 21 and grooves 22 with a certain depth are etched from the surface of the interposer 1 to the inside of the interposer 1, that is, the openings of the holes 21 and grooves 22 are on the top surface of the interposer 1, and the depth direction of the holes 21 and grooves 22 is perpendicular to the plane where the top surface of the interposer 1 is located and faces the inside of the interposer 1, which is opposite to the Z direction in the figure. On the plane parallel to the top surface of the interposer 1, the grooves 22 extend along a preset direction, and the holes 21 are arranged at intervals along the preset direction. Figure 2 In the embodiment, the preset direction may be the X direction or its reverse direction, the groove 22 extends along the X direction or its reverse direction, and connects a plurality of holes 21 arranged at intervals along the X direction or its reverse direction. Figure 2 As shown in (a) or 3(a), the width dimension of the hole 21 is greater than the width dimension of the groove 22, wherein the direction of the width dimension is parallel to the top surface of the interposer 1 and is perpendicular to the preset direction in the aforementioned embodiment, that is, the direction of the width dimension is in the same direction or in the opposite direction to the Y direction. In some embodiments, the cross-sectional schematic diagram of the hole 21 and / or groove 22 along the depth direction is rectangular, that is, the opening dimension of the hole 21 and / or groove 22 is substantially consistent with the bottom dimension. In other embodiments, the cross-sectional schematic diagram of the hole 21 and / or groove 22 is trapezoidal, for example, the opening dimension of the hole 21 and / or groove 22 is greater than the bottom dimension, or the bottom dimension of the hole 21 and / or groove 22 is greater than the opening dimension. In an exemplary embodiment of the present disclosure, as Figure 2 As shown in (b), the hole groove 21 and the groove 22 have the same depth. In another exemplary embodiment of the present disclosure, as Figure 3 As shown in (b), the depth of the hole 21 is greater than that of the groove 22 because the hole 21 has a larger width. Therefore, in the synchronous adaptive etching process, a larger opening size often corresponds to a larger etching depth. In other embodiments, the depths of the hole 21 and the groove 22 can also be controlled separately by etching in steps.

[0052] In some embodiments, the surface of the interposer 1 may be etched by a photolithography process to form the aperture 21 and / or the groove 22. Specifically, a photoresist mask layer may be formed on the surface of the interposer 1, and the pattern of the aperture 21 and / or the groove 22 may be formed in the photoresist mask layer by exposure and development, and then dry etching may be performed to etch the interposer 1 along the pattern to form the aperture 21 and / or the groove 22. In some embodiments, before applying the photoresist mask layer, an anti-reflection layer and a hard mask layer (not shown) may be formed on the surface of the interposer 1, and both are removed after the aperture 21 and / or the groove 22 are formed. In some embodiments, the aperture 21 and the groove 22 are formed by synchronous etching, that is, during exposure and development, the patterns of the aperture 21 and the groove 22 are both formed in the photoresist mask layer (the aperture 21 and the groove 22 may be exposed in one time or the aperture 21 and the groove 22 may be exposed in two times), and then etched. In other embodiments, the hole 21 and the groove 22 are formed by step-by-step etching, that is, the hole 21 can be formed by a first photolithography, and then the groove 22 can be formed by a second photolithography, wherein the order of forming the hole 21 and the groove 22 can also be reversed.

[0053] Next, in an exemplary embodiment of the present disclosure, a bottom dielectric layer 3 is formed in the hole groove 21 and the groove 22, at least covering the bottom and sidewalls of the hole groove 21 and the groove 22. Figure 4 As shown, Figure 4 (a) is a top view of the intermediate layer 1 in the opposite direction of the Z direction. Figure 4 (b) along Figure 4 (a) Schematic diagram of the cross section along the dotted line A-A'. Figure 4 (c) along Figure 4 (a) is a schematic cross-sectional view along the dotted line BB', wherein the cross section along the dotted line AA' and the cross section along the dotted line BB' are perpendicular to each other and are both perpendicular to the top surface of the interposer 1 .

[0054] In some embodiments, the material of the bottom dielectric layer 3 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride. In an exemplary embodiment of the present disclosure, the material of the bottom dielectric layer 3 is silicon oxide. In some embodiments, the deposition method of the bottom dielectric layer 3 may be at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), in-situ water vapor growth (ISSG), thermal oxidation growth method.

[0055] Then, a capacitor 4 consisting of a first electrode layer 41, a capacitor dielectric layer 42 and a second electrode layer 43 stacked in sequence is formed in the hole 21 and the groove 22, wherein the capacitor dielectric layer 42 covers the surface of the first electrode layer 41, and the second electrode layer 43 covers the surface of the capacitor dielectric layer 42. Figure 5 As shown, Figure 5 (a) is a top view of the intermediate layer 1 in the opposite direction of the Z direction. Figure 5 (b) along Figure 5 (a) Schematic diagram of the cross section along the dotted line A-A'. Figure 5 (c) along Figure 5 (a) Schematic diagram of the cross section along the dotted line BB'. Figure 5 (d) is along Figure 5 (a) Schematic diagram of the cross section along the dotted line C-C'. Figure 5 (e) is along Figure 5 (b) is a schematic cross-sectional diagram along the dotted line D-D' direction, the cross section along the dotted line A-A' direction and the cross section along the dotted line B-B' direction are perpendicular to each other and are both perpendicular to the top surface of the intermediary layer 1, the cross section along the dotted line C-C' direction and the cross section along the dotted line B-B' direction are parallel to each other, and the cross section along the dotted line D-D' direction is parallel to the top surface of the intermediary layer 1.

[0056] In some embodiments, after forming the capacitor 4, the trench 22 is filled with the material of the capacitor 4, such as Figure 5 As shown in (d), the hole 21 is not fully filled and a gap 50 is formed. Figure 5 (b) and Figure 5As shown in (c), the gaps 50 correspond to the holes 21 one by one and are arranged at intervals along a preset direction. The gaps 50 are surrounded by the second electrode layer 43 located in the holes 21. In some embodiments, the capacitor 4 also extends to cover the top surface of the intermediary layer 1.

[0057] In some embodiments, the bottom dielectric layer 3 is located between the intermediary layer 1 and the first electrode layer 41, and the first electrode layer 41 covers the surface of the bottom dielectric layer 3. The function of the bottom dielectric layer 3 is to prevent the intermediary layer 1 from interfering with the potential of the first electrode layer 41 and the impurities in the intermediary layer 1 from contaminating the material of the first electrode layer 41, thereby affecting the working performance of the capacitor 4. In other embodiments, when the purity of the silicon-based material in the intermediary layer 1 is high, the semiconductor structure may not have the bottom dielectric layer 3, and the first electrode layer 41 may directly contact the inner surface of the hole 21 and the groove 22 in the intermediary layer 1, and even the first electrode layer 41 may be directly formed by doping the inner surface of the hole 21 and the groove 22.

[0058] In some embodiments, the material of the first electrode layer 41 and / or the second electrode layer 43 may be a combination of at least one or more of doped silicon, titanium nitride (TiN), silicon-doped titanium nitride (TiSiN), titanium (Ti), tungsten (W), tungsten nitride (WN), and silicon-doped tungsten nitride (WSiN), and the material of the capacitor dielectric layer 42 may be a combination of at least one or more of silicon oxide (SiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), and lead titanate (PZT). In an exemplary embodiment of the present disclosure, the material of the first electrode layer 41 and / or the second electrode layer 43 is titanium nitride, and the material of the capacitor dielectric layer 42 is a high dielectric constant (high-K) material.

[0059] In some embodiments, the formation method of the first electrode layer 41, the capacitor dielectric layer 42 and the second electrode layer 43 can adopt at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and sputtering.

[0060] Next, a lead contact layer 5 is formed in the hole groove 21 to cover the surface of the second electrode layer 43 in the hole groove 21 and fill the hole groove 21. Figure 6 As shown, Figure 6 (a) is a top view of the intermediate layer 1 in the opposite direction of the Z direction. Figure 6 (b) along Figure 6 (a) Schematic diagram of the cross section along the dotted line A-A'. Figure 6 (c) along Figure 6 (a) Schematic diagram of the cross section along the dotted line BB'. Figure 6 (d) is along Figure 6 (a) Schematic diagram of the cross section along the dotted line C-C'. Figure 6 (e) is along Figure 6 (b) is a schematic cross-sectional diagram along the dotted line D-D' direction, the cross section along the dotted line A-A' direction and the cross section along the dotted line B-B' direction are perpendicular to each other and are both perpendicular to the top surface of the intermediary layer 1, the cross section along the dotted line C-C' direction and the cross section along the dotted line B-B' direction are parallel to each other, and the cross section along the dotted line D-D' direction is parallel to the top surface of the intermediary layer 1.

[0061] Specifically, the lead-out contact layer 5 is cylindrically inserted into the hole groove 21 and fills the gap 50 left in the hole groove 21 after the capacitor 4 is formed. The lead-out contact layer 5 is only located in the hole groove 21 and shares a central axis with the hole groove 21. The hole groove 21 corresponds to the lead-out contact layer 5 one by one. In some embodiments, the material filling the lead-out contact layer 5 will escape the gap 50, and the excess material can be removed by back etching or planarization treatment later, so that the top surface of the lead-out contact layer 5 is equal to the top surface of the second electrode layer 43.

[0062] In some embodiments, the material of the lead-out contact layer 5 may be a combination of one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), platinum (Pt), copper (Cu) and / or their nitrides. In an exemplary embodiment of the present disclosure, the material of the lead-out contact layer 5 is copper. In some embodiments, the method for forming the lead-out contact layer 5 may be at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering.

[0063] Then continue to refer to Figure 6, a first contact 61 and a second contact 62 are formed above the capacitor 4, the first contact 61 is connected to the lead-out contact layer 5, and the second contact 62 is connected to the first electrode layer 41, wherein the lead-out contact layer 5 and the first contact 61 are in one-to-one correspondence. Specifically, the bottom of the first contact 61 is in direct contact with the top surface of the lead-out contact layer 5, and in some embodiments, the first contact 61 may also directly contact a portion of the second electrode layer 43 adjacent to the lead-out contact layer 5; a window is formed on the surface of the capacitor 4, the window opens the second electrode layer 43 and the capacitor dielectric layer 42 to expose a portion of the top surface of the first electrode layer 41, and the second contact 62 is in direct contact with the first electrode layer 41 through the window.

[0064] In some embodiments, the material of the first contact 61 and / or the second contact 62 may be tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), platinum (Pt), copper (Cu) and / or a combination of one or more of their nitrides. In an exemplary embodiment of the present disclosure, the material of the first contact 61 and the second contact 62 is tungsten. In some embodiments, the formation method of the first contact 61 and / or the second contact 62 may adopt at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering.

[0065] In some embodiments, before forming the first contact 61 and the second contact 62, the method further includes: forming an interlayer dielectric layer 7 to cover the top surface of the capacitor 4, and the first contact 61 and the second contact 62 penetrate the interlayer dielectric layer 7 to be connected to the lead contact layer 5 and the first electrode layer 41 respectively. Specifically, an interlayer dielectric layer 7 is formed on the capacitor 4 to cover the second electrode layer 43 and the top surface of the lead contact layer 5, and then the interlayer dielectric layer 7 is etched to form a first through hole and a second through hole, the first through hole penetrates the interlayer dielectric layer 7 and at least exposes the top surface of the lead contact layer 5, and the second through hole penetrates the interlayer dielectric layer 7 and forms a window on the surface of the capacitor 4, the window opens the second electrode layer 43 and the capacitor dielectric layer 42 to expose a portion of the top surface of the first electrode layer 41, and the first through hole is filled in the first through hole to form the first contact 61 and the second through hole is filled in the second through hole to form the second contact 62. In some embodiments, the bottom of the first contact member 61 directly contacts the top surface of the lead-out contact layer 5 and may also directly contact a portion of the second electrode layer 43 adjacent to the lead-out contact layer 5 . The bottom of the second contact member 62 directly contacts the top surface of the exposed portion of the first electrode layer 41 .

[0066] In some embodiments, the material of the interlayer dielectric layer 7 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon nitride. In an exemplary embodiment of the present disclosure, the material of the interlayer dielectric layer 7 is silicon oxide. In some embodiments, the deposition method of the interlayer dielectric layer 7 may be at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), in-situ water vapor growth (ISSG), thermal oxidation growth method.

[0067] In another exemplary embodiment of the present disclosure, a plurality of grooves 22 extending along a preset direction are formed in the interposer 1, and the plurality of grooves 22 are arranged at intervals in a direction perpendicular to the preset direction. Moreover, in the direction perpendicular to the preset direction, the plurality of holes 21 connected by adjacent grooves 22 are arranged in a staggered manner, such as Figure 7 As shown, Figure 7 (a) is a top view of the intermediate layer 1 in the opposite direction of the Z direction. Figure 7 (b) along Figure 7 (a) Schematic diagram of the cross section along the dotted line A-A'. Figure 7 (c) along Figure 7(a) Schematic diagram of the cross section along the dotted line BB'. Figure 7 (d) is along Figure 7 (a) Schematic diagram of the cross section along the dotted line C-C'. Figure 7 (e) is along Figure 7 (b) is a schematic cross-sectional diagram along the dotted line D-D' direction, the cross section along the dotted line A-A' direction and the cross section along the dotted line B-B' direction are perpendicular to each other and are both perpendicular to the top surface of the intermediary layer 1, the cross section along the dotted line C-C' direction and the cross section along the dotted line B-B' direction are parallel to each other, and the cross section along the dotted line D-D' direction is parallel to the top surface of the intermediary layer 1.

[0068] In this embodiment, except for the method steps of simultaneously forming a plurality of grooves 22 extending along a preset direction and arranged at intervals in a direction perpendicular to the preset direction, the remaining subsequent method steps of forming a low dielectric layer 3 in the grooves 22 and the holes 21, forming a capacitor 4, forming a lead contact layer 5, forming an interlayer dielectric layer 7 and a first contact member 61 and a second contact member 62 are the same as the formation method steps described in the aforementioned embodiment and will not be repeated here.

[0069] In some embodiments, Figure 7 As shown in (a)-7(e), the hole groove 21 and the lead contact layer 5 are arranged in a hexagonal close-packed manner, and the first contact member 61 and the second contact member 62 can be arranged in a hexagonal close-packed manner with a higher density, so as to obtain a higher integration density under the premise of avoiding short circuit or interference between each other. In other embodiments, the second contact member 62 can also be located at other positions, and its number can also be reduced accordingly, but it is necessary to ensure that the first contact member 61 and the second contact member 62 have a certain distance to avoid short circuit or interference between each other.

[0070] In some embodiments, reference Figure 8 As shown, the intermediary layer 1 also includes a first region 11 and a second region 12 that are adjacently arranged. In the first region 11, the preset direction is the first direction, that is, the same direction or the opposite direction to the X direction. In the second region 12, the preset direction is the second direction, that is, the same direction or the opposite direction to the Y direction. In some embodiments, the intermediary layer 1 also includes a third region 13 and a fourth region 14 that are adjacently arranged, wherein the third region 13 has the same preset direction as the second region 12, and the fourth region 14 has the same preset direction as the first region 11. The third region 13 is also adjacently arranged to the first region 11 in the Y direction, and the fourth region 14 is also adjacently arranged to the second region in the Y direction. In other embodiments, the intermediary layer 1 may include more regions, but the preset directions in the adjacently arranged regions must be perpendicular to each other. Regions with preset directions perpendicular to each other can effectively solve problems such as stress in the intermediary layer 1.

[0071] In the above embodiment, a plurality of grooves 22 extending in different preset directions and holes 21 penetrating therethrough are formed in different regions, and the subsequent steps of forming a low dielectric layer 3, forming a capacitor 4, forming a lead contact layer 5, forming an interlayer dielectric layer 7 and a first contact member 61 and a second contact member 62 in the grooves 22 and the holes 21 can be performed simultaneously and are the same as the steps of the formation method described in the above embodiment, and will not be repeated here.

[0072] In an exemplary embodiment of the present disclosure, a semiconductor device is also provided. Fig. 9 As shown, at least the semiconductor structure 101 in any of the aforementioned embodiments and the chip 201 located on the semiconductor structure 101 are included, wherein the chip 201 is electrically connected to the semiconductor structure 101 through solder ball bumps 401 and / or pads (not shown). In other embodiments, the chip 201 and the semiconductor structure can also be electrically connected by wire bonding. In some embodiments, the interposer 1 in the semiconductor structure 101 also includes interconnect structures such as a redistribution layer 1011 (Re-distribution Layer, RDL) and a through silicon via 1012 (TSV). In some embodiments, the chip 201 can be a plurality of memory chips stacked on each other, such as a DRAM chip or a NAND FLASH chip, and the chips 201 can be interconnected by bumps or hybrid bonding and through silicon vias 202 (TSV). In other embodiments, the chip 201 can also be a processor chip or an image sensor chip. In some embodiments, the semiconductor device further includes: a substrate 301, on which the semiconductor structure 101 is located, and the substrate 301 and the semiconductor structure 101 can also be electrically connected through solder ball bumps 402. In some embodiments, the substrate 301 can be a glass substrate, an organic substrate or an insulating substrate, and the substrate 301 also includes solder ball bumps 403 below for connecting to a mainboard or other PCB.

[0073] It should be noted that the semiconductor structure or semiconductor device in the embodiment of the present disclosure can be used to manufacture the HBM packaging structure of the memory chip, and can also be used to manufacture other devices that require a capacitor structure to be manufactured in an intermediate layer, and no excessive restrictions are made here.

[0074] The various semiconductor structures shown in this specific embodiment can be used for electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be realized by the following memories: dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), magnetic random access memory (MRAM) or resistive random access memory (RRAM), flash memory (FLASH) or some integrated storage products or systems on chip.

[0075] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: An intermediary layer, wherein the intermediary layer has holes and grooves extending from the top surface of the intermediary layer toward the interior of the intermediary layer; A capacitor is located in the hole and the groove, the capacitor comprises a first electrode layer, a capacitor dielectric layer and a second electrode layer stacked in sequence, the capacitor dielectric layer covers a surface of the first electrode layer, and the second electrode layer covers a surface of the capacitor dielectric layer; Among them, the groove also extends along a preset direction parallel to the top surface of the intermediary layer and connects multiple hole grooves arranged at intervals along the preset direction. The width dimension of the hole groove is larger than the width dimension of the groove, and the direction of the width dimension is parallel to the top surface of the intermediary layer and perpendicular to the preset direction.

2. The semiconductor structure according to claim 1, characterized in that: Also includes: A lead-out contact layer is located in the hole groove, covers the surface of the second electrode layer located in the hole groove and fills the hole groove.

3. The semiconductor structure according to claim 2, characterized in that: The material of the lead-out contact layer includes copper.

4. The semiconductor structure according to claim 2, characterized in that: Also includes: A first contact and a second contact are located above the capacitor, wherein the first contact is connected to the lead-out contact layer, and the second contact is connected to the first electrode layer.

5. The semiconductor structure according to claim 4, characterized in that: The hole grooves and the lead-out contact layers, and the lead-out contact layers and the first contact members all correspond one to one.

6. The semiconductor structure according to claim 1, characterized in that The intermediate layer includes a plurality of grooves, and in a direction perpendicular to the preset direction, a plurality of holes connected by adjacent grooves are arranged in a staggered manner.

7. The semiconductor structure according to claim 1, characterized in that: The intermediate layer further includes a first region and a second region adjacent to each other. In the first region, the preset direction is a first direction, and in the second region, the preset direction is a second direction. The first direction and the second direction are perpendicular to each other.

8. The semiconductor structure according to claim 7, characterized in that: In the first region, a plurality of the grooves extend along the first direction and are arranged at intervals along the second direction. In the second region, a plurality of the grooves extend along the second direction and are arranged at intervals along the first direction.

9. The semiconductor structure according to claim 1, characterized in that: Also includes: The bottom dielectric layer at least covers the bottom and sidewalls of the hole and the groove, the bottom dielectric layer is located between the intermediate layer and the first electrode layer, and the first electrode layer covers the surface of the bottom dielectric layer.

10. A method for manufacturing a semiconductor structure, characterized in that: include: Provide an intermediary layer; Forming holes and grooves in the interposer extending from the top surface of the interposer toward the interior of the interposer; A capacitor composed of a first electrode layer, a capacitor dielectric layer and a second electrode layer stacked in sequence is formed in the hole and the groove, wherein the capacitor dielectric layer covers a surface of the first electrode layer, and the second electrode layer covers a surface of the capacitor dielectric layer; Among them, the groove also extends along a preset direction parallel to the top surface of the intermediary layer and connects multiple hole grooves arranged at intervals along the preset direction. The width dimension of the hole groove is larger than the width dimension of the groove, and the direction of the width dimension is parallel to the top surface of the intermediary layer and perpendicular to the preset direction.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: Also includes: A lead-out contact layer is formed in the hole groove, covering the surface of the second electrode layer in the hole groove and filling the hole groove.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: Also includes: forming a first contact and a second contact above the capacitor, wherein the first contact is connected to the lead-out contact layer, and the second contact is connected to the first electrode layer; The hole grooves and the lead-out contact layers, and the lead-out contact layers and the first contact members all correspond one to one.

13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: The interposer further comprises a first region and a second region which are adjacently arranged, wherein in the first region, the preset direction is a first direction, and in the second region, the preset direction is a second direction, and the first direction and the second direction are perpendicular to each other; Forming holes and grooves in the interposer extending from the top surface of the interposer toward the inside of the interposer includes: A plurality of grooves extending along the first direction and arranged at intervals along the second direction are formed in the first region, and a plurality of grooves extending along the second direction and arranged at intervals along the first direction are formed in the second region. In a direction perpendicular to the preset direction, a plurality of holes connected by adjacent grooves are arranged alternately.

14. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: Before forming the capacitor in the hole and the groove, the method further includes: forming a bottom dielectric layer in the hole and the groove, at least covering the bottom and sidewall of the hole and the groove; The bottom dielectric layer is located between the intermediate layer and the first electrode layer formed subsequently, and the first electrode layer covers the surface of the bottom dielectric layer.

15. A semiconductor device, characterized in that: include: The semiconductor structure according to any one of claims 1 to 9; A chip, located on the semiconductor structure; The chip and the semiconductor structure are electrically connected via solder ball bumps and / or solder pads.

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