Semiconductor structure, manufacturing method thereof and semiconductor device

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof and a semiconductor device, the semiconductor structure comprises an intermediate layer, the intermediate layer is provided with a plurality of groove arrays formed by grooves extending from the top surface of the intermediate layer to the interior of the intermediate layer, and the grooves also extend along a preset direction parallel to the top surface of the intermediate layer; the capacitor is located in the groove, the capacitor comprises a first electrode layer, a first capacitor dielectric layer and a second electrode layer which are stacked in sequence, the first capacitor dielectric layer covers the surface of the first electrode layer, and the second electrode layer covers the surface of the first capacitor dielectric layer; the extraction electrode layer is located in the intermediate layer, and the extraction electrode layer is electrically connected with the first electrode layer and / or the second electrode layer and extends in the preset direction. The semiconductor structure has the advantages of large capacity, rapid charging and discharging, high integration level and high reliability, and the stress problem can be well solved through the arrangement mode of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof, and a semiconductor device. Background Art

[0002] In order to improve the integration of semiconductor structures, many chips can be stacked and welded together, such as 3D stack (3DS) memory. In this way, the original 2D layout can be expanded to 2.5D (between 2D and 3D packaging) or 3D, thereby greatly improving the density of the chip. In the field of advanced packaging technology, especially in 2.5D and 3D packaging technology, interposer packaging is widely used, that is, multiple chips (Die) are arranged on a substrate through an interposer device, and different chips can receive signals from other chips or transmit signals to other chips through the interposer device, thereby improving the overall signal density of the package and at the same time achieving the advantage of reducing the overall volume.

[0003] In order to maintain signal stability in interposer devices, a deep trench capacitor (DTC) structure is usually used to prevent signal lines from interfering with each other. However, the structural design of the deep trench capacitor structure in the prior art has obvious limitations, and the performance still needs to be further enhanced. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising: an interposer, wherein the interposer has a groove array consisting of a plurality of grooves extending from the top surface of the interposer toward the inside of the interposer, and the grooves also extend along a preset direction parallel to the top surface of the interposer; a capacitor located in the groove, wherein the capacitor comprises at least a first electrode layer, a first capacitor dielectric layer, and a second electrode layer stacked in sequence, wherein the first capacitor dielectric layer covers the surface of the first electrode layer, and the second electrode layer covers the surface of the first capacitor dielectric layer; an extraction electrode layer located in the interposer, wherein the extraction electrode layer is electrically connected to the first electrode layer and / or the second electrode layer, and extends along the preset direction.

[0005] In some embodiments, the extraction electrode layer further extends along the depth direction of the groove in the intermediate layer, and the extraction electrode layer only includes a first extraction electrode layer, which is located between adjacent grooves and electrically connected to the first electrode layer.

[0006] In some embodiments, the lead-out electrode layer also extends along the depth direction of the groove in the intermediate layer, and the lead-out electrode layer includes a first lead-out electrode layer and a second lead-out electrode layer, the first lead-out electrode layer is located between adjacent grooves and is electrically connected to the first electrode layer, and the second lead-out electrode layer is located in the groove and is electrically connected to the second electrode layer.

[0007] In some embodiments, the capacitor further includes a second capacitor dielectric layer, a third electrode layer, a third capacitor dielectric layer and a fourth electrode layer stacked in sequence, the second capacitor dielectric layer covers the surface of the second electrode layer, the third electrode layer covers the surface of the second capacitor dielectric layer, the third capacitor dielectric layer covers the surface of the third electrode layer, and the fourth electrode layer covers the surface of the third capacitor dielectric layer; the lead-out electrode layer also extends along the depth direction of the groove in the intermediate layer, the lead-out electrode layer includes a first lead-out electrode layer, a second lead-out electrode layer, a third lead-out electrode layer and a fourth lead-out electrode layer, and the first lead-out electrode layer is located between adjacent grooves and is electrically connected to the first electrode layer, the second lead-out electrode layer is located on the outside of the first outermost groove of the groove array and is electrically connected to the second electrode layer, the third lead-out electrode layer is located on the outside of the second outermost groove of the groove array and is electrically connected to the third electrode layer, and the fourth lead-out electrode layer is located in the groove and is electrically connected to the fourth electrode layer; wherein, the first outermost side and the second outermost side are two opposite sides of the groove array, the direction of the two opposite sides is perpendicular to the preset direction, and the outer side of the groove is a side of the groove located at the first outermost side or the second outermost side away from the groove adjacent to it.

[0008] In some embodiments, the capacitor also includes a second capacitor dielectric layer, a third electrode layer, a third capacitor dielectric layer and a fourth electrode layer stacked in sequence, the second capacitor dielectric layer covers the surface of the second electrode layer, the third electrode layer covers the surface of the second capacitor dielectric layer, the third capacitor dielectric layer covers the surface of the third electrode layer, and the fourth electrode layer covers the surface of the third capacitor dielectric layer; the lead-out electrode layer is only located in the area of ​​the groove close to the bottom of the groove, the lead-out electrode layer includes a first lead-out electrode layer, a second lead-out electrode layer and a third lead-out electrode layer, the first lead-out electrode layer covers the upper surface of the portion of the second electrode layer located at the bottom of the groove and is electrically connected to the second electrode layer, the second lead-out electrode layer covers the upper surface of the portion of the third electrode layer located at the bottom of the groove and is electrically connected to the third electrode layer, and the third lead-out electrode layer covers the upper surface of the portion of the fourth electrode layer located at the bottom of the groove and is electrically connected to the fourth electrode layer.

[0009] In some embodiments, the capacitor further includes a second capacitor dielectric layer, a third electrode layer, a third capacitor dielectric layer and a fourth electrode layer stacked in sequence, the second capacitor dielectric layer covers the surface of the second electrode layer, the third electrode layer covers the surface of the second capacitor dielectric layer, the third capacitor dielectric layer covers the surface of the third electrode layer, and the fourth electrode layer covers the surface of the third capacitor dielectric layer; the lead-out electrode layer is only located in the area of ​​the groove close to the bottom of the groove, the lead-out electrode layer includes a first lead-out electrode layer, a second lead-out electrode layer, a third lead-out electrode layer and a fourth lead-out electrode layer, the first lead-out electrode layer covers the upper surface of the portion of the first electrode layer located at the bottom of the groove and is electrically connected to the first electrode layer, the second lead-out electrode layer covers the upper surface of the portion of the second electrode layer located at the bottom of the groove and is electrically connected to the second electrode layer, the third lead-out electrode layer covers the upper surface of the portion of the third electrode layer located at the bottom of the groove and is electrically connected to the third electrode layer, and the fourth lead-out electrode layer covers the upper surface of the portion of the fourth electrode layer located at the bottom of the groove and is electrically connected to the fourth electrode layer.

[0010] In some embodiments, the semiconductor structure further includes: a contact and an interlayer dielectric layer, the interlayer dielectric layer covers the top surface of the capacitor, and the contact penetrates the interlayer dielectric layer and is electrically connected to the lead electrode layer and / or the first electrode layer and the second electrode layer.

[0011] In some embodiments, a region where the contact element is electrically connected to the extraction electrode layer and / or the first electrode layer and the second electrode layer is located outside the groove array.

[0012] In some embodiments, the semiconductor structure further includes: a bottom dielectric layer, at least covering the bottom and sidewalls of the trench, the bottom dielectric layer is located between the intermediate layer and the first electrode layer, and the first electrode layer covers the surface of the bottom dielectric layer.

[0013] In some embodiments, the interposer also includes a first region and a second region that are adjacent to each other, in the first region, the preset direction is a first direction, and in the second region, the preset direction is a second direction, and the first direction and the second direction are perpendicular to each other; in the first region, a plurality of the grooves extend along the first direction and are arranged at intervals along the second direction, and in the second region, a plurality of the grooves extend along the second direction and are arranged at intervals along the first direction.

[0014] According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing an interposer; forming in the interposer layer a groove array consisting of a plurality of grooves extending from the top surface of the interposer layer toward the interior of the interposer layer and a lead-out electrode layer, wherein the grooves also extend in a preset direction parallel to the top surface of the interposer layer; forming in the grooves a capacitor comprising at least a first electrode layer, a first capacitor dielectric layer, and a second electrode layer stacked in sequence, wherein the first capacitor dielectric layer covers the surface of the first electrode layer, and the second electrode layer covers the surface of the first capacitor dielectric layer; wherein the lead-out electrode layer is electrically connected to the first electrode layer and / or the second electrode layer, and extends along the preset direction.

[0015] In some embodiments, before forming the groove, the lead-out electrode layer is formed in the intermediate layer, and subsequently the groove is formed on both sides of the lead-out electrode layer; wherein the lead-out electrode layer also extends along the depth direction of the groove in the intermediate layer, and the lead-out electrode layer is located between adjacent grooves and is electrically connected only to the first electrode layer.

[0016] In some embodiments, the lead-out electrode layer includes a first lead-out electrode layer and a second lead-out electrode layer. Before forming the groove, the first lead-out electrode layer is formed in the intermediate layer, and subsequently the groove is formed on both sides of the first lead-out electrode layer. After forming the capacitor, the second lead-out electrode layer is formed in the groove; wherein, the lead-out electrode layer also extends along the depth direction of the groove in the intermediate layer, the first lead-out electrode layer is located between adjacent grooves and is electrically connected to the first electrode layer, and the second lead-out electrode layer is electrically connected to the second electrode layer.

[0017] In some embodiments, forming the capacitor further includes forming a second capacitor dielectric layer, a third electrode layer, a third capacitor dielectric layer and a fourth electrode layer stacked in sequence in the groove after forming the second electrode layer, the second capacitor dielectric layer covers the surface of the second electrode layer, the third electrode layer covers the surface of the second capacitor dielectric layer, the third capacitor dielectric layer covers the surface of the third electrode layer, and the fourth electrode layer covers the surface of the third capacitor dielectric layer; the extraction electrode layer includes a first extraction electrode layer, a second extraction electrode layer, a third extraction electrode layer and a fourth extraction electrode layer, before forming the groove, the first extraction electrode layer is formed in the intermediate layer, and the groove is subsequently formed on both sides of the first extraction electrode layer, the first extraction electrode layer is located between adjacent grooves and is electrically connected to the first electrode layer; after forming the second electrode layer and before forming the second capacitor dielectric layer Before forming the second lead-out electrode layer, the second lead-out electrode layer is formed, and the second lead-out electrode layer is located on the outside of the first outermost groove in the groove array and is electrically connected to the second electrode layer; after forming the third electrode layer and before forming the third capacitor dielectric layer, the third lead-out electrode layer is formed, and the third lead-out electrode layer is located on the outside of the second outermost groove in the groove array and is electrically connected to the third electrode layer; after forming the fourth electrode layer, the fourth lead-out electrode layer is formed in the groove and is electrically connected to the fourth electrode layer; wherein the lead-out electrode layer also extends along the depth direction of the groove in the interposer, the first outermost side and the second outermost side are opposite sides of the groove array, the direction of the opposite sides is perpendicular to the preset direction, and the outer side of the groove is the side of the groove located at the first outermost side or the second outermost side away from the groove adjacent to it.

[0018] In some embodiments, forming the capacitor further includes forming a second capacitor dielectric layer, a third electrode layer, a third capacitor dielectric layer and a fourth electrode layer stacked in sequence in the groove after forming the second electrode layer, the second capacitor dielectric layer covers the surface of the second electrode layer, the third electrode layer covers the surface of the second capacitor dielectric layer, the third capacitor dielectric layer covers the surface of the third electrode layer, and the fourth electrode layer covers the surface of the third capacitor dielectric layer; the extraction electrode layer includes a first extraction electrode layer, a second extraction electrode layer and a third extraction electrode layer, and after forming the second electrode layer and before forming the second capacitor dielectric layer, in the groove The first lead-out electrode layer is formed, the first lead-out electrode layer covers the upper surface of the portion of the second electrode layer located at the bottom of the groove and is electrically connected to the second electrode layer; after forming the third electrode layer and before forming the third capacitor dielectric layer, the second lead-out electrode layer is formed in the groove, the second lead-out electrode layer covers the upper surface of the portion of the third electrode layer located at the bottom of the groove and is electrically connected to the third electrode layer; after forming the fourth electrode layer, the third lead-out electrode layer is formed in the groove, the third lead-out electrode layer covers the upper surface of the portion of the fourth electrode layer located at the bottom of the groove and is electrically connected to the fourth electrode layer.

[0019] In some embodiments, forming the capacitor further includes forming a second capacitor dielectric layer, a third electrode layer, a third capacitor dielectric layer and a fourth electrode layer stacked in sequence in the groove after forming the second electrode layer, the second capacitor dielectric layer covers the surface of the second electrode layer, the third electrode layer covers the surface of the second capacitor dielectric layer, the third capacitor dielectric layer covers the surface of the third electrode layer, and the fourth electrode layer covers the surface of the third capacitor dielectric layer; the extraction electrode layer includes a first extraction electrode layer, a second extraction electrode layer, a third extraction electrode layer and a fourth extraction electrode layer, and before forming the first electrode layer, the first extraction electrode layer is formed in the groove, the first extraction electrode layer covers the lower surface of the portion of the first electrode layer located at the bottom of the groove and is aligned with the first extraction electrode layer. an electrode layer electrically connected; after forming the second electrode layer and before forming the second capacitor dielectric layer, forming the second lead-out electrode layer in the groove, the second lead-out electrode layer covers the lower surface of the portion of the second electrode layer located at the bottom of the groove and is electrically connected to the second electrode layer; after forming the third electrode layer and before forming the third capacitor dielectric layer, forming the third lead-out electrode layer in the groove, the third lead-out electrode layer covers the lower surface of the portion of the third electrode layer located at the bottom of the groove and is electrically connected to the third electrode layer; after forming the fourth electrode layer, forming the fourth lead-out electrode layer in the groove, the fourth lead-out electrode layer covers the lower surface of the portion of the fourth electrode layer located at the bottom of the groove and is electrically connected to the fourth electrode layer.

[0020] In some embodiments, after forming the capacitor, the method for forming the semiconductor structure also includes: forming an interlayer dielectric layer to cover the top surface of the capacitor, and forming a contact piece that penetrates the interlayer dielectric layer and electrically connects the lead electrode layer and / or the first electrode layer and the second electrode layer.

[0021] In some embodiments, before forming the capacitor in the trench, the method for forming the semiconductor structure also includes: forming a bottom dielectric layer in the trench, covering at least the bottom and side walls of the trench; the bottom dielectric layer is located between the intermediate layer and the first electrode layer, and the first electrode layer covers the surface of the bottom dielectric layer.

[0022] According to a third aspect of an embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor structure as described in any one of the aforementioned embodiments; a chip located on the semiconductor structure; wherein the chip and the semiconductor structure are electrically connected via solder ball bumps and / or solder pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of providing an intermediary layer according to an exemplary embodiment 1;

[0024] Figure 2 is a schematic diagram showing the formation of a first extraction electrode layer according to an exemplary embodiment 1;

[0025] Figure 3 is a schematic diagram showing the formation of a groove according to an exemplary embodiment;

[0026] Figure 4 is a schematic diagram of forming a capacitor according to an exemplary embodiment 1;

[0027] Figure 5 is a schematic diagram of forming a contact according to an exemplary embodiment 1;

[0028] Figure 6 is a schematic diagram of forming a contact according to another exemplary embodiment;

[0029] Figure 7 is a schematic diagram showing the formation of a second extraction electrode layer according to a second exemplary embodiment;

[0030] Figure 8 is a schematic diagram showing the formation of a contact according to a second exemplary embodiment;

[0031] Fig. 9 is a schematic diagram showing a method of forming a contact according to another exemplary embodiment;

[0032] Fig.10 is a schematic diagram of forming a groove according to a third exemplary embodiment;

[0033] Fig.11 is a schematic diagram showing the formation of a capacitor and an extraction electrode layer according to a third exemplary embodiment;

[0034] Fig.12 is a schematic diagram of forming a contact according to a third exemplary embodiment;

[0035] Fig.13 is a schematic diagram of forming a contact according to another exemplary embodiment three;

[0036] Fig.14 is a schematic diagram showing the formation of a groove according to a fourth exemplary embodiment;

[0037] Fig.15 is a schematic diagram showing the formation of a capacitor and an extraction electrode layer according to a fourth exemplary embodiment;

[0038] Fig.16 is a schematic diagram of forming a contact according to a fourth exemplary embodiment;

[0039] Fig.17is a schematic diagram showing the formation of a capacitor and an extraction electrode layer according to a fifth exemplary embodiment;

[0040] Fig.18 is a schematic diagram showing the formation of a contact according to a fifth exemplary embodiment;

[0041] Fig.19 is a schematic diagram showing the formation of a bottom dielectric layer according to an exemplary embodiment 6;

[0042] Fig. 20 is a schematic diagram showing the arrangement of a groove array according to an exemplary embodiment;

[0043] Fig.21 is a schematic diagram of a semiconductor device according to an exemplary embodiment. DETAILED DESCRIPTION

[0044] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0045] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0046] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0047] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0048] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0049] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0050] In the related art, the DTC structure is basically a deep hole, and is usually made simultaneously by making a through silicon via (TSV) process in an interposer. The inventor of the present application found that with the development of 2.5D packaging technology, the device size is further miniaturized, the DTC structure capacitor area is reduced, and it is increasingly difficult to achieve an increase in capacitor density, accompanied by increasingly serious stress during the support process. It is becoming increasingly important to seek a new DTC structure design solution.

[0051] In view of the above technical problems, the present disclosure provides a semiconductor structure and a method for manufacturing the same, and a semiconductor device. Figures 1 to 21 A semiconductor structure, a method for preparing the semiconductor structure, and a semiconductor device exemplarily provided by the present disclosure are specifically introduced. Figures 1 to 19 is a schematic diagram of a method for preparing a semiconductor structure according to multiple exemplary embodiments of the present disclosure. Fig. 20 FIG. 1 is a schematic diagram showing the arrangement of a groove array according to an exemplary embodiment of the present disclosure. Fig. 9 FIG. 1 is a schematic diagram of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0052] In an exemplary embodiment of the present disclosure, a semiconductor structure is provided, referring to Figure 5 , 6 , 8, 9, 12, 13, 16, 18 or Fig.19(d) is shown. The semiconductor structure includes: an interposer 1, wherein the interposer 1 has a groove array 300 composed of a plurality of grooves 30 extending from the top surface of the interposer 1 toward the inside of the interposer 1, and the grooves 30 also extend in a preset direction parallel to the top surface of the interposer 1; a capacitor 3, located in the groove 30, wherein the capacitor 3 includes a first electrode layer 31, a first capacitor dielectric layer 32 and a second electrode layer 33 stacked in sequence, wherein the first capacitor dielectric layer 32 covers the surface of the first electrode layer 31, and the second electrode layer 33 covers the surface of the first capacitor dielectric layer 32; an extraction electrode layer, located in the interposer 1, wherein the extraction electrode layer is electrically connected to the first electrode layer 31 and / or the second electrode layer 33, and extends in a preset direction. It should be noted that in an exemplary embodiment of the present disclosure, the preset direction is in the same direction or in the opposite direction to the X direction. It should be noted that the X direction, the Y direction, and the Z direction in all the drawings in the specification of the present disclosure are perpendicular to each other.

[0053] In an exemplary embodiment of the present disclosure, the interposer 1 adopts a silicon interposer. The material of the silicon interposer can be at least one of the following materials: silicon, germanium, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI) and other semiconductor materials or a combination of III-V materials and organic materials.

[0054] The groove 30 is located in the interposer 1, extending from the top surface of the interposer 1 toward the inside of the interposer 1, that is, the opening of the groove 30 is on the top surface of the interposer 1, and the depth direction of the groove 30 is perpendicular to the plane where the top surface of the interposer 1 is located and faces the inside of the interposer 1, which is opposite to the Z direction in the figure. On the plane parallel to the top surface of the interposer 1, multiple grooves 30 extend along a preset direction and are arranged at intervals in a direction perpendicular to the preset direction to form a groove array 300, that is, as shown in the figure, multiple grooves 30 in the groove array 300 extend along the X direction or its reverse direction and are arranged at intervals in the Y direction or its reverse direction. In some embodiments, the number of grooves 30 in the groove array 300 is greater than or equal to 2. In some embodiments, the cross-sectional schematic diagram of the groove 30 is rectangular. In other embodiments, the cross-sectional schematic diagram of the groove 30 is trapezoidal, for example, the opening size of the groove 30 is larger than the bottom size, or the bottom size of the groove 30 is larger than the opening size. In other embodiments, the bottom of the groove 30 is an arc shape that is concave toward the inside of the interposer 1. The direction of the opening size or the bottom size is parallel to the top surface of the intermediary layer 1 and perpendicular to the preset direction in the above embodiment, that is, the direction of the opening size or the bottom size is in the same direction or in the opposite direction to the Y direction.

[0055] The capacitor 3 is located in the groove 30, and includes a first electrode layer 31, a first capacitor dielectric layer 32, and a second electrode layer 33 stacked in sequence. The first capacitor dielectric layer 32 covers the surface of the first electrode layer 31, and the second electrode layer 33 covers the surface of the first capacitor dielectric layer 32. In some embodiments, the capacitor 3 also includes one or more other electrode layers in addition to the first electrode layer 31 and the second electrode layer 33. Adjacent electrode layers are separated by the first capacitor dielectric layer 32 or other capacitor dielectric layers, for example Fig.12 , 13 The capacitor 3 in 16 and 18 also includes a third electrode layer 35, a fourth electrode layer 37, a second capacitor dielectric layer 34 separating the second electrode layer 33 and the third electrode layer 35, a third capacitor dielectric layer 36 separating the third electrode layer 35 and the fourth electrode layer 37, the second capacitor dielectric layer 34 covers the surface of the second electrode layer 33, the third electrode layer 35 covers the surface of the second capacitor dielectric layer 34, the third capacitor dielectric layer 36 covers the surface of the third electrode layer 35, and the fourth electrode layer 37 covers the surface of the third capacitor dielectric layer 36. The capacitor 3 also extends to the top surface of the intermediate layer 1 outside the groove 30. In some embodiments, the capacitors 3 located in adjacent grooves 30 are connected as a whole, that is, the film layers of the capacitor 3 on the top surface of the intermediate layer 1 between the adjacent grooves 30 (for example, the first electrode layer 31, the first capacitor dielectric layer 32, and the second electrode layer 33) are connected as a whole; while in other embodiments, the capacitors 3 located in adjacent grooves 30 are isolated from each other, that is, the film layers of the capacitor 3 on the top surface of the intermediate layer 1 between the adjacent grooves 30 (for example, the first electrode layer 31, the first capacitor dielectric layer 32, and the second electrode layer 33) are disconnected and kept isolated, so as to improve the flexibility and controllability of the semiconductor structure.

[0056] In some embodiments, the material of the first electrode layer 31, the second electrode layer 33 and / or other electrode layers (for example, the third electrode layer 35 and the fourth electrode layer 37) can be a combination of at least one or more of doped silicon, titanium nitride (TiN), silicon-doped titanium nitride (TiSiN), titanium (Ti), tungsten (W), tungsten nitride (WN), and silicon-doped tungsten nitride (WSiN), and the material of the first capacitor dielectric layer 32 and / or other capacitor dielectric layers (for example, the second capacitor dielectric layer 34 and the third capacitor dielectric layer 36) can be a combination of at least one or more of silicon oxide (SiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), and lead titanate (PZT). In an exemplary embodiment of the present disclosure, the material of the first electrode layer 31, the second electrode layer 33 and / or other electrode layers (for example, the third electrode layer 35, the fourth electrode layer 37) is titanium nitride, and the material of the first capacitor dielectric layer 32 and / or other capacitor dielectric layers (for example, the second capacitor dielectric layer 34, the third capacitor dielectric layer 36) is high dielectric constant (high-K) material.

[0057] The lead-out electrode layer is located in the intermediate layer 1 , is electrically connected to the first electrode layer 31 and / or the second electrode layer 33 , and extends along a preset direction.

[0058] In an exemplary embodiment of the present disclosure, specifically, Figure 5 or Figure 6 As shown, the lead-out electrode layer also extends along the depth direction of the groove 30 in the interposer 1 , and the lead-out electrode layer only includes a first lead-out electrode layer 21 . The first lead-out electrode layer 21 is located between adjacent grooves 30 and is electrically connected to the first electrode layer 31 .

[0059] In the second exemplary embodiment of the present disclosure, specifically, as Figure 8 or Fig. 9 As shown, the lead-out electrode layer also extends along the depth direction of the groove 30 in the intermediate layer 1, and the lead-out electrode layer includes a first lead-out electrode layer 21 and a second lead-out electrode layer 22. The first lead-out electrode layer 21 is located between adjacent grooves 30 and is electrically connected to the first electrode layer 31, and the second lead-out electrode layer 22 is located in the groove 30 and is electrically connected to the second electrode layer 33.

[0060] In the third exemplary embodiment of the present disclosure, specifically, Fig.12 or Fig.13As shown, the extraction electrode layer also extends along the depth direction of the groove 30 in the interposer 1, and the extraction electrode layer includes a first extraction electrode layer 21, a second extraction electrode layer 22, a third extraction electrode layer 23 and a fourth extraction electrode layer 24. The first extraction electrode layer 21 is located between adjacent grooves 30 and is electrically connected to the first electrode layer 31, the second extraction electrode layer 22 is located outside of one outermost groove 30 of the groove array 300 and is electrically connected to the second electrode layer 33, the third extraction electrode layer 23 is located outside of another outermost groove 30 of the groove array 300 and is electrically connected to the third electrode layer 35, and the fourth extraction electrode layer 24 is located in the groove 30 and is electrically connected to the fourth electrode layer 37. It should be noted that the "first outermost" and "second outermost" here are opposite sides of the groove array 300, and the direction of the opposite sides is perpendicular to the preset direction, and the outer side of the groove 30 is the side of the groove 30 located at the first outermost or second outermost away from the adjacent groove 30.

[0061] In the fourth exemplary embodiment of the present disclosure, specifically, as Fig.16 As shown, the lead-out electrode layer is only located in the area of ​​the groove 30 close to the bottom of the groove 30, and the lead-out electrode layer includes a first lead-out electrode layer 21, a second lead-out electrode layer 22 and a third lead-out electrode layer 23. The first lead-out electrode layer 21 covers the upper surface of the second electrode layer 33 located at the bottom of the groove 30 and is electrically connected to the second electrode layer 33. The second lead-out electrode layer 22 covers the upper surface of the third electrode layer 35 located at the bottom of the groove 30 and is electrically connected to the third electrode layer 35. The third lead-out electrode layer 23 covers the upper surface of the fourth electrode layer 37 located at the bottom of the groove 30 and is electrically connected to the fourth electrode layer 37.

[0062] In the fifth exemplary embodiment of the present disclosure, specifically, as Fig.18 As shown, the lead-out electrode layer is only located in the area of ​​the groove 30 near the bottom of the groove 30, and the lead-out electrode layer includes a first lead-out electrode layer 21, a second lead-out electrode layer 22, a third lead-out electrode layer 23 and a fourth lead-out electrode layer 24. The first lead-out electrode layer 21 covers the upper surface of the first electrode layer 31 located at the bottom of the groove 30 and is electrically connected to the first electrode layer 31. The second lead-out electrode layer 22 covers the upper surface of the second electrode layer 33 located at the bottom of the groove 30 and is electrically connected to the second electrode layer 33. The third lead-out electrode layer 23 covers the upper surface of the third electrode layer 35 located at the bottom of the groove 30 and is electrically connected to the third electrode layer 35. The fourth lead-out electrode layer 24 covers the upper surface of the fourth electrode layer 37 located at the bottom of the groove 30 and is electrically connected to the fourth electrode layer 37.

[0063] In the above-mentioned multiple embodiments, the material of the first extraction electrode layer 21, the second extraction electrode layer 22, the third extraction electrode layer 23 and / or the fourth extraction electrode layer 24 can be tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), platinum (Pt), copper (Cu) and / or a combination of one or more of their nitrides. In an exemplary embodiment of the present disclosure, the material of the first extraction electrode layer 21, the second extraction electrode layer 22, the third extraction electrode layer 23 and / or the fourth extraction electrode layer 24 is copper. In the above-mentioned embodiments three, four and five, the capacitor 3 includes an electrode layer greater than 2, and the adjacent electrode layers are separated by a capacitor dielectric layer, thereby forming a plurality of sub-capacitors connected in series in sequence, and the total resistance thereof can be regarded as the parallel connection of the resistances of the sub-capacitors. It can be seen from the calculation formula of the parallel resistance that the total resistance of the capacitor 3 is less than the resistance of any of the sub-capacitors, and as the number of electrode layers increases, the total resistance of the capacitor 3 will become smaller, thereby reducing the delay effect of the capacitor device to a certain extent, so that the capacitor can be charged and discharged quickly.

[0064] In some embodiments, the semiconductor structure further includes: a contact 5 and an interlayer dielectric layer 4, the interlayer dielectric layer 4 covers the top surface of the capacitor 3, and the contact 5 penetrates the interlayer dielectric layer 4 and is electrically connected to the extraction electrode layer and / or the first electrode layer 31 and the second electrode layer 33. Specifically, in some embodiments, the contact 5 can be electrically connected to the extraction electrode layer in a one-to-one contact, and the contact 5 can also be electrically connected to the first electrode layer 31, the second electrode layer 33 and / or other electrode layers without direct contact through the extraction electrode layer. Specifically, a window is formed on the surface of the capacitor 3, and the window opens all or part of the film layer of the capacitor 3 to expose the top surface of the extraction electrode layer and / or part of the top surface of the first electrode layer 31, the second electrode layer 33 or other electrode layers, and the contact 5 directly contacts the extraction electrode layer and / or the first electrode layer 31, the second electrode layer 33 or other electrode layers through the window.

[0065] In some embodiments, the region where the lead-out electrode layer and / or the first electrode layer 31, the second electrode layer 33 or other electrode layers contact the corresponding contact element 5 is located in the region where the groove array 300 is located. Specifically, for example Figure 5 The area where the first extraction electrode layer 21 and the second electrode layer 33 contact the corresponding contact element 5 is located in the area where the groove array 300 is located; Figure 8 The area where the first extraction electrode layer 21 and the second extraction electrode layer 22 contact the corresponding contact element 5 is located in the area where the groove array 300 is located.

[0066] In other embodiments, the region where the lead-out electrode layer and / or the first electrode layer 31, the second electrode layer 33 or other electrode layers contact the corresponding contact element 5 is located outside the groove array 300, and the corresponding lead-out electrode layer also extends outside the region where the groove array 300 is located. Specifically, Fig.16 The areas where the first electrode layer 31, the first extraction electrode layer 21, the second extraction electrode layer 22, and the third extraction electrode layer 23 contact the corresponding contact members 5 are located outside the area where the groove array 300 is located; Fig.18 The areas where the first extraction electrode layer 21 , the second extraction electrode layer 22 , the third extraction electrode layer 23 , and the fourth extraction electrode layer 24 contact the corresponding contact elements 5 are located outside the area where the groove array 300 is located.

[0067] In other embodiments, a portion of the lead-out electrode layer or the region where the electrode layer contacts the corresponding contact 5 is located in the region where the groove array 300 is located, and another portion of the lead-out electrode layer or the region where the electrode layer contacts the corresponding contact 5 is located outside the region where the groove array 300 is located. Specifically, Figure 6 The area where the first extraction electrode layer 21 contacts the corresponding contact element 5 is located outside the area where the groove array 300 is located, and the area where the second electrode layer 33 contacts the corresponding contact element 5 is located within the area where the groove array 300 is located; Fig. 9 The area where the first extraction electrode layer 21 contacts the corresponding contact element 5 is located outside the area where the groove array 300 is located, and the area where the second extraction electrode layer 22 contacts the corresponding contact element 5 is located within the area where the groove array 300 is located; Fig.12 The second extraction electrode layer 22, the third extraction electrode layer 23, Fig.13 The areas where the first extraction electrode layer 21, the second extraction electrode layer 22, and the third extraction electrode layer 23 contact the corresponding contact elements 5 are located outside the area where the groove array 300 is located. Fig.12 The first extraction electrode layer 21, the fourth extraction electrode layer 24, Fig.13 The area where the fourth extraction electrode layer 24 contacts the corresponding contact element 5 is located in the area where the groove array 300 is located.

[0068] In some embodiments, Fig.16 or Fig.18 As shown, the structure where the contact element 5 contacts each extraction electrode layer extending outside the area where the groove array 300 is located is in a stepped morphology, so as to facilitate the contact between each extraction electrode layer and the corresponding contact element 5. Compared with the area where adjacent grooves 30 are arranged more densely in the groove array 300, the area outside the groove array 300 is relatively open, which is conducive to avoiding problems such as short circuits between adjacent contact elements 5 due to limited spatial positions.

[0069] In some embodiments, the material of the contact 5 may be tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), platinum (Pt), copper (Cu) and / or a combination of one or more of their nitrides. In an exemplary embodiment of the present disclosure, the material of the contact 5 is tungsten. In some embodiments, the material of the interlayer dielectric layer 4 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride. In an exemplary embodiment of the present disclosure, the material of the interlayer dielectric layer 4 is silicon oxide.

[0070] In some embodiments, the semiconductor structure further includes: a bottom dielectric layer 6, the bottom dielectric layer 6 is located below the capacitor 3, at least covers the bottom and sidewalls of the groove 30, the bottom dielectric layer 6 is located between the intermediary layer 1 and the first electrode layer 31, in some embodiments, the bottom dielectric layer 6 is also located between the intermediary layer 1 and the first extraction electrode layer 21, and the first electrode layer 31 (and the first extraction electrode layer 21) covers the surface of the bottom dielectric layer 6. The function of the bottom dielectric layer 6 is to prevent the intermediary layer 1 from interfering with the potential of the first electrode layer 31 and the impurities in the intermediary layer 1 from contaminating the material of the first electrode layer 31, thereby affecting the working performance of the capacitor 3. In some embodiments, the material of the bottom dielectric layer 6 can be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon, silicon carbon nitride, and silicon oxycarbonitride. In an exemplary embodiment of the present disclosure, the material of the interlayer dielectric layer 6 is silicon oxide. In other embodiments, when the purity of the silicon-based material in the intermediate layer 1 is relatively high, the semiconductor structure may not have the bottom dielectric layer 6, the first electrode layer 31 may directly contact the inner surface of the groove 30 in the intermediate layer 1, and even the first electrode layer 31 may be directly formed by doping the inner surface of the groove 30.

[0071] In some embodiments, the plurality of grooves 30 extending along the same preset direction are parallel to each other and arranged at intervals in a direction perpendicular to the preset direction. Specifically, the plurality of grooves 30 extending along the X direction or its reverse direction are arranged at intervals in the Y direction or its reverse direction. In some embodiments, the spacing between adjacent grooves 30 is equal.

[0072] In an exemplary embodiment of the present disclosure, referring to Fig. 20As shown, the intermediary layer 1 further includes a first region 11 and a second region 12 disposed adjacently. In the first region 11, the preset direction in which the groove 30 extends is a first direction, that is, in the same direction or in the opposite direction to the X direction. In the second region 12, the preset direction in which the groove 30 extends is a second direction, that is, in the same direction or in the opposite direction to the Y direction. In some embodiments, the intermediary layer 1 further includes a third region 13 and a fourth region 14 disposed adjacently, wherein the third region 13 has the same preset direction as the first region 11, and the fourth region 14 has the same preset direction as the second region 12. The third region 13 is also disposed adjacently to the second region 12 in the Y direction, and the fourth region 14 is also disposed adjacently to the first region 11 in the Y direction. In other embodiments, the intermediary layer 1 may include more regions, but the preset directions in which the grooves 30 extend in the adjacent regions must be perpendicular to each other. The preset directions in different regions are perpendicular to each other, which can effectively solve problems such as stress in the intermediary layer 1.

[0073] The semiconductor structure provided by the present disclosure has a groove array composed of multiple grooves in the intermediary layer, and the capacitor is at least located in the groove, which effectively increases the capacitor area and improves the capacitance, thereby improving the performance of the capacitor. The capacitors in the grooves are connected in series in multiple stages, and their resistance is reduced as a parallel resistance, the delay effect of the circuit is reduced, and the charging and discharging speed of the capacitor is improved. In addition, an extraction electrode layer of a material with a higher conductivity is also provided in the intermediary layer, and the extraction electrode layer also extends in a preset direction, which greatly reduces the on-resistance, and at the same time, the extraction electrode layer is connected to the first electrode layer, the second electrode layer and / or other electrode layers in the contact or capacitor in a one-to-one correspondence, which can further meet the fast charging and discharging requirements of the capacitor. The extraction electrode layer extends outside the groove array, and the area where the contact and the extraction electrode layer contact is located outside the groove array, avoiding the problem of short circuits between adjacent contacts caused by space limitations in the grooves (capacitors) with high density in the groove array, thereby improving the reliability of the device. The preset directions of the groove extensions in adjacent areas in the intermediary layer are perpendicular to each other, which effectively solves the problems of stress in the intermediary layer. In summary, the semiconductor structure provided by the present invention has the advantages of large capacity, fast charging and discharging, high integration, and high reliability, thereby greatly improving the device performance of the DTC structure. Its arrangement method also has a good improvement effect on the stress problem in the intermediate layer.

[0074] Based on the above semiconductor structure, the present disclosure also provides a method for preparing a semiconductor structure, including: providing an intermediate layer 1, such as Figure 1 As shown, Figure 1 (a) is a top view of the intermediate layer 1 in the opposite direction of the Z direction. Figure 1 (b) along Figure 1 (a) is a schematic cross-sectional view along the dotted line AA′, where the cross-section along the dotted line AA′ is perpendicular to the top surface of the interposer 1 .

[0075] In an exemplary embodiment of the present disclosure, the interposer 1 adopts a silicon interposer. The material of the silicon interposer can be at least one of the following materials: silicon, germanium, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI) and other semiconductor materials or a combination of III-V materials and organic materials.

[0076] Next, a groove array 300 consisting of a plurality of grooves 30 extending from the top surface of the interposer 1 toward the inside of the interposer 1 and an extraction electrode layer are formed in the interposer 1. In an exemplary embodiment 1 of the present disclosure, the extraction electrode layer only includes the first extraction electrode layer 21. Figure 2 and Figure 3 As shown, first, a first extraction electrode layer 21 extending along a preset direction is formed in the interposer 1; then, grooves 30 are formed on both sides of the first extraction electrode 21, and a plurality of grooves 30 extend along the preset direction and are arranged at intervals perpendicular to the preset direction to form a groove array 300. Both the first extraction electrode layer 21 and the grooves 30 extend from the top surface of the interposer 1 toward the depth direction of the inside of the interposer 1, wherein Figure 2 (a) / 3(a) is a top view toward the intermediate layer 1 in the opposite direction of the Z direction. Figure 2 (b) / 3(b) is along Figure 2 (a) / 3(a) is a schematic cross-sectional view of the dotted line A-A' direction, where the cross section along the dotted line A-A' direction is perpendicular to the top surface of the interposer 1. Specifically, Figure 2 As shown, first, an electrode groove with a certain depth is formed by etching from the surface of the intermediary layer 1 to the inside of the intermediary layer 1 (not shown in the figure), and an extraction electrode material is filled in the electrode groove to form a first extraction electrode layer 21. The first extraction electrode layer 21 extends in a depth direction perpendicular to the plane where the top surface of the intermediary layer 1 is located and toward the inside of the intermediary layer 1. The depth direction is opposite to the Z direction in the figure. On the plane parallel to the top surface of the intermediary layer 1, the first extraction electrode layer 21 extends in a preset direction. Figure 2 In the example, the preset direction is the X direction or its reverse direction. Figure 3As shown, on both sides of the first extraction electrode layer 21, grooves 30 with a certain depth are etched from the surface of the intermediary layer 1 to the inside of the intermediary layer 1, and the grooves 30 also extend along the preset direction. In some embodiments, the depth dimension of the groove 30 in the depth direction and / or the length dimension along the preset direction are also the same as those of the first extraction electrode layer 21. In other embodiments, the groove 30 is larger or smaller than the depth dimension of the first extraction electrode layer 21 in the depth direction and / or the length dimension along the preset direction. In some embodiments, the cross-sectional schematic diagram of the groove 30 along the depth direction is rectangular, that is, the opening size of the groove 30 is substantially consistent with the bottom size. In other embodiments, the cross-sectional schematic diagram of the groove 30 is trapezoidal, for example, the opening size of the groove 30 is larger than the bottom size, or the bottom size of the groove 30 is larger than the opening size.

[0077] In some embodiments, the surface of the interposer 1 may be etched by a photolithography process to form an electrode groove (not shown) or a groove 30. Specifically, a photoresist mask layer may be formed on the surface of the interposer 1, and a pattern of the electrode groove (not shown) or the groove 30 may be formed in the photoresist mask layer by exposure and development, and then dry etching is performed to etch the interposer 1 along the pattern to form the electrode groove (not shown) or the groove 30. In some embodiments, before applying the photoresist mask layer, an anti-reflection layer and a hard mask layer (not shown) are formed on the surface of the interposer 1, and both are removed after the electrode groove (not shown) or the groove 30 is formed. In some embodiments, the groove 30 may be formed on both sides of the first extraction electrode layer 21 by self-aligned etching after the first extraction electrode layer 21 is formed, that is, by adjusting the high material selectivity of the first extraction electrode layer 21 and the interposer 1 so as to selectively etch and form.

[0078] Then, a capacitor 3 including at least a first electrode layer 31, a first capacitor dielectric layer 32 and a second electrode layer 33 stacked in sequence is formed in the groove 30, wherein the first capacitor dielectric layer 32 covers the surface of the first electrode layer 31, and the second electrode layer 33 covers the surface of the first capacitor dielectric layer 32. Figure 4 As shown, Figure 4 (a) is a top view of the intermediate layer 1 in the opposite direction of the Z direction. Figure 4 (b) along Figure 4 (a) Schematic diagram of the cross section along the dotted line A-A'. Figure 4 (c) along Figure 4 (b) is a schematic cross-sectional view along the dotted line BB', wherein the cross section along the dotted line AA' is perpendicular to the top surface of the interposer 1 , and the cross section along the dotted line BB' is parallel to the top surface of the interposer 1 .

[0079] In some embodiments, the first extraction electrode layer 21 extends along the depth direction of the groove 30 in the interposer 1, and the first electrode layer 31 covers the surface of the first extraction electrode layer 21, and is in direct contact with and electrically connected to the first extraction electrode layer 21, such as Figure 5 As shown in (b), the capacitor 3 located in each groove 30 is spaced apart from the first extraction electrode layer 21 in a direction perpendicular to the preset direction. Figure 5 The preset direction is the X direction or its opposite direction, and the direction perpendicular to the preset direction is the Y direction or its opposite direction. The first electrode layer 31 in the capacitor 3 also covers the inner wall and bottom surface of the groove 30. In some embodiments, the capacitor 3 also extends to cover the top surface of the intermediary layer 1.

[0080] Next, after forming the capacitor 3, an interlayer dielectric layer 4 and a contact 5 are formed on the intermediate layer 1. Specifically, an interlayer dielectric layer 4 is first formed on the intermediate layer 1 to at least cover the top surface of the capacitor 3, and then a contact 5 is formed to penetrate the interlayer dielectric layer 4 to contact and electrically connect with the lead-out electrode layer or the electrode layer in the capacitor 3 (for example, the first electrode layer, the second electrode layer or other electrode layers).

[0081] In an exemplary embodiment of the present disclosure, Figure 5 or Figure 6 As shown, the contact member 5 penetrates the interlayer dielectric layer 4, and contacts and electrically connects with the second electrode layer 33 of the capacitor 3 in each groove 30, and directly contacts and electrically connects with the first extraction electrode layer 21 between adjacent grooves 30. Before forming the interlayer dielectric layer 4 to cover the top surface of the capacitor 3, it also includes: forming a window in the film layer of the capacitor 3 located on the top of the first extraction electrode layer 21 to expose the top of the first extraction electrode layer 21, and the subsequently formed interlayer dielectric layer 4 fills the window and the contact member 5 penetrates the interlayer dielectric layer 4 through the window to contact the top of the first extraction electrode layer 21. In some embodiments, as Figure 5 As shown, the area where the first extraction electrode layer 21 and the second electrode layer 33 contact the corresponding contact element 5 is located in the area where the groove array 300 is located; in other embodiments, such as Figure 6 As shown, the area where the second electrode layer 33 contacts the corresponding contact element 5 is located within the area where the groove array 300 is located, and the area where the first lead-out electrode layer 21 contacts the corresponding contact element 5 is located outside the area where the groove array 300 is located. Accordingly, the first lead-out electrode layer 21 also extends outside the groove array 300.

[0082] In the second exemplary embodiment of the present disclosure, Figure 7As shown, before forming the interlayer dielectric layer 4 and the contact member 5 on the intermediary layer 1, the method further includes: after forming the second electrode layer 33, the capacitor 3 does not fill the groove 30, then, forming the second extraction electrode layer 22 in the groove 30, covering the surface of the second electrode layer 33 and filling the groove 30, and the second extraction electrode layer 22 is in direct contact with and electrically connected to the second electrode layer 33. Then, as Figure 8 or Fig. 9 As shown, the contact member 5 penetrates the interlayer dielectric layer 4, and directly contacts and electrically connects with the second extraction electrode layer 22 in each groove 30, and directly contacts and electrically connects with the first extraction electrode layer 21 between adjacent grooves 30. Before forming the interlayer dielectric layer 4 to cover the top surface of the capacitor 3, it also includes: forming a window in the film layer of the capacitor 3 located on the top of the first extraction electrode layer 21 to expose the top of the first extraction electrode layer 21, and the subsequently formed interlayer dielectric layer 4 fills the window and the contact member 5 penetrates the interlayer dielectric layer 4 through the window to contact the top of the first extraction electrode layer 21. In some embodiments, as Figure 8 As shown, the area where the first extraction electrode layer 21 and the second extraction electrode layer 22 contact the corresponding contact element 5 is located in the area where the groove array 300 is located; in other embodiments, such as Fig. 9 As shown, the area where the second lead-out electrode layer 22 contacts the corresponding contact element 5 is located within the area where the groove array 300 is located, and the area where the first lead-out electrode layer 21 contacts the corresponding contact element 5 is located outside the area where the groove array 300 is located. Accordingly, the first lead-out electrode layer 21 also extends outside the groove array 300.

[0083] In the third exemplary embodiment of the present disclosure, Figure 10 to Figure 11As shown, before forming the groove 30, a first extraction electrode layer 21 is formed in the intermediary layer 1, and subsequently grooves 30 are formed on both sides of the first extraction electrode layer 21, the first extraction electrode layer 21 is located between adjacent grooves 30, and the first electrode layer 31 formed subsequently covers the surface of the first electrode layer 31 and contacts and is electrically connected to the first electrode layer 31. After forming the first extraction electrode layer 21 and the groove 30, a capacitor 3 is formed in the groove 30. In addition to the first electrode layer 31, the first capacitor dielectric layer 32 and the second electrode layer 33, the capacitor 3 also includes a second capacitor dielectric layer 34, a third electrode layer 35, a third capacitor dielectric layer 36 and a fourth electrode layer 37 stacked in sequence. The second capacitor dielectric layer 34 covers the surface of the second electrode layer 33, the third electrode layer 35 covers the surface of the second capacitor dielectric layer 34, the third capacitor dielectric layer 36 covers the surface of the third electrode layer 35, and the fourth electrode layer 37 covers the surface of the third capacitor dielectric layer 36. In addition to the first extraction electrode layer 21 and the second extraction electrode layer 22, the extraction electrode layer also includes a third extraction electrode layer 23 and a fourth extraction electrode layer 24. Specifically, after forming the second electrode layer 33 and before forming the second capacitor dielectric layer 34, the second extraction electrode layer 22 is formed, and the second extraction electrode layer 22 is located outside the first outermost groove 30 in the groove array 300 and is electrically connected to the second electrode layer 33; after forming the third electrode layer 35 and before forming the third capacitor dielectric layer 36, the third extraction electrode layer 23 is formed, and the third extraction electrode layer 23 is located outside the second outermost groove 30 in the groove array 300 and is electrically connected to the third electrode layer 35; after forming the fourth electrode layer 37, the fourth extraction electrode layer 24 is formed in the groove 30 to fill the groove 30 and is electrically connected to the fourth electrode layer 37. More specifically, after forming the first electrode layer 31 and before forming the first capacitor dielectric layer 32, an extraction groove 30' is formed on the outer side of the first outermost groove 30 in the groove array 300, and then the first capacitor dielectric layer 32 and the second electrode layer 33 stacked in sequence are formed in the extraction groove 30', and the second extraction electrode layer 22 covers the surface of the second electrode layer 33 and fills the extraction groove 30'; after forming the second electrode layer 33 and before forming the second capacitor dielectric layer 34, another extraction groove 30' is formed on the outer side of the second outermost groove 30 in the groove array 300, and then the second capacitor dielectric layer 34 and the third electrode layer 35 stacked in sequence are formed in the extraction groove 30', and the third extraction electrode layer 23 covers the surface of the third electrode layer 35 and fills the extraction groove 30'. It should be noted that the "first outermost side" and the "second outermost side" here are the opposite sides of the groove array 300, and the directions of the two opposite sides are perpendicular to the preset direction. The outer side of the groove 30 is the side of the groove 30 located at the first outermost side or the second outermost side away from the groove 30 adjacent to it.

[0084] Then, if Fig.12 or Fig.13 As shown, an interlayer dielectric layer 4 and a contact member 5 are formed on the interlayer 1, the interlayer dielectric layer 4 at least covers the top surface of the capacitor 3, and the contact member 5 penetrates the interlayer dielectric layer 4, and is directly in contact with and electrically connected to the first lead electrode layer 21 between adjacent grooves 30, directly in contact with and electrically connected to the second lead electrode layer 22 and the third lead electrode layer 23 in each lead groove 30', and directly in contact with and electrically connected to the fourth lead electrode layer 24 in each groove 30. Before forming the interlayer dielectric layer 4 to cover the top surface of the capacitor 3, the method further includes: forming a window in the film layer of the capacitor 3 located on the top of the first extraction electrode layer 21, the second extraction electrode layer 22 and the third extraction electrode layer 23 to expose the top of the first extraction electrode layer 21, the second extraction electrode layer 22 and the third extraction electrode layer 23, and the interlayer dielectric layer 4 formed subsequently fills the window and the contact member 5 passes through the window and penetrates the interlayer dielectric layer 4 to contact the top of the first extraction electrode layer 21, the second extraction electrode layer 22 and the third extraction electrode layer 23 respectively. In some embodiments, as Fig.12 As shown, the areas where the first extraction electrode layer 21 and the fourth extraction electrode layer 24 contact the corresponding contact members 5 are located in the area where the groove array 300 is located, and the areas where the second extraction electrode layer 22 and the third extraction electrode layer 23 contact the corresponding contact members 5 are located outside the area where the groove array 300 is located (located in the extraction groove 30' outside the groove array 300); in other embodiments, such as Fig.13 As shown, only the area where the fourth lead-out electrode layer 24 contacts the corresponding contact element 5 is located within the area where the groove array 300 is located, and the areas where the first lead-out electrode layer 21, the second lead-out electrode layer 22 and the third lead-out electrode layer 23 contact the corresponding contact element 5 are located outside the area where the groove array 300 is located. Accordingly, the first lead-out electrode layer 21, the second lead-out electrode layer 22 and the third lead-out electrode layer 23 also extend outside the groove array 300.

[0085] In the fourth exemplary embodiment of the present disclosure, Fig.14 and Fig.15As shown, a groove 30 is first formed in the intermediary layer 1, and then a capacitor 3 including a first electrode layer 31, a first capacitor dielectric layer 32, a second electrode layer 33, a second capacitor dielectric layer 34, a third electrode layer 35, a third capacitor dielectric layer 36 and a fourth electrode layer 37 stacked in sequence is formed in the intermediary layer 1. The first capacitor dielectric layer 32 covers the surface of the first electrode layer 31, the second electrode layer 33 covers the surface of the first capacitor dielectric layer 32, the second capacitor dielectric layer 34 covers the surface of the second electrode layer 33, the third electrode layer 35 covers the surface of the second capacitor dielectric layer 34, the third capacitor dielectric layer 36 covers the surface of the third electrode layer 35, and the fourth electrode layer 37 covers the surface of the third capacitor dielectric layer 36. Among them, after forming the second electrode layer 33 and before forming the second capacitor dielectric layer 34, a first lead-out electrode layer 21 is formed in the groove 30, and the first lead-out electrode layer 21 only covers the upper surface of the portion of the second electrode layer 33 located at the bottom of the groove 30 and is in direct contact with and electrically connected to the second electrode layer 33; after forming the third electrode layer 35 and before forming the third capacitor dielectric layer 36, a second lead-out electrode layer 22 is formed in the groove 30, and the second lead-out electrode layer 22 only covers the upper surface of the portion of the third electrode layer 35 located at the bottom of the groove 30 and is in direct contact with and electrically connected to the third electrode layer 35; after forming the fourth electrode layer 37, a third lead-out electrode layer 23 is formed in the groove to only cover the upper surface of the portion of the fourth electrode layer 37 located at the bottom of the groove 30 and is in direct contact with and electrically connected to the fourth electrode layer 37.

[0086] Then, if Fig.16 As shown, an interlayer dielectric layer 4 and a contact 5 are formed on the interlayer 1, the interlayer dielectric layer 4 at least covers the top surface of the capacitor 3, and the contact 5 penetrates the interlayer dielectric layer 4, and is directly in contact with and electrically connected to the first electrode layer 31, the first lead electrode layer 21, the second lead electrode layer 22, and the third lead electrode layer 23 respectively. Before the interlayer dielectric layer 4 is formed to cover the top surface of the capacitor 3, it also includes: forming a window in the film layer of the capacitor 3 located at the top of the first electrode layer 31 extending to the top surface of the interlayer 1 to expose part of the top of the first electrode layer 31, and the contact 5 formed subsequently penetrates the interlayer dielectric layer 4 through the window and is in direct contact with the first electrode layer 31; and etching and trimming one end of the groove array 300 to obtain the second boundary 300b of the groove array 300, including etching and removing the film layer of the capacitor 3 outside the second boundary 300b, and only retaining part of the film layer of the capacitor 3 located at the bottom of the groove 30, and the first lead electrode layer 21, the second lead electrode layer 22, and the third lead electrode layer 23 are in a stepped shape, as shown in FIG. Fig.16As shown in (c), the contact member 5 formed subsequently penetrates the interlayer dielectric layer 4 and directly contacts the first lead-out electrode layer 21, the second lead-out electrode layer 22 and the third lead-out electrode layer 23 in a stepped shape outside the groove array 300. In some embodiments, the contact member 5 also penetrates the second capacitor dielectric layer 34 located on the top surface of the first lead-out electrode layer 21 to contact and be electrically connected to the first lead-out electrode layer 21, and penetrates the third capacitor dielectric layer 36 located on the top surface of the second lead-out electrode layer 22 to contact and be electrically connected to the second lead-out electrode layer 22. In some embodiments, the film layers of the capacitor 3 on the top surface of the interlayer 1 between adjacent grooves 30 are connected as a whole, as shown in FIG. Fig.16 In some other embodiments, the film layers of the capacitor 3 on the top surface of the interlayer 1 between adjacent grooves 30 are disconnected and isolated from each other, such as Fig.16 (d) as shown.

[0087] In an exemplary embodiment 5 of the present disclosure, as Fig.14 and Fig.17 As shown, a groove 30 is first formed in the intermediary layer 1, and then a capacitor 3 including a first electrode layer 31, a first capacitor dielectric layer 32, a second electrode layer 33, a second capacitor dielectric layer 34, a third electrode layer 35, a third capacitor dielectric layer 36 and a fourth electrode layer 37 stacked in sequence is formed in the intermediary layer 1. The first capacitor dielectric layer 32 covers the surface of the first electrode layer 31, the second electrode layer 33 covers the surface of the first capacitor dielectric layer 32, the second capacitor dielectric layer 34 covers the surface of the second electrode layer 33, the third electrode layer 35 covers the surface of the second capacitor dielectric layer 34, the third capacitor dielectric layer 36 covers the surface of the third electrode layer 35, and the fourth electrode layer 37 covers the surface of the third capacitor dielectric layer 36. Before or after forming the first electrode layer 31, a first extraction electrode layer 21 is formed in the groove 30, the first extraction electrode layer 21 only covers the lower surface or upper surface of the portion of the first electrode layer 31 located at the bottom of the groove 30 and is in direct contact with and electrically connected to the first electrode layer 31; after forming the second electrode layer 33 and before forming the second capacitor dielectric layer 34, a second extraction electrode layer 22 is formed in the groove 30, the second extraction electrode layer 22 only covers the upper surface of the portion of the second electrode layer 33 located at the bottom of the groove 30 and is in direct contact with and electrically connected to the second electrode layer 33 is directly in contact with and electrically connected to; after the third electrode layer 35 is formed and before the third capacitor dielectric layer 36 is formed, a third lead electrode layer 23 is formed in the groove 30, and the third lead electrode layer 23 only covers the upper surface of the portion of the third electrode layer 35 located at the bottom of the groove 30 and is directly in contact with and electrically connected to the third electrode layer 35; after the fourth electrode layer 37 is formed, a fourth lead electrode layer 24 is formed in the groove and only covers the upper surface of the portion of the fourth electrode layer 37 located at the bottom of the groove 30 and is directly in contact with and electrically connected to the fourth electrode layer 37.

[0088] Then, if Fig.18As shown, an interlayer dielectric layer 4 and a contact 5 are formed on the interlayer 1, the interlayer dielectric layer 4 at least covers the top surface of the capacitor 3, and the contact 5 penetrates the interlayer dielectric layer 4, and is directly in contact with and electrically connected to the first extraction electrode layer 21, the second extraction electrode layer 22, the third extraction electrode layer 23 and the fourth extraction electrode layer 24 respectively. Before the interlayer dielectric layer 4 is formed to cover the top surface of the capacitor 3, it also includes: etching and trimming one end of the groove array 300 to obtain a second boundary 300b of the groove array 300, including etching and removing the film layer of the capacitor 3 outside the second boundary 300b, and only retaining a part of the film layer of the capacitor 3 located at the bottom of the groove 30, and the first extraction electrode layer 21, the second extraction electrode layer 22, the third extraction electrode layer 23 and the fourth extraction electrode layer 24 are in a stepped shape, as shown in FIG. Fig.18 As shown in (c), the contact member 5 formed subsequently penetrates the interlayer dielectric layer 4 and directly contacts the first lead-out electrode layer 21, the second lead-out electrode layer 22, the third lead-out electrode layer 23 and the fourth lead-out electrode layer 24 in a stepped shape outside the groove array 300. In some embodiments, the contact member 5 also penetrates the first capacitor dielectric layer 33 located on the top surface of the first lead-out electrode layer 21 to contact and be electrically connected to the first lead-out electrode layer 21, penetrates the second capacitor dielectric layer 34 located on the top surface of the second lead-out electrode layer 22 to contact and be electrically connected to the second lead-out electrode layer 22, and penetrates the third capacitor dielectric layer 36 located on the top surface of the third lead-out electrode layer 23 to contact and be electrically connected to the third lead-out electrode layer 23.

[0089] In the sixth exemplary embodiment of the present disclosure, Fig.19 As shown, a bottom dielectric layer 6 is first formed in the intermediary layer 1, and then a groove 30 is formed in the bottom dielectric layer 6. In some embodiments, a first lead electrode layer 21 is formed in the bottom dielectric layer 6 before forming the groove 30, and then a capacitor 3 is formed in the groove 30. The bottom dielectric layer 6 is at least located between the first electrode layer 31 of the capacitor 3 and the intermediary layer 1 (as well as between the first lead electrode layer 21 and the intermediary layer 1).

[0090] In the above-mentioned multiple embodiments, the materials of the first electrode layer 31, the second electrode layer 33, the third electrode layer 35 and the fourth electrode layer 37 can be a combination of at least one or more of doped silicon, titanium nitride (TiN), silicon-doped titanium nitride (TiSiN), titanium (Ti), tungsten (W), tungsten nitride (WN), and silicon-doped tungsten nitride (WSiN); the materials of the first capacitor dielectric layer 32, the second capacitor dielectric layer 34 and the third capacitor dielectric layer 36 can be silicon oxide (SiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), lead titanate (PZT) The materials of the first extraction electrode layer 21, the second extraction electrode layer 22, the third extraction electrode layer 23 and the fourth extraction electrode layer 24 can be a combination of one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), platinum (Pt), copper (Cu) and / or their nitrides; the material of the contact 5 can be a combination of one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), platinum (Pt), copper (Cu) and / or their nitrides; the materials of the interlayer dielectric layer 4 and the bottom dielectric layer 6 can be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride. In an exemplary embodiment of the present disclosure, the material of the first electrode layer 31, the second electrode layer 33, the third electrode layer 35 and the fourth electrode layer 37 is titanium nitride, the material of the first capacitor dielectric layer 32, the second capacitor dielectric layer 34 and the third capacitor dielectric layer 36 is a high dielectric constant (high-K) material, the material of the first lead electrode layer 21, the second lead electrode layer 22, the third lead electrode layer 23 and / or the fourth lead electrode layer 24 is copper, the material of the contact 5 is tungsten, and the material of the interlayer dielectric layer 4 and the bottom dielectric layer 6 is silicon oxide.

[0091] In some embodiments, the formation method of each electrode layer and each capacitor dielectric layer, each lead electrode layer and the contact 5 in the capacitor 3 can adopt at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and sputtering. In some embodiments, the deposition method of the interlayer dielectric layer 4 and the bottom dielectric layer 6 can adopt at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), in situ water vapor growth (ISSG), thermal oxidation growth method.

[0092] In an exemplary embodiment of the present disclosure, a semiconductor device is also provided. Fig.21As shown, at least the semiconductor structure 101 in any of the aforementioned embodiments and the chip 201 located on the semiconductor structure 101 are included, wherein the chip 201 is electrically connected to the semiconductor structure 101 through solder ball bumps 401 and / or pads (not shown). In other embodiments, the chip 201 and the semiconductor structure can also be electrically connected by wire bonding. In some embodiments, the interposer 1 in the semiconductor structure 101 also includes interconnect structures such as a redistribution layer 1011 (Re-distribution Layer, RDL) and a through silicon via 1012 (TSV). In some embodiments, the chip 201 can be a plurality of memory chips stacked on each other, such as a DRAM chip or a NAND FLASH chip, and the chips 201 can be interconnected by bumps or hybrid bonding and through silicon vias 202 (TSV). In other embodiments, the chip 201 can also be a processor chip or an image sensor chip. In some embodiments, the semiconductor device further includes: a substrate 301, on which the semiconductor structure 101 is located, and the substrate 301 and the semiconductor structure 101 can also be electrically connected through solder ball bumps 402. In some embodiments, the substrate 301 can be a glass substrate, an organic substrate or an insulating substrate, and the substrate 301 also includes solder ball bumps 403 below for connecting to a mainboard or other PCB.

[0093] It should be noted that the semiconductor structure or semiconductor device in the embodiment of the present disclosure can be used to manufacture a stacked packaging structure of a memory chip, and can also be used to manufacture other devices that require a capacitor structure to be manufactured in an intermediate layer, and no excessive restrictions are made here.

[0094] The various semiconductor structures shown in this specific embodiment can be used for electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be realized by the following memories: dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), magnetic random access memory (MRAM) or resistive random access memory (RRAM), flash memory (FLASH) or some integrated storage products or systems on chip.

[0095] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: An interposer, wherein the interposer has a groove array consisting of a plurality of grooves extending from the top surface of the interposer toward the inside of the interposer, and the grooves also extend in a preset direction parallel to the top surface of the interposer; A capacitor is located in the groove, the capacitor at least comprising a first electrode layer, a first capacitor dielectric layer and a second electrode layer stacked in sequence, the first capacitor dielectric layer covers a surface of the first electrode layer, and the second electrode layer covers a surface of the first capacitor dielectric layer; The lead-out electrode layer is located in the intermediate layer, the lead-out electrode layer is electrically connected to the first electrode layer and / or the second electrode layer, and extends along the preset direction.

2. The semiconductor structure according to claim 1, characterized in that: The extraction electrode layer also extends along the depth direction of the groove in the intermediate layer. The extraction electrode layer only includes a first extraction electrode layer. The first extraction electrode layer is located between adjacent grooves and is electrically connected to the first electrode layer.

3. The semiconductor structure according to claim 1, characterized in that: The lead-out electrode layer also extends along the depth direction of the groove in the intermediate layer, and the lead-out electrode layer includes a first lead-out electrode layer and a second lead-out electrode layer. The first lead-out electrode layer is located between adjacent grooves and is electrically connected to the first electrode layer, and the second lead-out electrode layer is located in the groove and is electrically connected to the second electrode layer.

4. The semiconductor structure according to claim 1, characterized in that: The capacitor further includes a second capacitor dielectric layer, a third electrode layer, a third capacitor dielectric layer and a fourth electrode layer stacked in sequence, the second capacitor dielectric layer covers the surface of the second electrode layer, the third electrode layer covers the surface of the second capacitor dielectric layer, the third capacitor dielectric layer covers the surface of the third electrode layer, and the fourth electrode layer covers the surface of the third capacitor dielectric layer; The extraction electrode layer also extends along the depth direction of the groove in the interposer, and the extraction electrode layer includes a first extraction electrode layer, a second extraction electrode layer, a third extraction electrode layer and a fourth extraction electrode layer, the first extraction electrode layer is located between adjacent grooves and is electrically connected to the first electrode layer, the second extraction electrode layer is located outside the first outermost groove of the groove array and is electrically connected to the second electrode layer, the third extraction electrode layer is located outside the second outermost groove of the groove array and is electrically connected to the third electrode layer, and the fourth extraction electrode layer is located in the groove and is electrically connected to the fourth electrode layer; Among them, the first outermost side and the second outermost side are two opposite sides of the groove array, the directions of the two opposite sides are perpendicular to the preset direction, and the outer side of the groove is the side of the groove located at the first outermost side or the second outermost side away from the groove adjacent to it.

5. The semiconductor structure according to claim 1, characterized in that: The capacitor further includes a second capacitor dielectric layer, a third electrode layer, a third capacitor dielectric layer and a fourth electrode layer stacked in sequence, the second capacitor dielectric layer covers the surface of the second electrode layer, the third electrode layer covers the surface of the second capacitor dielectric layer, the third capacitor dielectric layer covers the surface of the third electrode layer, and the fourth electrode layer covers the surface of the third capacitor dielectric layer; The lead-out electrode layer is only located in the area of ​​the groove close to the bottom of the groove, and the lead-out electrode layer includes a first lead-out electrode layer, a second lead-out electrode layer and a third lead-out electrode layer. The first lead-out electrode layer covers the upper surface of the second electrode layer located at the bottom of the groove and is electrically connected to the second electrode layer. The second lead-out electrode layer covers the upper surface of the third electrode layer located at the bottom of the groove and is electrically connected to the third electrode layer. The third lead-out electrode layer covers the upper surface of the fourth electrode layer located at the bottom of the groove and is electrically connected to the fourth electrode layer.

6. The semiconductor structure according to claim 1, characterized in that The capacitor further includes a second capacitor dielectric layer, a third electrode layer, a third capacitor dielectric layer and a fourth electrode layer stacked in sequence, the second capacitor dielectric layer covers the surface of the second electrode layer, the third electrode layer covers the surface of the second capacitor dielectric layer, the third capacitor dielectric layer covers the surface of the third electrode layer, and the fourth electrode layer covers the surface of the third capacitor dielectric layer; The lead-out electrode layer is only located in the area of ​​the groove close to the bottom of the groove, and the lead-out electrode layer includes a first lead-out electrode layer, a second lead-out electrode layer, a third lead-out electrode layer and a fourth lead-out electrode layer. The first lead-out electrode layer covers the upper surface of the portion of the first electrode layer located at the bottom of the groove and is electrically connected to the first electrode layer, the second lead-out electrode layer covers the upper surface of the portion of the second electrode layer located at the bottom of the groove and is electrically connected to the second electrode layer, the third lead-out electrode layer covers the upper surface of the portion of the third electrode layer located at the bottom of the groove and is electrically connected to the third electrode layer, and the fourth lead-out electrode layer covers the upper surface of the portion of the fourth electrode layer located at the bottom of the groove and is electrically connected to the fourth electrode layer.

7. The semiconductor structure according to claim 1, characterized in that: Also includes: A contact member and an interlayer dielectric layer, wherein the interlayer dielectric layer covers the top surface of the capacitor, and the contact member penetrates the interlayer dielectric layer and is electrically connected to the lead-out electrode layer and / or the first electrode layer and the second electrode layer.

8. The semiconductor structure according to claim 7, characterized in that: The area where the contact element is electrically connected to the extraction electrode layer and / or the first electrode layer and the second electrode layer is located outside the groove array.

9. The semiconductor structure according to claim 1, characterized in that: Also includes: The bottom dielectric layer at least covers the bottom and sidewalls of the trench. The bottom dielectric layer is located between the intermediate layer and the first electrode layer. The first electrode layer covers the surface of the bottom dielectric layer.

10. The semiconductor structure according to claim 1, wherein: The interposer further comprises a first region and a second region which are adjacently arranged, wherein in the first region, the preset direction is a first direction, and in the second region, the preset direction is a second direction, and the first direction and the second direction are perpendicular to each other; In the first region, a plurality of the grooves extend along the first direction and are arranged at intervals along the second direction. In the second region, a plurality of the grooves extend along the second direction and are arranged at intervals along the first direction.

11. A method for manufacturing a semiconductor structure, characterized in that: include: Provide an intermediary layer; Forming a plurality of groove arrays and a lead-out electrode layer in the interposer layer, which are composed of grooves extending from the top surface of the interposer layer toward the inside of the interposer layer, wherein the grooves also extend in a preset direction parallel to the top surface of the interposer layer; A capacitor is formed in the groove, which includes at least a first electrode layer, a first capacitor dielectric layer, and a second electrode layer stacked in sequence, wherein the first capacitor dielectric layer covers a surface of the first electrode layer, and the second electrode layer covers a surface of the first capacitor dielectric layer; Wherein, the lead-out electrode layer is electrically connected to the first electrode layer and / or the second electrode layer, and extends along the preset direction.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: Before forming the groove, forming the extraction electrode layer in the intermediary layer, and subsequently forming the groove on both sides of the extraction electrode layer; The lead-out electrode layer further extends along the depth direction of the groove in the intermediate layer, and the lead-out electrode layer is located between adjacent grooves and is electrically connected only to the first electrode layer.

13. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The extraction electrode layer includes a first extraction electrode layer and a second extraction electrode layer. Before forming the groove, the first extraction electrode layer is formed in the intermediary layer, and then the groove is formed on both sides of the first extraction electrode layer. After forming the capacitor, the second extraction electrode layer is formed in the groove. The lead-out electrode layer also extends along the depth direction of the groove in the intermediate layer, the first lead-out electrode layer is located between adjacent grooves and electrically connected to the first electrode layer, and the second lead-out electrode layer is electrically connected to the second electrode layer.

14. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The forming of the capacitor further comprises, after forming the second electrode layer, forming a second capacitor dielectric layer, a third electrode layer, a third capacitor dielectric layer and a fourth electrode layer stacked in sequence in the groove, wherein the second capacitor dielectric layer covers the surface of the second electrode layer, the third electrode layer covers the surface of the second capacitor dielectric layer, the third capacitor dielectric layer covers the surface of the third electrode layer, and the fourth electrode layer covers the surface of the third capacitor dielectric layer; The extraction electrode layer includes a first extraction electrode layer, a second extraction electrode layer, a third extraction electrode layer and a fourth extraction electrode layer. Before forming the grooves, the first extraction electrode layer is formed in the intermediary layer, and subsequently the grooves are formed on both sides of the first extraction electrode layer. The first extraction electrode layer is located between adjacent grooves and is electrically connected to the first electrode layer. After forming the second electrode layer and before forming the second capacitor dielectric layer, the second extraction electrode layer is formed. The second extraction electrode layer is located outside the first outermost groove in the groove array and is electrically connected to the second electrode layer. After forming the third electrode layer and before forming the third capacitor dielectric layer, the third extraction electrode layer is formed. The third extraction electrode layer is located outside the second outermost groove in the groove array and is electrically connected to the third electrode layer. After forming the fourth electrode layer, the fourth extraction electrode layer is formed in the grooves and is electrically connected to the fourth electrode layer. In which, the lead-out electrode layer also extends along the depth direction of the groove in the intermediate layer, the first outermost side and the second outermost side are the opposite sides of the groove array, the directions of the opposite two sides are perpendicular to the preset direction, and the outer side of the groove is the side of the groove located at the first outermost side or the second outermost side away from the groove adjacent to it.

15. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The forming of the capacitor further comprises, after forming the second electrode layer, forming a second capacitor dielectric layer, a third electrode layer, a third capacitor dielectric layer and a fourth electrode layer stacked in sequence in the groove, wherein the second capacitor dielectric layer covers the surface of the second electrode layer, the third electrode layer covers the surface of the second capacitor dielectric layer, the third capacitor dielectric layer covers the surface of the third electrode layer, and the fourth electrode layer covers the surface of the third capacitor dielectric layer; The lead-out electrode layer includes a first lead-out electrode layer, a second lead-out electrode layer and a third lead-out electrode layer. After forming the second electrode layer and before forming the second capacitor dielectric layer, the first lead-out electrode layer is formed in the groove, the first lead-out electrode layer covers the upper surface of the second electrode layer located at the bottom of the groove and is electrically connected to the second electrode layer; after forming the third electrode layer and before forming the third capacitor dielectric layer, the second lead-out electrode layer is formed in the groove, the second lead-out electrode layer covers the upper surface of the third electrode layer located at the bottom of the groove and is electrically connected to the third electrode layer; after forming the fourth electrode layer, the third lead-out electrode layer is formed in the groove, the third lead-out electrode layer covers the upper surface of the fourth electrode layer located at the bottom of the groove and is electrically connected to the fourth electrode layer.

16. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The forming of the capacitor further comprises, after forming the second electrode layer, forming a second capacitor dielectric layer, a third electrode layer, a third capacitor dielectric layer and a fourth electrode layer stacked in sequence in the groove, wherein the second capacitor dielectric layer covers the surface of the second electrode layer, the third electrode layer covers the surface of the second capacitor dielectric layer, the third capacitor dielectric layer covers the surface of the third electrode layer, and the fourth electrode layer covers the surface of the third capacitor dielectric layer; The lead-out electrode layer includes a first lead-out electrode layer, a second lead-out electrode layer, a third lead-out electrode layer and a fourth lead-out electrode layer. Before forming the first electrode layer, the first lead-out electrode layer is formed in the groove, the first lead-out electrode layer covers the lower surface of the portion of the first electrode layer located at the bottom of the groove and is electrically connected to the first electrode layer; after forming the second electrode layer and before forming the second capacitor dielectric layer, the second lead-out electrode layer is formed in the groove, the second lead-out electrode layer covers the lower surface of the portion of the second electrode layer located at the bottom of the groove and is electrically connected to the second electrode layer; after forming the third electrode layer and before forming the third capacitor dielectric layer, the third lead-out electrode layer is formed in the groove, the third lead-out electrode layer covers the lower surface of the portion of the third electrode layer located at the bottom of the groove and is electrically connected to the third electrode layer; after forming the fourth electrode layer, the fourth lead-out electrode layer is formed in the groove, the fourth lead-out electrode layer covers the lower surface of the portion of the fourth electrode layer located at the bottom of the groove and is electrically connected to the fourth electrode layer.

17. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: After forming the capacitor, the method further includes: forming an interlayer dielectric layer to cover the top surface of the capacitor, and forming a contact member to penetrate the interlayer dielectric layer and electrically connect to the lead electrode layer and / or the first electrode layer and the second electrode layer.

18. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: Before forming the capacitor in the trench, the method further includes: forming a bottom dielectric layer in the trench to at least cover the bottom and sidewalls of the trench; The bottom dielectric layer is located between the intermediate layer and the first electrode layer, and the first electrode layer covers the surface of the bottom dielectric layer.

19. A semiconductor device, characterized in that: include: The semiconductor structure according to any one of claims 1 to 10; A chip, located on the semiconductor structure; The chip and the semiconductor structure are electrically connected via solder ball bumps and / or solder pads.

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