Inner cavity VCSEL epitaxial structure and manufacturing method thereof

Abstract

The invention provides an inner cavity VCSEL epitaxial structure, and belongs to the technical field of semiconductor lasers, the inner cavity VCSEL epitaxial structure comprises an epitaxial wafer, the epitaxial wafer comprises a GaAs substrate, an n-region undoped DBR, an n-type DBR, a quantum well active region, an oxide layer, a p-type DBR and a p-region undoped DBR, a thicker In0. 49Ga0. 51P layer matched with a GaAs substrate lattice is inserted between distributed Bragg reflectors on the two sides of the active region, and the quantum well active region is provided with an N-region undoped DBR, an N-region undoped DBR, an N-region undoped DBR, an N-region undoped DBR and an N-region undoped DBR. The layer is exposed by etching and then an ohmic contact electrode is fabricated thereon to form inner cavity contact. The number of pairs of serially connected DBRs is reduced through inner cavity contact, and the series resistance of the chip can be greatly reduced. In addition, the band gap width of the In0. 49Ga0. 51P layer is 1.88 eV which is much larger than 1.42 V of GaAs, and the In0. 49Ga0. 51P layer does not contain an aluminum component which is easy to oxidize, so that the defect that an AlGaAs inner cavity contact layer is easy to oxidize when exposed and the negative effect that GaAs is easy to absorb in short-wave band light are improved. By adopting the structure, the series resistance and heating of the device can be more flexibly controlled, and the photoelectric conversion efficiency and reliability of the chip are better.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor lasers, and in particular to an intracavity VCSEL epitaxial structure and a manufacturing method thereof. Background Art

[0002] Vertical cavity surface emitting laser (VCSEL) has many advantages such as low threshold, high speed, small wavelength temperature drift coefficient, high coupling efficiency and low production cost, and is widely used in optical communication, three-dimensional sensing and lidar. The epitaxial structure of VCSEL generally includes N-DBR, quantum well and P-DBR. DBR is composed of about 20 to 40 pairs of AlxGa1-xAs / AlyGa1-yAs epitaxial layers with different components. Different components make the materials of DBR have larger band gaps. Although the transition can be achieved by gradual composition change, the resistance of DBR still accounts for the main proportion of the device resistance. Larger resistance will increase the heat generation of the chip, reduce the photoelectric conversion efficiency, and deteriorate the high temperature characteristics and reliability of the device, which will have an adverse effect on the actual application of the device. Summary of the invention

[0003] The present invention aims to solve the above technical problems and provides an intracavity VCSEL epitaxial structure and a manufacturing method thereof.

[0004] In order to solve the above technical problems, the technical solution provided by the present invention is:

[0005] An intracavity VCSEL epitaxial structure comprises an epitaxial wafer, wherein the epitaxial wafer comprises a GaAs substrate, an n-region undoped DBR, an n-type DBR, a quantum well active region, an oxide layer, a p-type DBR, and a p-region undoped DBR;

[0006] The p-type DBR and the n-type DBR on both sides of the quantum well active region have an In layer inserted in the middle of at least one side that matches the GaAs substrate lattice. 0.49 Ga 0.51 P layer;

[0007] Through the photoresist mask, the p-region undoped DBR and the adjacent In 0.49 Ga 0.51 After photolithography, the P layer is formed by electron beam evaporation on In 0.49 Ga 0.51 A p-region metal contact electrode is made on the P layer, and after deposition, the photoresist is stripped off and removed;

[0008] The oxidation mesa is etched to the n-type DBR to form an oxidation groove, and wet oxidation is used to form an oxidation hole;

[0009] The front N electrode area is photolithographically processed and the PN is deeply etched. The etching depth exceeds the n-type DBR and reaches the In electrode adjacent to the n-type DBR. 0.49 Ga0.51 P layer, In adjacent to the n-type DBR 0.49 Ga 0.51 An n-region metal contact electrode is prepared on the P layer.

[0010] Preferably, the In inserted in the p-type DBR 0.49 Ga 0.51 The P layer is p-type In 0.49 Ga 0.51 P insertion layer, In inserted in the n-type DBR 0.49 Ga 0.51 The P layer is n-type In 0.49 Ga 0.51 P insertion layer.

[0011] Preferably, the p-type In 0.49 Ga 0.51 P insertion layer and n-type In 0.49 Ga 0.51 The equivalent thickness of the P insertion layer is 2-5λ, and the light field intensity at this layer is 1 / e of the maximum standing wave light field intensity.

[0012] Preferably, the p-type In 0.49 Ga 0.51 The typical carbon doping value of the P insertion layer is 1-5×10 19 cm -3 , the n-type In 0.49 Ga 0.51 The doping concentration of the P insertion layer is 2×10 18 cm -3 .

[0013] Preferably, the gradient transition layer is eliminated before the high and low aluminum component layers of the n-region undoped DBR and the p-region undoped DBR.

[0014] Preferably, the adjacent In 0.49 Ga 0.51 The thickness of the P layer is less than half of the thickness of this layer.

[0015] A method for manufacturing an intracavity VCSEL epitaxial structure comprises the following steps:

[0016] Step 1: Using the MOCVD growth method, epitaxially grow n-region undoped DBR, n-type In 0.49 Ga 0.51 P insertion layer, n-type DBR, quantum well active region, oxide layer, p-type DBR, p-type In 0.49 Ga 0.51 The P insertion layer and the p region are undoped DBR;

[0017] Step 2: After cleaning, remove the p-region undoped DBR and p-type In through the photoresist mask. 0.49 Ga 0.51 After photolithography, the P insertion layer is formed by electron beam evaporation on the p-type In 0.49 Ga 0.51 A p-region metal contact electrode is made on the P insertion layer, and after deposition, the photoresist is stripped off and removed;

[0018] Step 3: etching the oxidation mesa to the n-type DBR 23 to form an oxidation trench 29, and using wet oxidation to form an oxidation hole;

[0019] Step 4: Photolithography of the front N electrode area and deep etching of the PN, the etching depth exceeds the n-type DBR and reaches the n-type In 0.49 Ga 0.51 P insertion layer, in n-type In 0.49 Ga 0.51 Prepare n-region metal contact electrode on the P insertion layer;

[0020] Step 5: Thinning the back surface to an overall thickness of about 150um or 200um, followed by preparation of the back metal electrode and thermal annealing;

[0021] Step 6: After laser cutting, a single or array VCSEL die is obtained.

[0022] After adopting the above structure, the present invention has the following advantages:

[0023] The present invention inserts a thicker In layer that matches the GaAs substrate lattice between the distributed Bragg reflectors on both sides of the active area. 0.49 Ga 0.51 The P layer is exposed by etching and then an ohmic contact electrode is made on it to form an intracavity contact. The intracavity contact reduces the number of DBR pairs in series and can greatly reduce the series resistance of the chip. 0.49 Ga 0.51 The band gap width of the P layer is 1.88eV, which is much larger than the 1.42V of GaAs. It also does not contain easily oxidized aluminum components, which improves the disadvantages of using AlGaAs intracavity contact layer that is easily exposed and easily oxidized and the negative effect of GaAs being easily absorbed in short-wavelength light. This structure can more flexibly control the series resistance and heat generation of the device, and the photoelectric conversion efficiency and reliability of the chip are better.

[0024] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present invention will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 It is a preparation process step diagram of the present invention;

[0027] Figure 2 It is a schematic diagram of the preparation of the present invention.

[0028] As shown in the figure: 21, n-region undoped DBR; 22, n-type In 0.49 Ga 0.51 P insertion layer; 23, n-type DBR; 24, quantum well active region; 25, p-type DBR; 26, p-type In 0.49 Ga 0.51 P insertion layer; 27, p-region undoped DBR; 28, p-region metal contact electrode; 29, oxidation trench; 30, n-region metal contact electrode. DETAILED DESCRIPTION

[0029] Specific embodiments of the present invention will now be mentioned in detail. Although the present invention is described in conjunction with these specific embodiments, it should be appreciated that it is not intended to limit the present invention to these specific embodiments. On the contrary, these embodiments are intended to cover substitutions, changes or equivalent embodiments that may be included in the spirit and scope of the invention defined by the claims. In the following description, a large number of specific details are set forth in order to provide a comprehensive understanding of the present invention. The present invention can be implemented without some or all of these specific details. In other cases, in order not to make the present invention unnecessarily obscure, well-known process operations are not described in detail.

[0030] When used in conjunction with "including," "methods comprising," or similar language in this specification and the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

[0031] The present invention is further described in detail below in conjunction with the full text.

[0032] Combined with Figure 1 and Figure 2, an intracavity VCSEL epitaxial structure, comprising an epitaxial wafer, the epitaxial wafer comprising a GaAs substrate, an n-region undoped DBR 21, an n-type DBR 23, a quantum well active region 24, an oxide layer, a p-type DBR 25, and a p-region undoped DBR 27;

[0033] The p-type DBR 25 and the n-type DBR 23 on both sides of the quantum well active region 24 have an In layer inserted in the middle of at least one side that matches the GaAs substrate lattice. 0.49 Ga 0.51 P layer;

[0034] Through the photoresist mask, the p-region undoped DBR27 and the adjacent In 0.49 Ga 0.51 After photolithography, the P layer is formed by electron beam evaporation on In 0.49 Ga 0.51 A p-region metal contact electrode 28 is formed on the P layer, and after deposition, the photoresist is stripped off and removed;

[0035] The oxidation mesa is etched to the n-type DBR 23 to form an oxidation trench 29, and wet oxidation is used to form an oxidation hole;

[0036] The front N electrode region is photolithographically processed and the PN region is deeply etched. The etching depth exceeds the n-type DBR23 and reaches the In electrode adjacent to the n-type DBR23. 0.49 Ga 0.51 P layer, In adjacent to the n-type DBR 23 0.49 Ga 0.51 An n-region metal contact electrode 30 is formed on the P layer.

[0037] In inserted into the p-type DBR25 0.49 Ga 0.51 The P layer is p-type In 0.49 Ga 0.51 The P insertion layer 26 is an In inserted into the n-type DBR 23. 0.49 Ga 0.51 The P layer is n-type In 0.49 Ga 0.51 P insertion layer 22.

[0038] p-type In 0.49 Ga 0.51 The P insertion layer 26 and the n-type In 0.49 Ga 0.51 The equivalent thickness of the P insertion layer 22 is 2-5λ, and the optical field intensity at this layer is 1 / e of the maximum value of the standing wave optical field intensity.

[0039] p-type In 0.49 Ga 0.51 The carbon doping value of the P insertion layer 26 is typically 1-5×10 19 cm-3 , n-type In 0.49 Ga 0.51 The doping concentration of the P insertion layer 22 is 2×10 18 cm -3 Specifically, the P type is doped with carbon, and the N type is doped with silicon.

[0040] The gradient transition layer is eliminated before the high and low aluminum composition layers of the n-region undoped DBR 21 and the p-region undoped DBR 27.

[0041] Embodiment 1:

[0042] This embodiment takes 850nm data communication VCSEL as an example, and the specific process steps are as follows:

[0043] (1) Using the MOCVD growth method, on the GaAs substrate, the n-region undoped DBR21, the n-region undoped DBR21, the n-type In 0.49 Ga 0.51 P layer 22, n-type DBR 23, quantum well active region 24, oxide layer, p-type DBR 25, p-type In 0.49 Ga 0.51 The P layer 26 and the p region are not doped with the DBR 27 .

[0044] (2) After the epitaxial wafer is cleaned, the p-type metal ring deposition area is produced by photolithography.

[0045] (3) Etch and remove the p-region undoped DBR27 and p-type In through the photoresist mask. 0.49 Ga 0.51 P insertion layer 26, such as Figure 2 shown.

[0046] (4) After photolithography, electron beam evaporation is used to make a p-type metal contact electrode 28 in the p-type metal deposition area, where Ti Pt Au After metal deposition, the photoresist is removed by stripping. The inner side of the TiPtAu electrode ring is 3μm away from the u-DBR table.

[0047] (5) PECVD growth thickness is about of SiNx.

[0048] (6) Using photoresist as a mask, etch out the oxidized mesa and then perform wet oxidation.

[0049] (7) After oxidation, the growth thickness is about SiNx passivation layer.

[0050] (8)BCB process.

[0051] (9) PECVD growth thickness is about SiNx protective layer.

[0052] (10) Contact hole Via photolithography and RIE etching are used to remove part of the SiNx on the contact electrode, so that part of the metal is exposed.

[0053] (11) After the seed layer is deposited, a photolithography process is performed, and then Au with a thickness of about 3.5 μm is electroplated. After the resist is removed, a part of the metal is removed by wet etching, and then rinsed clean.

[0054] (12) Street lithography and SiNx etching.

[0055] (13) Photolithography and deep etching of the front N electrode area, the etching depth exceeds the n-type DBR23, reaching the n-type In 0.49 Ga 0.51 P insertion layer 22.

[0056] (14) Photolithography of the front N electrode and n-type In 0.49 Ga 0.51 An n-region metal contact electrode 30 is formed on the P insertion layer 22 .

[0057] (15)PECVD growth thickness is about SiNx protective layer.

[0058] (16) Photolithography, etching to remove the electrodes and the passivation layer on the scribe line.

[0059] (17) The back side is thinned to an overall thickness of about 150 μm, followed by preparation of the back side metal electrode and thermal annealing.

[0060] (18) After laser cutting, a single or array VCSEL die is obtained.

[0061] Etching to remove p-type In 0.49 Ga 0.51 P layer 26 and n-type In 0.49 Ga 0.51 The thickness of the P layer 22 is less than half of the thickness of this layer.

[0062] The present invention inserts a thicker In layer that matches the GaAs substrate lattice between the distributed Bragg reflectors (DBR) on both sides of the active region. 0.49 Ga 0.51 The P layer is exposed by etching and then an ohmic contact electrode is made on it to form an intracavity contact. The intracavity contact reduces the number of DBR pairs in series and can greatly reduce the series resistance of the chip. 0.49 Ga 0.51The band gap width of the P layer is 1.88eV, which is much larger than the 1.42V of GaAs. It also does not contain easily oxidized aluminum components, which improves the disadvantages of using AlGaAs intracavity contact layer that is easily exposed and easily oxidized and the negative effect of GaAs being easily absorbed in short-wavelength light. This structure can more flexibly control the series resistance and heat generation of the device, and the photoelectric conversion efficiency and reliability of the chip are better.

[0063] The present invention and its embodiments are described above, and such description is not restrictive. What is shown in the full text is only one of the embodiments of the present invention, and the actual structure is not limited thereto. In short, if ordinary technicians in the field are inspired by it, without departing from the purpose of the invention, they can design a structure and embodiment similar to the technical solution without creativity, which should belong to the protection scope of the present invention.

Claims

1. An intracavity VCSEL epitaxial structure, characterized in that: The epitaxial wafer comprises a GaAs substrate, an n-region undoped DBR (21), an n-type DBR (23), a quantum well active region (24), an oxide layer, a p-type DBR (25), and a p-region undoped DBR (27); The p-type DBR (25) and the n-type DBR (23) on both sides of the quantum well active region (24) have an In layer inserted in the middle of at least one side that matches the GaAs substrate lattice. 0.49 Ga 0.51 P layer; The p-region undoped DBR (27) and the adjacent In 0.49 Ga 0.51 After photolithography, the P layer is formed by electron beam evaporation on In 0.49 Ga 0.51 A p-region metal contact electrode (28) is fabricated on the P layer, and after deposition, the photoresist is stripped off and removed; The oxidation mesa is etched to the n-type DBR (23) to form an oxidation groove (29), and a wet oxidation method is used to form an oxidation hole; The front N-electrode region is photolithographically processed and the PN is deeply etched, and the etching depth exceeds the n-type DBR (23) and reaches the In adjacent to the n-type DBR (23). 0.49 Ga 0.51 P layer, In adjacent to the n-type DBR (23) 0.49 Ga 0.51 An n-region metal contact electrode (30) is prepared on the P layer.

2. The intracavity VCSEL epitaxial structure according to claim 1, characterized in that: The In inserted into the p-type DBR (25) 0.49 Ga 0.51 The P layer is p-type In 0.49 Ga 0.51 The P insertion layer (26) is a layer of In inserted into the n-type DBR (23). 0.49 Ga 0.51 The P layer is n-type In 0.49 Ga 0.51 P insertion layer (22).

3. The intracavity VCSEL epitaxial structure according to claim 1, characterized in that: The p-type In 0.49 Ga 0.51 P insertion layer (26) and n-type In 0.49 Ga 0.51 The equivalent thickness of the P insertion layer (22) is 2-5λ, and the light field intensity at the layer is 1 / e of the maximum value of the standing wave light field intensity.

4. An intracavity VCSEL epitaxial structure according to claim 2 or 3, characterized in that: The p-type In 0.49 Ga 0.51 The carbon doping value of the P insertion layer (26) is typically 1-5×10 19 cm -3 , the n-type In 0.49 Ga 0.51 The doping concentration of the P insertion layer (22) is 2×10 18 cm -3 .

5. The intracavity VCSEL epitaxial structure according to claim 1, characterized in that: The gradient transition layer is eliminated before the high and low aluminum component layers of the n-region undoped DBR (21) and the p-region undoped DBR (27).

6. The intracavity VCSEL epitaxial structure according to claim 1, characterized in that: Etching to remove the adjacent In 0.49 Ga 0.51 The thickness of the P layer is less than half of the thickness of this layer.

7. A method for manufacturing an intracavity VCSEL epitaxial structure, characterized in that: The following steps are involved: Step 1: Using the MOCVD growth method, epitaxially grow n-region undoped DBR (21), n-type In 0.49 Ga 0.51 P insertion layer (22), n-type DBR (23), quantum well active region (24), oxide layer, p-type DBR (25), p-type In 0.49 Ga 0.51 P insertion layer (26) and p-region undoped DBR (27); Step 2: After cleaning, remove the p-region undoped DBR (27) and p-type In through the photoresist mask. 0.49 Ga 0.51 The P insertion layer (26) is formed by electron beam evaporation on the p-type In 0.49 Ga 0.51 A p-region metal contact electrode (28) is fabricated on the p insertion layer (26), and after deposition, the photoresist is stripped off and removed; Step 3: etching the oxidation mesa to the n-type DBR (23) to form an oxidation trench (29), and using wet oxidation to form oxidation holes; Step 4: Photolithography of the front N-electrode region and deep etching of the PN region, the etching depth exceeds the n-type DBR (23) and reaches the n-type In 0.49 Ga 0.51 The P insertion layer (22) is formed in the n-type In 0.49 Ga 0.51 An n-region metal contact electrode (30) is prepared on the P insertion layer (22); Step 5: Thinning the back surface to an overall thickness of about 150um or 200um, followed by preparation of the back metal electrode and thermal annealing; Step 6: After laser cutting, a single or array VCSEL die is obtained.

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