Charger integrated circuit and electronic device including same

Abstract

An electronic device includes a charger integrated circuit configured to perform a step-down conversion operation based on an input voltage applied to a first node thereof to generate an output voltage output to a second node thereof, where the charger integrated circuit includes: a power switching circuit including a flying capacitor; a current sensing circuit including an inductor; and a control circuit including: a compensation circuit configured to compensate for the inductor current value sensed from the current sensing circuit; an error voltage selection circuit configured to generate a minimum error voltage based on the feedback signal; and a comparison circuit configured to control a voltage of the flying capacitor, in which the control circuit is configured to generate a control voltage by correcting the inductor current value based on the minimum error voltage, and to supply the control voltage to the comparison circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0113303 filed on August 29, 2023 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a charger integrated circuit and an electronic device including the charger integrated circuit. Background Art

[0004] With the rapid development of electronic devices, various electronic devices that can exchange information or data with each other are being used. Electronic devices may adopt rechargeable batteries as power sources to provide mobility advantages. The capacity of rechargeable batteries is limited, so users may need to properly charge the rechargeable batteries before they are exhausted.

[0005] A DC-DC converter (e.g., a switching converter such as a buck converter) can use a switching transistor to convert an input voltage to an output voltage. A buck converter can use an inductor and / or a capacitor to generate and regulate an output voltage to a load (e.g., a rechargeable battery).

[0006] In a charging circuit using a conventional 3-level buck converter, a voltage mode control scheme may be applied in which the output voltage is used as feedback to control the voltage charged to a battery (e.g., a rechargeable battery) and the current flowing through the battery. In this regard, it may be difficult to achieve satisfactory control characteristics in a voltage mode control scheme compared to a current mode control scheme in which the inductor current of the circuit is detected for use (e.g., for feedback). Summary of the invention

[0007] One technical object sought to be achieved by the present disclosure is to provide a charger integrated circuit that can use a detected inductor current to ensure stable control characteristics.

[0008] Another technical object that the present disclosure aims to solve is to provide an electronic device that can ensure stable control characteristics using a detected inductor current.

[0009] The purpose according to the present disclosure is not limited to the above-mentioned purpose. Other purposes and advantages according to the present disclosure that are not mentioned can be understood based on the following description, and can be more clearly understood based on the embodiments according to the present disclosure. In addition, it will be easily understood that the purposes and advantages according to the present disclosure can be achieved using the components shown in the claims or their combinations.

[0010] An electronic device according to some embodiments of the present disclosure includes: a battery; and a charger integrated circuit, the charger integrated circuit being configured to perform a step-down conversion operation based on an input voltage applied to a first node thereof to generate an output voltage output to a second node thereof, wherein the charger integrated circuit includes: a power switching circuit, the power switching circuit being configured to receive an input voltage, wherein the power switching circuit includes a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor and a flying capacitor, the flying capacitor being electrically connected to a first end of the second switching transistor and a first end of the third switching transistor; a current sensing circuit, the current sensing circuit including a first switching transistor electrically connected to a first terminal of the second switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor; An inductor having a second node and a third node and arranged between the second node and the third node, wherein the third node is electrically connected to the second end of the second switching transistor and the second end of the third switching transistor; and a control circuit, the control circuit comprising: a compensation circuit, the compensation circuit being configured to compensate for the inductor current value sensed from the current sensing circuit; an error voltage selection circuit, the error voltage selection circuit being configured to generate a minimum error voltage based on a feedback signal; and a comparison circuit, the comparison circuit being configured to control the voltage of the flying capacitor, wherein the control circuit is configured to generate a control voltage by correcting the inductor current value based on the minimum error voltage, and provide the control voltage to a first input stage of the comparison circuit.

[0011] A charger integrated circuit according to some embodiments of the present disclosure includes: a conversion circuit configured to generate an output voltage output to a second node thereof based on an input voltage applied to a first node thereof; and a control circuit configured to generate a first pulse width modulation (PWM) signal and a second PWM signal for controlling the conversion circuit, wherein the conversion circuit includes: a power switching circuit configured to receive an input voltage, wherein the power switching circuit includes a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor electrically connected in series with each other and a flying capacitor electrically connected to a first end of the second switching transistor and a first end of the third switching transistor; and a current sensing circuit including an inductor electrically connected to a third node and disposed between the third node and the second node, wherein the control circuit includes: a compensation circuit configured to compensate for an inductor current value sensed from the current sensing circuit; an error voltage selection circuit configured to generate a minimum error voltage based on a feedback signal; and a comparison circuit configured to control a voltage of the flying capacitor, wherein the inductor current value is compensated to have the same value as the minimum error voltage.

[0012] A charger integrated circuit according to some embodiments of the present disclosure includes: a conversion circuit, which is configured to generate an output voltage output to a second node thereof based on an input voltage applied to a first node thereof; and a control circuit, which is configured to generate a first switching voltage, a second switching voltage, a third switching voltage, and a fourth switching voltage based on a signal provided from the conversion circuit, wherein the conversion circuit includes: an input / output selection circuit, which includes a first input transistor configured to receive a first input voltage and a second input transistor configured to receive a second input voltage; a power switching circuit, which is configured to receive an input voltage based on the first input voltage and / or the second input voltage, and includes a first switching transistor, a second switching transistor electrically connected in series with each other, and a control circuit. a transistor, a third switching transistor and a fourth switching transistor and a flying capacitor electrically connected to the first end of the second switching transistor and the first end of the third switching transistor; and a current sensing circuit, the current sensing circuit including an inductor electrically connected to a third node and arranged between the third node and the second node, wherein a control voltage is generated based on an inductor current value sensed from the inductor of the current sensing circuit, wherein the control voltage is provided to an input stage of the control circuit, wherein the control circuit is configured to: control the amplitude of the control voltage and each of the first comparison voltage and the second comparison voltage; and control the duration of conduction of each of the first switching transistor, the second switching transistor, the third switching transistor and the fourth switching transistor, so that the voltage of the flying capacitor is balanced to have half the voltage of the input voltage.

[0013] Details of other embodiments are included in the detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects and features of the present disclosure will become more apparent by describing in detail illustrative embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0015] Figure 1 is a block diagram schematically illustrating an electronic device including a charger integrated circuit according to some embodiments;

[0016] Figure 2 is a diagram for illustrating a conversion circuit of a charger integrated circuit according to some embodiments;

[0017] Figure 3 and Figure 4 is a timing diagram when a charger integrated circuit according to some embodiments performs a step-down conversion operation;

[0018] Figure 5 is a diagram for illustrating a control circuit of a charger integrated circuit according to some embodiments;

[0019] Figure 6 is a diagram for illustrating control logic and gate drivers of a charger integrated circuit according to some embodiments;

[0020] Figure 7 and Figure 8 is a timing diagram of signals of a conversion circuit and a control circuit according to some embodiments;

[0021] Figures 9 to 12 is a diagram for illustrating the effect of using a charger integrated circuit according to some embodiments; and

[0022] Fig.13 is a diagram schematically illustrating an electronic device including a charger integrated circuit according to some embodiments. DETAILED DESCRIPTION

[0023] In the following detailed description of the present disclosure, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it should be understood that the present disclosure can be practiced without these specific details. In other cases, well-known methods, processes, components and circuits are not described in detail to avoid unnecessary obscurity of various aspects of the present disclosure. The examples of various embodiments are further described and described below. It should be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, it is intended to cover substitutions, modifications and equivalents that may be included within the scope of the present disclosure defined by the appended claims.

[0024] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include" and "comprise" specify the presence of the features, integers, operations, elements and / or components, but do not exclude the presence of one or more other features, integers, operations, elements, components and / or parts thereof or the addition thereof.

[0025] It should be understood that although the terms "first", "second", "third", etc. may be used herein to illustrate various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the scope of the present disclosure, the first element, first component, first region, first layer or first part described below may be referred to as the second element, second component, second region, second layer or second part.

[0026] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by those skilled in the art to which the inventive concept belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this article.

[0027] In one example, when a certain embodiment can be implemented differently, the functions or operations specified in a particular block can occur in an order different from the order specified in the flow chart. For example, two consecutive blocks can actually be executed at the same time. Depending on the related functions or operations, the blocks can be executed in reverse order.

[0028] In the description of a temporal relationship, for example, the temporal sequence between two events, such as "after", "after...", "before", etc., unless "directly after", "directly after", or "directly before" is not indicated, another event may occur between the two events.

[0029] In the following, reference Figures 1 to 8 , a charger integrated circuit and an electronic device including the charger integrated circuit according to some embodiments will be described.

[0030] Figure 1 is a block diagram schematically illustrating an electronic device including a charger integrated circuit according to some embodiments.

[0031] refer to Figure 1 , the electronic device 10 may include a charger integrated circuit 100 and a battery 200. The electronic device 10 may also include a main processor and peripheral devices. For example, the electronic device 10 may be a mobile device such as a smart phone, a tablet personal computer (PC), a mobile phone, a personal digital assistant (PDA), a laptop computer, a wearable device, a global positioning system (GPS) device, an e-book terminal, a digital broadcast terminal, an MP3 player, a digital camera, etc. For example, the electronic device 10 may be an electric vehicle.

[0032] The battery 200 may be built into the electronic device 10. In some embodiments, the battery 200 may be removed from the electronic device 10. The battery 200 may include one or more battery cells. A plurality of battery cells may be connected to each other (e.g., electrically connected) in series or in parallel. When an external charging device is not connected (e.g., not electrically connected) to the electronic device 10, the battery 200 may supply power to the electronic device 10. It should be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it may be directly on another element or layer, directly connected to or coupled to another element or layer, or one or more intermediate elements or layers may exist. In contrast, when an element is referred to as being "directly coupled," "directly connected," or "directly responsive to" another element or "directly on" another element, there is no intermediate element. In addition, "electrical connection" conceptually includes physical connection and physical disconnection. In addition, it should also be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also exist. As used below, the terms "external configuration," "external device," "external power," "external signal," or "external" are intended to broadly refer to devices, circuits, blocks, modules, power, and / or signals that reside externally (e.g., outside the functional or physical boundaries) relative to a given circuit, block, module, system, or device.

[0033] The charger integrated circuit 100 can charge the battery 200 and can be referred to as a "battery charger". In addition, the charger integrated circuit 100 can supply power to an external device (e.g., a first power interface 310 and / or a second power interface 320) connected (e.g., electrically connected) to the charger integrated circuit 100 based on the voltage charged into the battery 200. The first power interface 310 may be a wired power interface to be described later, and the second power interface 320 may be a wireless power interface to be described later. For example, the charger integrated circuit 100 may be implemented as one or more integrated circuit chips and may be mounted on a printed circuit board.

[0034] The charger integrated circuit 100 may include a conversion circuit 110 and a control circuit 120. The conversion circuit 110 may be implemented as a circuit including a plurality of switching transistors (eg, Figure 2 Q1, Q2, Q3 and Q4 in the ), flying capacitors (e.g., Figure 2 CF in) and inductors (e.g. Figure 2In this regard, 3-level refers to the number of voltage levels used in the switching operation. The 3-level DC-DC converter can switch an input voltage, a (1 / 2)* input voltage (half the voltage of the input voltage), and a ground voltage (e.g., 0V) to generate an output voltage. For example, the conversion circuit 110 can perform a buck conversion operation to reduce the input voltage to generate an output voltage.

[0035] When the conversion circuit 110 reduces the input voltage, i.e., during a step-down conversion operation, a power path can be formed through which power is provided from at least one external device connected (e.g., electrically connected) to the battery 200 via the wired power interface 310 and / or the wireless power interface 320.

[0036] The conversion circuit 110 may reduce the input voltage by performing a step-down conversion operation, and may charge the battery 200 based on the reduced voltage.

[0037] The control circuit 120 may control the switching operation of the conversion circuit 110 .

[0038] The control circuit 120 may control the switch operation of the conversion circuit 110 so that a flying capacitor (eg, Figure 2 The voltage at two opposite ends of CF in (hereinafter, referred to as flying capacitor voltage) can be maintained at a target level, for example, a set target level of the flying capacitor voltage.

[0039] The control circuit 120 may generate a signal (eg, Figure 5 PWM1 and PWM2 in the converter circuit 110) to control the switching operation of the converter circuit 110. For example, the control circuit 120 may be based on the current (eg, Figure 2 and Figure 5 IL, IBAT and IIN in the PWM module) to generate a first pulse width modulation (PWM) signal (eg, Figure 5 PWM1 in) and a second PWM signal (e.g., Figure 5 PWM2 in the PWM2, and can send signals (for example, Figure 5 PWM1 and PWM2 in the example are provided to the conversion circuit 110. Regarding the signal (for example, Figure 5 PWM1 and PWM2 in the converter circuit 110), a plurality of switch transistors (eg, Figure 2 At least two switching transistors (Q1, Q2, Q3, and Q4) in the embodiment may be based on a first PWM signal (eg, Figure 5 PWM1 in the example is turned on or off, while at least two other switching transistors thereof can be turned on or off based on a second PWM signal (e.g., Figure 5 PWM2 in is turned on or off.

[0040] The control circuit 120 may sense the inductor current IL flowing in the inductor L provided in the conversion circuit 110, and may convert the sensed inductor current IL into information about its average value, and may adjust the plurality of switching transistors (eg, Figure 2 The on-period or off-period of each of Q1, Q2, Q3, and Q4 in the charger integrated circuit 100 is controlled so that the flying capacitor voltage VCF can be maintained at the target voltage. This may be referred to as flying capacitor balancing. In this way, stable control characteristics of the charger integrated circuit 100 may be ensured while maintaining flying capacitor balancing.

[0041] Will refer to it later Figures 2 to 8 A method of converting a sensed inductor current (eg, inductor current IL) into information about an average value thereof and performing flying capacitor balancing based on the information is described.

[0042] In some embodiments, the electronic device 10 may support wired charging and / or wireless charging, and may include a wired power interface 310 for wired charging and / or a wireless power interface 320 for wireless charging. The wired power interface 310 may include a wired charging circuit. The wireless power interface 320 may include a wireless charging circuit. For example, each of the wired charging circuit and the wireless charging circuit may include a rectifier, a regulator, etc.

[0043] The charger IC 100 may receive a first input voltage CHGIN from the wired power interface 310 and / or a second input voltage WCIN from the wireless power interface 320 , and may charge the battery 200 based on the first input voltage CHGIN and / or the second input voltage WCIN.

[0044] For example, a travel adapter (TA) or an auxiliary battery may be electrically connected to the wired power interface 310. The TA may convert AC110V to AC220V as household power, or convert power supplied from another power supply component (e.g., a computer) to DC power required to charge the battery 200, and provide the DC power to the electronic device 10. The charger integrated circuit 100 may charge the battery 200 using the first input voltage CHGIN received from the TA or the auxiliary battery.

[0045] For example, the wireless power receiving circuit or the wireless power transmitting circuit may be connected (eg, electrically connected) to the wireless power interface 320. The charger integrated circuit 100 may charge the battery 200 using the second input voltage WCIN received from the wireless power receiving circuit.

[0046] In this manner, the charger integrated circuit 100 may operate to support wired charging and / or wireless charging.

[0047] Figure 2 is a diagram for illustrating a conversion circuit of a charger integrated circuit according to some embodiments.

[0048] refer to Figure 2 The conversion circuit 110 may include an input / output selection circuit 111 , a power switching circuit 112 , and a current sensing circuit 113 .

[0049] The input / output selection circuit 111 may include a first input transistor QI1 and a second input transistor QI2. The first input transistor QI1 and the second input transistor QI2 may be connected (eg, electrically connected) in parallel to each other.

[0050] The first input voltage CHGIN may be applied to the first input transistor QI1, or the OTG device may be connected (eg, electrically connected) to the first input transistor QI1. The second input voltage WCIN may be applied to the second input transistor QI2, or the wireless power transmission circuit may be connected (eg, electrically connected) to the second input transistor QI2.

[0051] The first input transistor QI1 can be turned on or off in response to the first input control signal SI1, and the second input transistor QI2 can be turned on or off in response to the second input control signal SI2. For example, when the first input voltage CHGIN is applied to the first input transistor QI1 or the OTG device is connected to the first input transistor QI1, the first input control signal SI1 can have an active level, and the first input transistor QI1 can be turned on in response to the first input control signal SI1. When the second input voltage WCIN is applied to the second input transistor QI2 or the wireless power transmission circuit is connected to the second input transistor QI2, the second input control signal SI2 can have an active level, and the second input transistor QI2 can be turned on in response to the second input control signal SI2. The control circuit (for example, Figure 1 120) receives a first input control signal SI1 and a second input control signal SI2.

[0052] The power switching circuit 112 may include a plurality of switching transistors including a first switching transistor Q1 , a second switching transistor Q2 , a third switching transistor Q3 , and a fourth switching transistor Q4 connected in series (eg, electrically connected) to each other, and a flying capacitor CF.

[0053] The first switch transistor Q1, the second switch transistor Q2, the third switch transistor Q3, and the fourth switch transistor Q4 may be connected in series (e.g., electrically connected) to the first node N1. For example, one end of the first switch transistor Q1 may be connected (e.g., electrically connected) to the first node N1, and the other end thereof may be connected (e.g., electrically connected) to the second node N2. In some embodiments, one end of the second switch transistor Q2 may be connected (e.g., electrically connected) to the second node N2, and the other end thereof may be connected (e.g., electrically connected) to the third node N3. In some embodiments, one end of the third switch transistor Q3 may be connected (e.g., electrically connected) to the third node N3, and the other end thereof may be connected (e.g., electrically connected) to the fourth node N4. In some embodiments, one end of the fourth switch transistor Q4 may be connected (e.g., electrically connected) to the fourth node N4, and a ground voltage may be applied to the other end thereof.

[0054] The first switching transistor Q1 can be turned on or off in response to the first switching voltage VG1. The second switching transistor Q2 can be turned on or off in response to the second switching voltage VG2. The third switching transistor Q3 can be turned on or off in response to the third switching voltage VG3. The fourth switching transistor Q4 can be turned on or off in response to the fourth switching voltage VG4.

[0055] Each of the first switching voltage VG1 , the second switching voltage VG2 , the third switching voltage VG3 , and the fourth switching voltage VG4 may be a periodic signal having a specific frequency.

[0056] In some embodiments, the first switching voltage VG1 and the fourth switching voltage VG4 may be complementary to each other, and the second switching voltage VG2 and the third switching voltage VG3 may be complementary to each other. Therefore, the first switching transistor Q1 and the fourth switching transistor Q4 may perform switching operations in a complementary manner. The second switching transistor Q2 and the third switching transistor Q3 may perform switching operations in a complementary manner.

[0057] In some embodiments, the flying capacitor CF may be connected (e.g., electrically connected) to the second node N2 and the fourth node N4. In other words, one end of the flying capacitor CF may be connected (e.g., electrically connected) to the other end of the first switch transistor Q1 and one end of the second switch transistor Q2, and the other end of the flying capacitor CF may be connected (e.g., electrically connected) to the other end of the third switch transistor Q3 and one end of the fourth switch transistor Q4. The voltage VCF of the flying capacitor CF may be equal to the difference between the voltage VDDM of the second node N2 and the voltage VSSM of the fourth node N4.

[0058] The current sensing circuit 113 may include, for example, an inductor L and a first resistor DCR connected in series (e.g., electrically connected) to each other, and, for example, a second resistor RS and a sensing capacitor CS connected in series (e.g., electrically connected) to each other. In some embodiments, the inductor L and the first resistor DCR may be connected in parallel (e.g., electrically connected) with the second resistor RS and the sensing capacitor (CS), for example, based on the fifth node N5 and the sixth node N6.

[0059] The inductor L may be connected (e.g., electrically connected) to the third node N3 and the sixth node N6 and disposed between the third node N3 and the sixth node N6. The inductor L may store therein energy generated from the inductor current IL flowing through the inductor L, and may release the stored energy. According to the step-down conversion operation of the conversion circuit 110, the inductor current IL may flow from the third node N3 to the sixth node N6.

[0060] The inductor current IL can be sensed by a voltage VCS across two opposite ends of the sensing capacitor CS, and can be amplified by the amplifier 121a and can be converted into a voltage. The sensed inductor current value VIL,SEN as a converted value can be provided to a control circuit (eg, Figure 1 120 in the table).

[0061] The current IIN flowing in the first node N1, the input voltage VBYP and the output voltage VSYS (also referred to as the system voltage VSYS), the full charge voltage VBAT of the battery 200, and the current IBAT flowing into the battery 200 may be provided to a control circuit (eg, Figure 1 The control circuit 120 may generate the first to fourth switching voltages VG1 to VG4 based on a signal provided from the conversion circuit 110 and / or a signal from the battery 200 .

[0062] The conversion circuit 110 can operate as a buck converter to reduce the input voltage VBYP to generate an output voltage. In this regard, the input voltage VBYP can be generated based on the first input voltage CHGIN or the second input voltage WCIN. The output voltage can be output as a system voltage VSYS via the sixth node N6. In this regard, the output voltage can have a voltage of, for example, 0 to about 4.4V. One end of the conversion circuit 110 can be connected (e.g., electrically connected) to one end of the power transistor QBAT. The battery 200 can be charged based on the output voltage (e.g., output voltage VSYS). The charging battery voltage VBAT of the battery 200 can be equal to the output voltage (e.g., output voltage VSYS). The control switch BS for controlling charging can be connected (e.g., electrically connected) to one end of the battery 200.

[0063] Figure 3 and Figure 4 is a timing diagram when a charger integrated circuit according to some embodiments performs a step-down conversion operation. For reference, Figure 3 is the waveform diagram when the duty cycle (D) is greater than or equal to 0.5, and Figure 4 This is the waveform diagram when the duty cycle is less than 0.5.

[0064] The conversion circuit 110 can perform a step-down conversion operation based on the first switch voltage VG1 to the fourth switch voltage VG4. For example, when the first switch voltage VG1 is at an effective level (e.g., logic high), the first switch transistor Q1 can be turned on. When the first switch voltage VG1 is at an inactive level (e.g., logic low), the first switch transistor Q1 can be turned off.

[0065] A duration for which each of the first to fourth switching voltages VG1 to VG4 has each of the active level and the inactive level within one cycle may be variable.

[0066] In some embodiments, when the first switch transistor Q1 is turned on, the fourth switch transistor Q4 may be turned off. When the first switch transistor Q1 is turned off, the fourth switch transistor Q4 may be turned on. When the second switch transistor Q2 is turned on, the third switch transistor Q3 may be turned off. When the second switch transistor Q2 is turned off, the third switch transistor Q3 may be turned on.

[0067] refer to Figure 3 , at time point t0, when the first switching transistor Q1 and the second switching transistor Q2 are turned on, the input voltage (e.g., the input voltage VBYP of the first node N1) may be applied to the third node N3, and the voltage VL of the third node N3 may have the same voltage level as the input voltage VBYP, and the inductor current IL may increase.

[0068] At time point t1, when the second switching transistor Q2 is turned off and the third switching transistor Q3 is turned on, current may flow to the inductor L via the first switching transistor Q1, the flying capacitor CF, and the third switching transistor Q3. The voltage VL of the third node N3 may have a voltage level obtained by subtracting the voltage VCF at the two opposite ends of the flying capacitor CF from the input voltage VBYP of the first node N1. For example, when the voltage VCF at the two opposite ends of the flying capacitor CF is 1 / 2 times (half voltage) of the input voltage VBYP of the first node N1 (e.g., 1 / 2*VBYP), the voltage VL of the third node N3 may have the same level as the voltage VCF at the two opposite ends of the flying capacitor CF (e.g., 1 / 2*VBYP). As the level of the voltage VL of the third node N3 decreases, the inductor current IL may decrease.

[0069] At time point t2, when the third switching transistor Q3 is turned off and the second switching transistor Q2 is turned on, the voltage VL of the third node N3 may have the same level as the input voltage VBYP of the first node N1, and the inductor current IL may increase.

[0070] At time point t3, when the fourth switch transistor Q4 is turned on and the first switch transistor Q1 is turned off, current may flow to the inductor L via the second switch transistor Q2, the flying capacitor CF, and the fourth switch transistor Q4. The voltage VL of the third node N3 may have the same level as that of the voltage VCF at both opposite ends of the flying capacitor CF (e.g., 1 / 2*VBYP (half voltage of the input voltage VBYP)). As the level of the voltage VL of the third node N3 decreases, the inductor current IL may decrease.

[0071] refer to Figure 4 At time point t0, when the fourth switching transistor Q4 and the third switching transistor Q3 are turned on, a ground voltage (e.g., 0V) is applied to the third node N3, and the voltage VL of the third node N3 may have the same level as that of the ground voltage. The inductor current IL generated by the energy that has been charged in the inductor L may be output, and the inductor current IL may decrease.

[0072] At time point t1, when the fourth switch transistor Q4 is turned off and the first switch transistor Q1 is turned on, current may flow to the inductor L via the first switch transistor Q1, the flying capacitor CF, and the third switch transistor Q3. The voltage VL of the third node N3 may have a level obtained by subtracting the voltage VCF at both opposite ends of the flying capacitor CF from the input voltage VBYP of the first node N1. For example, when the voltage VCF at both opposite ends of the flying capacitor CF is 1 / 2 times (half voltage) of the input voltage VBYP of the first node N1 (e.g., 1 / 2*VBYP), the voltage VL of the third node N3 may have a level of 1 / 2 times (half voltage) of the input voltage VBYP of the first node N1 (e.g., 1 / 2*VBYP). Due to the increase in the level of the voltage VL of the third node N3, the inductor current IL may increase.

[0073] At time point t2, when the fourth switching transistor Q4 is turned on and the first switching transistor Q1 is turned off, the voltage VL of the third node N3 may have the same level as the ground voltage, and the inductor current IL may decrease.

[0074] At time point t3, when the second switching transistor Q2 is turned on and the third switching transistor Q3 is turned off, current may flow to the inductor L via the fourth switching transistor Q4, the flying capacitor CF, and the second switching transistor Q2. The voltage VL of the third node N3 may have the same level as that of the voltage VCF at both opposite ends of the flying capacitor CF (e.g., 1 / 2*VBYP (half voltage of the input voltage VBYP)), and the inductor current IL may increase.

[0075] In this way, the switching operation of the first switching transistor Q1 to the fourth switching transistor Q4 can be repeated within one period T, and therefore, the output voltage (e.g., the output voltage VSYS) obtained by gradually reducing the input voltage (e.g., the input voltage VBYP of the first node N1) can be output via the sixth node N6.

[0076] In one example, in the conversion circuit 110 implemented as a 3-level DC-DC converter, as described above, the voltage VL of the third node N3 can be determined based on the input voltage VBYP of the first node N1 and the voltage VCF at the two opposite ends of the flying capacitor CF. The control circuit 120 can control the voltage VCF at the two opposite ends of the flying capacitor CF to have a median value of the input voltage VBYP of the first node N1, thereby reducing the ripple of the output voltage (e.g., the output voltage VSYS). In this way, the balancing of the flying capacitor CF can be performed by controlling the voltage VCF at the two opposite ends of the flying capacitor CF to have a median value of the input voltage VBYP of the first node N1.

[0077] Figure 5 is a diagram for illustrating a control circuit of a charger integrated circuit according to some embodiments.

[0078] refer to Figure 5 The control circuit 120 may include a compensation circuit 121 , an error voltage selection circuit 122 , and a comparison circuit 123 .

[0079] The compensation circuit 121 may compensate for the inductor current value VIL,SEN sensed from the current sensing circuit 113 .

[0080] The compensation circuit 121 may include an amplifier 121b and passive elements, such as resistors R1 and R2 and capacitors C1 and C2. A minimum error voltage VE,SEL described later may be applied to a first input stage (+) of the amplifier 121b. One end of the resistor R1 may be connected (e.g., electrically connected) to a second input stage (-) of the amplifier 121b. The sensed inductor current value VIL,SEN may be applied to the other end of the resistor R1. The resistor R2 and the capacitors C1 and C2 may be connected (e.g., electrically connected) to the second input stage (-) and output stage of the amplifier 121b and may be disposed between the second input stage (-) and output stage of the amplifier 121b.

[0081] The error voltage selection circuit 122 can detect an error in the output voltage based on the current IIN flowing in the first node N1, the input voltage VBYP, the output voltage VSYS, the full charge voltage VBAT of the battery 200 and the current IBAT flowing into the battery 200, and can select the minimum error voltage among the error voltages.

[0082] The error voltage selection circuit 122 may amplify differences between voltage or current values ​​of the reference signals IREF1, VREF1, IREF2, and VREF2 and the feedback signals F1, F2, F3, F4, and F5, and may output a minimum error voltage VE,SEL among the amplified differences.

[0083] The amplifier 122a of the error voltage selection circuit 122 may amplify the difference between the current value of the first feedback signal F1 generated based on the current IBAT flowing into the battery 200 and the current value of the first reference current IREF1 and may output the amplified difference as the first error voltage VE,IBAT.

[0084] Furthermore, the second feedback signal F2 or the third feedback signal F3 may be generated based on the output voltage VSYS or the full charge voltage VBAT of the battery 200. One of the second feedback signal F2 and the third feedback signal F3 may be selected by the multiplexer M1, and the selected one feedback signal may be output.

[0085] The amplifier 122 b of the error voltage selection circuit 122 may amplify the difference between the voltage value of the second feedback signal F2 or the third feedback signal F3 and the voltage value of the first reference voltage VREF1 , and may output the amplified difference as the second error voltage VE,VBAT.

[0086] In addition, the amplifier 122c of the error voltage selection circuit 122 can amplify the difference between the current value of the fourth feedback signal F4 generated based on the current IIN of the first node (e.g., the first node N1) and the current value of the second reference current IREF2, and can output the amplified difference as the third error voltage VE,IIN.

[0087] Furthermore, the amplifier 122d of the error voltage selection circuit 122 may amplify a difference between a voltage value of the fifth feedback signal F5 generated based on the input voltage VBYP and a voltage value of the second reference voltage VREF2 and may output the amplified difference as a fourth error voltage VE,VBYP.

[0088] Although not specifically shown, the error voltage selection circuit 122 may include passive elements such as resistors and capacitors in addition to the amplifiers 122a to 122d. Depending on the impedance ratio of the passive elements, the differences between the current or voltage values ​​of the reference signals IREF1, VREF1, IREF2, and VREF2 and the feedback signals F1, F2, F3, F4, and F5 may be amplified, and the amplified differences may be output as error voltages VE,IBAT, VE,VBAT, VE,IIN, and VE,VBYP, respectively.

[0089] The minimum error selector MES of the error voltage selection circuit 122 can select the minimum error voltage VE,SEL among the error voltages VE,IBAT, VE,VBAT, VE,IIN and VE,VBYP. The minimum error voltage VE,SEL can be the one having the minimum value among the error voltages VE,IBAT, VE,VBAT, VE,IIN and VE,VBYP.

[0090] The compensation circuit 121 can compensate the (sensed) inductor current value VIL,SEN so as to have the same value as the minimum error voltage VE,SEL. Therefore, the final error voltage VE,ACM can be provided to the first input stage of the comparison circuit 123, that is, the first input stage (+) of the amplifier 123a. In some embodiments, the final error voltage VE,ACM can be referred to as a control voltage. In some embodiments, the control voltage VE,ACM can be a voltage generated in an inductor average current control scheme (average current mode).

[0091] The comparison circuit 123 may be based on the output signal from the conversion circuit (e.g., Figure 1 The comparison circuit 123 can generate a first pulse width modulation (PWM) signal PWM1 and a second PWM signal PWM2 based on the sensed input voltage VBYP,SEN, the sensed voltage VCF,SEN at two opposite ends of the flying capacitor CF, and the sensed current (e.g., the inductor current ( Figure 2IL)) in generates a first PWM signal PWM1 and a second PWM signal PWM2.

[0092] The comparison circuit 123 may include a first comparator COM1, a second comparator COM2, a plurality of amplifiers 123a, 123b, and 123c, and resistors R3 and R4.

[0093] The first PWM signal PWM1 may be generated based on the first triangular wave signal VTRI,POS and the first comparison voltage VC,POS. The second PWM signal PWM2 may be generated based on the second triangular wave signal VTRI,NEG and the second comparison voltage VC,NEG. The first triangular wave signal VTRI,POS and the second triangular wave signal VTRI,NEG may have the same period Ts and opposite phases to each other.

[0094] The comparison circuit 123 may use the sensed input voltage VBYP,SEN as a reference voltage to balance the sensed voltages VCF,SEN on two opposite ends of the flying capacitor CF.

[0095] For example, when the sensed voltage VCF,SEN on two opposite ends of the flying capacitor CF is equal to ½ (half voltage) of the sensed input voltage VBYP,SEN, the flying capacitor balancing current ICF,BAL may not flow.

[0096] In another example, when the sensed voltage VCF,SEN on two opposite ends of the flying capacitor CF is less than ½ (half voltage) of the sensed input voltage VBYP,SEN, the flying capacitor balancing current ICF,BAL may flow in a positive direction under the operation of the comparison circuit 123. The first comparison voltage VC,POS may be provided to a second input stage of the comparison circuit 123, which may be, for example, a second input stage (-) of the amplifier 123a.

[0097] In this case, under the operation of the comparison circuit 123, the amplitude of the first comparison voltage VC,POS can be controlled to be greater than the amplitude of the control voltage VE,ACM, and the amplitude of the second comparison voltage VC,NEG can be controlled to be less than the amplitude of the control voltage VE,ACM.

[0098] Therefore, the duration of the first and third switching transistors Q1 and Q3 being turned on may be controlled to be greater (longer) than the duration of the second and fourth switching transistors Q2 and Q4 being turned on. Therefore, the voltage VCF (level) on both opposite ends of the flying capacitor CF may increase.

[0099] In another example, when the sensed voltage VCF,SEN on two opposite ends of the flying capacitor CF is greater than ½ (half voltage) of the sensed input voltage VBYP,SEN, the flying capacitor balancing current ICF,BAL may flow in a reverse direction.

[0100] In this case, under the operation of the comparison circuit 123, the amplitude of the first comparison voltage VC,POS can be controlled to be smaller than the amplitude of the control voltage VE,ACM, and the amplitude of the second comparison voltage VC,NEG can be controlled to be larger than the amplitude of the control voltage VE,ACM.

[0101] Therefore, the duration of the second and fourth switching transistors Q2 and Q4 being turned on can be controlled to be greater (longer) than the duration of the first and third switching transistors Q1 and Q3 being turned on. Therefore, the voltage VCF (level) on both opposite ends of the flying capacitor CF can be reduced.

[0102] Figure 6 is a diagram for illustrating control logic and gate drivers of a charger integrated circuit according to some embodiments.

[0103] The control logic CL may generate a first switch control signal and a fourth switch control signal (eg, Figure 6 S1 and S4 in the figure), and a second switch control signal and a third switch control signal (for example, Figure 6 S2 and S3 in ).

[0104] The first switch control signal S1 may be a signal outputted by the control logic CL according to the first PWM signal PWM1, and the fourth switch control signal S4 may be a signal outputted by the first inverter INV1 and the control logic CL according to the first PWM signal PWM1. The second switch control signal S2 may be a signal outputted by the control logic CL according to the second PWM signal PWM2, and the third switch control signal S3 may be a signal outputted by the second inverter INV2 and the control logic CL according to the second PWM signal PWM2.

[0105] The gate driver GD can change the first switch control signal and the fourth switch control signal (eg, Figure 6 The voltage levels of S1, S4) in the circuit can be controlled, and the first switching voltage VG1 and the fourth switching voltage VG4 can be generated respectively.

[0106] In addition, the gate driver GD can change the second switch control signal and the third switch control signal (eg, Figure 6The voltage levels of S2, S3 in the circuit can be changed, and the second switching voltage VG2 and the third switching voltage VG3 can be generated respectively.

[0107] Each of the first to fourth switching control signals S1, S2, S3, and S4 may be transmitted to the first to fourth switching transistors ( Figure 2 The gate of each of Q1 to Q4).

[0108] For example, the control logic CL may be a first switch transistor to a fourth switch transistor (eg, Figure 2 Each of Q1 to Q4 in the embodiment generates an over-current control signal OCP, a zero-current control signal ZCS and / or a dead-time control signal DT.

[0109] For example, when the inductor current IL increases to a predetermined value, the gate driver GD can prevent the first switch voltage VG1, the second switch voltage VG2, the third switch voltage VG3, and the fourth switch voltage VG4 from being generated under the overcurrent control signal OCP. When the inductor current IL decreases to a predetermined value (e.g., "0"), zero current can be sensed under the zero current control signal ZCS, so that the gate driver GD can prevent current from flowing in the reverse direction in the power switch circuit 112. Under the dead time control signal DT, the first to fourth switch voltages VG1, VG2, VG3, and VG4 can be controlled not to overlap with each other.

[0110] Figure 7 and Figure 8 is a timing diagram of signals of a conversion circuit and a control circuit according to some embodiments.

[0111] refer to Figure 7 , current flows through the flying capacitor CF during the duration that the first switching transistor Q1 and the third switching transistor Q3 are turned on. When current flows from the second node N2 to the fourth node N4, the flying capacitor CF may be charged, so that the voltage level VCF at two opposite ends of the flying capacitor CF increases.

[0112] When the voltage VCF at the two opposite ends of the flying capacitor CF is lower than the target voltage (T_VCF, i.e., 1 / 2*VBYP), the control circuit 120 can control the duration of the first switch transistor Q1 and the third switch transistor Q3 to be turned on to be greater (longer) than the duration of the second switch transistor Q2 and the fourth switch transistor Q4 to be turned on. Therefore, the voltage VCF at the two opposite ends of the flying capacitor CF increases so as to be closer to the target voltage (T_VCF, i.e., 1 / 2*VBYP).

[0113] refer to Figure 8 During the duration that the second switching transistor Q2 and the fourth switching transistor Q4 are turned on, current flows from the fourth node N4 to the second node N2. As the flying capacitor CF is discharged, the voltage level VCF at the two opposite ends of the flying capacitor CF decreases.

[0114] When the voltage VCF at the two opposite ends of the flying capacitor CF is higher than the target voltage (T_VCF, i.e., 1 / 2*VBYP (half the voltage of the input voltage VBYP)), the control circuit 120 can control the duration of the first switching transistor Q1 and the third switching transistor Q3 to be turned on to be less than (shorter than) the duration of the second switching transistor Q2 and the fourth switching transistor Q4 to be turned on. Therefore, the voltage VCF at the two opposite ends of the flying capacitor CF decreases so as to be closer to the target voltage (T_VCF, i.e., 1 / 2*VBYP (half the voltage of the input voltage VBYP)).

[0115] According to some embodiments, the final error voltage VE,ACM obtained by correcting the sensed inductor current value VIL,SEN may be used to generate the first switching signal SS1 and the second switching signal SS2 for controlling the switching operations of the first to fourth switching transistors Q1 to Q4. Therefore, when balancing the voltage VCF at the two opposite ends of the flying capacitor CF to the target voltage (T_VCF, i.e., 1 / 2*VBYP (half the voltage of the input voltage VBYP)) and providing the voltage and / or current to the battery 200, the charger integrated circuit may be controlled in a more stable and faster response manner.

[0116] Figures 9 to 12 is a diagram for illustrating the effect of using a charger integrated circuit according to some embodiments.

[0117] Fig. 9 and Fig.10 A comparison between the control characteristics of an average current control scheme (average current mode control) and a voltage control scheme (voltage mode control) under the same operating conditions is shown.

[0118] refer to Fig. 9 In the voltage control scheme (voltage mode control), the resonant pole frequency split phenomenon occurs at about 100kHz, and therefore, a bandwidth (BW) of about 5kHz can be obtained. However, in the average current control scheme (average current mode control), the resonant pole frequency split phenomenon can be reduced compared to the voltage control scheme (voltage mode control), and therefore, a bandwidth (BW) of about 80kHz can be obtained.

[0119] In addition, reference Fig.10, it can be determined that in the voltage control scheme (voltage mode control), the phase margin (PM) is about 100°, while in the average current control scheme (average current mode control), the phase margin (PM) is about 73°. That is, in the average current control scheme (average current mode control), the charger integrated circuit (for example, Figure 1 of 100).

[0120] In another example, in a peak current control scheme (peak current mode control) that directly compares the current sensing values ​​of the first switch transistor Q1 and the second switch transistor Q2 or the current sensing values ​​of the third switch transistor Q3 and the fourth switch transistor Q4 with the error voltage, the current sensing values ​​of the first switch transistor Q1 and the second switch transistor Q2 or the current sensing values ​​of the third switch transistor Q3 and the fourth switch transistor Q4 may be mismatched. This does not guarantee the same on-time of the first switch transistor Q1 and the second switch transistor Q2 or the third switch transistor Q3 and the fourth switch transistor Q4, so that the voltage (e.g., voltage VCF) at two opposite ends of the flying capacitor (e.g., flying capacitor CF) is not controlled to be 0.5 times (half voltage) of the input voltage (e.g., input voltage VBYP), and distortion of current and voltage waveforms may occur, thereby not guaranteeing stable operation.

[0121] However, in an average current control scheme (average current mode control) according to some embodiments, the average value of the inductor current (e.g., the inductor current IL) can be used to minimize the mismatch of the current sensing values ​​of the switching transistors (e.g., the first switching transistor Q1 to the fourth switching transistor Q4).

[0122] Fig.11 and Fig.12 is a graph comparing load transient response characteristics of a voltage control scheme (voltage mode (VM) control) and an average current control scheme (average current mode (ACM) control).

[0123] refer to Fig.11 and Fig.12 , it can be determined that the transient voltage in the average current control scheme (average current mode (ACM) control) is smaller and shorter than that in the voltage control scheme (voltage mode (VM) control).

[0124] That is, in the average current control scheme (average current mode (ACM) control), the frequency characteristic of the control loop can be more stable, and the fluctuation of the output voltage VBAT or VSYS can be suppressed to a minimum level.

[0125] Fig.13is a diagram schematically illustrating an electronic device including a charger integrated circuit according to some embodiments.

[0126] The electronic device 1000 may include various electronic circuits. For example, the electronic circuits of the electronic device 1000 may include an image processing block 1100, a communication block 1200, an audio processing block 1300, a buffer memory 1400, a non-volatile memory 1500, a user interface 1600, a main processor 1800, a power management circuit 1900, and a charger integrated circuit 1910.

[0127] The electronic device 1000 may be connected (eg, electrically connected) to the battery 1920, and the battery 1920 may supply thereto power for operating the electronic device 1000. However, the present disclosure is not limited thereto, and power supplied to the electronic device 1000 may be provided from an internal / external power source other than the battery 1920.

[0128] The image processing block 1100 may receive light through the lens 1110. The image sensor 1120 and the image signal processor 1130 included in the image processing block 1100 may generate image information related to an external object based on the received light.

[0129] The communication block 1200 may exchange signals with an external device / system via an antenna 1210. The transceiver 1220 and the modulator / demodulator (MODEM) 1230 of the communication block 1200 may process signals exchanged with the external device / system according to one or more of various wired / wireless communication protocols.

[0130] The audio processing block 1300 may process sound information using an audio signal processor 1310. The audio processing block 1300 may receive audio input through a microphone 1320 and output audio through a speaker 1330.

[0131] The buffer memory 1400 may store therein data used in the operation of the electronic device 1000. In an example, the buffer memory 1400 may temporarily store therein data processed by or to be processed by the main processor 1800. For example, the buffer memory 1400 may include a volatile memory (such as a static random access memory (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM)) and / or a nonvolatile memory (such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), etc.).

[0132] The non-volatile memory 1500 may store data therein regardless of whether it is powered. For example, the non-volatile memory 1500 may include a non-volatile memory such as flash memory, PRAM, MRAM, ReRAM, FRAM. For example, the non-volatile memory 1500 may include a removable memory such as a secure digital (SD) card or a solid state drive (SSD) and / or an embedded memory such as an embedded multimedia card (eMMC).

[0133] The user interface 1600 may transfer communication between a user and the electronic device 1000. For example, the user interface 1600 may include an input interface for receiving an input from a user and an output interface for providing information to the user.

[0134] The main processor 1800 may control the overall operation of the components of the electronic device 1000. The main processor 1800 may process various calculations to operate the electronic device 1000. For example, the main processor 1800 may be implemented as a general processor, a dedicated processor, an application processor, a microprocessor, etc., and may include one or more processor cores.

[0135] The power management circuit 1900 may supply power to the components of the electronic device 1000 and may manage the power. For example, the power management circuit 1900 may output a system voltage based on the power supplied from the charger integrated circuit 1910 and / or the battery 1920. The power management circuit 1900 may adjust the frequency of each component and the voltage level of the supplied system voltage based on the temperature and operation mode of each of the components.

[0136] The charger integrated circuit 1910 may charge the battery 1920 based on power provided from an external power source, or may provide power to the power management circuit 1900. The charger integrated circuit 1910 may provide power to an external device based on power provided from the battery 1920 via a wired or wireless power interface.

[0137] refer to Figures 1 to 12The described charger integrated circuit 100 may be applied to the charger integrated circuit 1910 of the electronic device 1000. The charger integrated circuit 100 may be implemented as a 3-level DC-DC converter. The charger integrated circuit 100 may generate a first switching signal SS1 and a second switching signal SS2 for controlling the switching operation of the first switching transistor Q1 to the fourth switching transistor Q4 using a control voltage VE,ACM obtained by correcting the sensed inductor current value VIL,SEN. Therefore, when balancing the voltage VCF at the two opposite ends of the flying capacitor CF so as to have a target level (T_VCF, i.e., 1 / 2*VBYP (half voltage of the input voltage VBYP)) and providing a voltage and / or current to the battery 200, the charger integrated circuit 100 may be controlled in a more stable and faster response manner.

[0138] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above-described embodiments, but can be implemented in various different forms. It will be appreciated by those skilled in the art that the present disclosure can be practiced in other specific forms without changing the technical spirit or core characteristics of the present disclosure. Therefore, it should be understood that the embodiments described above are not restrictive, but illustrative in all aspects.

Claims

1. An electronic device, comprising: Battery; as well as a charger integrated circuit configured to perform a step-down conversion operation based on an input voltage applied to a first node thereof to generate an output voltage output to a second node thereof, Wherein, the charger integrated circuit comprises: a power switching circuit configured to receive the input voltage, wherein the power switching circuit comprises a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor, and a flying capacitor electrically connected to a first end of the second switching transistor and a first end of the third switching transistor; a current sensing circuit including an inductor electrically connected to the second node and a third node and disposed between the second node and the third node, wherein the third node is electrically connected to a second terminal of the second switching transistor and a second terminal of the third switching transistor; and Control circuit, including: a compensation circuit configured to compensate for an inductor current value sensed from the current sensing circuit; an error voltage selection circuit configured to generate a minimum error voltage based on the feedback signal; and a comparison circuit configured to control the voltage of the flying capacitor, The control circuit is configured to generate a control voltage by correcting the inductor current value based on the minimum error voltage, and provide the control voltage to the first input stage of the comparison circuit.

2. The electronic device according to claim 1, wherein: The compensation circuit is configured to compensate the inductor current value based on the minimum error voltage to have the same value as the minimum error voltage.

3. The electronic device according to claim 1, wherein: The error voltage selection circuit is configured to amplify a difference between a voltage value of a reference signal and a voltage value of the feedback signal, and determine the minimum error voltage according to the amplified difference, and The compensation circuit is configured to compensate the inductor current based on the minimum error voltage.

4. The electronic device according to claim 1, wherein: The comparison circuit is configured as follows: generating a first pulse width modulation (PWM) signal based on the first triangular wave signal and the first comparison voltage, generating a second PWM signal based on the second triangular wave signal and the second comparison voltage, controlling the first comparison voltage compared to the control voltage, and The second comparison voltage is controlled compared to the control voltage.

5. The electronic device according to claim 4, wherein: The charger integrated circuit further includes control logic configured to generate a first switch control signal and a fourth switch control signal based on the first PWM signal, and to generate a second switch control signal and a third switch control signal based on the second PWM signal.

6. The electronic device according to claim 5, wherein: The charger integrated circuit further includes a gate driver configured to: generating a first switching voltage and a fourth switching voltage based on the first switching control signal and the fourth switching control signal; and A second switching voltage and a third switching voltage are generated based on the second switching control signal and the third switching control signal.

7. The electronic device according to claim 6, wherein: The first switching voltage and the fourth switching voltage are complementary to each other, and the second switching voltage and the third switching voltage are complementary to each other.

8. The electronic device according to claim 1, wherein: The voltage of the flying capacitor is controlled to be equal to a half voltage of the input voltage.

9. The electronic device according to claim 4, wherein: The first comparison voltage is provided to a second input stage of the comparison circuit, and The comparison circuit is configured to control the amplitude of the first comparison voltage to be greater than the amplitude of the control voltage.

10. The electronic device according to claim 4, wherein: The comparison circuit is configured to control the magnitude of the first comparison voltage to be smaller than the magnitude of the control voltage.

11. The electronic device according to claim 9, wherein: The comparison circuit is configured to: when the voltage of the flying capacitor is less than half the voltage of the input voltage, make the flying capacitor balancing current flow in the positive direction, and control the first duration of conduction of the first switching transistor and the third switching transistor to be longer than the second duration of conduction of the second switching transistor and the fourth switching transistor, so that the voltage of the flying capacitor increases.

12. The electronic device according to claim 10, wherein: The comparison circuit is configured to: when the voltage of the flying capacitor is greater than half the voltage of the input voltage, make the flying capacitor balancing current flow in the reverse direction, and control the second duration of the conduction of the second switching transistor and the fourth switching transistor to be longer than the first duration of the conduction of the first switching transistor and the third switching transistor, so that the voltage of the flying capacitor is reduced.

13. A charger integrated circuit, comprising: a conversion circuit configured to generate an output voltage output to a second node thereof based on an input voltage applied to a first node thereof; as well as a control circuit configured to generate a first pulse width modulation (PWM) signal and a second PWM signal for controlling the conversion circuit, Wherein, the conversion circuit comprises: a power switching circuit configured to receive the input voltage, wherein the power switching circuit comprises a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor electrically connected in series with each other, and a flying capacitor electrically connected to a first end of the second switching transistor and a first end of the third switching transistor; and a current sensing circuit including an inductor electrically connected to a third node and disposed between the third node and the second node, Wherein, the control circuit comprises: a compensation circuit configured to compensate for an inductor current value sensed from the current sensing circuit; an error voltage selection circuit configured to generate a minimum error voltage based on the feedback signal; and a comparison circuit configured to control the voltage of the flying capacitor, The inductor current value is compensated to have the same value as the minimum error voltage.

14. The charger integrated circuit according to claim 13, wherein: The comparison circuit is configured to control the voltage of the flying capacitor based on the inductor current value.

15. The charger integrated circuit according to claim 13, wherein: The error voltage selection circuit is configured to amplify a difference between a voltage value of a reference signal and a voltage value of the feedback signal, and determine the minimum error voltage according to the amplified difference.

16. The charger integrated circuit according to claim 13, wherein: The conversion circuit further includes a first input transistor and a second input transistor, the first input transistor being configured to receive a first input voltage, the second input transistor being configured to receive a second input voltage, The input voltage is generated based on the first input voltage and / or the second input voltage.

17. The charger integrated circuit according to claim 13, wherein: The comparison circuit is configured as follows: generating the first PWM signal based on the first triangular wave signal and the first comparison voltage; as well as generating the second PWM signal based on the second triangular wave signal and the second comparison voltage, Wherein, the charger integrated circuit further includes: a control logic configured to generate a first switch control signal and a fourth switch control signal based on the first PWM signal, and to generate a second switch control signal and a third switch control signal based on the second PWM signal; and The gate driver is configured as: generating a first switching voltage and a fourth switching voltage based on the first switching control signal and the fourth switching control signal; and A second switching voltage and a third switching voltage are generated based on the second switching control signal and the third switching control signal.

18. The charger integrated circuit according to claim 13, wherein: The voltage of the flying capacitor is controlled to have a half voltage of the input voltage.

19. The charger integrated circuit according to claim 13, wherein: The control circuit is configured to generate a control voltage by compensating the inductor current value based on the minimum error voltage, and provide the control voltage to a first input stage of the comparison circuit, wherein the control circuit is configured to provide a first comparison voltage to a second input stage of the comparison circuit, and The comparison circuit is configured to control a first duration of conduction of the first switch transistor and the third switch transistor and a second duration of conduction of the second switch transistor and the fourth switch transistor to control the voltage of the flying capacitor.

20. A charger integrated circuit, comprising: a conversion circuit configured to generate an output voltage output to a second node thereof based on an input voltage applied to a first node thereof; as well as a control circuit configured to generate a first switching voltage, a second switching voltage, a third switching voltage, and a fourth switching voltage based on a signal provided from the conversion circuit, Wherein, the conversion circuit comprises: an input / output selection circuit including a first input transistor configured to receive a first input voltage and a second input transistor configured to receive a second input voltage; a power switching circuit configured to receive the input voltage based on the first input voltage and / or the second input voltage, and comprising a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor electrically connected in series with each other, and a flying capacitor electrically connected to a first end of the second switching transistor and a first end of the third switching transistor, and a current sensing circuit including an inductor electrically connected to a third node and disposed between the third node and the second node, wherein the control voltage is generated based on an inductor current value sensed from the inductor of the current sensing circuit, wherein the control voltage is provided to an input stage of the control circuit, Wherein, the control circuit is configured as follows: controlling the magnitude of the control voltage and each of the first comparison voltage and the second comparison voltage; and A duration for which each of the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor is turned on is controlled so that a voltage of the flying capacitor is balanced to have a half voltage of the input voltage.

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