Control device and control method for switching voltage regulator

Abstract

The embodiment of the invention relates to a control device and a control method for a switching voltage regulator. A control device of a regulator having a switching circuit is disclosed. The apparatus includes: an oscillator that provides a clock signal having a switching period; a circuit providing a comparison signal indicative of a comparison between the input voltage and the output voltage; and circuitry to generate a signal to drive a switch of the switching circuit according to an error between the output voltage and the nominal voltage. The device controls a first phase, a second phase, and a third phase within a switching period, the first phase having a current path between an input node and an output node through an inductive element; the second stage has a current path between the input node and the common node through the inductive element; the third stage has a current path between the output node and the common node through the inductive element. The sequence of the first phase, the second phase and the third phase is a function of the comparison signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Italian Application No. 102023000017658, filed on August 28, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present invention relates to a control device and a control method for a switching voltage regulator. Background Art

[0004] As is known, a switching voltage regulator can convert an input direct current (DC) voltage into an output DC voltage using different operation schemes and can be obtained using different topologies, the most common of which is a four-switch non-inverting topology.

[0005] Figure 1 A switching voltage regulator 1 is shown, which includes a four-switch non-inverting switching circuit (hereinafter referred to as switching circuit 3 ) and a control device 5 . The switching circuit 3 is formed by a first half-bridge 7 , a second half-bridge 9 , and an inductor 10 .

[0006] The first half bridge 7 is formed by a first high-side switch 11 and a first low-side switch 13 (here two N-MOS transistors), which are coupled in series between an input terminal 15 and a common node 17. The common node 17 is coupled to a reference potential line (ground) 18 via a shunt resistor 19. The input voltage V relative to ground 18 is in is applied to the input terminal 15 .

[0007] The second half-bridge 9 is formed by a second high-side switch 20 and a second low-side switch 22 (here also two N-MOS transistors), which are coupled in series between the output node 24 and the common node 17 .

[0008] The output voltage V out appears at output node 24 and is applied to load 25 .

[0009] Input voltage V in The input capacitor 26 is coupled to the input terminal 15. The output voltage V out A dropping output capacitor 27 is coupled to the output terminal 24 .

[0010] The inductor 10 is coupled between the middle node of the first half-bridge 7 and the middle node of the second half-bridge 9 .

[0011] According to the input voltage V inWith the output voltage V out The switching voltage regulator 1 can operate in one of three operating modes if V in >V out +V th1 , the operating mode is called "buck" mode, if V in <V out -V th2 , the operating mode is called "boost" mode, and if V in ≈V out (That is, if V out +V th1 <V in <V out -V th2 ), the operating mode is called transition or "buck-boost" mode.

[0012] According to the operation mode, by appropriately controlling the switches of the first half-bridge 7 and the second half-bridge 9, the output voltage V out Maintain the reference voltage V ref , for example, is selected by the user according to the specific application, and the input voltage V in The value of is irrelevant.

[0013] To this end, the control device 5 is coupled to the input node 15 and the output node 24 and receives a reference voltage V ref Furthermore, the control device 5 is coupled to the shunt resistor 19 to operate a current control of the switching circuit 3 .

[0014] In buck mode, if Figure 2A and Figure 2B As shown, the control device switches the clock signal CLK during the switching period T CLK A PWM signal with a variable duty cycle is generated internally.

[0015] The signal PWM defines a buck on phase and a buck off phase. The buck off phase precedes the buck on phase. In the off phase, the control device 5 controls the closing of the first low-side switch 13 and the second high-side switch 20, and the opening of the first high-side switch 11 and the second low-side switch 22. In fact, during the buck off phase, the current passes through the current path 30 between the ground 18 and the output terminal 24 (at Figure 2A The current is indicated by a dotted line in FIG. 1 ), passes through the inductor 10, and flows into the switching circuit 3.

[0016] In the on-phase, the control device 5 controls the opening of the first low-side switch 13 and the second low-side switch 22, and the closing of the first high-side switch 11 and the second high-side switch 20. In fact, during the buck on-phase, the current flows through the current path 31 between the input terminal 15 and the output terminal 24 (at Figure 2A The current is indicated by a dotted line in FIG. 1 ), passes through the inductor 10, and flows into the switching circuit 3.

[0017] In boost mode, if Figure 3A and Figure 3B As shown, the control device 5 is in the period T of the clock signal CLK CLK The duty cycle of the signal PWM is modified in the boost on-phase, and the signal PWM defines a boost on-phase and a boost off-phase. The boost on-phase precedes the boost off-phase. During the on-phase, the control device 5 controls the closing of the first high-side switch 11 and the second low-side switch 22, and the opening of the first low-side switch 13 and the second high-side switch 20. In fact, during the boost on-phase, the current flows through the current path 33 (formed by the ground 18 and the input terminal 15) between the ground 18 and the input terminal 15. Figure 3A ), passes through the inductor 10, and flows into the switching circuit 3.

[0018] In the off phase, the control device 5 controls the closing of the first high-side switch 11 and the second high-side switch 20, and the opening of the first low-side switch 13 and the second low-side switch 22. In fact, during the boost off phase, the current flows through the current path 34 between the input terminal 15 and the output terminal 24 (by Figure 3A ), passes through the inductor 10, and flows into the switching circuit 3.

[0019] In the transition mode, Figure 4 As shown, the control device 5 switches the clock signal CLK during the switching period T CLK In fact, the control device 5 performs a step-up cycle and a step-down cycle alternately in the switching period T CLK Internal alternating reference Figure 2B and Figure 3B The four control phases described are shown in FIG. 1 . In the transition mode, the switching frequency is therefore halved relative to the frequency obtainable in the buck mode and the boost mode. Therefore, in the transition mode, the control device 5 reduces the output voltage V out In fact, in transition mode, the maximum duration of the on-phase of the boost cycle cannot be higher than the clock period T CLK half of the duration.

[0020] In addition, the voltage threshold V th1 、V th2 The selection of the voltage threshold V th1 、V th2defines the voltage range in which the regulator 1 is in transition mode. In addition, the applicant has verified that when entering and exiting the transition mode, for example when switching from transition mode ( Figure 4 ) to boost mode ( Figure 3A and 3B ) and vice versa, the control device 5 may be subjected to high current peaks due to the different operating points (values ​​of the control nodes) between the transition mode and the buck (or boost) mode. Such high current peaks may cause malfunction of the regulator 1. Summary of the invention

[0021] Therefore, according to the present invention, there is provided a control device, a control method and a voltage regulator for a switching voltage regulator as defined in the accompanying claims.

[0022] The object of the present invention is to overcome the disadvantages of the prior art.

[0023] A first aspect relates to a control device for a switching voltage regulator, the control device comprising: an oscillator configured to generate a clock signal having a switching period; a voltage comparison circuit configured to generate a comparison signal indicating a comparison between an input voltage of a switching circuit of the switching voltage regulator at an input node and an output voltage of the switching circuit at an output node; and a drive signal generator circuit configured to generate a switch control signal according to an error between the output voltage and a nominal voltage to drive a switch of the switching circuit, and control a first control stage, a second control stage, and a third control stage within the switching period, wherein the switch control signal controls the formation of a first current path between an input node and an output node through an inductor element, the formation of a second current path between the input node and a common node through the inductor element, and the formation of a third current path between the output node and a common node through the inductor element, the common node being a node of the switching circuit having a common reference potential, and modifying a sequence of the first control stage, the second control stage, and the third control stage within the switching period according to the comparison signal.

[0024] The second aspect relates to a switching voltage regulator, which includes: a switching circuit; and a control device configured to control the switching circuit, the control device including: an oscillator configured to generate a clock signal having a switching period; a voltage comparison circuit configured to generate a comparison signal indicating a comparison between an input voltage of the switching circuit at an input node and an output voltage of the switching circuit at an output node; and a drive signal generator circuit configured to generate a switch control signal according to an error between the output voltage and a nominal voltage to drive a switch of the switching circuit, and control a first control stage, a second control stage, and a third control stage within the switching period, wherein the switch control signal controls the formation of a first current path between an input node and an output node through an inductor element, the formation of a second current path between the input node and a common node through the inductor element, and the formation of a third current path between the output node and a common node through the inductor element, the common node being a node of the switching circuit having a common reference potential, and the sequence of the first control stage, the second control stage, and the third control stage is modified within the switching period according to the comparison signal.

[0025] A third aspect relates to a method for operating a switching voltage regulator, the method comprising: generating a clock signal having a switching period by an oscillator of a control device for operating a switching circuit of the switching voltage regulator; generating a comparison signal by a voltage comparison circuit of the control device, the comparison signal indicating a comparison between an input voltage of the switching circuit at an input node and an output voltage of the switching circuit at an output node; generating a switch control signal by a drive signal generator circuit of the control device according to an error between the output voltage and a nominal voltage to drive a switch of the switching circuit; controlling a first control stage, a second control stage, and a third control stage within the switching period, wherein the switch control signal controls the formation of a first current path between an input node and an output node through an inductor element, the formation of a second current path between an input node and a common node through an inductor element, and the formation of a third current path between an output node and a common node through an inductor element, the common node being a node of the switching circuit having a common reference potential; and modifying the sequence of the first control stage, the second control stage, and the third control stage within the switching period according to the comparison signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] For a better understanding of the present invention, embodiments of the present invention will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0027] Figure 1 shows a block diagram of a known switching voltage regulator;

[0028] Figure 2A Shows Figure 1A circuit diagram of a switching circuit of a regulator when used in a buck mode;

[0029] Figure 2B Shows Figure 1 The waveform of the regulator when used in buck mode;

[0030] Figure 3A Shows Figure 1 A circuit diagram of a switching circuit of a regulator when used in a boost mode;

[0031] Figure 3B Shows Figure 1 Waveforms when the regulator is used in boost mode;

[0032] Figure 4 Shows Figure 1 Waveforms when the regulator is used in transition mode;

[0033] Figure 5 shows a block diagram of a switching voltage regulator according to one embodiment;

[0034] Figure 6 Shows Figure 5 The waveform of the regulator when in use;

[0035] Figure 7 Shows Figure 5 A circuit diagram of a switching circuit of a regulator when used in a first operating mode;

[0036] Figure 8 Shows Figure 5 A circuit diagram of a switching circuit of a regulator when used in a second operating mode;

[0037] Fig. 9 shows a block diagram of a switching voltage regulator according to various embodiments;

[0038] Fig.10 According to an embodiment Fig. 9 The waveform of the regulator when in use;

[0039] Fig.11 According to an embodiment Fig. 9 The waveform of the regulator when in use;

[0040] Fig.12 shows a block diagram of a switching voltage regulator according to another embodiment;

[0041] Fig.13 According to an embodiment Fig.12 A detailed circuit diagram of a portion of the regulator;

[0042] Fig.14 Shows Fig.13 An exemplary waveform of a portion of when in use; and

[0043] Fig.15 A block diagram of a switching voltage regulator according to another embodiment is shown. DETAILED DESCRIPTION

[0044] Figure 5 The block diagram of a switching voltage regulator 50 , which is also referred to as regulator 50 for short in the following text, is shown, comprising a switching circuit 53 and a control device 55 which are coupled to one another.

[0045] The regulator 50 has an input node 51 and an output node 54. The input node 51 receives an input voltage V IN , the output node 54 provides an output voltage V OUT The output node 54 may be coupled to a load (not shown here) that receives the output voltage V OUT .

[0046] Specifically, the regulator 50 is a buck-boost type DC-DC converter configured to convert an input voltage V IN Starts to generate output voltage V out , so that the output voltage V OUT Equal to the reference voltage or nominal voltage V REF , reference voltage or nominal voltage V REF It can be selected by the user according to the specific application.

[0047] The switch circuit 53 and the control device 55 may be integrated into the same die, or formed in different dies. IN ≤V OUT and V IN ≥V OUT In both cases, the switch circuit 53 is configured to output the voltage V OUT Adjust to the reference value V REF , as discussed in detail below. The switch circuit 53 is a circuit having a plurality of switches and at least one inductive element. In this embodiment, the switch circuit 53 is a four-switch non-inverting circuit. In detail, the switch circuit 53 is formed by a first half-bridge 64 and a second half-bridge 65.

[0048] The first half-bridge 64 is formed by a first high-side switch 68 and a first low-side switch 69 , here two N-MOS transistors, coupled in series between the input node 51 and a common node 72 .

[0049] In detail, the first high-side switch 68 is coupled between the input node 51 and the middle node 74 of the first half-bridge 64 , and the first low-side switch 69 is coupled between the middle node 74 of the first half-bridge 64 and the common node 72 .

[0050] The switch circuit 53 receives an input voltage V relative to a reference potential line (ground) 78. IN .

[0051] Input capacitor 76 may be coupled between input node 51 and ground 78 .

[0052] The second half-bridge 65 is formed by a second high-side switch 82 and a second low-side switch 83 , which here are also two N-MOS transistors, coupled in series between the output node 54 and the common node 72 .

[0053] In detail, the second high-side switch 82 is coupled between the output node 54 and the middle node 85 of the second half-bridge 65 , and the second low-side switch 83 is coupled between the middle node 85 of the second half-bridge 65 and the common node 72 .

[0054] The switch circuit 53 provides an output voltage V relative to ground 78. OUT .

[0055] An output capacitor 77 may be coupled between the output node 54 and ground 78 .

[0056] The switch circuit 53 further includes an inductor 87 having an inductance L and coupled between the middle node 74 of the first half-bridge 64 and the middle node 85 of the second half-bridge 65 .

[0057] The common node 72 is connected to the resistor R S A shunt resistor 80 is coupled to ground 78. The shunt resistor 80 is optional and may help to achieve current control of the regulator 1.

[0058] The first high-side switch 68 , the first low-side switch 69 , the second high-side switch 82 , and the second low-side switch 83 are each controlled by a corresponding switch control signal T1 , T2 , T3 , and T4 .

[0059] A control device 55 is coupled to the input node 51 and the output node 54 .

[0060] The control device 55 controls the output voltage V OUT With reference voltage V REF The error between the input voltage V IN With the output voltage V OUT The switch control signals T1, T2, T3, T4 (hereinafter also collectively indicated as T1-T4) are generated by comparison between them.

[0061] The control device 55 comprises an oscillator 91 which provides a clock signal CLK, for example Figure 6 In the example of a square wave periodic signal, with a duration T CLK cycle.

[0062] Depending on the application, the duration T CLK It can be between about 10 microseconds to hundreds of nanoseconds.

[0063] In this embodiment, the clock signal CLK has a fixed duration T CLK However, the clock signal CLK may have a cycle of variable duration.

[0064] The period of the clock signal CLK defines the switching period of the regulator 50, hereinafter referred to as CMT or T CLK .

[0065] The control device 55 also includes a (feedback) loop control circuit or module 92, which receives an indication of the output voltage V OUT The signal (here is the output voltage V OUT ) and indicates the reference voltage V REF The signal REF, and according to the output voltage V OUT With reference voltage V REF The error between them is used to provide the modulation signal PWM.

[0066] In this embodiment, the control device 55 comprises a generator 93 which generates the signal REF. However, the loop control circuit 92 may receive the signal REF from an external user.

[0067] The modulation signal PWM is in the switching period T CLK A pulse width modulated signal with a duty cycle D.

[0068] The loop control circuit 92 performs a switching operation in each switching cycle T. CLK According to the output voltage V OUT With reference voltage V REF The error between them is used to adjust the duty cycle D of the modulation signal PWM.

[0069] The modulation signal PWM has a switching period T CLK The first modulation phase PWM1 has a duration of TP1, wherein it assumes a first value (eg Figure 6 ), and a second modulation phase PWM2 of duration TP2, in which it assumes a second value (eg Figure 6 ) in the example above.

[0070] The loop control circuit 92 determines the switching time between the first modulation stage PWM1 and the second modulation stage PWM2 ( Figure 6 t in c ), and thus determine the corresponding durations TP1, TP2, and thus also determine the duty cycle D of the modulation signal PWM.

[0071] The duty cycle D of the modulation signal PWM depends on the durations TP1 and TP2. Figure 6 The period T CLK , when the control device 55 performs valley type control, for example, for V IN >V OUT , it can be D = TP2 / (TP1 + TP2). In contrast, when the control device 55 performs peak type control, for example, for V IN <V OUT , it can be D=TP1 / (TP1+TP2).

[0072] The loop control circuit 92 can adjust the duty cycle D of the modulation signal PWM according to the current or voltage control mode.

[0073] The control device 55 also includes a voltage comparison circuit or comparator 94, which receives an input voltage V IN and output voltage V OUT , and in response, provides an indication of the input voltage V IN With the output voltage V OUT For example, the comparator 94 can compare the output voltage V OUT With input voltage V IN The difference or ratio between them is used to provide a comparison signal BB.

[0074] In fact, the comparison signal BB indicates that the input voltage V IN Is it greater than, less than, or equal to the output voltage V OUT .

[0075] The control device 55 comprises an intermediate phase circuit or module 95 which is responsive to the switching of the modulation signal PWM between the first value and the second value ( Figure 6 In the example of c ) to provide an intermediate phase control signal PH_INT.

[0076] The intermediate phase control signal PH_INT may be a square wave signal or other type of signal having a duration TF2 indicating the duration of the intermediate phase of the regulator 50 .

[0077] The intermediate phase circuit 95 may be configured such that the duration TF2 of the intermediate phase signal PH_INT is shorter than or equal to the nominal duration.

[0078] The nominal duration may be programmed, for example, by a user during a calibration or initialization phase of the regulator 50. This allows a high degree of configurability of the regulator 50 to be obtained.

[0079] The nominal duration may be indicated as the duration of the switching period T CLK small part.

[0080] The nominal duration can be determined by the comparator 94 when the input voltage V IN With the output voltage V OUT The switching period T is selected according to the accuracy of the comparison and the internal parameters of the control device 55, such as the blanking time. CLK The nominal duration of the intermediate phase signal PH_INT between 15% and 30% of the current flow rate may allow the output voltage V to be obtained in a wide range of operating scenarios of the regulator 50. OUT At the nominal value V REF Correct adjustment of the

[0081] In this embodiment, the switching period T CLK The duration TF2 within the switching period T is equal to the nominal duration. However, the intermediate phase circuit 95 can modify the duration TF2 according to the duty cycle D of the signal PWM so that CLK shorter than the nominal duration or even equal to zero.

[0082] The control device 55 comprises a driver logic circuit or module 96 which provides the switch control signals T1 - T4 starting from the modulation signal PWM, the comparison signal BB and the intermediate phase signal PH_INT.

[0083] In practice, the drive logic circuit 96, the intermediate phase circuit 95 and the feedback circuit 92 form a generator circuit for the switch control signals T1-T4.

[0084] In detail, in each switching cycle T CLK In the embodiment, the control device 55 controls the regulator 50 in the following phases: an initial control phase PH1 (in Figure 6 In the example, at the initial time t s With the switching time t c The duration of the intermediate control phase PH2 (between PH_INT and PH_INT) is equal to the duration TF2 of the intermediate phase signal PH_INT. Figure 6 In the example, at time t c With td and a final control phase PH3 of duration TF3 (between Figure 6 In the example, at time t d With t f between).

[0085] In particular, as a first approximation, the duration TF1 of the initial control phase PH1 may be shorter than or equal to the duration TP1 of the first modulation phase PWM1 .

[0086] As a first approximation, the duration TF3 of the final control phase PH3 may be shorter than or equal to the difference between the duration TP2 of the second modulation phase PWM2 and the duration TF2 of the intermediate phase signal PH_INT.

[0087] refer to Figure 7 , describes when the comparison signal BB indicates the input voltage V IN Greater than the output voltage V OUT The operation of the regulator 50 is performed.

[0088] In the initial control phase PH1 , the driving logic circuit 96 generates switch control signals T1 - T4 to control the closing of the first low-side switch 69 and the second high-side switch 82 , and the opening of the first high-side switch 68 and the second low-side switch 83 .

[0089] In fact, if V IN >V OUT , then in the initial control phase PH1, the control device 55 controls the initial current path 100 in the switch circuit 53 (at Figure 7 ) is formed between ground 78 and output node 54 through inductor 87.

[0090] In detail, referring to the illustrated embodiment of the switch circuit 53 , the initial current path 100 includes the shunt resistor 80 , the first low-side switch 69 , the inductor 87 , and the second high-side switch 82 in sequence.

[0091] In the intermediate control phase PH2 , the driving logic circuit 96 generates switch control signals T1 - T4 to control the closing of the first high-side switch 68 and the second low-side switch 83 , and the opening of the first low-side switch 69 and the second high-side switch 82 .

[0092] In fact, if V IN >V OUT , then in the intermediate control stage PH2, the control device 55 controls the intermediate current path 101 in the switch circuit 53 (at Figure 7 The inductor 87 forms an inductor 87 between the input node 51 and the ground 78 (indicated by the dot-dash arrow in the figure).

[0093] In detail, referring to the illustrated embodiment of the switch circuit 53 , the intermediate current path 101 includes, in sequence, the first high-side switch 68 , the inductor 87 , the second low-side switch 83 , and the shunt resistor 80 .

[0094] In the final control phase PH3 , the drive logic circuit 96 generates switch control signals T1 - T4 to control the closing of the first high-side switch 68 and the second high-side switch 82 , and the opening of the first low-side switch 69 and the second low-side switch 83 .

[0095] In fact, if V IN >V OUT , then in the final control stage PH3, the control device 55 controls the final current path 102 in the switch circuit 53 (at Figure 7 ) is formed between the input node 51 and the output node 54 through the inductor 87.

[0096] In detail, referring to the illustrated embodiment of the switch circuit 53 , the final current path 102 includes the first high-side switch 68 , the inductor 87 , and the second high-side switch 83 in sequence.

[0097] refer to Figure 7 , it can be verified, for example, that for V IN >V OUT And D = TP2 / (TP1+TP2),

[0098] (Vin-Vout)·[(D·T CLK )-TF2]-Vout·(1-D)·T+Vin·

[0099] TF2=0, so

[0100] refer to Figure 8 , describes when the comparison signal BB indicates the input voltage V IN Lower than the output voltage V OUT The operation of the regulator 50 is performed.

[0101] In the initial control phase PH1 , the driving logic circuit 96 generates switch control signals T1 - T4 to control the closing of the first high-side switch 68 and the second low-side switch 83 , and the opening of the first low-side switch 69 and the second high-side switch 82 .

[0102] In fact, if V IN <V OUT , then in the initial control phase PH1, the control device 55 controls the initial current path 105 in the switch circuit 53 (at Figure 8 ) is formed between the input node 51 and the ground 78 through the inductor 87.

[0103] In detail, referring to the illustrated embodiment of the switch circuit 53 , the initial current path 105 includes the first high-side switch 68 , the inductor 87 , the second low-side switch 83 , and the shunt resistor 80 in sequence.

[0104] In the intermediate control phase PH2 , the driving logic circuit 96 generates switch control signals T1 - T4 to control the closing of the first low-side switch 69 and the second high-side switch 82 , and the opening of the first high-side switch 68 and the second low-side switch 83 .

[0105] In fact, if V IN <V OUT , then in the intermediate control phase PH2, the control device 55 controls the intermediate current path 106 in the switch circuit 53 (at Figure 8 8 (indicated by the dash-dot arrow in the figure) is formed between the ground 78 and the output node 54 through the inductor 87.

[0106] In detail, referring to the illustrated embodiment of the switch circuit 53 , the intermediate current path 106 includes, in sequence, the shunt resistor 80 , the first low-side switch 69 , the inductor 87 , and the second high-side switch 82 .

[0107] In the final control phase PH3 , the drive logic circuit 96 generates switch control signals T1 - T4 to control the closing of the first high-side switch 68 and the second high-side switch 82 , and the opening of the first low-side switch 69 and the second low-side switch 83 .

[0108] In fact, if V IN <V OUT , then in the final control stage PH3, the control device 55 controls the final current path 107 in the switch circuit 53 (at Figure 8 ) is formed between the input node 51 and the output node 54 through the inductor 87.

[0109] In detail, referring to the illustrated embodiment of the switch circuit 53 , the final current path 107 includes the first high-side switch 68 , the inductor 87 , and the second high-side switch 82 in sequence.

[0110] refer to Figure 8 , it can be verified, for example, that for V IN <V OUT And D = TP1 / (TP1+TP2),

[0111] Vin·(D·T CLK )-Vout·TF2+(Vin-Vout)[(1-D)*T CLK -TF2]=0, so

[0112] If the comparison signal BB indicates V IN =V OUT , the control device 55 may be configured according to a specific embodiment, according to the reference Figure 7 For V IN >V OUT description made, or alternatively based on the referenced Figure 8 For V IN <V OUT As described above, the switch circuit 53 is controlled.

[0113] according to Figure 7 and Figure 8 The presented V OUT / V IN Formula, by selecting the duration TF2 of the intermediate control phase PH2, it is possible to limit the control device 55 to output the voltage V OUT Controlled at reference value V REF capability, even for V OUT ≈V IN .

[0114] In fact, according to the input voltage V IN With the output voltage V OUT The control device 55 compares the switching period T CLK Modify the sequence (order) of the three different control stages.

[0115] The applicant has verified that in the switching period T CLK The memory allows the output voltage V OUT is effectively regulated to the reference value V REF , whether for V IN >V OUT Or for V IN <V OUT , even at V IN ≈V OUT This also applies in the case of . In fact, this allows the control device 55 to avoid using the transition mode described with reference to the known regulator 1.

[0116] In particular, according to V IN With V OUT A direct comparison between IN >V OUT or V IN <V OUT ) The possibility of determining the order of the three phases allows avoiding the use of complex voltage thresholds for determining the operating mode of the regulator 50.

[0117] The order of use depends on the input voltage V IN With the output voltage V OUTThe comparison between the initial control stage, the intermediate control stage and the final control stage, when the regulator 50 is from V IN >V OUT becomes V IN <V OUT (and vice versa), it also allows to avoid discontinuities in the control variable of the control device, such as the feedback circuit 92. Thus, the regulator 50 is not affected by high current peaks through the inductor 87.

[0118] Fig. 9 Different embodiments of a regulator 50 are shown, which comprises a switching circuit 53 and a control device 155 .

[0119] The control device 155 is configured to perform current control of the regulator 50 .

[0120] The control device 155 includes a comparator 94 , an oscillator 160 , a loop control circuit 161 , an intermediate phase generator circuit 162 , and a drive logic circuit 96 .

[0121] The oscillator 160 provides a clock signal CLK and a stop signal STOP.

[0122] The stop signal STOP, for example a square wave logic signal, indicates a maximum modulation duration (or stop duration) stp. The maximum modulation duration stp may indicate a switching period T CLK small part.

[0123] For example, longer than or equal to the switching period T CLK 40% especially included in the switching period T CLK Values ​​of the maximum modulation duration stp between 50% and 65% can ensure a high regulating efficiency of the control device 55 .

[0124] The oscillator 161 may receive a maximum duration signal D_STOP, for example from an external user of the regulator 50 , for example during an initialization step for setting a maximum modulation duration stp.

[0125] According to one embodiment, Fig.10 and Fig.11 As shown in the example of FIG. 1 , after a time interval from the start of the switching period, the oscillator 160 switches the stop signal STOP from the first value to the second value (at Fig.10 and Fig.11 The time interval is equal to the maximum modulation duration stp.

[0126] In this embodiment, the loop control circuit 161 includes an error amplifier, here OTA 170, which receives an indication output voltage V OUTWith reference voltage V REF The error signal between V E ; and a compensation network 171 coupled to an output terminal 172 of the OTA 170.

[0127] Specifically, in this embodiment, a voltage divider circuit 173, for example formed here by two resistors R'd, R"d coupled in series, is coupled to the output node 54. The OTA 170 has an input terminal and a second input terminal, the input terminal being coupled to the middle node of the voltage divider circuit 173 at a voltage FB, and the second input terminal receiving an indication reference voltage V REF signal REF.

[0128] The output terminal 172 of OTA 170, also referred to as the control node, is controlled at a control voltage V C The loop control circuit 161 further includes a voltage-current conversion circuit 174, for example, formed by a series circuit including a resistor Rc and an NMOS transistor, and the voltage-current conversion circuit 174 converts the control voltage V C Converted into control current I C .

[0129] In this embodiment, the compensation network 171 is second order and includes two capacitors Cp1, Cp2 and a resistor Rp. E With control voltage V C Depending on the particular desired transfer function between the two, the compensation network can be of different types, for example first order or third order, and include a different number of electrical components.

[0130] The loop control circuit 161 further includes a current comparator 176, which is coupled to the shunt resistor 80 of the switch circuit 53 at an input terminal and is configured to provide a transition signal CMP according to a comparison between the current flowing through the shunt resistor 80 and the threshold current Ith. For example, by measuring the current flowing through the shunt resistor 80, the control device 155 can adjust the current level of V IN >V OUT valley current control is performed and the V IN <V OUT Performs peak type current control.

[0131] The threshold current Ith is the control current I c , and optionally, one or more correction current values. For example, in the embodiment shown, the threshold current is determined by the control current I C The sum of the slope compensation current Islp (eg, the current ramp generated by the dedicated ramp generator 177) gives .

[0132] The modulation logic circuit 180 of the loop control circuit 161 receives the transition signal CMP and the clock signal CLK and, in response, provides a modulation signal PWM.

[0133] Specifically, the modulation logic circuit 180 responds to the change of the current comparator 176 during the switching period T CLK The modulation signal PWM is switched from a first value to a second value.

[0134] In this embodiment, the modulation logic circuit 180 also provides a trigger signal TRG in response to the switching of the modulation signal PWM. The trigger signal TRG indicates the switching of the modulation signal PWM from the first value to the second value. For example, the trigger signal TRG can be the rising edge (or falling edge) of the modulation signal PWM itself. Alternatively, in order to simplify the design, the trigger signal TRG can be one of the switch control signals T1-T4.

[0135] The intermediate phase circuit 162 receives the stop signal STOP and the trigger signal TRG, and in response, provides an intermediate phase signal PH_INT.

[0136] In fact, also here, the drive logic circuit 96 , the intermediate phase circuit 162 and the feedback circuit 161 form a generator circuit of the switch control signals T1 - T4 .

[0137] refer to Fig.10 , the intermediate phase circuit 162 switches the intermediate phase signal PH_INT to a high logic value in response to receiving the trigger signal TRG, here in response to the rising edge of the trigger signal TRG.

[0138] The intermediate phase circuit 162 switches the switching period T according to the stop duration stp and the switching time of the modulation signal PWM. CLK The intermediate phase signal PH_INT is switched to a low logic value.

[0139] In detail, Fig.10 As shown, if the difference T'diff between the stop duration stp and the duration TP1 of the first modulation phase PWM1 of the modulation signal PWM is greater than the nominal duration TF2 of the intermediate phase signal PH_INT (time t s With t' f The switching period CMT1 between the intermediate control phases PH2 and PH2 is equal to the nominal duration TF2.

[0140] If the difference T"diff between the stop duration stp and the duration TP1 of the first modulation phase PWM1 of the modulation signal PWM is less than the nominal duration TF2 of the intermediate phase signal PH_INT (at time t' f with t'f The duration of the intermediate control phase PH2 is equal to the difference T"diff, i.e. shorter than the nominal duration TF2.

[0141] In other words, the intermediate phase circuit 162 adjusts the duration of the intermediate control phase PH2 according to the time distance T'diff, T"diff between the event (here the rising edge) of the stop signal STOP and the switching moment of the modulation signal PWM between the first modulation phase PWM1 and the second modulation phase PWM2.

[0142] In practice, the duration of the intermediate control phase PH2 is adjusted according to the duty cycle D of the modulation signal PWM.

[0143] Adjusting the duration of the intermediate control phase PH2, in particular shortening it, allows the control device 55 to adjust the output voltage V OUT Adjust to the reference voltage V REF capability is optimized even if the output voltage V OUT With input voltage V IN The difference between them increases.

[0144] According to one embodiment, the duration TF2 of the intermediate control phase PH2 may be adjusted to a minimum value (eg comprised between 1 ns and 200 ns, in particular between 50 ns and 100 ns) to ensure safe operation of the driver generating the switch control signals T1 - T4 .

[0145] According to one embodiment, if the switching of the signal PWM in the switching period is after the switching of the stop signal STOP, the intermediate phase circuit 162 may be configured to not activate the intermediate control phase PH2, such as Fig.11 An exemplary waveform is shown.

[0146] In other words, if the duration TP1 of the first modulation phase PWM1 is longer than the maximum modulation duration stp, the control device 155 does not command the execution of the intermediate control phase PH2.

[0147] In fact, in this embodiment, the control device 155 modifies the order of the control phases so that the intermediate control phase PH2 is not executed and the final control phase PH3 is executed in response to the end of the initial control phase PH1. Fig.10 As discussed, the final control phase PH3 may have a longer duration (e.g. at a limit equal to TP2). IN >V OUT Control Mode and V IN <V OUTTransitions between control modes may occur without discontinuities in control parameters of control device 155 .

[0148] This allows the output voltage V OUT is effectively regulated to the reference voltage V REF , even when the output voltage V OUT With input voltage V IN When the difference between the IN >V OUT The duty cycle tends to a minimum value (e.g., several %) when V IN <V OUT The duty cycle tends to a maximum value (eg, about 60-70%).

[0149] Fig.12 A further exemplary embodiment of a regulator 50 is shown, which comprises a switching circuit 53 and a control device 205 .

[0150] The control device 205 has Figure 5 The control device 55 and Fig. 9 The overall structure of the control device 155 in FIG. 1 is similar to the overall structure of FIG. 1 ; therefore, common elements are indicated by the same figure marks and will not be described in further detail.

[0151] The control device 205 here also includes a control loop circuit 92 , a comparator 94 , a drive logic circuit 96 , and an intermediate phase circuit 162 .

[0152] In this embodiment, the oscillator indicated by 208 provides a long stop signal STOP_H and a short stop signal STOP_L. The long stop signal STOP_H indicates a maximum modulation duration stp_h, and the short stop signal STOP_L indicates a maximum modulation duration stp_l, where stp_l <stp_h。

[0153] For example, the long stop signal STOP_H and the short stop signal STOP_L may indicate a switching period T CLK A portion of the invention is included between 40% and 65%.

[0154] Here, the oscillator 208 may also receive a signal D_STOP, for example, from an external user of the regulator 200 , to set the durations stp_1 and stp_h.

[0155] The control device 205 further includes a stop selection circuit 210 which receives the long stop signal STOP_H, the short stop signal STOP_L and the intermediate phase signal PH_INT and provides one of the long stop signal STOP_H and the short stop signal STOP_L at an output terminal.

[0156] As in Fig.13 As shown in detail in FIG. 2 , the stop selection circuit 210 includes two or more memory elements, here two flip-flops 213A and 213B cascaded to each other and a multiplexer 215 .

[0157] The output of the last flip-flop 213B forms the selection signal SEL.

[0158] The multiplexer 215 receives the long stop signal STOP_H, the short stop signal STOP_L, and the selection signal SEL, and provides one of the long stop signal STOP_H and the short stop signal STOP_L according to the selection signal SEL.

[0159] The flip-flop 213A is reset according to the intermediate phase signal PH_INT. In particular, in the illustrated embodiment, the inverter 217 receives the intermediate phase signal PH_INT. The AND logic gate 218 has an input terminal coupled to the output terminal of the inverter 217 and another input terminal, in which the AND logic gate receives the enable signal EN. The flip-flop 213A has a reset input terminal RST, which is coupled to the output terminal of the AND logic gate 218.

[0160] The AND logic gate 220 receives the enable signal EN and the stop signal output from the multiplexer 215 at its input.

[0161] The enable signal EN is optional and may be used to enable or disable the stop selection circuit 210 depending on the specific application.

[0162] When using, refer to Fig.14 In the exemplary waveform of the switching cycle CMT-1, the stop signal STOP is equal to one of the long stop signal STOP_H and the short stop signal STOP_L. For simplicity and by way of example only, it is assumed that in the switching cycle CMT-1, the stop signal STOP is equal to the long stop signal STOP_H.

[0163] In the switching cycle CMT-1, the intermediate phase signal PH_INT is asserted. Actually, in the switching cycle CMT-1, the modulation signal PWM has been switched before the long stop signal STOP_H.

[0164] At the end of the switching cycle CMT-1 (time t' f ), the selection signal SEL does not switch (specifically, here, it maintains a low value).

[0165] Then, in the subsequent switching cycle CMT- 2 , the multiplexer 215 still provides the long stop signal STOP_H.

[0166] Reference again Fig.14 In the example of , in the consecutive switching cycle CMT-N, the intermediate phase signal PH_INT is not asserted. In fact, in the switching cycle CMT-N, the modulation signal PWM has been switched after the long stop signal STOP_H.

[0167] In this case, at the end of the switching cycle CMT-N (time t'' f ), the selection signal SEL switches, in particular assumes a high logic value here. Then, for the successive switching cycles CMT-N+1, the multiplexer 215 provides a short stop signal STOP_L.

[0168] The short stop signal STOP_L will be provided until, in a subsequent switching cycle not shown here, a switching of the modulation signal PWM occurs before the short stop signal STOP_L, thus leading to activation of the intermediate control phase TF2 .

[0169] In other words, the stop selection circuit 210 is configured to implement a hysteresis between the long stop signal STOP_H and the short stop signal STOP_L in response to the inactivation of the intermediate control stage TF2 within the switching cycle.

[0170] This allows to prevent two consecutive switching cycles CMT N 、CMT N+1 A small change in the duration TP1 of the modulation signal PWM between 1 and 2 causes the activation of the intermediate control phase TF2 . Thus, the control device 205 can provide a high stability of the regulator 50 .

[0171] In particular, when the input voltage V IN Lower than the output voltage V OUT In response to the previous switching cycle CMT N-1 The intermediate control stage TF2 is not activated during the switching period CMT N The fact that a short stop signal STOP_L is used may be useful for increasing the stability of the regulator 50 .

[0172] Finally, modifications and variations may be made to the regulator 50 , the control devices 55 , 155 , 205 and the associated control methods described and illustrated herein, without thereby departing from the scope of the present invention as defined in the appended claims.

[0173] For example, comparator 94 may be implemented in a manner known per se using a threshold comparator with hysteresis, which helps to IN With V OUT hysteresis is introduced in the comparison between VIN Exactly equal to V OUT Oscillates between high and low values.

[0174] For example, the shunt resistor 80 may be configured according to the specific application, for example, according to the desired IN >V OUT and V IN <V OUT The switch circuit 53 is arranged at different locations depending on the type of current control implemented (valley or peak).

[0175] Alternatively, the shunt resistor 80 may not be present, and one or more of the switches 68, 69, 82, 83 may be used by the control device as a resistive element to measure the current flowing into the switch circuit 53 when in use, for implementation of current control. In particular, this may be useful if one or more of the switches 68, 69, 82, 83 are integrated into the same die as the control device.

[0176] Alternatively, the control device may be configured to perform voltage control of a voltage regulator. Fig.15 An embodiment of a regulator indicated by 250 is shown, the regulator comprising a switching circuit 253 and a control device 255 .

[0177] Unlike the switch circuit 53, in the switch circuit 253, the shunt resistor 80 may not be present. In fact, the common node 72 is directly coupled to the ground 78.

[0178] The control device 255 has Fig. 9 The overall structure of the control device 155 in FIG. 255 is similar to the overall structure of the control device 155 in FIG. 255 in detail, the control device 255 here also includes a comparator 94, a drive logic circuit 96, an intermediate phase circuit 162, an oscillator 160, and a feedback circuit indicated here by 260.

[0179] In the feedback circuit 260, the compensator 262 is configured to output the indicated output voltage V OUT With reference voltage V REF The difference between the error V E Start generating control voltage V C The compensator 262 may be formed, for example, by an error amplifier (eg, an operational amplifier) ​​and a compensation network. The feedback circuit 260 further includes a modulator 265, such as a voltage comparator, which modulates the control voltage V C With the threshold voltage V th is compared, and in response, a modulation signal PWM is provided. For example, the threshold voltage V th It has a sawtooth behavior and is generated by a specific generator 267 controlled by the clock signal CLK.

[0180] For example, the control device may be formed from analog, digital or mixed signal circuits or modules, depending on the specific application and implementation.

[0181] Finally, the different embodiments described above may be combined to provide additional solutions.

Claims

1. A control device for a switching voltage regulator, the control device comprising: an oscillator configured to generate a clock signal having a switching period; a voltage comparison circuit configured to generate a comparison signal indicating a comparison between an input voltage of a switch circuit of the switching voltage regulator at an input node and an output voltage of the switch circuit at an output node; as well as A drive signal generator circuit, the drive signal generator circuit being configured to: generating a switch control signal according to an error between the output voltage and the nominal voltage to drive a switch of the switch circuit, controlling a first control phase, a second control phase, and a third control phase within the switching cycle, wherein the switch control signal controls the formation of a first current path between the input node and the output node through the inductor element during the first control phase, the formation of a second current path between the input node and a common node through the inductor element during the second control phase, and the formation of a third current path between the output node and the common node through the inductor element during the third control phase, the common node being a node of the switch circuit having a common reference potential, A sequence of the first control phase, the second control phase, and the third control phase is modified within the switching cycle according to the comparison signal.

2. The control device according to claim 1, wherein the drive signal generator circuit is configured as: In response to the comparison signal indicating that the input voltage is greater than the output voltage, controlling the execution of the second control stage between the third control stage and the first control stage, and In response to the comparison signal indicating that the input voltage is less than the output voltage, the third control phase is controlled to be executed between the second control phase and the first control phase.

3. The control device according to claim 1, wherein the drive signal generator circuit comprises: a feedback circuit configured to provide a pulse width modulation signal, wherein the pulse width modulation signal defines a first modulation phase, a second modulation phase, and a third modulation phase within the switching period, wherein the pulse width modulated signal has a first value at the first modulation phase, a second value at the second modulation phase, a duration of the first modulation phase, and a duration of the second modulation phase, the duration of the first modulation phase and the duration of the second modulation phase being a function of an error between the output voltage and the nominal voltage, wherein the drive signal generator circuit is configured to control an initial control phase, an intermediate control phase, and a final control phase within the switching period, the initial control phase corresponding to the first modulation phase, the intermediate control phase corresponding to the switching of the pulse width modulation signal between the first value and the second value, The initial control stage, the intermediate control stage and the final control stage correspond to the first control stage, the second control stage and the third control stage respectively.

4. A control device according to claim 3, wherein the drive signal generator circuit is configured to adjust the duration of the intermediate control phase according to a duty cycle of the pulse width modulation signal, the duty cycle indicating a ratio between the duration of the first modulation phase and the duration of the second modulation phase.

5. The control device of claim 3, wherein the drive signal generator circuit is configured to adjust the duration of the intermediate control phase according to a duty cycle of the pulse width modulation signal between a nominal value and a minimum value, the minimum value being less than the nominal value.

6. A control device according to claim 3, wherein the drive signal generator circuit is configured to adjust the duration of the intermediate control phase according to the difference between a maximum modulation duration and a duration of the first modulation phase, wherein the maximum modulation duration is shorter than or equal to the duration of the switching cycle.

7. The control device according to claim 6, wherein the oscillator is configured to generate a stop signal during the switching period, the stop signal having an event, the event indicating the maximum modulation duration, and The driving signal generator circuit is configured as follows: receiving the stop signal, and The duration of the intermediate control phase is adjusted depending on the temporal distance between the event of the stop signal and the switching of the pulse width modulation signal.

8. The control device according to claim 7, wherein the drive signal generator circuit is configured to: In response to the duration of the first modulation phase within the switching period being shorter than the maximum modulation duration, commanding execution of the intermediate control phase within the switching period, and In response to the duration of the first modulation phase being longer than the maximum modulation duration, execution of the intermediate control phase within the switching cycle is not commanded.

9. The control device according to claim 6, wherein the control device is configured to: receiving a maximum duration signal indicating the maximum modulation duration; and The maximum modulation duration is set according to the maximum duration signal.

10. The control device according to claim 6, wherein the maximum modulation duration is a first maximum modulation duration, Wherein the oscillator is configured as: generating a first stop signal, the first stop signal indicating the first maximum modulation duration, and generating a second stop signal, the second stop signal indicating a second maximum modulation duration, the second maximum modulation duration being different from the first maximum modulation duration, The driving signal generator circuit is configured as follows: comparing the duration of the first modulation phase with the first maximum modulation duration in a first switching cycle, and In response to the duration of the first modulation phase being longer than the first maximum modulation duration, the duration of the first modulation phase is compared with the second maximum modulation duration in a second switching cycle, the second switching cycle being subsequent to the first switching cycle.

11. The control device of claim 10, wherein the first maximum modulation duration is longer than the second maximum modulation duration.

12. A switching voltage regulator, comprising: Switching circuit; as well as A control device, the control device being configured to control the switch circuit, the control device comprising: an oscillator configured to generate a clock signal having a switching period; a voltage comparison circuit configured to generate a comparison signal indicating a comparison between an input voltage of the switch circuit at an input node and an output voltage of the switch circuit at an output node; and A drive signal generator circuit, the drive signal generator circuit being configured to: generating a switch control signal according to an error between the output voltage and the nominal voltage to drive a switch of the switch circuit, A first control stage, a second control stage, and a third control stage are controlled within the switching cycle, wherein the switch control signal controls the formation of a first current path between the input node and the output node through the inductor element during the first control stage, the formation of a second current path between the input node and a common node through the inductor element during the second control stage, and the formation of a third current path between the output node and the common node through the inductor element during the third control stage, the common node being a node of the switch circuit having a common reference potential, and the sequence of the first control stage, the second control stage, and the third control stage are modified within the switching cycle according to the comparison signal.

13. The switching voltage regulator of claim 12, wherein the switching circuit is a four-switch non-inverting switching circuit.

14. The switching voltage regulator of claim 12, wherein the drive signal generator circuit is configured to: In response to the comparison signal indicating that the input voltage is greater than the output voltage, controlling the execution of the second control stage between the third control stage and the first control stage, and In response to the comparison signal indicating that the input voltage is less than the output voltage, the third control phase is controlled to be executed between the second control phase and the first control phase.

15. The switching voltage regulator of claim 12, wherein the drive signal generator circuit comprises: a feedback circuit configured to provide a pulse width modulation signal, wherein the pulse width modulation signal defines a first modulation phase, a second modulation phase, and a third modulation phase within the switching period, wherein the pulse width modulated signal has a first value at the first modulation phase, a second value at the second modulation phase, a duration of the first modulation phase, and a duration of the second modulation phase, the duration of the first modulation phase and the duration of the second modulation phase being a function of an error between the output voltage and the nominal voltage, wherein the drive signal generator circuit is configured to control an initial control phase, an intermediate control phase, and a final control phase within the switching period, the initial control phase corresponding to the first modulation phase, the intermediate control phase corresponding to the switching of the pulse width modulation signal between the first value and the second value, The initial control stage, the intermediate control stage and the final control stage correspond to the first control stage, the second control stage and the third control stage respectively.

16. A method for operating a switching voltage regulator, the method comprising: generating a clock signal by an oscillator of a control device, the control device being used to operate a switching circuit of the switching voltage regulator, the clock signal having a switching period; generating, by a voltage comparison circuit of the control device, a comparison signal indicating a comparison between an input voltage of the switch circuit at an input node and an output voltage of the switch circuit at an output node; generating a switch control signal by a drive signal generator circuit of the control device according to an error between the output voltage and a nominal voltage to drive a switch of the switch circuit; controlling a first control phase, a second control phase, and a third control phase within the switching cycle, wherein the switch control signal controls the formation of a first current path between the input node and the output node through the inductor element during the first control phase, the formation of a second current path between the input node and a common node through the inductor element during the second control phase, and the formation of a third current path between the output node and the common node through the inductor element during the third control phase, the common node being a node of the switch circuit having a common reference potential; as well as A sequence of the first control phase, the second control phase, and the third control phase is modified within the switching cycle according to the comparison signal.

17. The method according to claim 16, further comprising: In response to the comparison signal indicating that the input voltage is greater than the output voltage, the drive signal generator circuit controls the second control stage to be executed between the third control stage and the first control stage, and The third control stage is controlled by the drive signal generator circuit to be executed between the second control stage and the first control stage in response to the comparison signal indicating that the input voltage is less than the output voltage.

18. The method according to claim 16, further comprising: generating a pulse width modulation signal by a feedback circuit of the drive signal generator circuit, wherein the pulse width modulation signal defines a first modulation phase, a second modulation phase, and a third modulation phase within the switching period, wherein the pulse width modulated signal has a first value at the first modulation phase, a second value at the second modulation phase, a duration of the first modulation phase, and a duration of the second modulation phase, the duration of the first modulation phase and the duration of the second modulation phase being a function of an error between the output voltage and the nominal voltage, The driving signal generator circuit controls an initial control phase, an intermediate control phase and a final control phase within the switching period, wherein the initial control phase corresponds to the first modulation phase, and the intermediate control phase corresponds to the switching of the pulse width modulation signal between the first value and the second value. The initial control stage, the intermediate control stage and the final control stage correspond to the first control stage, the second control stage and the third control stage respectively.

19. The method according to claim 18, further comprising: The duration of the intermediate control phase is adjusted by the drive signal generator circuit according to a duty cycle of the pulse width modulation signal, the duty cycle indicating a ratio between a duration of the first modulation phase and a duration of the second modulation phase.

20. The method of claim 18, further comprising: The duration of the intermediate control phase is adjusted by the drive signal generator circuit according to a duty cycle of the pulse width modulation signal between a nominal value and a minimum value, the minimum value being less than the nominal value.

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