A low-voltage and high-voltage compatible LDO circuit

Abstract

The present invention discloses an LDO circuit compatible with a low voltage domain and an overvoltage domain, belonging to the technical field of LDO circuits, wherein the LDO circuit comprises PMOS tubes P1-P14, NMOS tubes N1-N17, an input IB1 and an output VOUT; wherein the PMOS tubes P1-P4 constitute a current mirror, the NMOS tubes N5-N9 are a first voltage-dividing structure connected by a diode, and the NMOS tubes N16-N17 are a second voltage-dividing structure connected by a diode; the NMOS tubes N14-N15 and the PMOS tube P13 divide the voltage under overvoltage to ensure that no MOS tube has an overvoltage voltage from the power supply AVDD to the ground GND; at the same time, the NMOS tubes N14-N15 and the PMOS tube P13 do not divide the voltage under low voltage, and do not affect the normal operation of the LDO circuit. The present invention uses low-voltage devices to realize an LDO structure compatible with both overvoltage and low voltage, which can not only realize the demand for overvoltage with low-voltage devices, but also meet the requirement that the performance does not decay under low voltage.

Description

Technical Field

[0001] The present invention belongs to the technical field of LDO circuits, and in particular relates to an LDO circuit that is compatible with a low voltage domain and an overvoltage domain. Background Art

[0002] Existing LDO circuits select devices based on the size of the power supply voltage domain; for example, a 3.3v power supply voltage will select a 3.3v device, and a 5v power supply voltage will select a 5v device. However, for some processes, the design requirement is to meet the 5v power supply voltage, but the process only supports 3.3v devices. At the same time, it is also necessary to take into account the performance requirements at low voltage after battery attenuation. For example, when the battery attenuates to 2.3v, the performance cannot be attenuated. This requires a special design that can not only meet the overvoltage requirements with low-voltage devices, but also meet the requirement of no performance attenuation at low voltage. To this end, we propose an LDO circuit that is compatible with both the low-voltage domain and the overvoltage domain. Summary of the invention

[0003] The object of the present invention is to provide an LDO circuit compatible with a low voltage domain and an overvoltage domain, and to implement an LDO structure compatible with both overvoltage and low voltage by using low voltage devices, so as to solve the problems raised in the above background technology.

[0004] To achieve the above object, the present invention provides the following technical solutions: an LDO circuit compatible with a low voltage domain and an overvoltage domain, the LDO circuit comprising PMOS tubes P1 to P14, NMOS tubes N1 to N17, an input IB1 and an output VOUT;

[0005] Among them, the PMOS tubes P1~P4 form a current mirror, the NMOS tubes N5~N9 are a first voltage-dividing structure connected by diodes, and the NMOS tubes N16~N17 are a second voltage-dividing structure connected by diodes; the NMOS tubes N14~N15 and the PMOS tube P13 divide the voltage under overvoltage to ensure that no MOS tube has overvoltage from the power supply AVDD to the ground GND; at the same time, the NMOS tubes N14~N15 and the PMOS tube P13 do not divide the voltage under low voltage, so as not to affect the normal operation of the LDO circuit;

[0006] In the overvoltage state, the NMOS tubes N14, N15 and the PMOS tube P13 work in the saturation region for voltage division; in the low voltage state, the NMOS tubes N14, N15 work in the linear resistance region to form a switch tube. At this time, the source and drain of the NMOS tubes N14, N15 do not divide the voltage, and the PMOS tubes P12 and P13 form a series tube.

[0007] Preferably, in the overvoltage state of the LDO circuit, the NMOS tubes N14, N15 and the PMOS tube P13 operate in the saturation region for voltage division, specifically including:

[0008] When the power supply voltage works under overvoltage, the gate voltages of NMOS tubes N14 and N15 are biased by NMOS tubes N5~N9, and NMOS tube N15 works in the saturation region or subthreshold region, and the source and drain of NMOS tubes N14 and N15 play a voltage-dividing role; at the same time, NMOS tube N15 acts as a source follower, and the source voltage is used to provide bias voltage to PMOS tube P13; at this time, PMOS tube P13 works in the saturation region, and the source and drain play a voltage-dividing role, ensuring that PMOS tube P12 works in a non-overvoltage state.

[0009] Preferably, in the low voltage state, the NMOS tubes N14 and N15 work in the linear resistance region to form a switch tube. At this time, the source and drain of the NMOS tubes N14 and N15 are not divided, and the PMOS tubes P12 and P13 form a series tube, specifically including:

[0010] When the power supply voltage works at a lower voltage, the bias voltage provided by NMOS tubes N5~N9 to NMOS tubes N14 and N15 is the power supply voltage. At this time, NMOS tubes N14 and N15 work in the linear resistance area to form switch tubes, and the source and drain do not consume voltage; at the same time, PMOS tubes P12 and P13 form a series tube, which ensures the normal working state of the MOS tubes at a lower voltage.

[0011] Preferably, the LDO circuit further includes resistors R1, R2, capacitors C1, C2 and a feedback voltage VFB;

[0012] Among them, one end of the resistor R1 is connected to the output VOUT, and the other end is connected to the feedback voltage VFB, while one end of the resistor R2 is connected to the feedback voltage VFB, and the other end is grounded GND; one end of the capacitor C1 is connected to the output VOUT, and the other end is connected to the feedback voltage VFB, while one end of the capacitor C2 is connected to the output VOUT, and the other end is grounded GND.

[0013] Preferably, the NMOS tubes N14 and N15 are deep n-well MOS tubes, which are 6-terminal devices, Gate is a gate, source is a source, drain is a drain, dnw is a deep N-well, buck is a substrate, and psub is a P-type substrate.

[0014] Preferably, the substrates of the NMOS transistors N1 - N17 are connected to the ground GND, and the substrates of the PMOS transistors P1 - P14 are connected to the power supply voltage AVDD.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] The present invention realizes voltage division by combining conventional current mirrors and common source and common gate transistors through PMOS transistors P1-P4 and NMOS transistors N1-N17, and can make the MOS transistors work in the saturation region or subthreshold region under 2.3V (low voltage state) and 5.5V (high voltage state). NMOS transistors N5-N9 obtain a bias voltage under current mirrors P2 and P4 to provide bias to N14 and N15, wherein N14 and N15 are deep n-well MOS transistors (deep N well process NMOS transistors), and the drain end of N15 provides a bias voltage to P13. Under 5.5V overvoltage, N14, N15, and P13 work in the saturation region for voltage division. Under 2.3V low voltage, N14 and N15 work in the linear resistance region, similar to a switch tube, the source and drain are not divided, and P12 and P13 form a series tube. The design of this special circuit can not only meet the overvoltage requirements with low-voltage devices, but also ensure that the performance does not decay under low voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The present invention is a circuit diagram of an LDO circuit that is compatible with a low voltage domain and an overvoltage domain. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] like Figure 1 As shown, an LDO circuit compatible with low voltage domain and overvoltage domain, in which P1~P14 are PMOS tubes; N1~N17 are NMOS tubes; R1 and R2 are resistors; C1 and C2 are capacitors. The substrates of all NMOS tubes are grounded GND, and the substrates of PMOS tubes are connected to the power supply voltage AVDD.

[0020] N14 and N15 are deep n-well MOS tubes (deep N well process NMOS tubes), which are 6-terminal devices. Figure 1 The upper left corner shows the port information. Gate is the gate, source is the source, drain is the drain, dnw is the deep N-well, buck is the substrate, and psub is the P-type substrate.

[0021] Below is Figure 1 The connection structure relationship of each circuit element in:

[0022] Input IB1 is connected to the drain and gate of NMOS tube N3, and the gates of NMOS tubes N4, N12, and N13; the drain and gate of NMOS tube N1 are electrically connected to the source of NMOS tube N3, and the gates of N2, N10, and N11; the sources of NMOS tubes N1 and N2 are connected to GND; the source of NMOS tube N4 is connected to the drain of NMOS tube N2; the drain of NMOS tube N4 is connected to the drain and gate of PMOS tube P3, and the gates of PMOS tubes P4 and P6; the source of PMOS tube P3 is connected to the drain and gate of PMOS tube P1, and the gates of PMOS tubes P2, P5, and P11; the drain of PMOS tube P2 is connected to the source of PMOS tube P4; the sources of PMOS tubes P1 and P2 are connected to AVDD; the drain of PMOS tube P4 is connected to the drain and gate of NMOS tube N9, and deep n-well The gates of MOS tubes N14 and N15 are connected; the source of NMOS tube N9 is connected to the gate and drain of NMOS tube N8; the source of NMOS tube N8 is connected to the gate and drain of NMOS tube N7; the source of NMOS tube N7 is connected to the gate and drain of NMOS tube N6; the source of NMOS tube N6 is connected to the gate and drain of NMOS tube N5; the source of NMOS tube N5 is connected to GND; the source of PMOS tube P5 is connected to AVDD, and the drain is connected to the source of PMOS tube P6;

[0023] The drain of PMOS tube P6 is connected with the source of PMOS tubes P7 and P8; the gate of PMOS tube P7 is connected with the reference voltage VREF, the gate of PMOS tube P8 is connected with the feedback voltage VFB, and one end of capacitor C1, resistor R1, R2 is also connected with the feedback voltage VFB; the drain of PMOS tube P7 is connected with the source of NMOS tube N13 and the drain of NMOS tube N11; the drain of PMOS tube P8 is connected with the source of N12 and the drain of NMOS tube N10; the source of NMOS tubes N10 and N11 is connected with GND;

[0024] The source and substrate of deep n-well MOS tube N14 and the drain of NMOS tube N12 are connected together; the drain of deep n-well MOS tube N14 and the deep N well are connected to the gate of PMOS tube P9, and the drain and the gate of PMOS tube P10 are electrically connected; the P-type substrates of deep n-well MOS tubes N14 and N15 are connected to GND; deep n-well The substrate and source of MOS tube N15 are connected to the drain of NMOS tube N13 and the gate of PMOS tube P13; the drain of NMOS tube N15 and the deep N well are connected to the drain of PMOS tube P10 and the gate of PMOS tube P12; the source of PMOS tubes P9~P14 are connected to AVDD; the drain of PMOS tube P11 is connected to the source of PMOS tube P12 and the gate of PMOS tube P14; the drain of PMOS tube P12 is connected to the source of PMOS tube P13; the drain of PMOS tube P13 is connected to the gate and drain of NMOS tube N17; the source of NMOS tube N17 is connected to the gate and drain of NMOS tube N16; the source of NMOS tube N16 is connected to GND; the drain of deep n-well MOS tube P14 is connected to the output VOUT, capacitors C1, C2, and one end of resistor R1; the other end of resistor R2 and capacitor C2 is connected to GND.

[0025] like Figure 1 As shown, for example, a 3.3 device is used to implement a design under a power supply voltage of 2.3v~5.5v. The voltage division is achieved by combining conventional current mirrors and common source and common gate transistors through PMOS tubes P1~P4 and NMOS tubes N1~N17, and the MOS tubes can be made to work in the saturation region or subthreshold region under 2.3v and 5.5v. NMOS tubes N5~N9 obtain a bias voltage under the current mirror PMOS tubes P2 and P4 to provide bias to N14 and N15, wherein N14 and N15 are deep n-well MOS tubes (deep N well process NMOS tubes), and the drain end of N15 provides a bias voltage to P13. Under the overvoltage of 5.5v, deep n-well MOS tubes N14, N15, and PMOS tube P13 work in the saturation region for voltage division. Under 2.3V low voltage, deep n-well MOS tubes, N14 and N15 work in the linear resistance region, similar to a switch tube, the source and drain are not divided, and PMOS tubes P12 and P13 form a series tube. This special circuit design can not only meet the requirements of overvoltage with low-voltage devices, but also meet the requirements of performance without attenuation under low voltage.

[0026] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0027] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An LDO circuit compatible with a low voltage domain and an overvoltage domain, characterized in that: The LDO circuit includes PMOS tubes P1 to P14, NMOS tubes N1 to N17, input IB1 and output VOUT; Among them, input IB1 is connected to the drain and gate of NMOS tube N3, and the gates of NMOS tubes N4, N12, and N13; the drain and gate of NMOS tube N1 are electrically connected to the source of NMOS tube N3, and the gates of NMOS tubes N2, N10, and N11; the sources of NMOS tubes N1 and N2 are connected to GND; the source of NMOS tube N4 is connected to the drain of NMOS tube N2; the drain of NMOS tube N4 is connected to the drain and gate of PMOS tube P3, and the gates of PMOS tubes P4 and P6; the source of PMOS tube P3 is connected to the drain and gate of PMOS tube P1, and the gates of PMOS tubes P2, P5, and P11; the drain of PMOS tube P2 is connected to GND; the source of NMOS tube N4 is connected to the drain of PMOS tube P3, and the gates of PMOS tubes P4 and P6; the source of PMOS tube P3 is connected to the drain and gate of PMOS tube P1, and the gates of PMOS tubes P2, P5, and P11; The gate of PMOS tube P4 is connected to the source of PMOS tube P1 and P2; the source of PMOS tube P1 and P2 is connected to AVDD; the drain of PMOS tube P4 is connected to the drain of NMOS tube N9, the gate and the gate of NMOS tube N14 and N15; the source of NMOS tube N9 is connected to the gate and drain of NMOS tube N8; the source of NMOS tube N8 is connected to the gate and drain of NMOS tube N7; the source of NMOS tube N7 is connected to the gate and drain of NMOS tube N6; the source of NMOS tube N6 is connected to the gate and drain of NMOS tube N5; the source of NMOS tube N5 is connected to GND; the source of PMOS tube P5 is connected to AVDD, and the drain is connected to the source of PMOS tube P6; The drain of PMOS tube P6 is connected with the source of PMOS tubes P7 and P8; the gate of PMOS tube P7 is connected with the reference voltage VREF, the gate of PMOS tube P8 is connected with the feedback voltage VFB, and one end of capacitor C1, resistor R1, R2 is also connected with the feedback voltage VFB; the drain of PMOS tube P7 is connected with the source of NMOS tube N13 and the drain of NMOS tube N11; the drain of PMOS tube P8 is connected with the source of N12 and the drain of NMOS tube N10; the source of NMOS tubes N10 and N11 is connected with GND; The source and substrate of NMOS tube N14, and the drain of NMOS tube N12 are connected together; the drain of NMOS tube N14 and the deep N well are connected to the gate of PMOS tube P9, and the drain and the gate of PMOS tube P10 are electrically connected; the P-type substrates of NMOS tubes N14 and N15 are connected to GND; the substrate and source of NMOS tube N15 are connected to the drain of NMOS tube N13 and the gate of PMOS tube P13; the drain of NMOS tube N15 and the deep N well are connected to the drain of PMOS tube P10 and the gate of PMOS tube P12; the source of PMOS tubes P9~P14 are connected to AVD D; the drain of PMOS tube P11 is connected with the source of PMOS tube P12 and the gate of PMOS tube P14; the drain of PMOS tube P12 is connected with the source of PMOS tube P13; the drain of PMOS tube P13 is connected with the gate and drain of NMOS tube N17; the source of NMOS tube N17 is connected with the gate and drain of NMOS tube N16; the source of NMOS tube N16 is connected to GND; the drain of NMOS tube P14 is connected with the capacitors C1, C2 and one end of resistor R1 to output VOUT; the other end of resistor R2 and capacitor C2 is connected to GND; At the same time, the PMOS tubes P1~P4 form a current mirror, the NMOS tubes N5~N9 are in the first voltage-dividing structure connected by diodes, and the NMOS tubes N16~N17 are in the second voltage-dividing structure connected by diodes; the NMOS tubes N14~N15 and the PMOS tube P13 divide the voltage under overvoltage to ensure that no MOS tube has overvoltage from the power supply AVDD to the ground GND; at the same time, the NMOS tubes N14~N15 and the PMOS tube P13 do not divide the voltage under low voltage, so as not to affect the normal operation of the LDO circuit; In the overvoltage state, NMOS tubes N14, N15 and PMOS tube P13 work in the saturation region for voltage division; in the low voltage state, the bias voltage provided by NMOS tubes N5~N9 to NMOS tubes N14 and N15 is the power supply voltage. At this time, NMOS tubes N14 and N15 work in the linear resistance region to form switch tubes, and the source and drain do not consume voltage; at the same time, PMOS tubes P12 and P13 form a series tube, which ensures the normal working state of the MOS tubes at a lower voltage.

2. The LDO circuit compatible with the low voltage domain and the overvoltage domain according to claim 1, characterized in that: In the overvoltage state, the NMOS tubes N14, N15 and the PMOS tube P13 of the LDO circuit work in the saturation region for voltage division, specifically including: When the power supply voltage works under overvoltage, the gate voltages of NMOS tubes N14 and N15 are biased by NMOS tubes N5~N9, and NMOS tube N15 works in the saturation region or subthreshold region, and the source and drain of NMOS tubes N14 and N15 play a voltage-dividing role; at the same time, NMOS tube N15 acts as a source follower, and the source voltage is used to provide bias voltage to PMOS tube P13; at this time, PMOS tube P13 works in the saturation region, and the source and drain play a voltage-dividing role, ensuring that PMOS tube P12 works in a non-overvoltage state.

3. A low voltage domain and overvoltage domain compatible LDO circuit according to any one of claims 1-2, characterized in that: The NMOS tubes N14 and N15 are deep n-well MOS tubes.

4. The LDO circuit compatible with the low voltage domain and the overvoltage domain according to claim 3, characterized in that: The substrates of the NMOS transistors N1 - N17 are connected to the ground GND, and the substrates of the PMOS transistors P1 - P14 are connected to the power supply AVDD.

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