Low-noise power amplification circuit, electronic circuit and electronic equipment

Abstract

The invention provides a low-noise power amplifier circuit, an electronic circuit and an electronic apparatus. According to the circuit, an input signal is amplified through a first cascode unit, and a first power signal is output; compensating an n-order nonlinear coefficient of drain current of a first MOS (Metal Oxide Semiconductor) tube in the first cascode unit through a nonlinear compensation unit; wherein n is a positive integer, and n is greater than or equal to 1; the grid electrode of the first MOS tube receives an input signal; the input impedance of the first cascode unit and the input impedance of the nonlinear compensation unit are matched through the first inductor; filtering the first power signal through a filtering unit; matching the output impedance of the first cascode unit through a buffer unit, buffering the first power signal, and outputting an output signal; according to the low-noise power amplification circuit provided by the invention, the linearity and the output impedance can be coordinated on the basis of coordinating the gain and the input impedance through the technical means.

Description

Technical Field

[0001] The present invention relates to the field of power amplification, and in particular to a low-noise power amplifier circuit, an electronic circuit and an electronic device. Background Art

[0002] In the core circuit of a traditional low noise amplifier (LNA), an inductor is usually connected in series between the source and ground of a low-order transistor. The inductor is adjusted to match the input impedance of the LNA and to increase the gain of the LNA through the LC parallel resonant network of the load.

[0003] However, the conventional LNA generally optimizes the linearity of transistors by adjusting the bias point of the transistors so that the transistors work in the linear amplification region. However, this method is easily affected by PVT (Process, Voltage, Temperature) and causes large deviations. At the same time, the output impedance of the conventional LNA is also very high. An LNA that coordinates linearity and output impedance on the basis of coordinating gain and input impedance is now needed. Summary of the invention

[0004] The present invention provides a low-noise power amplifier circuit, an electronic circuit and an electronic device, which can coordinate the linearity and output impedance of the circuit on the basis of coordinating the gain and the input impedance.

[0005] According to a first aspect of the present invention, there is provided a low-noise power amplifier circuit for amplifying power of an input signal, the circuit comprising:

[0006] A first cascode unit is used to power amplify the input signal and output a first power signal; wherein the first cascode unit includes a first MOS tube and a second MOS tube; the gate of the first MOS tube receives the input signal and a first bias voltage, the second end of the first MOS tube is connected to the first end of the second MOS tube, and the first end of the first MOS tube is grounded; the gate of the second MOS tube is connected to the power supply end, and the second end of the second MOS tube serves as the output end of the first cascode unit; wherein the first bias voltage and the power supply voltage are used to bias the first MOS tube and the second MOS tube respectively;

[0007] A nonlinear compensation unit, coupled to the gate of the first MOS tube and the second end of the first MOS tube respectively; the nonlinear compensation unit is used to compensate for the n-th order nonlinear coefficient of the drain current of the first MOS tube; wherein n is a positive integer, and n≥1;

[0008] A first inductor, coupled between the first end of the first MOS tube and the ground end and coupled between the nonlinear compensation unit and the ground end; the first inductor is used to match the input impedance of the first cascode unit and the nonlinear compensation unit;

[0009] a filter unit, coupled between the output end of the first cascode unit and the power end, the filter unit being used to filter the first power signal;

[0010] A buffer unit is coupled to the output end of the first cascode unit; the buffer unit is used to match the output impedance of the first cascode unit; the buffer unit is also used to buffer the first power signal and output an output signal.

[0011] Optionally, the first cascode unit further includes a first resistor, a second resistor, a first capacitor, a second capacitor, and a second inductor;

[0012] The first resistor is coupled between the first bias voltage and the gate of the first MOS tube; the second resistor is coupled between the power supply terminal and the gate of the second MOS tube; the first resistor and the second resistor are used to buffer the first bias voltage and the power supply voltage respectively;

[0013] The first end of the second inductor is connected to the input signal, the first capacitor is coupled between the second inductor and the gate of the first MOS tube; the second capacitor is coupled between the gate of the first MOS tube and the first end of the first MOS tube; the second inductor and the second capacitor are both used to assist the first inductor in matching the input impedance of the first cascode unit; the first capacitor is also used to block the first bias voltage from flowing to the input signal.

[0014] Optionally, the nonlinear compensation unit includes a third MOS tube and a fourth MOS tube;

[0015] The gate of the third MOS tube is coupled to the gate of the first MOS tube, the first end of the third MOS tube is coupled to the second end of the first MOS tube, and the second end of the third MOS tube is grounded through the first inductor;

[0016] The second end of the fourth MOS tube is connected to the first end of the third MOS tube, the gate of the fourth MOS tube is connected to the second bias voltage, and the first end of the fourth MOS tube is connected to the ground; wherein the second bias voltage is used to bias the fourth MOS tube.

[0017] Optionally, the first MOS tube, the second MOS tube, and the fourth MOS tube are all NMOS tubes; and the third MOS tube is a PMOS tube.

[0018] Optionally, the nonlinear compensation unit includes a third MOS tube and a fourth MOS tube;

[0019] The gate of the third MOS tube is coupled to the gate of the first MOS tube, the first end of the third MOS tube is coupled to the second end of the first MOS tube, and the second end of the third MOS tube is grounded through the first inductor;

[0020] The first end of the fourth MOS tube is connected to the first end of the third MOS tube, the gate of the fourth MOS tube is connected to the second bias voltage, and the second end of the fourth MOS tube is connected to the ground; wherein the second bias voltage is used to bias the fourth MOS tube.

[0021] Optionally, the first MOS tube and the second MOS tube are both NMOS tubes; the third MOS tube and the fourth MOS tube are both PMOS tubes.

[0022] Optionally, the buffer unit includes a fifth MOS tube and a third resistor;

[0023] The gate of the fifth MOS tube is coupled to the second end of the second MOS tube and receives a third bias voltage; wherein the third bias voltage is used to bias the fifth MOS tube, the first end of the fifth MOS tube is coupled to the power supply end, the second end of the fifth MOS tube is coupled to the first end of the third resistor and serves as the output end of the buffer unit;

[0024] A second end of the third resistor is connected to the ground.

[0025] Optionally, the buffer unit includes a fifth MOS tube and a sixth MOS tube;

[0026] The gate of the fifth MOS tube is coupled to the second end of the second MOS tube and receives a third bias voltage; wherein the third bias voltage is used to bias the fifth MOS tube, the first end of the fifth MOS tube is coupled to the power supply end, the second end of the fifth MOS tube is coupled to the second end of the sixth MOS tube and serves as the output end of the buffer unit;

[0027] The gate of the sixth MOS tube is connected to a fourth bias voltage, and the first end of the sixth MOS tube is connected to a ground end; the fourth bias voltage is used to bias the sixth MOS tube.

[0028] Optionally, the buffer unit further includes a fourth capacitor and a fourth resistor;

[0029] The fourth resistor is coupled between the fourth bias voltage and the gate of the sixth MOS tube; the fourth resistor is used to buffer the fourth bias voltage;

[0030] The fourth capacitor is coupled between the gate of the sixth MOS tube and the ground terminal; the fourth capacitor is used to filter the fourth bias voltage.

[0031] Optionally, the buffer unit further includes a fifth capacitor, a sixth capacitor, and a fifth resistor;

[0032] The fifth capacitor is coupled between the second end of the second MOS tube and the gate of the fifth MOS tube; the fifth capacitor is used to block the third bias voltage from flowing to the second MOS tube;

[0033] The sixth capacitor is coupled between the gate of the fifth MOS tube and the ground terminal; the sixth capacitor is used to filter the first power signal;

[0034] The fifth resistor is coupled between the third bias voltage and the gate of the fifth MOS tube; the fifth resistor is used for buffering the third bias voltage.

[0035] According to a second aspect of the present invention, there is provided an electronic circuit, comprising the low-noise power amplifier circuit provided by the first aspect of the present invention and the optional solution.

[0036] According to a third aspect of the present invention, there is provided an electronic device comprising the electronic circuit according to the second aspect of the present invention.

[0037] The low-noise power amplifier circuit provided by the present invention compensates the n-order nonlinear coefficient of the drain current of the first MOS tube through the nonlinear compensation unit to coordinate the linearity of the first cascode unit; and filters the first power signal through the filtering unit and adjusts and improves the output gain of the first cascode unit; and also adjusts the output impedance of the first cascode unit through the buffer unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0039] Figure 1 is a circuit module diagram of a low-noise power amplifier circuit provided by an embodiment of the present invention;

[0040] Figure 2 The circuit structure of the low noise power amplifier circuit provided by the embodiment of the present invention is Figure 1 ;

[0041] Figure 3The circuit structure of the low noise power amplifier circuit provided by the embodiment of the present invention is Figure 2 ;

[0042] Figure 4 The circuit structure of the low noise power amplifier circuit provided by the embodiment of the present invention is Figure 3 ;

[0043] Figure 5 The circuit structure of the low noise power amplifier circuit provided by the embodiment of the present invention is Figure 4 ;

[0044] Figure 6 The circuit structure of the low noise power amplifier circuit provided by the embodiment of the present invention is Figure 5 ;

[0045] Figure 7 The circuit structure of the low noise power amplifier circuit provided by the embodiment of the present invention is Figure 6 ;

[0046] Figure 8 is a waveform diagram of an initial third-order nonlinear coefficient of a first MOS tube provided by an embodiment of the present invention;

[0047] Fig. 9 is a waveform diagram of an initial third-order nonlinear coefficient of a second MOS tube provided by an embodiment of the present invention;

[0048] Fig.10 is a waveform diagram of a third-order nonlinear coefficient after the first MOS tube and the third MOS tube are connected in parallel according to an embodiment of the present invention;

[0049] Fig.11 is a waveform diagram of an initial third-order nonlinear coefficient of a fourth MOS tube provided by an embodiment of the present invention;

[0050] Fig.12 It is a waveform diagram of the third-order nonlinear coefficient after the first MOS tube, the fourth MOS tube and the third MOS tube are connected in parallel according to an embodiment of the present invention. Description of the drawings:

[0052] 10- first cascode unit;

[0053] 20- nonlinear compensation unit;

[0054] 30- filtering unit;

[0055] 40-buffer unit;

[0056] M1-first MOS tube;

[0057] M2-second MOS tube;

[0058] M3-the third MOS tube;

[0059] M4-the fourth MOS tube;

[0060] M5-fifth MOS tube;

[0061] M6-sixth MOS tube;

[0062] RFin-input signal;

[0063] R1-first resistor;

[0064] R2-second resistor;

[0065] R3-the third resistor;

[0066] R4-the fourth resistor;

[0067] R5-fifth resistor;

[0068] VDD-power supply terminal;

[0069] RFout - output signal;

[0070] VB1-first bias voltage;

[0071] VB2-second bias voltage;

[0072] VB3-third bias voltage;

[0073] VB4-fourth bias voltage;

[0074] L1-first inductor;

[0075] L2-second inductor;

[0076] L3-third inductor;

[0077] C1-first capacitor;

[0078] C2-second capacitor;

[0079] C3-third capacitor;

[0080] C4-fourth capacitor;

[0081] C5-fifth capacitor;

[0082] C6 - sixth capacitor. DETAILED DESCRIPTION

[0083] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0084] Before describing the embodiments of the present invention, the design concept of the present invention is briefly described:

[0085] The basic architecture of a low-noise power amplifier is usually composed of a cascode circuit with a source-level negative feedback inductor; the cascode circuit is usually composed of two MOS tubes in series. In actual work, the MOS tube that amplifies the signal input is usually the most affected by linearity, so the linearity of the MOS tube that amplifies the signal input needs to be optimized. The current formula flowing through the MOS tube is:

[0086] I=gm*Vgs; wherein, I is used to characterize the current flowing through the MOS tube; gm is used to characterize the transconductance of the MOS tube; and Vgs is used to characterize the gate-source voltage input to the MOS tube.

[0087] From the formula, I is a first-order equation that changes with Vgs. However, in actual circuits, I is a multi-term equation of Vgs, and each coefficient of the equation corresponds to a gm of different orders, i.e., a nonlinear coefficient. Therefore, the essence of optimizing the linearity of the MOS tube is to compensate for the nonlinear coefficient. In actual applications, the linearity of the MOS tube is mainly affected by the third-order nonlinear coefficient. Therefore, the present invention optimizes the linearity of the MOS tube by compensating for the third-order nonlinear coefficient of I.

[0088] Meanwhile, the cascode circuit also has the problem of too large output impedance, but in the radio frequency field, the input impedance and the output impedance need to be matched. Therefore, the present invention connects a buffer circuit to the output end of the cascode circuit to reduce the output impedance of the cascode circuit and match the output impedance of the cascode circuit with the input impedance.

[0089] Please refer to Figure 1 An embodiment of the present invention provides a low-noise power amplifier circuit for amplifying the power of an input signal RFin, the circuit comprising:

[0090] The first cascode unit 10 is used to power amplify the input signal RFin and output a first power signal; wherein the first cascode unit 10 includes a first MOS tube M1 and a second MOS tube M2; the gate of the first MOS tube M1 receives the input signal RFin and the first bias voltage VB1, the second end of the first MOS tube M1 is connected to the first end of the second MOS tube M2, and the first end of the first MOS tube M1 is grounded; the gate of the second MOS tube M2 is connected to the power supply terminal VDD, and the second end of the second MOS tube M2 serves as the output end of the first cascode unit 10; wherein the first bias voltage VB1 and the power supply voltage are used to bias the first MOS tube M1 and the second MOS tube M2 respectively;

[0091] The nonlinear compensation unit 20 is respectively coupled to the gate of the first MOS transistor M1 and the second end of the first MOS transistor M1; the nonlinear compensation unit 20 is used to compensate for the n-order nonlinear coefficient of the drain current of the first MOS transistor M1; wherein n is a positive integer, and n≥1;

[0092] A first inductor L1 is coupled between the first end of the first MOS tube M1 and the ground and between the nonlinear compensation unit 20 and the ground; the first inductor L1 is used to match the input impedance of the first cascode unit 10 and the nonlinear compensation unit 20;

[0093] A filter unit 30, coupled between the output terminal of the first cascode unit 10 and the power supply terminal VDD, the filter unit 30 is used to filter the first power signal;

[0094] The buffer unit 40 is coupled to the output end of the first cascode unit 10 . The buffer unit 40 is used to match the output impedance of the first cascode unit 10 . The buffer unit 40 is also used to buffer the first power signal and output an output signal RFout.

[0095] The embodiment of the present invention adopts the above technical solution to coordinate the linearity and output impedance of the first cascode unit 10 on the basis of coordinating the gain and input impedance of the first cascode unit 10. The specific principle is:

[0096] According to the input impedance formula of the first cascode unit 10:

[0097] Zin=j*w*(Lg+L1)+1 / (j*w*Cgs)+(gm*L1) / Cgs; wherein the first two terms of the formula are used to characterize the imaginary part of the input impedance, and the second term of the formula is used to characterize the real part of the input impedance; Zin is used to characterize the input impedance of the first cascode unit 10; L1 is used to characterize the first inductor L1; Lg is used to characterize the gate inductance of the first MOS tube M1; Cgs is used to characterize the gate-source capacitance of the first MOS tube M1; j is used to characterize the imaginary sign of the imaginary part of the input impedance; w is used to characterize the angular frequency; gm is used to characterize the transconductance of the first MOS tube M1.

[0098] From the above formula, it can be known that the input impedance of the first cascode unit 10 is divided into a real part and an imaginary part, and the influencing factors of the real part include the first inductor L1. Therefore, the embodiment of the present invention coordinates the input impedance of the first cascode unit 10 by adjusting the inductance value of the first inductor L1.

[0099] In the embodiment of the present invention, the filtering unit 30 filters the first power signal output by the first cascode unit 10 , and improves the output gain of the first cascode unit 10 .

[0100] In the embodiment of the present invention, the nonlinear compensation unit 20 compensates for the n-order nonlinear coefficient of the drain current of the first MOS tube M1. As can be seen from the above design ideas, the third-order nonlinear coefficient of the drain current is mainly offset to eliminate the influence of the third-order drain current of the first MOS tube M1 and improve the linearity of the first cascode unit 10. Of course, the parameters of the nonlinear compensation unit 20 can also be adjusted according to actual needs to offset the nonlinear coefficients of other orders, which is not limited here.

[0101] In the embodiment of the present invention, the buffer unit 40 reduces the output impedance of the first cascode unit 10 , so that the output impedance of the first cascode unit 10 matches the input impedance of the first cascode unit 10 .

[0102] The first cascode unit 10 in the embodiment of the present invention is described in detail below.

[0103] Please refer to Figure 2 As a specific implementation, the first cascode unit 10 further includes a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, and a second inductor L2;

[0104] The first resistor R1 is coupled between the first bias voltage VB1 and the gate of the first MOS transistor M1; the second resistor R2 is coupled between the power supply terminal VDD and the gate of the second MOS transistor M2; the first resistor R1 and the second resistor R2 are used to buffer the first bias voltage VB1 and the power supply voltage respectively;

[0105] The first end of the second inductor L2 is connected to the input signal RFin, the first capacitor C1 is coupled between the second inductor L2 and the gate of the first MOS transistor M1; the second capacitor C2 is coupled between the gate of the first MOS transistor M1 and the first end of the first MOS transistor M1; the second inductor L2 and the second capacitor C2 are both used to assist the first inductor L1 in matching the input impedance of the first cascode unit 10; the first capacitor C1 is also used to block the first bias voltage VB1 from flowing to the input signal RFin.

[0106] It can be seen from the above formula of input impedance that factors affecting the input impedance also include the second inductor L2 and the second capacitor C2, so by adjusting the inductance of the second inductor L2 and the capacitance of the second capacitor C2, the input impedance of the first cascode unit 10 is coordinated with the first inductor L1. At the same time, the first capacitor C1 blocks the first bias voltage VB1 from flowing to the input signal RFin to prevent the first bias voltage VB1 from affecting the input signal RFin.

[0107] Several implementations of the nonlinear compensation unit 20 in the embodiments of the present invention are described in detail below.

[0108] Please refer to Figure 2 As a specific implementation, the nonlinear compensation unit 20 includes a third MOS tube M3 and a fourth MOS tube M4;

[0109] The gate of the third MOS tube M3 is coupled to the gate of the first MOS tube M1, the first end of the third MOS tube M3 is coupled to the second end of the first MOS tube M1, and the second end of the third MOS tube M3 is grounded through the first inductor L1;

[0110] The second end of the fourth MOS tube M4 is connected to the first end of the third MOS tube M3, the gate of the fourth MOS tube M4 is connected to the second bias voltage VB2, and the first end of the fourth MOS tube M4 is connected to the ground; wherein the second bias voltage VB2 is used to bias the fourth MOS tube M4. The first MOS tube M1, the second MOS tube M2, and the fourth MOS tube M4 are all NMOS tubes; the third MOS tube M3 is a PMOS tube.

[0111] The embodiment of the present invention uses the above technical solution to achieve dynamic cancellation of the n-order nonlinear coefficient of the drain current of the first MOS tube M1 as the input signal RFin changes. The principle is:

[0112] The nonlinear coefficients of the PMOS tube and the NMOS tube can offset each other. For example, if the third-order nonlinear coefficient of the PMOS tube is -2 and the third-order nonlinear coefficient of the NMOS tube is 3, the PMOS tube and the NMOS tube can be connected in parallel to offset the third-order nonlinear coefficient of the NMOS tube to a certain extent. Of course, the third-order nonlinear coefficient of the PMOS tube and the third-order nonlinear coefficient of the NMOS tube are just examples. The specific values ​​are related to many factors such as production process, gate-source voltage, temperature, etc., and are not limited here. Therefore, in the embodiment of the present invention, the third MOS tube M3 is set as a PMOS tube connected in parallel with the first MOS tube M1 of the NMOS tube, so that the nonlinear coefficients of the first MOS tube M1 and the third MOS tube M3 can offset each other during the wide range change of the input signal RFin. At the same time, the embodiment of the present invention also sets the fourth MOS tube M4 to be connected in parallel with the third MOS tube M3. The second bias voltage VB2 acts on the gate of the fourth MOS tube M4, so that the fourth MOS tube M4 works in the linear region or the subthreshold region to obtain a smaller third-order nonlinear coefficient; and the third MOS tube M3 is assisted by the nonlinear coefficient to offset the third-order nonlinear coefficient of the first MOS tube M1, thereby improving the linearity of the first MOS tube M1, that is, improving the linearity of the first cascode unit 10. Taking the first MOS tube M1 and the fourth MOS tube M4 as NMOS tubes, and the third MOS tube M3 as a PMOS tube as an example, the technical effect of the third MOS tube M3 and the fourth MOS tube M4 offsetting the third-order nonlinear coefficient of the first MOS tube M1 is demonstrated; please refer to Figures 8 to 12 , Figure 8 is a waveform diagram of the initial third-order nonlinear coefficient of the first MOS tube M1, Fig. 9 is a waveform diagram of the initial third-order nonlinear coefficient of the third MOS tube M3, and the third MOS tube M3 is connected in parallel with the first MOS tube M1 to obtain Fig.10From the waveform diagram of the third-order nonlinear coefficient shown, it can be seen that after the initial third-order nonlinear coefficient of the first MOS tube M1 and the initial third-order nonlinear coefficient of the third MOS tube are superimposed, the superimposed third-order nonlinear coefficient can become relatively flat within a period of time. Fig.11 is a waveform diagram of the initial third-order nonlinear coefficient of the fourth MOS tube M4, and then the fourth MOS tube M4 and the third MOS tube M3 are connected in parallel to obtain Fig.12 From the waveform diagram of the third-order nonlinear coefficient shown, it can be seen that after the initial third-order nonlinear coefficient of the first MOS tube M1, the initial third-order nonlinear coefficient of the third MOS tube and the initial third-order nonlinear coefficient of the fourth MOS tube M4 are superimposed, the superimposed third-order nonlinear coefficient can become relatively gentle within a wide range of time. Of course, the above diagram is only experimental data, and the bias point of the fourth MOS tube M4 can be adjusted according to actual needs to change the initial third-order nonlinear coefficient of the fourth MOS tube M4 to achieve different technical effects, which is not limited here.

[0113] Please refer to Figure 3 As another specific implementation, the nonlinear compensation unit 20 includes a third MOS tube M3 and a fourth MOS tube M4;

[0114] The gate of the third MOS tube M3 is coupled to the gate of the first MOS tube M1, the first end of the third MOS tube M3 is coupled to the second end of the first MOS tube M1, and the second end of the third MOS tube M3 is grounded through the first inductor L1;

[0115] The first end of the fourth MOS tube M4 is connected to the first end of the third MOS tube M3, the gate of the fourth MOS tube M4 is connected to the second bias voltage VB2, and the second end of the fourth MOS tube M4 is connected to the ground; wherein the second bias voltage VB2 is used to bias the fourth MOS tube M4. The first MOS tube M1 and the second MOS tube M2 are both NMOS tubes; the third MOS tube M3 and the fourth MOS tube M4 are both PMOS tubes.

[0116] The structural difference between this embodiment and another embodiment of the nonlinear compensation unit 20 is that the fourth MOS tube M4 of this embodiment is replaced by a PMOS tube from an NMOS tube. The functional difference is that since the fourth MOS tube M4 is a PMOS tube, the second bias voltage VB2 is changed from a high voltage to a low voltage compared to another embodiment to reduce the circuit cost. The other contents are the same and will not be repeated here.

[0117] The filtering unit 30 in the embodiment of the present invention is described in detail below.

[0118] Please refer to Figure 3 As a specific implementation, the filtering unit 30 includes a third inductor L3 and a third capacitor C3;

[0119] The first end of the third inductor L3 is connected to the first end of the third capacitor C3 and the second end of the second MOS tube M2 respectively; the second end of the third inductor L3 is connected to the second end of the third capacitor C3 and the power supply terminal VDD respectively. The filtering unit 30 can not only filter the first power signal and improve the output gain of the first cascode unit 10, but also adjust the resonance point of the first power signal to balance the resonance point offset caused by parasitic effects.

[0120] The buffer unit 40 in the embodiment of the present invention is described in detail below.

[0121] Please refer to Figure 4 As a specific implementation, the buffer unit 40 includes: a fifth MOS tube M5 and a third resistor R3;

[0122] The gate of the fifth MOS tube M5 is coupled to the second end of the second MOS tube M2, and receives a third bias voltage VB3; wherein the third bias voltage VB3 is used to bias the fifth MOS tube M5, the first end of the fifth MOS tube M5 is coupled to the power supply terminal VDD, the second end of the fifth MOS tube M5 is coupled to the first end of the third resistor R3, and serves as the output end of the buffer unit 40;

[0123] The second end of the third resistor R3 is connected to the ground. The third resistor R3 is set as a large resistor.

[0124] The diode buffer structure formed by the fifth MOS tube M5 and the third resistor R3 makes the output impedance of the output end of the first cascode unit 10 1 / gm; wherein gm is used to characterize the transconductance of the fifth MOS tube M5. By adjusting the width-to-length ratio of the fifth MOS tube M5 so that gm is equal to 20mS, an output impedance of 50Ω is obtained; here, matching the output impedance of the first cascode unit 10 to 50Ω is an industry standard in the radio frequency field. Of course, the output impedance of the first cascode unit 10 can also be adjusted according to actual needs, which is not limited here.

[0125] Please refer to Figure 5 , but the use of a diode buffer structure composed of large resistors will increase the circuit area and increase the production cost. In order to further optimize the buffer unit 40, in another specific embodiment, the third resistor R3 is replaced by the sixth MOS tube M6 to reduce the circuit area;

[0126] The gate of the fifth MOS tube M5 is coupled to the second end of the second MOS tube M2 and receives a third bias voltage VB3; the third bias voltage VB3 is used to bias the fifth MOS tube M5, the first end of the fifth MOS tube M5 is coupled to the power supply end VDD, the second end of the fifth MOS tube M5 is coupled to the second end of the sixth MOS tube M6 and serves as the output end of the buffer unit 40;

[0127] The gate of the sixth MOS tube M6 is connected to the fourth bias voltage VB4, and the first end of the sixth MOS tube M6 is connected to the ground; the fourth bias voltage VB4 is used to bias the sixth MOS tube M6.

[0128] Please refer to Figure 6 As a specific implementation, the buffer unit 40 further includes a fourth capacitor C4 and a fourth resistor R4;

[0129] The fourth resistor R4 is coupled between the fourth bias voltage VB4 and the gate of the sixth MOS transistor M6; the fourth resistor R4 is used to buffer the fourth bias voltage VB4;

[0130] The fourth capacitor C4 is coupled between the gate of the sixth MOS transistor M6 and the ground terminal; the fourth capacitor C4 is used for filtering the fourth bias voltage VB4.

[0131] Please refer to Figure 7 As a specific implementation, the buffer unit 40 further includes a fifth capacitor C5, a sixth capacitor C6, and a fifth resistor R5;

[0132] The fifth capacitor C5 is coupled between the second end of the second MOS transistor M2 and the gate of the fifth MOS transistor M5; the fifth capacitor C5 is used to block the third bias voltage VB3 from flowing to the second MOS transistor M2, so as to reduce the high-frequency noise interference caused by the bias;

[0133] The sixth capacitor C6 is coupled between the gate of the fifth MOS transistor M5 and the ground terminal; the sixth capacitor C6 is used to filter the first power signal;

[0134] The fifth resistor R5 is coupled between the third bias voltage VB3 and the gate of the fifth MOS transistor M5 ; the fifth resistor R5 is used for buffering the third bias voltage VB3 .

[0135] As a preferred embodiment, the buffer unit 40 further includes a seventh capacitor, which is coupled to the drain of the fifth MOS tube M5 as the output end of the buffer unit 40. The seventh capacitor has the beneficial effect of improving the isolation of the low-noise power amplifier circuit together with the first capacitor C1, so that the input and output of the low-noise power amplifier circuit do not affect each other.

[0136] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-noise power amplifier circuit for amplifying the power of an input signal, characterized in that: The circuit includes: A first cascode unit is used to power amplify the input signal and output a first power signal; wherein the first cascode unit includes a first MOS tube and a second MOS tube; the gate of the first MOS tube receives the input signal and a first bias voltage, the second end of the first MOS tube is connected to the first end of the second MOS tube, and the first end of the first MOS tube is grounded; the gate of the second MOS tube is connected to the power supply end, and the second end of the second MOS tube serves as the output end of the first cascode unit; wherein the first bias voltage and the power supply voltage are used to bias the first MOS tube and the second MOS tube respectively; A nonlinear compensation unit, coupled to the gate of the first MOS tube and the second end of the first MOS tube respectively; the nonlinear compensation unit is used to compensate for the n-th order nonlinear coefficient of the drain current of the first MOS tube; wherein n is a positive integer, and n≥1; A first inductor, coupled between the first end of the first MOS tube and the ground end and coupled between the nonlinear compensation unit and the ground end; the first inductor is used to match the input impedance of the first cascode unit and the nonlinear compensation unit; a filter unit, coupled between the output end of the first cascode unit and the power end, the filter unit being used to filter the first power signal; A buffer unit is coupled to the output end of the first cascode unit; the buffer unit is used to match the output impedance of the first cascode unit; the buffer unit is also used to buffer the first power signal and output an output signal.

2. The low-noise power amplifier circuit according to claim 1, characterized in that: The first cascode unit further includes a first resistor, a second resistor, a first capacitor, a second capacitor, and a second inductor; The first resistor is coupled between the first bias voltage and the gate of the first MOS tube; the second resistor is coupled between the power supply terminal and the gate of the second MOS tube; the first resistor and the second resistor are used to buffer the first bias voltage and the power supply voltage respectively; The first end of the second inductor is connected to the input signal, the first capacitor is coupled between the second inductor and the gate of the first MOS tube; the second capacitor is coupled between the gate of the first MOS tube and the first end of the first MOS tube; the second inductor and the second capacitor are both used to assist the first inductor in matching the input impedance of the first cascode unit; the first capacitor is also used to block the first bias voltage from flowing to the input signal.

3. The low-noise power amplifier circuit according to claim 1, characterized in that: The nonlinear compensation unit includes a third MOS tube and a fourth MOS tube; The gate of the third MOS tube is coupled to the gate of the first MOS tube, the first end of the third MOS tube is coupled to the second end of the first MOS tube, and the second end of the third MOS tube is grounded through the first inductor; The second end of the fourth MOS tube is connected to the first end of the third MOS tube, the gate of the fourth MOS tube is connected to the second bias voltage, and the first end of the fourth MOS tube is connected to the ground; wherein the second bias voltage is used to bias the fourth MOS tube.

4. The low-noise power amplifier circuit according to claim 3, characterized in that: The first MOS tube, the second MOS tube, and the fourth MOS tube are all NMOS tubes; the third MOS tube is a PMOS tube.

5. The low-noise power amplifier circuit according to claim 1, characterized in that: The nonlinear compensation unit includes a third MOS tube and a fourth MOS tube; The gate of the third MOS tube is coupled to the gate of the first MOS tube, the first end of the third MOS tube is coupled to the second end of the first MOS tube, and the second end of the third MOS tube is grounded through the first inductor; The first end of the fourth MOS tube is connected to the first end of the third MOS tube, the gate of the fourth MOS tube is connected to the second bias voltage, and the second end of the fourth MOS tube is connected to the ground; wherein the second bias voltage is used to bias the fourth MOS tube.

6. The low-noise power amplifier circuit according to claim 5, characterized in that: The first MOS tube and the second MOS tube are both NMOS tubes; the third MOS tube and the fourth MOS tube are both PMOS tubes.

7. The low-noise power amplifier circuit according to claim 1, characterized in that: The filtering unit includes a third inductor and a third capacitor; The first end of the third inductor is respectively connected to the first end of the third capacitor and the second end of the second MOS tube; the second end of the third inductor is respectively connected to the second end of the third capacitor and the power supply end.

8. The low-noise power amplifier circuit according to claim 1, characterized in that: The buffer unit includes a fifth MOS tube and a third resistor; The gate of the fifth MOS tube is coupled to the second end of the second MOS tube and receives a third bias voltage; wherein the third bias voltage is used to bias the fifth MOS tube, the first end of the fifth MOS tube is coupled to the power supply end, the second end of the fifth MOS tube is coupled to the first end of the third resistor and serves as the output end of the buffer unit; A second end of the third resistor is connected to the ground.

9. The low-noise power amplifier circuit according to claim 1, characterized in that: The buffer unit includes a fifth MOS tube and a sixth MOS tube; The gate of the fifth MOS tube is coupled to the second end of the second MOS tube and receives a third bias voltage; wherein the third bias voltage is used to bias the fifth MOS tube, the first end of the fifth MOS tube is coupled to the power supply end, the second end of the fifth MOS tube is coupled to the second end of the sixth MOS tube and serves as the output end of the buffer unit; The gate of the sixth MOS tube is connected to a fourth bias voltage, and the first end of the sixth MOS tube is connected to a ground end; the fourth bias voltage is used to bias the sixth MOS tube.

10. The low-noise power amplifier circuit according to claim 9, characterized in that: The buffer unit further includes a fourth capacitor and a fourth resistor; The fourth resistor is coupled between the fourth bias voltage and the gate of the sixth MOS tube; the fourth resistor is used to buffer the fourth bias voltage; The fourth capacitor is coupled between the gate of the sixth MOS tube and the ground terminal; the fourth capacitor is used to filter the fourth bias voltage.

11. The low-noise power amplifier circuit according to claim 8 or 10, characterized in that: The buffer unit further includes a fifth capacitor, a sixth capacitor, and a fifth resistor; The fifth capacitor is coupled between the second end of the second MOS tube and the gate of the fifth MOS tube; the fifth capacitor is used to block the third bias voltage from flowing to the second MOS tube; The sixth capacitor is coupled between the gate of the fifth MOS tube and the ground terminal; the sixth capacitor is used to filter the first power signal; The fifth resistor is coupled between the third bias voltage and the gate of the fifth MOS tube; the fifth resistor is used for buffering the third bias voltage.

12. An electronic circuit, characterized in that: The electronic circuit comprises the low-noise power amplifier circuit according to any one of claims 1 to 11.

13. An electronic device, characterized in that: The electronic device comprises the electronic circuit according to claim 12.

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