Class-d power amplifier circuit and control method for realizing high voltage resistance by using low-voltage devices

Abstract

The application discloses a kind of to be realized with low-voltage device high pressure-resistant class-D power amplifier circuit and control method, the class-D power amplifier circuit includes MOS tube module, non-overlapping control module, bias voltage generation module, bias voltage buffer module, PMOS drive control module and NMOS drive control module;Non-overlapping control module outputs non-overlapping control P signal and non-overlapping control N signal;Bias voltage generation module is used to generate the bias signal of PMOS power tube output;Bias voltage buffer module is connected with the grid of second PMOS tube, bias voltage buffer module is used to convert bias signal voltage into drive voltage signal, to control the grid of second PMOS tube, and provide drive control signal for PMOS drive control module;PMOS drive control module is used to control the grid of first PMOS tube;NMOS drive control module is used to control the grid of first NMOS tube.Class-D power amplifier can be realized with low-voltage device high pressure-resistant, reduce circuit damage risk, reduce chip manufacturing cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of class D power amplifier, and particularly relates to a class D power amplifier circuit and control method for realizing high-voltage resistance by using low-voltage devices. BACKGROUND

[0002] In electronic products, a signal usually needs to be power amplified before driving the next stage circuit to work. For example, in an audio playing system, an audio signal is power amplified before being connected to a loudspeaker. The module for power amplification is usually referred to as a power amplifier module. Common power amplifier types include class A power amplifier, class B power amplifier, class AB power amplifier and class D power amplifier. The class D power amplifier has the characteristics of high efficiency and small size.

[0003] In a system on chip (SoC), a processor, a memory, peripherals, a signal processing module and a power amplifier are usually integrated into one chip to simplify the number of board-level chips and peripheral components. In CMOS integrated circuit design, the devices have a voltage resistance range. Exceeding the voltage resistance range will cause damage to the integrated circuit devices. The CMOS device voltage resistance damage is usually caused by gate-source breakdown and gate-drain breakdown. For example, the maximum operating voltage of a core device is 1.32V, and the maximum operating voltage of an IO device is 3.63V. Since the power amplifier module needs to have very high output power, it is generally powered by an external power supply, and the voltage is usually 5V. The maximum gate-source voltage and gate-drain voltage of the driver tube of the class D power amplifier circuit are the module supply voltage. When the supply voltage of the circuit is greater than 3.63V, the circuit has a risk of damage. The voltage resistance range of the integrated circuit device is strongly related to the manufacturing process. If a higher operating voltage is required, a new manufacturing process needs to be used, thereby increasing the chip manufacturing cost. SUMMARY

[0004] The present application aims to at least solve one of the technical problems in the prior art. To this end, the present application provides a class D power amplifier circuit and control method for realizing high-voltage resistance by using low-voltage devices, which can realize a class D power amplifier with low-voltage devices, reduce the risk of circuit damage and reduce chip manufacturing cost.

[0005] In one aspect, the embodiment of the present application provides a class D power amplifier circuit with low-voltage devices for high-voltage resistance, comprising a MOS tube module, a non-overlapping control module, a bias voltage generation module, a bias voltage buffer module, a PMOS drive control module and an NMOS drive control module; the MOS tube module comprises a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, the source of the first PMOS tube is connected to a VCC5 power supply, the drain of the first PMOS tube is connected to the source of the second PMOS tube, the drain of the second PMOS tube is connected to the drain of the second NMOS tube, the source of the first NMOS tube is connected to ground, and the drain of the first NMOS tube is connected to the source of the second NMOS tube; the input of the non-overlapping control module is a PA_DIN signal, the PA_DIN signal is a digital signal modulated by PWM, the non-overlapping control module performs delay processing on the PA_DIN signal and outputs a non-overlapping control P signal and a non-overlapping control N signal; the bias voltage generation module is used to generate a bias signal output by a PMOS power tube to avoid the gate-source and gate-drain voltages of the MOS tube module being greater than the rated voltage; the bias voltage buffer module is connected to the gate of the second PMOS tube, and is used to convert the bias signal voltage into a drive voltage signal to control the gate of the second PMOS tube and provide a drive control signal for the PMOS drive control module; the input of the PMOS drive control module is the non-overlapping control P signal, the PMOS drive control module is connected to the gate of the first PMOS tube, and is used to control the gate of the first PMOS tube; the input of the NMOS drive control module is the non-overlapping control N signal, the NMOS drive control module is connected to the gate of the first NMOS tube, and is used to control the gate of the first NMOS tube.

[0006] According to some embodiments of the present application, the non-overlapping control module comprises a plurality of buffers, the plurality of buffers perform delay processing on the PA_DIN signal and output a non-overlapping control P signal and a non-overlapping control N signal, the non-overlapping control P signal is output by or operation of the PA_DIN signal and a PA_DLY delay signal, the non-overlapping control N signal is output by and operation of the PA_DIN signal and the PA_DLY delay signal, and the PA_DLY delay signal is a delay signal of the PA_DIN signal.

[0007] According to some embodiments of the present application, the bias voltage generating module comprises a first bias NMOS tube, a second bias NMOS tube, a third bias NMOS tube, a first bias PMOS tube, a second bias PMOS tube and a third bias PMOS tube, the source of the first bias PMOS tube is connected to a VCC5 power supply, the gate and the drain of the first bias PMOS tube are connected to the source of the second bias PMOS tube, the gate and the drain of the second bias PMOS tube are connected to the source of the third bias PMOS tube, the gate and the drain of the third bias PMOS tube are connected to the drain of the first bias NMOS tube, the gate of the first bias NMOS tube is connected to a second resistor, the source of the first bias NMOS tube is connected to the drain of the third bias NMOS tube, the gate and the source of the second bias NMOS tube are respectively connected to the gate and the source of the third bias NMOS tube, the second bias NMOS tube and the third bias NMOS tube are connected to form a current mirror structure, when the power supply voltage VCC5 is greater than 3.3V, the voltage higher than 3.3V is borne by the first bias PMOS tube, the second bias PMOS tube and the third bias PMOS tube, the first bias NMOS tube is a protection tube, which ensures that the output of the power supply voltage VCC5-3.3 is not greater than 3.3V.

[0008] According to some embodiments of the present application, the bias voltage buffer module comprises a first buffer NMOS tube, a second buffer NMOS tube, a third buffer NMOS tube, a fourth buffer NMOS tube, a first buffer PMOS tube, a second buffer PMOS tube, a third buffer PMOS tube, and a fourth buffer PMOS tube, the source of the first buffer NMOS tube is connected to the source of the second buffer NMOS tube, the drain and gate of the second buffer NMOS tube are connected to the source of the third buffer NMOS tube, the drain and gate of the third buffer NMOS tube are connected to the gate of the fourth buffer NMOS tube, the gate of the first buffer PMOS tube is connected to a VCC5 power supply, the drain of the first buffer PMOS tube is connected to ground, the source of the first buffer PMOS tube is connected to the source of the second buffer PMOS tube, the drain and gate of the second buffer PMOS tube are connected to the source of the third buffer PMOS tube, the gate of the third buffer PMOS tube is connected to the gate of the fourth buffer PMOS tube, the source of the fourth buffer PMOS tube is connected to the source of the fourth buffer NMOS tube, a first differential amplifier is formed by the first buffer NMOS tube and the second buffer NMOS tube, the voltage generated at the VBN end of the first differential amplifier is VCC5-3.3+VGS, a second differential amplifier is formed by the first buffer PMOS tube and the second buffer PMOS tube, the voltage generated at the VBP end of the second differential amplifier is VCC5-3.3-VGS, and a source follower is formed by the fourth buffer NMOS tube and the fourth buffer PMOS tube, so that the voltage of the output protection control P signal is VCC5-3.3.

[0009] According to some embodiments of the present application, the PMOS drive control module comprises a first drive NMOS tube, a second drive NMOS tube, a third drive NMOS tube, a fourth drive NMOS tube, a fifth drive NMOS tube, a sixth drive NMOS tube, a first drive PMOS tube, a second drive PMOS tube, a third drive PMOS tube, a fourth drive PMOS tube, a fifth drive PMOS tube, and a sixth drive PMOS tube, when the non-overlapping control P signal is high, the third drive NMOS tube and the fourth drive NMOS tube pull down the protection control E signal to VCC5-3.3V, when the third drive PMOS tube is turned on, the drive control P signal is output as VCC5, and when the non-overlapping control P signal is low, the fifth drive NMOS tube and the sixth drive NMOS tube pull down the drive control P signal to VCC5-3.3V.

[0010] According to some embodiments of the present application, the NMOS drive control module comprises a plurality of inverters for amplifying the drive signal step by step.

[0011] According to some embodiments of the present application, the PMOS drive control module PA_VDRVP outputs a PMOS drive control signal, when the first PMOS tube is turned on, the output of the PMOS drive control signal is not greater than VCC5-3.3V, so as to protect the gate-source voltage of the first PMOS tube not greater than 3.3V.

[0012] According to some embodiments of the present application, the bias voltage buffer module outputs a PMOS protection control signal, when the second PMOS tube is turned on, the output of the PMOS protection control signal is VCC5-3.3V, so as to protect the gate-source voltage of the second PMOS tube not greater than 3.6V.

[0013] According to some embodiments of the present application, the second NMOS tube is connected with a first resistor, the first end of the first resistor is connected with the gate of the second NMOS tube, and the other end of the first resistor R1 is connected with a voltage power supply, so as to protect the gate-drain voltage of the first NMOS tube not greater than 3.3V.

[0014] In another aspect, the embodiments of the present application provide a D-class power amplifier control method for realizing high-voltage resistance by using low-voltage devices, which comprises:

[0015] The non-overlapping control module performs delay processing on the PA_DIN signal and outputs a non-overlapping control P signal and a non-overlapping control N signal;

[0016] The bias voltage generation module generates a bias signal output by a PMOS power tube;

[0017] The bias voltage buffer module converts the bias signal into a drive voltage signal to control the gate of the second NMOS tube and provides a drive control signal for the PMOS drive control module;

[0018] The PMOS drive control module performs gate control on the first PMOS tube;

[0019] The NMOS drive control module performs gate control on the first NMOS tube;

[0020] The gate of the first PMOS tube and the first NMOS tube is controlled, so that the gate-drain voltage is not greater than the voltage resistance range.

[0021] The embodiments of the present application have at least the following beneficial effects:

[0022] The present invention provides a Class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance, including a MOS tube module, a non-overlapping control module, a bias voltage generation module, a bias voltage buffer module, a PMOS drive control module, and an NMOS drive control module. The bias voltage generation module generates a VCC5-3.3V reference voltage, and the bias voltage buffer module enhances the signal load capacity to generate a protection control P signal for controlling a second NMOS tube. The PMOS drive control module performs gate control on the first PMOS tube, and the NMOS drive control module performs gate control on the first NMOS tube; the gate of the second NMOS tube is clamped by power supply voltage VCC3. By stacking multiple PMOS and NMOS tubes and controlling the gate of each MOS tube to ensure that the gate-source voltage and gate-drain voltage are no greater than their voltage resistance range, a Class D power amplifier that can withstand high voltage can be achieved using low-voltage devices, reducing the risk of circuit damage and lowering chip manufacturing costs.

[0023] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0025] Figure 1 Schematic diagram of the circuit structure of a Class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance according to an embodiment of the present invention;

[0026] Figure 2 for Figure 1 The working timing diagram of the class D power amplifier circuit is shown;

[0027] Figure 3 for Figure 1 A schematic diagram of the circuit structure of a non-overlapping control module of a Class D power amplifier circuit is shown;

[0028] Figure 4 for Figure 1 A schematic diagram of the circuit structure of the bias voltage generating module of the class D power amplifier circuit is shown;

[0029] Figure 5 for Figure 1 A schematic diagram of the circuit structure of the bias voltage buffer module of the class D power amplifier circuit is shown;

[0030] Figure 6 for Figure 1 The circuit structure diagram of the PMOS drive control module of the class D power amplifier circuit is shown;

[0031] Figure 7 forFigure 1 The circuit structure schematic diagram of the NMOS drive control module of the D class power amplifier circuit is shown.

[0032] Figure 8 The flow chart of the D class power amplifier control method of the embodiment of the present application using low voltage devices to realize high voltage resistance is shown. DETAILED DESCRIPTION

[0033] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application, and cannot be understood as a limitation of the present application.

[0034] In the description of the present application, it should be understood that the orientation description, such as the orientation or position relationship indicated by up, down, front, back, left, right, etc. is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and cannot be understood as a limitation of the present application, which indicates or implies that the device or element indicated must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application.

[0035] In the description of the present application, the meaning of “several” is one or more, the meaning of “multiple” is two or more, greater than, less than, more than, etc. are understood as not including the number, “above”, “below”, “within”, etc. are understood as including the number. If it is described as “first”, “second”, etc., it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the sequence of indicated technical features.

[0036] In the description of the present application, unless otherwise explicitly limited, the words “set”, “install”, “connect” and “connected” should be understood in a broad sense, and the person skilled in the art can reasonably determine the specific meaning of the above words in the present application in combination with the specific content of the technical solution.

[0037] The technical solutions of the present application are described in detail below by referring to the drawings and specific embodiments.

[0038] Please refer to Figure 1 and Figure 2The embodiment discloses a kind of to realize high pressure-resistant class D power amplifier circuit with low-voltage device, including MOS tube module, non-overlapping control module PA_NONLAP, bias voltage generation module PA_VBGEN, bias voltage buffer module PA_VBBUF, PMOS drive control module PA_VDRVP and NMOS drive control module PA_VDRVN.MOS tube module includes first PMOS tube PM0, second PMOS tube PM1, first NMOS tube NM0 and second NMOS tube NM1, the source of first PMOS tube PM0 is connected VCC5 power supply, the drain of first PMOS tube is connected the source of second PMOS tube, the drain of second PMOS tube PM1 is connected the drain of second NMOS tube NM1, the source of first NMOS tube NM0 is connected to ground, the drain of first NMOS tube NM0 is connected the source of second NMOS tube NM1;Non-overlapping control module PA_NONLAP input is PA_DIN signal, PA_DIN signal is the digital signal that is well modulated by PWM, and non-overlapping control module PA_NONLAP carries out delay processing to PA_DIN signal and outputs non-overlapping control P signal NONLAPP and non-overlapping control N signal NONLAPN;Bias voltage generation module PA_VBGEN is used to generate the bias signal VCC5-3.3 of PMOS power tube output, to avoid the case that the gate source and gate drain of MOS tube module are greater than rated voltage;Bias voltage buffer module PA_VBBUF is connected the gate of second PMOS tube PM1, bias voltage buffer module PA_VBBUF is used to convert bias signal VCC5-3.3 voltage into voltage signal with driving ability, to control the gate of second PMOS tube PM1, and provide driving ability control signal for PMOS drive control module;The input of PMOS drive control module PA_VDRVP is non-overlapping control P signal NONLAPP, and PMOS drive control module PA_VDRVP is connected the gate of first PMOS tube PM0, and PMOS drive control module PA_VDRVP is used to carry out gate control to first PMOS tube PM0;The input of NMOS drive control module PA_VDRVN is non-overlapping control N signal NONLAPN, and NMOS drive control module PA_VDRVN is connected the gate of first NMOS tube NM0, and NMOS drive control module PA_VDRVN is used to carry out gate control to first NMOS tube NM0.

[0039] Please refer to Figure 3The non-overlapping control module PA_NONLAP includes a plurality of buffers, which delay process the PA_DIN signal and output a non-overlapping control P signal NONLAPP and a non-overlapping control N signal NONLAPN. The non-overlapping control P signal NONLAPP is output by the OR operation of the PA_DIN signal and a PA_DLY delay signal. The non-overlapping control N signal NONLAPN is output by the AND operation of the PA_DIN signal and the PA_DLY delay signal. The PA_DLY delay signal is a delay signal of the PA_DIN signal. The non-overlapping control module PA_NONLAP generates two non-overlapping signals, which can avoid the simultaneous opening of the PMOS power tube and the NMOS power tube.

[0040] Please refer to Figure 4 The bias voltage generation module PA_VBGEN includes a first bias NMOS tube NM10, a second bias NMOS tube NM11, a third bias NMOS tube NM12, a first bias PMOS tube PM10, a second bias PMOS tube PM11, a third bias PMOS tube PM12, and a second resistor R11. The source of the first bias PMOS tube PM10 is connected to the VCC5 power supply. The gate and the drain of the first bias PMOS tube PM10 are connected to the source of the second bias PMOS tube PM11. The gate and the drain of the second bias PMOS tube PM11 are connected to the source of the third bias PMOS tube PM12. The gate and the drain of the third bias PMOS tube PM12 are connected to the drain of the first bias NMOS tube PM10. The gate of the first bias NMOS tube PM10 is connected to the second resistor R11. The source of the first bias NMOS tube NM10 is connected to the drain of the third bias NMOS tube NM12. The gate and the source of the second bias NMOS tube NM11 are respectively connected to the gate and the source of the third bias NMOS tube NM12. The second bias NMOS tube NM11 and the third bias NMOS tube NM12 are connected to form a current mirror structure. When the power supply voltage VCC5 is greater than 3.3V, the voltage higher than 3.3V is borne by the first bias PMOS tube PM0, the second bias PMOS tube PM1, and the third bias PMOS tube PM2. The first bias NMOS tube NM0 is a protection tube, which ensures that the output of VCC5-3.3 is not greater than 3.3V.

[0041] Please refer to Figure 5The bias voltage buffer module PA_VBBUF includes a first buffer NMOS tube NM20, a second buffer NMOS tube NM21, a third buffer NMOS tube NM22, a fourth buffer NMOS tube NM23, a first buffer PMOS tube PM20, a second buffer PMOS tube PM21, a third buffer PMOS tube PM22, and a fourth buffer PMOS tube PM23. The source of the first buffer NMOS tube NM20 is connected to the source of the second buffer NMOS tube NM21. The source and the gate of the second buffer NMOS tube NM21 are connected to the source of the third buffer NMOS tube NM22. The drain and the gate of the third buffer NMOS tube NM22 are connected to the gate of the fourth buffer NMOS tube NM23. The gate of the first buffer PMOS tube PM20 is connected to the VCC5 power supply. The drain of the first buffer PMOS tube PM20 is connected to the ground. The source of the first buffer PMOS tube PM20 is connected to the source of the second buffer PMOS tube PM21. The drain and the gate of the second buffer PMOS tube PM21 are connected to the source of the third buffer PMOS tube PM22. The gate of the third buffer PMOS tube PM22 is connected to the gate of the fourth buffer PMOS tube PM23. The source of the fourth buffer PMOS tube PM23 is connected to the source of the fourth buffer NMOS tube NM23. The first differential amplifier is composed of the first buffer NMOS tube NM20 and the second buffer NMOS tube NM21. The voltage generated at the VBN end of the first differential amplifier is VCC5-3.3+VGS. The second differential amplifier is composed of the first buffer PMOS tube PM20 and the second buffer PMOS tube PM21. The voltage generated at the VBP end of the second differential amplifier is VCC5-3.3-VGS. The source follower is composed of the fourth buffer NMOS tube NM23 and the fourth buffer PMOS tube PM23. The output voltage of the PMOS protection control signal VPRCP is VCC5-3.3 due to the source follower.

[0042] Please refer to Figure 6, the PMOS drive control module PA_VDRVP includes a first drive NMOS tube NM30, a second drive NMOS tube NM31, a third drive NMOS tube NM32, a fourth drive NMOS tube NM33, a fifth drive NMOS tube NM34, a sixth drive NMOS tube NM35, a first drive PMOS tube PM30, a second drive PMOS tube PM31, a third drive PMOS tube PM32, a fourth drive PMOS tube PM33, a fifth drive PMOS tube PM34 and a sixth drive PMOS tube PM35, wherein the non-overlapping control PB signal NONLAPP_B corresponds to the non-overlapping control P signal NONLAPP; when the non-overlapping control P signal NONLAPP is high, the third drive NMOS tube NM32 and the fourth drive NMOS tube NM33 will pull down the protection control E signal VPRE to VCC5-3.3V, turn on the fifth drive PMOS tube PM34, and the drive control signal VDRVP output VCC5; when the non-overlapping control P signal NONLAPP is low, the non-overlapping control PB signal NONLAPP_B is high, the fifth drive NMOS tube NM34 and the sixth drive NMOS tube NM35 will pull down the drive control signal VDRVP to VCC5-3.3V.

[0043] Please refer to Figure 7 , the NMOS drive control module PA_VDRVN includes a plurality of inverters for amplifying the drive signal step by step.

[0044] Please refer to Figure 1 and Figure 2 , the PMOS drive control module PA_VDRVP outputs the PMOS drive control signal VDRVP, and when the first PMOS tube PM0 is turned on, the output of the PMOS drive control signal VDRVP is not greater than VCC5-3.3V, so as to protect the gate-source voltage of the first PMOS tube PM0 not greater than 3.3V.

[0045] Please refer to Figure 1 and Figure 2 , the bias voltage buffer module PA_VBBUF outputs the PMOS protection control signal VPRCP, and when the second PMOS tube PM1 is turned on, the output of the PMOS protection control signal VPRCP is VCC5-3.3V, so as to protect the gate-source voltage of the second PMOS tube PM1 not greater than 3.6V.

[0046] Please refer to Figure 1 and Figure 2 , the second NMOS tube NM1 is connected with the first resistor R1, the first end of the first resistor R1 is connected with the gate of the second NMOS tube NM1, and the other end of the first resistor R1 is connected with the voltage power supply VCC3, so as to protect the gate-drain voltage of the first NMOS tube NM0 not greater than 3.3V.

[0047] Please refer to Figure 8 The embodiment also provides a D-class power amplifier control method for realizing a high-voltage-resistant D-class power amplifier circuit by using low-voltage devices, mainly comprising steps S101-S106.

[0048] S101, the non-overlapping control module PA_NONLAP performs delay processing on the PA_DIN signal and outputs a non-overlapping control P signal NONLAPP and a non-overlapping control N signal NONLAPN.

[0049] S102, the bias voltage generation module PA_VBGEN generates a bias signal VCC5-3.3 output by the PMOS power tube.

[0050] S103, the bias voltage buffer module converts the bias signal VCC5-3.3 voltage into a drive voltage signal to control the gate of the second PMOS tube PM1 and provide a drive control signal for the PMOS drive control module.

[0051] S104, the PMOS drive control module performs gate control on the first PMOS tube PM0.

[0052] S105, the NMOS drive control module PA_VDRVN performs gate control on the first NMOS tube NM0.

[0053] S106, by controlling the gates of the first PMOS tube PM0 and the first NMOS tube NM0, the gate-drain voltage is not greater than the voltage resistance range.

[0054] Please refer to Figure 1, a VCC5-3.3V reference voltage is generated by the bias voltage generation module PA_VBGEN, and the signal load capacity is strengthened by the bias voltage buffer module PA_VBBUF to generate the PMOS protection control signal VPRCP for controlling the second NMOS tube PM1. The control signal of the first PMOS tube PM0 is generated by the PMOS drive control module PA_VDRVP. The gate of the second NMOS tube NM1 is clamped by the power supply voltage VCC3. To protect the gate-source voltage of the first PMOS tube PM0 not greater than 3.3V, the drive control P signal VDRVP outputs the minimum VCC5-3.3V when the first PMOS tube PM0 is turned on. To protect the gate-source voltage of the second PMOS tube PM1 not greater than 3.6V, the PMOS protection control signal VPRCP outputs a fixed VCC5-3.3V. To protect the gate-drain voltage of the first NMOS tube NM0 not greater than 3.3V, the NMOS protection control signal VPRCN outputs a fixed 3.3V. The NMOS drive control module PA_VDRVN drives the first NMOS tube NM0, and when the output signal PA_OUT needs to output a low level, the NMOS drive control module PA_VDRVN module drives VDRVN to high, at this time the first NMOS tube NM0 is opened, and the second NMOS tube NM1 is always open, so the output signal PA_OUT is driven to low level. Conversely, when the output signal PA_OUT needs to output a high level, the NMOS drive control module PA_VDRVN module drives the drive control N signal VDRVN to low, at this time the first NMOS tube NM0 is closed, and the second NMOS tube NM1 is always open, so the output signal PA_OUT is controlled by the first PMOS tube PM0 and the second PMOS tube PM1 to output a high level. By stacking multiple PMOS tubes and NMOS tubes and controlling the gate of each MOS tube, the gate-source voltage and the gate-drain voltage are ensured not to be greater than the voltage withstand range; the low-voltage device can be used to realize the high-voltage D-class power amplifier, reduce the risk of circuit damage, and reduce the chip manufacturing cost.

[0055] The embodiments of the application are described in detail above with reference to the drawings, but the application is not limited to the above-described embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the purpose of the application.

Claims

1. A class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance, characterized in that: include: A MOS transistor module, the MOS transistor module including a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, wherein the source of the first PMOS transistor is connected to the VCC5 power supply, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the source of the first NMOS transistor is connected to ground, and the drain of the first NMOS transistor is connected to the source of the second NMOS transistor; a non-overlapping control module, wherein the input of the non-overlapping control module is a PA_DIN signal, which is a digital signal modulated by PWM. The non-overlapping control module performs delay processing on the PA_DIN signal and outputs a non-overlapping control P signal and a non-overlapping control N signal; A bias voltage generating module, which is used to generate a bias signal to prevent the gate-source and gate-drain voltages of the MOS tube module from exceeding the rated voltage. A PMOS drive control module, wherein the input of the PMOS drive control module is a non-overlapping control P signal, the PMOS drive control module is connected to the gate of the first PMOS transistor, and the PMOS drive control module is used to control the gate of the first PMOS transistor; a bias voltage buffer module, the bias voltage buffer module being connected to the gate of the second PMOS transistor, the bias voltage buffer module being configured to convert the bias signal into a drive voltage signal to control the gate of the second PMOS transistor, and provide a drive control signal to the PMOS drive control module; An NMOS drive control module, the input of which is a non-overlapping control N signal, the NMOS drive control module is connected to the gate of the first NMOS tube, and the NMOS drive control module is used to control the gate of the first NMOS tube.

2. The class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance according to claim 1, characterized in that: The non-overlapping control module includes multiple buffers, which delay the PA_DIN signal and output non-overlapping control P signal and non-overlapping control N signal. The non-overlapping control P signal is output by performing an OR operation on the PA_DIN signal and the PA_DLY delay signal. The non-overlapping control N signal is output by performing an AND operation on the PA_DIN signal and the PA_DLY delay signal. The PA_DLY delay signal is a delayed signal of the PA_DIN signal.

3. The class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance according to claim 1, characterized in that: The bias voltage generating module includes a first bias NMOS transistor, a second bias NMOS transistor, a third bias NMOS transistor, a first bias PMOS transistor, a second bias PMOS transistor, a third bias PMOS transistor and a second resistor. The source of the first bias PMOS transistor is connected to the VCC5 power supply, the gate and drain of the first bias PMOS transistor are connected to the source of the second bias PMOS transistor, the gate and drain of the second bias PMOS transistor are connected to the source of the third bias PMOS transistor, the gate and drain of the third bias PMOS transistor are connected to the drain of the first bias NMOS transistor, and the gate of the first bias NMOS transistor is connected to the drain of the third bias PMOS transistor. A second resistor is connected, the source of the first bias NMOS transistor is connected to the drain of the third bias NMOS transistor, the gate and source of the second bias NMOS transistor are respectively connected to the gate and source of the third bias NMOS transistor, and the second bias NMOS transistor and the third bias NMOS transistor are connected to form a current mirror structure. When the power supply voltage VCC5 is greater than 3.3V, the voltage exceeding 3.3V is borne by the first bias PMOS transistor, the second bias PMOS transistor, and the third bias PMOS transistor. The first bias NMOS transistor serves as a protection transistor to ensure that the output of the power supply voltage VCC5-3.3 is not greater than 3.3V.

4. The class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance according to claim 1, characterized in that: The bias voltage buffer module includes a first buffer NMOS transistor, a second buffer NMOS transistor, a third buffer NMOS transistor, a fourth buffer NMOS transistor, a first buffer PMOS transistor, a second buffer PMOS transistor, a third buffer PMOS transistor and a fourth buffer PMOS transistor. The source of the first buffer NMOS transistor is connected to the source of the second buffer NMOS transistor, the drain and gate of the second buffer NMOS transistor are connected to the source of the third buffer NMOS transistor, the drain and gate of the third buffer NMOS transistor are connected to the gate of the fourth buffer NMOS transistor, the gate of the first buffer PMOS transistor is connected to the VCC5 power supply, the drain of the first buffer PMOS transistor is connected to the ground, the source of the first buffer PMOS transistor is connected to the source of the second buffer PMOS transistor, and the drain of the second buffer PMOS transistor is connected to the gate of the fourth buffer NMOS transistor. The electrode and gate of the third buffer PMOS transistor are connected to the source of the third buffer PMOS transistor, the gate of the third buffer PMOS transistor is connected to the gate of the fourth buffer PMOS transistor, and the source of the fourth buffer PMOS transistor is connected to the source of the fourth buffer NMOS transistor. The first buffer NMOS transistor and the second buffer NMOS transistor form a first differential amplifier, and the voltage generated at the VBN terminal by the first differential amplifier is VCC5-3.3+VGS. The first buffer PMOS transistor and the second buffer PMOS transistor form a second differential amplifier, and the voltage generated at the VBP terminal by the second differential amplifier is VCC5-3.3-VGS. The fourth buffer NMOS transistor and the fourth buffer PMOS transistor form a source follower, and the source follower makes the output voltage VPRCP be VCC5-3.

3.

5. The class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance according to claim 1, characterized in that: The PMOS drive control module includes a first drive NMOS transistor, a second drive NMOS transistor, a third drive NMOS transistor, a fourth drive NMOS transistor, a fifth drive NMOS transistor, a sixth drive NMOS transistor, a first drive PMOS transistor, a second drive PMOS transistor, a third drive PMOS transistor, a fourth drive PMOS transistor, a fifth drive PMOS transistor and a sixth drive PMOS transistor. When the non-overlapping control P signal is high, the third drive NMOS transistor and the fourth drive NMOS transistor will pull down the protection control E signal to VCC5-3.3V. When the fifth drive PMOS transistor is turned on, the drive control signal outputs VCC5. When the non-overlapping control P signal is low, the fifth drive NMOS transistor and the sixth drive NMOS transistor will pull down the drive control signal to VCC5-3.3V.

6. The class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance according to claim 1, characterized in that: The NMOS drive control module includes a plurality of inverters, and the plurality of inverters are used to amplify the drive signal step by step.

7. The class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance according to claim 1, characterized in that: The PMOS drive control module PA_VDRVP outputs a PMOS drive control signal. When the first PMOS tube is turned on, the output of the PMOS drive control signal is no greater than VCC5-3.3V to protect the gate-source voltage of the first PMOS tube from being greater than 3.3V.

8. The class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance according to claim 7, characterized in that: The bias voltage buffer module outputs a PMOS protection control signal. When the second PMOS transistor is turned on, the output of the PMOS protection control signal is VCC5-3.3V to protect the gate-source voltage of the second PMOS transistor PM1 from being greater than 3.6V.

9. The class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance according to claim 8, characterized in that: The second NMOS transistor is connected to a first resistor, a first end of the first resistor is connected to the gate of the second NMOS transistor, and the other end of the first resistor is connected to the voltage power supply VCC3 to protect the gate-drain voltage of the first NMOS transistor from being greater than 3.3V.

10. A method for controlling a Class D power amplifier with high voltage resistance using low voltage devices, characterized in that: A Class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance according to any one of claims 1 to 9, comprising: The non-overlap control module delays the PA_DIN signal and outputs a non-overlap control P signal and a non-overlap control N signal; The bias voltage generating module generates a bias signal; The bias voltage buffer module converts the bias signal into a driving voltage signal to control the gate of the second PMOS transistor and provides a driving control signal to the PMOS driving control module; The PMOS drive control module controls the gate of the first PMOS tube; The NMOS drive control module PA_VDRVN controls the gate of the first NMOS transistor; The gates of the first PMOS transistor and the first NMOS transistor are controlled so that the gate-to-drain voltage is not greater than a withstand voltage range.

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