Circuit device and circuit device setting method

Abstract

The invention provides a circuit device and a method for setting the circuit device, which solve the problem that the filter characteristic expected by a user cannot be set according to the use of the user in the prior art. The circuit device is provided with: an A / D conversion circuit that performs A / D conversion on a signal output from a sensor element; an interface circuit that receives filter setting data that determines the characteristics of each of the plurality of digital filtering processes; a storage circuit that stores the filter setting data; and a signal processing circuit that sequentially performs, on the digital signal output from the A / D conversion circuit, each of the plurality of digital filtering processes having characteristics determined by the filter setting data.

Description

Technical Field

[0001] The invention relates to a circuit device and a setting method of the circuit device. Background Art

[0002] Conventionally, there is known a technique for converting an analog signal output from a sensor element into a digital signal and performing digital filtering processing. For example, Patent Document 1 discloses a structure in which a component of a detuning frequency Δf corresponding to the difference between a driving-side resonant frequency fd and a detecting-side resonant frequency fs of a vibrator is attenuated by a band-stop filter.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2015-108566

[0004] Conventionally, it has been impossible to set filter characteristics to the user's desired characteristics in accordance with the user's application. Summary of the invention

[0005] The circuit device comprises: an A / D conversion circuit that performs A / D conversion on a signal output from a sensor element; an interface circuit that receives filter setting data that determines the characteristics of each of a plurality of digital filter processes; a storage circuit that stores the filter setting data; and a signal processing circuit that sequentially performs each of the plurality of digital filter processes having the characteristics determined by the filter setting data on a digital signal output from the A / D conversion circuit.

[0006] A setting method for a circuit device is a setting method for a circuit device comprising: an A / D conversion circuit that performs A / D conversion on a signal output from a sensor element; an interface circuit; a storage circuit; and a signal processing circuit that performs digital filtering on a digital signal output from the A / D conversion circuit. In the setting method for the circuit device, filter setting data that determines the characteristics of each of a plurality of digital filtering processes is input into the interface circuit and stored in the storage circuit, so that the signal processing circuit sequentially performs each of the plurality of digital filtering processes having the characteristics determined by the filter setting data on the digital signal output from the A / D conversion circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a functional block diagram of the physical quantity sensor according to the first embodiment.

[0008] Figure 2 It is a diagram showing an example of filter characteristics.

[0009] Figure 3 is a block diagram showing the structure of a DSP.

[0010] Figure 4 It is a diagram showing a configuration example of a programmable filter.

[0011] Figure 5 It is a diagram showing a configuration example of a second-order IIR filter.

[0012] Figure 6 This is a flowchart of the setting process.

[0013] Description of symbols

[0014] 1: physical quantity sensor; 2: sensor element; 3: circuit device; 10: reference voltage circuit; 20: drive circuit; 30: detection circuit; 40: digital processing unit; 42: A / D conversion circuit; 44a: temperature correction unit; 44b: programmable filter; 44b1~44b4: second-order IIR filter; 44b11~44b14: addition unit; 44b17~44b111: multiplication unit; 44b15, 44b16: delay unit; 44c: selectable filter; 44d: notch filter; 44e: selector; 44f: selector; 50: oscillation circuit; 60: storage unit; 61: register; 62: non-volatile memory; 70: interface circuit; 80: temperature sensor; 82: A / D conversion circuit; 84: temperature correction value calculation unit. DETAILED DESCRIPTION

[0015] Hereinafter, preferred embodiments of the present invention will be described in detail using the accompanying drawings. In addition, the embodiments described below do not unduly limit the contents of the present invention as described in the claims. In addition, not all structures described below are necessarily essential components of the present invention. Hereinafter, a physical quantity sensor (angular velocity sensor) that detects angular velocity as a physical quantity will be described as an example.

[0016] 1. First Implementation Method

[0017] Figure 1 This is a functional block diagram of a physical quantity sensor of the first embodiment. The physical quantity sensor 1 of the first embodiment includes a sensor element 2 and a circuit device 3. In this embodiment, the sensor element 2 is an angular velocity sensor. The angular velocity sensor can be implemented by various well-known structures. For example, the sensor element 2 can be composed of an element that outputs a signal representing a vibration based on the Coriolis force acting on the vibration arm. Of course, the shape of the sensor is not limited, and sensors of various shapes such as double T-type, tuning fork type, H-type, etc. can be used.

[0018] The sensor element 2 includes an input terminal for inputting a drive signal DRV from the drive circuit 20 and an output terminal for outputting a feedback signal DI to the drive circuit 20. In the present embodiment, the input terminal is electrically connected to the connection pad DS. In addition, the output terminal is electrically connected to the connection pad DG. The sensor element 2 includes two detection signal output terminals for outputting detection signals, and each detection signal output terminal is electrically connected to the connection pads S1 and S2.

[0019] The circuit device 3 in this embodiment is configured to include a reference voltage circuit 10, a drive circuit 20, a detection circuit 30, a digital processing unit 40, an oscillation circuit 50, a storage unit 60, an interface circuit 70, a temperature sensor 80, an A / D conversion circuit 82, and a temperature correction value calculation unit 84. The circuit device 3 may be, for example, a single-chip integrated circuit (IC). In addition, the circuit device 3 may be configured to omit or change some of these elements, or to add other elements.

[0020] The reference voltage circuit 10 generates a constant voltage and a constant current such as reference voltages VR1 and VR2 based on a power supply voltage supplied from a VDD terminal of the circuit device 3 , and supplies the constant voltage and the constant current to the drive circuit 20 and the detection circuit 30 .

[0021] The drive circuit 20 drives the sensor element 2. The drive circuit 20 is electrically connected to the sensor element 2 via the connection pads DS and DG. The drive circuit 20 receives the feedback signal DI from the sensor element 2 via the connection pad DG, and outputs the drive signal DRV corresponding to the feedback signal DI via the connection pad DS, thereby driving the sensor element 2. In addition, the drive circuit 20 generates a detection signal SDET having the same phase as the drive signal DRV, and outputs it to the detection circuit 30.

[0022] The drive circuit 20 can be implemented by various well-known circuits. For example, the drive circuit 20 can be implemented by a structure including a current-voltage converter (I / V converter), a gain control circuit, and two comparators. That is, the AC voltage signal output from the current-voltage converter is converted by each comparator to become a drive signal DRV and a detection signal SDET. The gain control circuit controls the reference voltage of the comparator so that the amplitude of the AC voltage signal input to the comparator generating the drive signal DRV is maintained at a fixed value. In addition, here, the frequency of the drive signal DRV is referred to as the drive frequency fd.

[0023] The detection circuit 30 detects the angular velocity component contained in the AC charge input from the sensor element 2 via the S1 and S2 terminals, and outputs a detection signal Sr as an analog signal of a voltage level corresponding to the magnitude of the angular velocity. In addition, in the present embodiment, the frequency of the AC charge input from the sensor element 2 via the S1 and S2 terminals is referred to as the detection frequency fr. The detection circuit 30 can be implemented by various well-known circuits. For example, the detection circuit 30 can be implemented by a structure including a QV amplifier, a differential amplifier, a variable gain amplifier (PGA: Programmable Gain Amplifier), a synchronous detection circuit, and a low-pass filter. The synchronous detection circuit uses the detection signal SDET to synchronously detect the angular velocity component contained in the signal output from the variable gain amplifier.

[0024] The storage unit 60 has a register 61 and a nonvolatile memory 62. The register 61 stores addresses and various data used in communication with an external device via the interface circuit 70. In the present embodiment, the various data include filter setting data. That is, the interface circuit 70 receives filter setting data that determines the characteristics of each of a plurality of digital filter processes (secondary IIR (Infinite impulse response) filters described later). The received filter setting data is stored in the register 61. In addition, the register 61 stores angular velocity data and angle data output from the DSP 44 described later.

[0025] The nonvolatile memory 62 stores various adjustment data and correction data for the drive circuit 20 and the detection circuit 30, and various information for establishing communication with the outside via the interface circuit 70. The nonvolatile memory 62 can be configured as a MONOS (Metal Oxide Nitride Oxide Silicon) type memory or an EEPROM (Electrically Erasable Programmable Read-Only Memory), for example.

[0026] The interface circuit 70 is electrically connected to the XCS terminal, the SCLK terminal, the SDI terminal, and the SDO terminal, and is a circuit for communicating with an external device via these terminals. In the communication via the interface circuit 70, the external device functions as a master device, and the physical quantity sensor 1 (circuit device 3) functions as a slave device. Furthermore, the external device can write data to a specified address of the register 61, read data from a specified address of the register 61, and send various commands to control the operation of the circuit device 3 via the interface circuit 70.

[0027] The interface circuit 70 may also function as either an SPI (Serial Peripheral Interface) interface circuit or an I2C (Inter-Integrated Circuit) interface circuit. For example, when the XCS terminal is at a low level, the interface circuit 70 functions as an SPI interface circuit, inputs a clock signal via the SCLK terminal, inputs a data signal via the SDI terminal, and outputs a data signal via the SDO terminal. In addition, when the XCS terminal is at a high level, the interface circuit 70 functions as an I2C interface circuit, inputs a clock signal via the SCLK terminal, and inputs and outputs a data signal via the SDI terminal.

[0028] Communication with an external device via the interface circuit 70 is performed based on various information stored in the register 61. Furthermore, the external device can read angular velocity data from a predetermined address of the register 61 via the interface circuit 70. In this way, the physical quantity sensor 1 (circuit device 3) is configured to be able to output angular velocity data in response to a request from an external device.

[0029] In the present embodiment, when manufacturing the physical quantity sensor 1, the frequency of the clock signal CLK is determined according to the natural frequency of the sensor element 2, and the sampling frequency fs in the A / D conversion described later is determined according to the frequency of the clock signal CLK. Specifically, at the time of shipment, as in the above-mentioned prior art, when the driving frequency of the driving signal used when driving the sensor element 2 is fd as described above and the frequency of the clock signal CLK is fck, it is assumed that j×fd≠fck / i (i, j are integers greater than 1). When the frequency fck of the clock signal is determined, the frequency that is the same as the frequency fck of the clock signal or is a frequency obtained by multiplying the frequency of the clock signal CLK is set as the sampling frequency fs. The frequency of the clock signal CLK and the sampling frequency fs are stored in the nonvolatile memory 62, and the sampling frequency fs is stored in a predetermined address of the register 61. The user can read the sampling frequency fs stored at the address using an external device. Here, the storage area in the register 61 storing the sampling frequency fs is referred to as the first area.

[0030] In addition, in the present embodiment, digital filtering is performed by the DSP 44 described later. In the present embodiment, the digital filtering includes a programmable filter 44b, a selectable filter 44c, and a notch filter 44d described later. The programmable filter 44b is a filter that can be set to a filter of arbitrary characteristics by setting a filter coefficient through filter setting data by the user, and the details will be described later.

[0031] The selectable filter 44c is a filter that allows the user to select a desired characteristic from a plurality of predetermined characteristics. The filter coefficients corresponding to each setting are stored in the nonvolatile memory 62. The filter characteristics and the number of selectable characteristics are arbitrary, and an example in which the characteristics of the low-pass filter processing can be selected from 24 characteristics is assumed here.

[0032] Specifically, the selectable filter 44c is composed of IIR filters of multiple orders, etc., and filter coefficients corresponding to each combination of the order n and the cutoff frequency fc (each combination of 24 combinations) are predetermined and stored in the nonvolatile memory 62. The filter coefficient is a value for setting the low-pass filter processing to the order n and the cutoff frequency fc corresponding to the filter coefficient.

[0033] In this embodiment, the characteristics of the low-pass filter processing realized by the combination of the order n and the cutoff frequency fc are shown to the user in advance through a manual, etc. Therefore, the user can understand the characteristics of the selectable low-pass filter processing by referring to the manual, etc.

[0034] Figure 2 : is a diagram showing an example of filter characteristics. In this embodiment, 3 orders (2nd to 4th order) and 8 cutoff frequencies fc can be selected, and a total of 24 characteristics can be selected. Figure 2 , an example of matching the phase delay characteristics when the input signal is 10 Hz with the group delay characteristics when the input signal is a DC signal for each combination is shown. For example, the phase delay characteristics of the low-pass filter processing with a degree of 2 and a cutoff frequency fc of 1 Hz are PD12 (deg) and the group delay characteristics are GD12 (ms).

[0035] The user selects a desired characteristic from the characteristics of these low-pass filter processes and operates an external device to specify the order n and the cutoff frequency fc. In the nonvolatile memory 62, the filter coefficient corresponds to the order n and the cutoff frequency fc. Therefore, by using the filter coefficient to operate the selectable filter 44c, the characteristics in the selectable filter 44c can be selected so that the low-pass filter process of the characteristics specified by the user is performed. In addition, the detailed processing in the selectable filter 44c will be described later.

[0036] The notch filter 44d is a band-stop filter for attenuating a signal of a specific frequency. In the present embodiment, the notch filter 44d is a filter that attenuates the component of the detuned frequency, which is the difference between the drive frequency fd and the detection frequency fr. The notch filter 44d can be implemented, for example, by an IIR filter or the like. In the nonvolatile memory 62, information indicating a filter coefficient to be applied to the notch filter 44d in order to attenuate the component of the detuned frequency is stored. When the physical quantity sensor 1 is activated, the information indicating the filter coefficient is transmitted to the register 61 and is referenced by the DSP 44 described later.

[0037] The oscillation circuit 50 generates a clock signal CLK and outputs the clock signal CLK to the digital processing unit 40. The oscillation circuit 50 includes a PLL (Phase Locked Loop) circuit and a DLL (Digital Locked Loop) circuit, and outputs a clock signal CLK having a frequency stored in a storage unit 60. That is, the frequency of the clock signal CLK is stored in the nonvolatile memory 62, and when the physical quantity sensor 1 is activated, the frequency is transferred to the register 61. The oscillation circuit 50 obtains the frequency stored in the register 61, and generates an oscillation signal as the clock signal CLK according to the frequency.

[0038] The digital processing unit 40 is configured to include an A / D (Analog to Digital) conversion circuit 42 and a DSP (Digital Signal Processor) 44 as a signal processing circuit. The A / D conversion circuit 42 operates at a sampling frequency fs synchronized with the clock signal CLK output by the oscillation circuit 50, converts the output signal of the detection circuit 30 into a digital signal (angular velocity data) Da and outputs it. The sampling frequency fs, which is the period at which the A / D conversion circuit 42 converts the analog signal into a digital signal, may be the same as the frequency of the clock signal CLK, or may be a frequency obtained by multiplying the frequency of the clock signal CLK. The A / D conversion circuit 42 can be implemented by various well-known circuits, such as a Δ-Σ type or a successive approximation type A / D conversion circuit.

[0039] The DSP 44 operates synchronously with the clock signal CLK output by the oscillation circuit 50, and performs digital processing including digital filtering processing on the digital signal (angular velocity data) Da output from the A / D conversion circuit 42. The structure of the DSP 44 will be described later, but in the digital processing, in addition to the digital filtering processing, it also includes digital processing for correcting the changes in the angular velocity data caused by temperature. The value of the angular velocity data after these digital processing represents the angular velocity detected by the sensor element 2, and is updated sequentially at a specified rate. In addition, the DSP 44 can also perform digital processing for correcting the offset of the zero point of the angular velocity data, and digital processing for calculating the angle data by time integration (addition) of the angular velocity data updated sequentially. The angular velocity data output from the DSP 44 is stored in the register 61, and is transmitted to an external device, etc., for example, via the interface circuit 70.

[0040] The temperature sensor 80 is a sensor that outputs a signal (temperature signal) of a voltage level corresponding to the temperature of its surroundings. It can be a positive polarity sensor whose output voltage increases as the temperature increases, or a negative polarity sensor whose output voltage decreases as the temperature increases. The temperature sensor 80 can also be a circuit that outputs a voltage proportional to the absolute temperature (PTAT (Proportional To Absolute Temperature) voltage). The temperature signal output from the temperature sensor 80 is input to the A / D conversion circuit 82.

[0041] The A / D conversion circuit 82 operates synchronously with the clock signal CLK output by the oscillation circuit 50, converts the signal output by the temperature sensor 80 into a digital signal (temperature data) and outputs it. The period at which the A / D conversion circuit 82 converts the analog signal into a digital signal, i.e., the sampling frequency fs, can be the same as the frequency of the clock signal CLK, or can be the frequency after multiplying the clock signal CLK. The A / D conversion circuit 82 can be implemented by various well-known circuits, for example, it can be a Δ-Σ type or a successive approximation type A / D conversion circuit. The signal output from the A / D conversion circuit 82 is input to the temperature correction value calculation unit 84.

[0042] The temperature correction value calculation unit 84 calculates and outputs the temperature correction value Ta based on the signal output by the A / D conversion circuit 82. The temperature correction value Ta can be calculated by various methods, for example, a method of calculating the temperature correction value Ta by a function with temperature as a variable, a method of obtaining the temperature correction value Ta corresponding to the temperature based on the information stored in the storage unit 60, etc. The temperature correction value Ta output from the temperature correction value calculation unit 84 is input to the DSP 44. The temperature correction value calculation unit 84 can be any circuit that performs digital processing, for example, it can be implemented by various integrated circuits such as a CPU, and can also be implemented by an FPGA (Field Programmable Gate Array) or the like.

[0043] 1.1 DSP Structure

[0044] Next, the structure of the DSP 44 will be described in detail. Figure 3 4 is a block diagram showing the structure of the DSP 44. The DSP 44 includes a temperature correction unit 44a, a programmable filter 44b, a selectable filter 44c, a notch filter 44d, and selectors 44e and 44f. The temperature correction unit 44a corrects the digital signal Da based on the temperature correction value Ta output by the temperature correction value calculation unit 84. The temperature correction value Ta is a value for canceling the temperature-induced variation of the output of the sensor element 2. In the present embodiment, the temperature correction unit 44a corrects the digital signal Da by performing a predetermined operation based on the temperature correction value Ta, such as Da+Ta, on the digital signal Da.

[0045] The programmable filter 44b is a filter that can be set to a filter of arbitrary characteristics by setting filter coefficients using filter setting data. The programmable filter 44b can be implemented by various structures, and in this embodiment, it is implemented by connecting four second-order IIR filters in series.

[0046] Figure 4 4 is a diagram for explaining the structure of the programmable filter 44b. The programmable filter 44b is a structure in which second-order IIR filters 44b1, 44b2, 44b3, and 44b4 are connected in series in this order. The second-order IIR filters 44b1, 44b2, 44b3, and 44b4 have the same structure. Figure 5 The structure of the second-order IIR filter 44b1 is shown in FIG.

[0047] The second-order IIR filter 44b1 has adders 44b11 to 44b14, delayers 44b15 and 44b16, and multipliers 44b17 to 44b111. The delayers 44b15 and 44b16 give unit delays to input signals and output them. The multipliers 44b17 to 44b111 multiply the input signals by coefficients and output them. The coefficients of the multipliers 44b17 to 44b111 are Figure 5 The multiplication units 44b17 to 44b111 respectively indicate a11, a21, b01, b11, and b21. The addition units 44b11 to 44b14 respectively indicate Figure 5 The input signals shown are given the signs shown in the figure, added and output.

[0048] Therefore, in Figure 5 In the example shown, the adding unit 44b11 adds the input signal and the signal obtained by making the feedback signal negative and outputs the added signal. The signal output from the adding unit 44b11 is delayed by the delay units 44b15 and 44b16. The signal delayed by the delay unit 44b15 is input to the multiplication units 44b17 and 44b110 and the delay unit 44b16. The signal delayed by the delay unit 44b16 is input to the multiplication units 44b18 and 44b111.

[0049] The signals input to the multiplication units 44b17 and 44b18 are multiplied by the coefficients a11 and a21 and added by the addition unit 44b12, and then input to the addition unit 44b11. The signals input to the multiplication units 44b110 and 44b111 are multiplied by the filter coefficients b11 and b21 and added by the addition unit 44b14, and then input to the addition unit 44b13. The addition unit 44b13 receives the signal obtained by multiplying the output of the addition unit 44b11 by the filter coefficient b01 by the multiplication unit 44b19. The addition unit 44b13 outputs the sum of the two input signals.

[0050] The above-mentioned secondary IIR filter 44b1 becomes a filter with various characteristics by adjusting the filter coefficients b01, b11, b21, a11, and a21. In the present embodiment, the user can specify these filter coefficients. That is, the user operates an external device to send filter setting data representing the filter coefficients to the physical quantity sensor 1. When the interface circuit 70 receives the filter setting data, the filter setting data is stored in the register 61. The secondary IIR filter 44b1 refers to the register 61 to determine the filter coefficients b01, b11, b21, a11, and a21 so that they become the values ​​shown in the obtained filter setting data.

[0051] The second order IIR filter 44b1 can be set to perform various digital filtering processes, for example, the filter setting data is defined as any of band pass filtering, notch filtering, low pass filtering, and high pass filtering. In addition, the filter setting data can also be defined in a manner that the phase delay and group delay are within the desired range.

[0052] The user can use various methods to determine the filter coefficient, but in this embodiment, a simulator is used. Specifically, the simulator is executed in an external device. In this case, the user operates the external device to temporarily determine the value of the filter coefficient, simulates the characteristics of the digital filter processing based on the temporarily determined filter coefficient, and displays it on the display unit, etc. If the displayed result is the desired result, the user uses the temporarily determined filter coefficient. If it is not the desired result, the user changes the filter coefficient to repeat the simulation.

[0053] The simulation can be performed by various methods, for example, the transfer function of the second-order IIR filter 44b1 can be used to simulate the gain characteristic, the phase delay characteristic, and the group delay characteristic. The transfer function of the second-order IIR filter 44b1 can be expressed by the following equation (1).

[0054]

[0055] Here, 1 / z is a transfer function of a time delay element (for example, delay unit 44b15). As shown in equation (1), the transfer function is a function of filter coefficients b01, b11, b21, a11, and a21.

[0056] Therefore, when the user changes the filter coefficients b01, b11, b21, a11, and a21, the characteristics of the digital filter processing represented by the transfer function change, and the characteristics can be visualized by using a simulator. As described above, by adjusting the filter coefficients, the characteristics of the secondary IIR filter 44b1 can be specified.

[0057] However, in this embodiment, by considering the sampling frequency fs, it is configured to accurately adjust to the characteristics desired by the user. Specifically, the filter characteristics are determined by the transfer function shown in the above formula (1), and 1 / z included in the transfer function depends on the sampling frequency fs. That is, even if the filter coefficients are the same, if the sampling frequency fs is different, the characteristics of the digital filter processing represented by the transfer function, such as the gain characteristic, the phase delay characteristic, and the group delay characteristic may also change.

[0058] In particular, in the present embodiment, the sampling frequency fs is a value determined by the frequency fck of the clock signal, which is determined by the drive frequency fd of the drive signal of the sensor element 2. Therefore, the sampling frequency fs is individual data that is different for each individual sensor element 2, and if the individual physical quantity sensor 1 is different, it may operate at a different sampling frequency fs. Therefore, the sampling frequency fs is a value that cannot be determined by the user.

[0059] In this way, the sampling frequency fs may be different for each individual, so in this embodiment, in the initial state after the physical quantity sensor 1 is started, the sampling frequency fs is stored in the first area of ​​the register 61. Therefore, before starting the simulation of the filter coefficient, the user operates the external device to read the sampling frequency fs through the interface circuit 70. And when performing the above-mentioned simulation, the obtained sampling frequency fs is used to determine the characteristics of the 1 / z part in the formula (1). Therefore, according to this embodiment, the filter coefficient for realizing the characteristics desired by the user can be determined according to the sampling frequency fs that is different for each individual. Therefore, the filter coefficient for realizing the characteristics desired by the user can be accurately determined.

[0060] In addition, in the present embodiment, the sampling frequency fs is stored in the first area of ​​the register 61. Moreover, when the sampling frequency fs is read out, the filter coefficient is determined and sent as the filter setting data, the filter setting data is stored in the first area of ​​the register 61. That is, the sampling frequency fs originally stored in the register 61 is overwritten by the filter setting data. In addition, the amount of information of the sampling frequency fs may be consistent with or different from the amount of information of the filter setting data. In either case, by writing the filter setting data in the first area where the sampling frequency fs is stored, the storage area of ​​the register 61 can be used efficiently.

[0061] The structure of the second-order IIR filter 44b2 to 44b4 is the same as that of the second-order IIR filter 44b1. That is, the user uses an external device to determine the filter coefficient for the characteristics shown by the analog transfer function of each of the second-order IIR filters 44b2 to 44b4. Figure 4 , the filter coefficients of the second-order IIR filter 44b2 are represented as b02, b12, b22, a12, and a22, and the filter coefficients of the second-order IIR filter 44b3 are represented as b03, b13, b23, a13, and a23. The filter coefficients of the second-order IIR filter 44b4 are represented as b04, b14, b24, a14, and a24.

[0062] The transfer functions of these second-order IIR filters 44b2 to 44b4 are respectively expressed as equations (2) to (4).

[0063]

[0064]

[0065]

[0066] The simulation may be performed for each of the second-order IIR filters 44b1 to 44b4, or the characteristics obtained by combining the second-order IIR filters 44b1 to 44b4 may be simulated. Figure 4 As shown, the programmable filter 44b composed of a plurality of second-order IIR filters 44b1 to 44b4 connected in series functions in a manner of sequentially performing each digital filtering process. Moreover, the characteristics of the programmable filter 44b can be described by a transfer function obtained by multiplying the transfer function of each filter. Therefore, it is possible to simulate each transfer function, or to simulate the characteristics of the combination of each filter based on the product of the transfer function. In addition, the characteristics obtained by connecting the filters in series can be described by the product of the transfer function, so the processing order of the second-order IIR filters 44b1 to 44b4 is arbitrary.

[0067] When the filter coefficient is determined by simulation, the user operates the external device to send the filter setting data indicating the determined filter coefficient to the physical quantity sensor 1. When the filter setting data is sent, the interface circuit 70 obtains the filter setting data and stores it in the first area of ​​the register 61. When the filter setting data is stored in the register 61, the programmable filter 44b applies each filter coefficient to the secondary IIR filters 44b1 to 44b4. As a result, the programmable filter 44b functions as a filter having characteristics desired by the user.

[0068] For example, the programmable filter 44b is set to perform any one of bandpass filtering, notch filtering, low-pass filtering, and high-pass filtering, or a combination thereof. In addition, if a21 and b21 in the filter coefficients of the second-order IIR filter 44b1 are set to 0, the second-order IIR filter 44b1 functions as a first-order filter. Therefore, the user can adjust the filter coefficients of the second-order IIR filters 44b1 to 44b4 to make the programmable filter 44b function as a filter of any order from 1st to 8th order.

[0069] The selectable filter 44c is a filter for digital filtering processing with predetermined characteristics that can be selected by the user. The user can refer to the manual, etc., and select the filter from the following table: Figure 2The desired characteristic is selected from the predetermined characteristics shown. That is, the desired order n and cutoff frequency fc are determined based on the phase delay characteristic, the group delay characteristic, etc. When the order n and the cutoff frequency fc are determined, the user operates the external device to send the order n and the cutoff frequency fc to the physical quantity sensor 1.

[0070] When the number n and the cutoff frequency fc are transmitted, the interface circuit 70 obtains these number n and the cutoff frequency fc and stores them in a predetermined area of ​​the register 61. When the number n and the cutoff frequency fc are stored in the register 61, the selectable filter 44c refers to the nonvolatile memory 62 and transmits the filter coefficient corresponding to the number n and the cutoff frequency fc to the register 61. Then, the selectable filter 44c applies the filter coefficient to the selectable filter 44c. As a result, the selectable filter 44c functions as a filter having the characteristics selected by the user.

[0071] The output signals of the programmable filter 44b and the selectable filter 44c are input to the selector 44e. The selector 44e selects and outputs any one of the two input signals according to the selection setting value sel1. The selection setting value sel1 is a value determined according to a mode set when the physical quantity sensor 1 is started, etc. In the present embodiment, when the selection setting value sel1 is turned on (on), the output of the programmable filter 44b is output from the selector 44e. When the selection setting value sel1 is turned off (off), the output of the selectable filter 44c is output from the selector 44e. Therefore, in the present embodiment, the digital filtering process of either the programmable filter 44b or the selectable filter 44c is applied to the signal output from the sensor element 2. According to the above structure, it is possible to select a variety of filters corresponding to the needs of the user. That is, if it is a predetermined characteristic prepared as the selectable filter 44c, it is possible to simply select a filter with a predetermined characteristic by specifying the order n and the cut-off frequency fc. If the desired characteristics are not present in the selectable filter 44c, a filter having characteristics desired by the user can be used by specifying filter coefficients in the programmable filter 44b.

[0072] The output signal of the selector 44e is input to the selector 44f and the notch filter 44d. The notch filter 44d is a band-stop filter for attenuating a signal of a specific frequency. The filter coefficient to be applied to the notch filter 44d is predetermined and stored in the nonvolatile memory 62, and is transferred to the register 61 when the physical quantity sensor 1 is activated. The notch filter 44d applies the filter coefficient to the notch filter 44d. As a result, the notch filter 44d functions as a filter that attenuates the component of the detuned frequency, which is the difference between the driving frequency fd and the detection frequency fr.

[0073] The selector 44f selects and outputs any one of the two input signals according to the selection setting value sel2. The selection setting value sel2 is a value determined according to a mode set when the physical quantity sensor 1 is started. In the present embodiment, when the selection setting value sel2 is turned on, the output of the selector 44e is output from the selector 44f. When the selection setting value sel2 is turned off, the output of the notch filter 44d is output from the selector 44f. Therefore, in the present embodiment, the selector 44f selects whether to apply the notch filter 44d to the signal output from the selector 44e. When focusing on the case where the output of the selector 44e is the output of the programmable filter 44b, the output from the selector 44f becomes either the output of the programmable filter 44b or the output when the notch filter 44d is applied to the programmable filter 44b. In addition, in the programmable filter 44b, it is also possible to select a setting in which the programmable filter 44b does not substantially function by means of a filter coefficient. Therefore, when the output of the selector 44e is the output of the programmable filter 44b, the output from the selector 44f becomes a signal Da' obtained by applying at least one of the programmable filter 44b and the notch filter 44d to the signal output from the sensor element 2. According to the above structure, a variety of filters can be selected according to the needs of the user.

[0074] The digital signal after the digital filtering process by the DSP 44 is output from the DSP 44 as a digital signal Da' after the digital signal (angular velocity data) indicating the detection result detected by the sensor element 2 is corrected. The output method is not limited, and the DSP 44 may output the generated digital signal Da' to an external device using the interface circuit 70, or may store it in the storage unit 60. In this case, the digital signal Da' is output to the external device via the interface circuit 70 in accordance with a request from the external device at an arbitrary timing.

[0075] 2. Setting process

[0076] Next, a description will be given of a setting process for causing a desired filter to function in the DSP 44 of the physical quantity sensor 1 . Figure 61 is a flowchart of a process performed after power is supplied to the physical quantity sensor 1 from the VDD terminal. When power is supplied to the physical quantity sensor 1, the DSP 44 executes a predetermined start sequence (step S100). The start sequence may include various processes. In the present embodiment, the start sequence includes information transfer from the nonvolatile memory 62 to the register 61. That is, the DSP 44 reads the sampling frequency fs used in the physical quantity sensor 1 from the nonvolatile memory 62 and stores it in the first area. In addition, the DSP 44 reads the filter coefficient of the notch filter 44d from the nonvolatile memory 62 and stores it in the register 61.

[0077] After the power supply starts, a predetermined period becomes a mode setting acceptance period. During this acceptance period, the user operates the external device to set information indicating the desired mode. The external device sends the information indicating the mode to the physical quantity sensor 1. The interface circuit 70 obtains the information indicating the mode and stores it in a predetermined area of ​​the register 61. When the information indicating the mode is stored in the predetermined area of ​​the register 61, the DSP 44 accepts the mode setting based on the information (step S105).

[0078] The information indicating the mode may be defined in any manner, and in this embodiment, includes information specifying which of the programmable filter 44b and the selectable filter 44c is to be used. In addition, in this embodiment, the information indicating the mode includes information specifying whether to use the notch filter 44d.

[0079] The DSP 44 determines the mode set by the user based on the information indicating the mode (step S110). In step S110, if it is determined that the mode set by the user is a mode using the programmable filter 44b, the DSP 44 performs the processing of steps S115 to S125. On the other hand, in step S110, if it is determined that the mode set by the user is a mode using the selectable filter 44c, the DSP 44 performs the processing of steps S130 to S140.

[0080] When the mode set by the user is the mode using the programmable filter 44 b , the DSP 44 outputs the sampling frequency to the external device in step S115 . That is, the user operates the external device to read the sampling frequency fs stored in the first area of ​​the register 61 .

[0081] Next, the DSP 44 writes the filter coefficient to the register 61 (step S120). That is, the user operates the external device to simulate the characteristics of the programmable filter 44b using the sampling frequency fs, and determines the filter coefficients of the secondary IIR filters 44b1 to 44b4. Then, the user operates the external device to send the filter setting data indicating the filter coefficient to the physical quantity sensor 1. In the physical quantity sensor 1, the interface circuit 70 receives the filter setting data and stores it in the first area of ​​the register 61. That is, the sampling frequency fs is overwritten with the filter setting data.

[0082] Next, the DSP 44 performs filter initialization (step S125). The filter initialization of step S125 is a process for applying the filter coefficients stored in the first area to the programmable filter 44b. In this filter initialization, the filter coefficients obtained in step S120 are applied to the second-order IIR filters 44b1~44b4. The setting process and the process of setting the selection setting value sel1 to on are included. In addition, when the setting of using the notch filter 44d is made in the information representing the mode, the process of turning off the selection setting value sel2 is included. When the setting of using the notch filter 44d is not made, the process of setting the selection setting value sel2 to on is included. If the filter initialization is performed, the DSP 44 sleeps for a specified period. After the specified period, the programmable filter 44b becomes a state of performing digital filtering processing by the filter coefficients determined by the user.

[0083] When the mode set by the user is a mode using the selectable filter 44c, in step S130, the DSP 44 receives the order n and the cutoff frequency fc of the selectable filter 44c. That is, the user determines the order n and the cutoff frequency fc for setting the filter having the desired characteristics based on the manual or the like. Then, the user operates the external device to send the order n and the cutoff frequency fc to the physical quantity sensor 1. In the physical quantity sensor 1, the interface circuit 70 receives the order n and the cutoff frequency fc and stores them in a predetermined area of ​​the register 61.

[0084] Next, the DSP 44 writes the filter coefficient to the register 61 (step S135 ). That is, the DSP 44 refers to a predetermined area of ​​the nonvolatile memory 62 and transfers the filter coefficient corresponding to the order n and the cutoff frequency fc to the register 61 .

[0085] Next, the DSP 44 performs filter initialization (step S140). The filter initialization of step S140 is a process for applying the filter coefficient stored in the register 61 in step S135 to the selectable filter 44c. The filter initialization includes a setting process for applying the filter coefficient obtained in step S135 to the selectable filter 44c and a process for turning off the selection setting value sel1. In addition, when the setting of using the notch filter 44d is performed in the information representing the mode, the process of turning off the selection setting value sel2 is included. When the setting of using the notch filter 44d is not performed, the process of setting the selection setting value sel2 to on is included. If the filter initialization is performed, the DSP 44 sleeps for a specified period. After the specified period, the selectable filter 44c becomes a state of performing digital filtering processing according to the filter coefficient determined by the user.

[0086] 3. Other implementation methods, etc.

[0087] The above-mentioned embodiments are examples for implementing the present invention, and various other embodiments can be adopted. For example, the processing order of DSP 44 is not limited to the processing order in the above-mentioned embodiments, and the processing order can be arbitrarily changed like the processing order of notch filter 44d and programmable filter 44b. In addition, the selectable filter 44c and notch filter 44d can be omitted as needed. Of course, other digital filtering processes can also be added. In addition, the filter coefficient of notch filter 44d can also be selected by the user.

[0088] The A / D conversion circuit only needs to be able to perform A / D conversion on the signal output from the sensor element. That is, since the sensor element outputs an analog signal, the A / D conversion circuit only needs to be able to convert the detection value of the physical quantity indicated by the analog signal into a digital signal. In addition, the signal input to the A / D conversion circuit may be the signal output from the sensor element itself, or may be a signal after various processing has been performed on the signal output from the sensor element.

[0089] The interface circuit only needs to be able to receive filter setting data that determines the characteristics of each of the multiple digital filter processes. That is, the characteristics of each of the multiple digital filter processes can be set by the filter setting data sent from the external device. The filter setting data can be set for all of the multiple digital filters or for a part of them. In the latter case, the digital filter that is not set, for example, applies the default filter setting data.

[0090] The filter setting data can be any data that specifies the characteristics of the digital filter processing. Therefore, regarding the above-mentioned second-order IIR filter, a structure that adjusts the characteristics by using 5 filter coefficients as filter setting data is an example. For example, IIR filters of any order can be connected in series, and the characteristics are specified by the filter setting data corresponding to the mode of the filter. In addition, the mode of the filter is not limited, and it can be an IIR filter of a mode different from the above example, or other filters such as FIR filters can be used.

[0091] Furthermore, in the representation of multiple digital filter processing, when counting the digital filter processing, any processing unit can be counted as 1. In the above-mentioned embodiment, the second-order IIR filter is counted as 1 digital filter processing, but it is not limited to this structure. For example, the amount of 1 digital filter processing of n times can also be counted as 1 digital filter processing.

[0092] The storage circuit only needs to be able to store filter setting data. That is, it only needs to be able to store filter setting data sent from an external device and maintain the filter setting data in a manner that can be referenced in the signal processing circuit. Of course, other data can also be stored in the storage circuit.

[0093] The signal processing circuit can sequentially perform each of a plurality of digital filtering processes of characteristics determined by the filter setting data on the digital signal output from the A / D conversion circuit. That is, a plurality of digital filtering processes are connected in series, and each digital filtering process is sequentially performed. Such a structure is equivalent to a digital filtering process of a transfer function obtained by multiplying the transfer functions of each of the plurality of digital filtering processes. Of course, the execution order of each digital filtering process is arbitrary. In addition, in the case of a digital filtering process that is invalidated according to the filter setting data, the digital filtering process may not be substantially performed.

[0094] The above-mentioned embodiment is an example and is not limited thereto. The present invention includes a structure substantially the same as the structure described in the embodiment (for example, a structure with the same function, method and result, or a structure with the same purpose and effect). In addition, the present invention includes a structure that replaces a non-essential part of the structure described in the embodiment. In addition, the present invention includes a structure that has the same effect as the structure described in the embodiment or a structure that can achieve the same purpose. In addition, the present invention includes a structure to which a known technology is added to the structure described in the embodiment.

Claims

1. A circuit device comprising: An A / D conversion circuit that performs A / D conversion on a signal output from the sensor element; an interface circuit that receives filter setting data that determines characteristics of each of a plurality of digital filter processes; a storage circuit storing the filter setting data; and A signal processing circuit sequentially performs each of the plurality of digital filter processes having characteristics determined by the filter setting data on the digital signal output from the A / D conversion circuit.

2. The circuit arrangement according to claim 1, wherein: The signal processing circuit performs bandpass filtering as the digital filtering.

3. The circuit arrangement according to claim 1, wherein: The signal processing circuit performs notch filter processing as the digital filter processing.

4. The circuit arrangement according to claim 1, wherein: The signal processing circuit performs low-pass filtering as the digital filtering.

5. The circuit arrangement according to claim 1, wherein: The signal processing circuit performs high-pass filtering as the digital filtering.

6. The circuit arrangement according to claim 1, wherein: The circuit device comprises: a driving circuit that causes the sensor element to vibrate at a driving frequency by a driving signal; and a detection circuit that obtains a signal of a detection frequency from the sensor element, The signal processing circuit performs at least one of the plurality of digital filter processes and a notch filter process that attenuates a component of a detuned frequency that is a difference between the drive frequency and the detection frequency.

7. The circuit arrangement according to claim 1, wherein: The storage circuit also stores information for setting the low-pass filter process to the number of times and cut-off frequency specified by the user. The signal processing circuit performs one of the plurality of digital filter processes and the low-pass filter process of the order and the cutoff frequency corresponding to the information.

8. The circuit arrangement according to claim 1, wherein: The storage circuit stores individual data corresponding to the sampling frequency of the A / D conversion circuit in a first area in an initial state, and the first area is overwritten by the filter setting data input from the interface circuit.

9. A method for setting a circuit device, the circuit device comprising: an A / D conversion circuit that performs A / D conversion on a signal output from a sensor element; an interface circuit; a storage circuit; and a signal processing circuit that performs digital filtering on a digital signal output from the A / D conversion circuit, wherein: inputting filter setting data for determining the characteristics of each of a plurality of digital filter processes into the interface circuit and storing the data in the storage circuit, The signal processing circuit is caused to sequentially perform each of the plurality of digital filter processes having characteristics determined by the filter setting data on the digital signal output from the A / D conversion circuit.

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