Delay circuit

Abstract

The invention discloses a delay circuit comprising a first bias unit used for generating a first bias current; the second bias unit is used for generating bias voltage; the current mirror image unit is connected between the first bias unit and the second bias unit and is used for generating an output voltage based on the first bias current and the bias voltage; and the delay unit comprises a plurality of cascaded inverters and is used for delaying the input clock signal based on the output voltage to generate a delayed clock signal. The first bias unit and the second bias unit are arranged to provide the output voltage for the delay unit, and the influence of the current mirror image unit on the output voltage is counteracted with the change of the process corner and the environment temperature, so that the output voltage can be changed with the change of the process corner and the environment temperature of the delay circuit; the delay clock signal is prevented from changing along with the process corner and the temperature, and meanwhile, the delay clock signal is prevented from changing along with the power supply voltage, so that the delay change of the delay circuit is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a delay circuit. Background Art

[0002] The SYSREF clock is generally provided by a Jitter Cleaner chip, so the SYSREF clock will change with the process corner (Corner) of chip manufacturing and the temperature.

[0003] In order to cope with the influence of process corners and temperature, the adjustable accuracy of SYSREF delay is usually required to be small enough (for example, less than 10ps), and the adjustable delay range is required to be large enough (for example, 0 to 500ps). There should also be no glitch during adjustment, and the impact of ambient temperature changes after an adjustment is completed should be considered.

[0004] Ginseng Figure 1 The figure shows an analog delay adjustment circuit in the prior art: SYSREF_in' and SYSREF_out' respectively represent the signals before and after SYSREF delay. An 8-bit capacitor array is set between inverters inv1' and inv2' to control the delay. Capacitors C0' to C7' are respectively connected to transistors M0' to M7', and the gates of M0' to M7' are controlled by signals S0 to S7. When S0 to S7 are all 1, the delay is maximum; when S0 to S7 are all 0, the delay is minimum.

[0005] The shortcomings of the prior art are: the physical parameters of the inverter itself (such as electron mobility, etc.) change with temperature, which will cause the delay to change with temperature; both inverters inv1' and inv2' require power supply voltage to work, and the delay changes when the power supply voltage changes, and the power supply voltage rejection ratio is very poor; when the load capacitance is different, the rising edge slope of the inverter inv1' varies greatly, and the linearity of the delay is not good, that is, the delay corresponding to different capacitive loads is not linearly proportional.

[0006] Therefore, in view of the above technical problems, it is necessary to provide a delay circuit. Summary of the invention

[0007] The object of the present invention is to provide a delay circuit which can solve the problem that the delayed clock signal follows the process angle of the inverter and the changes of the ambient temperature.

[0008] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0009] A delay circuit comprising:

[0010] A first bias unit, connected to a power supply voltage, and configured to generate a first bias current;

[0011] A second bias unit, connected to the reference potential, for generating a bias voltage;

[0012] A current mirror unit, connected between the first bias unit and the second bias unit and connected to a power supply voltage, for generating an output voltage based on a first bias current and a bias voltage;

[0013] The delay unit includes a plurality of cascaded inverters connected between an output voltage and a reference potential, and is used for delaying an input clock signal based on the output voltage to generate a delayed clock signal.

[0014] In one or more embodiments of the present invention, the first bias unit includes a fixed current source and a variable current source, wherein the fixed current source is used to generate a fixed current, and the variable current source is used to generate a variable current based on a control word.

[0015] In one or more embodiments of the present invention, the variable current source includes a first branch and a plurality of second branches; wherein,

[0016] The first branch is connected between the power supply voltage and the reference potential, and includes a first bias resistor, a plurality of first current mirror tubes and a reference current source, and the first branch is used to generate a reference current;

[0017] The second branch includes a plurality of second current mirror tubes and a switch tube. The second current mirror tube and the first current mirror tube form a current mirror to copy a reference current. The control end of the switch tube receives a control word, and the first end is connected to the second current mirror tube. The second ends of the plurality of switch tubes are connected to form a variable current output end. The switch tube is used to control its own on or off based on the control word to adjust the variable current.

[0018] In one or more embodiments of the present invention, the reference current source includes a first sub-current source and a second sub-current source; wherein,

[0019] The first sub-current source is used to generate a positive temperature coefficient current, the second sub-current source is used to generate a zero temperature coefficient current, and the reference current includes a positive temperature coefficient current and a zero temperature coefficient current.

[0020] In one or more embodiments of the present invention, the second bias unit includes a first MOS transistor and a second MOS transistor; wherein,

[0021] The first end of the first MOS tube is connected to the reference potential, and the second end is short-circuited with the control end;

[0022] The first end of the second MOS tube is directly or indirectly connected to the current mirror unit, the second end is short-circuited with the control end, and the second end is connected to the control end of the first MOS tube.

[0023] In one or more embodiments of the present invention, the second bias unit further includes a second bias resistor, a first end of the second bias resistor is connected to the current mirror unit, and a second end of the second bias resistor is connected to the first end of the second MOS tube.

[0024] In one or more embodiments of the present invention, the current mirror unit includes a third MOS tube and a fourth MOS tube; wherein,

[0025] The second end of the third MOS tube is short-circuited with the control end, the second end is connected to the first bias unit, the first end is connected to the second bias unit, and the control end is directly or indirectly connected to the control end of the fourth MOS tube;

[0026] The first end of the fourth MOS tube is connected to the delay unit and generates an output voltage, and the second end is connected to the power supply voltage.

[0027] In one or more embodiments of the present invention, the body end of the third MOS tube is connected to the first end, and the body end of the fourth MOS tube is connected to the first end; and / or,

[0028] The gate length of the third MOS tube is equal to the gate length of the fourth MOS tube.

[0029] In one or more embodiments of the present invention, the current mirror unit further includes a filtering unit for filtering out low-frequency noise; wherein,

[0030] The filtering unit includes a first resistor and a first capacitor, wherein a first end of the first resistor is connected to a control end of a third MOS tube, and a second end is connected to a control end of a fourth MOS tube, a first end of the first capacitor is connected to a control end of the fourth MOS tube, and a second end is connected to a reference potential.

[0031] In one or more embodiments of the present invention, the inverter includes a first PMOS tube and a first NMOS tube, wherein the first end of the first PMOS tube is connected to the output voltage, the second end is connected to the second end of the first NMOS tube, the control end is connected to the control end of the first NMOS tube, and the first end of the first NMOS tube is connected to the reference potential;

[0032] The gate length of the first MOS transistor is equal to the gate length of the first NMOS transistor; and / or,

[0033] The gate length of the second MOS tube is equal to the gate length of the first PMOS tube.

[0034] Compared with the prior art, the delay circuit of the present invention provides an output voltage for the delay unit by setting a first bias unit and a second bias unit, and the influence of the current mirror unit on the output voltage offsets each other due to following the changes of the process angle and the ambient temperature, so that the output voltage can follow the process angle and the ambient temperature changes of the delay unit, avoiding the delayed clock signal following the temperature or power supply voltage changes, and reducing the delay change of the delay circuit;

[0035] The output voltage of the delay circuit is adjusted through the control word, thereby adjusting the delay time of the delayed clock signal. This will not interrupt the operation of the SYSREF clock, has the advantage of being glitch-free, and can improve the linearity of the delay adjustment. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 A schematic diagram of an analog delay adjustment circuit in the prior art;

[0038] Figure 2 is a schematic diagram of a delay circuit in one embodiment of the present invention;

[0039] Figure 3 A schematic diagram of a delay unit of a delay circuit in one embodiment of the present invention;

[0040] Figure 4 A schematic diagram of a variable current source of a delay circuit in one embodiment of the present invention;

[0041] Figure 5 Schematic diagram of a reference current source of a delay circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0043] The term "coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purpose, such as connection through circuits or components such as switches and follower circuits. In addition, in the present invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0044] like Figure 2 As shown, the delay circuit in one embodiment of the present invention includes a first bias unit 10 , a second bias unit 20 , a current mirror unit 30 and a delay unit 40 .

[0045] Specifically, the first bias unit 10 is connected to the power supply voltage VDD and is used to generate a first bias current I B1 ;

[0046] The second bias unit 20 is connected to the reference potential Vss and is used to generate a bias voltage V Y ;

[0047] The current mirror unit 30 is connected between the first bias unit 10 and the second bias unit 20 and is connected to the power supply voltage VDD, and is used for B1 and bias voltage V Y An output voltage Vreg is generated.

[0048] The delay unit 40 includes a plurality of cascaded inverters, connected between the output voltage Vreg and the reference potential Vss, and connected to the current mirror unit 30, and is used to delay the input clock signal SYSREF_in based on the output voltage Vreg to generate a delayed clock signal SYSREF_out. It can be understood that the output voltage Vreg is used as the working voltage of the inverter.

[0049] like Figure 2 As shown, the first bias current I B1 Including fixed current I fix and variable current I DAC .

[0050] The first bias unit 10 includes a fixed current source and a variable current source. The fixed current source is used to generate a fixed current I fix , the variable current source is used to generate a variable current I based on the control word DAC .

[0051] The fixed current I fixThe value of can be regarded as the first bias current I B1 An embodiment controls a fixed current source by a multi-bit control word to generate a variable current I DAC Preferably, the control word is 8 bits.

[0052] like Figure 2 As shown, the second bias unit 20 in one embodiment includes a first MOS transistor M1, a second MOS transistor M2 and a second bias resistor R0, wherein the first MOS transistor M1 is an N-channel MOS transistor, and the second MOS transistor M2 is a P-channel MOS transistor.

[0053] The first end of the first MOS tube M1 is connected to the reference potential Vss, and the second end is short-circuited with the control end;

[0054] A first end of the second MOS transistor M2 is directly or indirectly connected to the current mirror unit 30, a second end is short-circuited with the control end, and a second end is connected to the control end of the first MOS transistor M1;

[0055] The first end of the second bias resistor R0 is connected to the current mirror unit 30 and generates a bias voltage V Y , and the second end is connected to the first end of the second MOS tube M2.

[0056] like Figure 2 As shown, the current mirror unit 30 in one embodiment includes a third MOS transistor M3 and a fourth MOS transistor M4. The third MOS transistor M3 and the fourth MOS transistor M4 are N-channel MOS transistors.

[0057] The second end of the third MOS tube M3 is short-circuited with the control end, and the second end is connected to the first bias unit 10, the first end is connected to the second bias unit 20, and the control end is directly or indirectly connected to the control end of the fourth MOS tube M4;

[0058] A first terminal of the fourth MOS transistor M4 is connected to the delay unit 40 and generates an output voltage Vreg, and a second terminal of the fourth MOS transistor M4 is connected to the power supply voltage VDD.

[0059] V X The voltage at the point (the first end of the second MOS tube M2) is determined by the first bias current I B1 And the size of the first MOS tube M1 and the second MOS tube M2 determines, V X =Vgs_M1+|Vgs_M2|, wherein Vgs_M1 represents the gate-source voltage of the first MOS tube M1, and |Vgs_M2| represents the absolute value of the gate-source voltage of the second MOS tube M2.

[0060] Bias voltage V Y , determined by the voltage at point Vx and the voltage drop across the second bias resistor R0, V Y =V X+(I fix +I DAC )*R0.

[0061] V Z The voltage V Z =V Y +Vgs_M3, Vgs_M3 is the gate-source voltage of the third MOS tube M3.

[0062] Output voltage Vreg=Vgs_M1+|Vgs_M2|+(I fix +I DAC )*R0+Vgs_M3-Vgs_M4.

[0063] Furthermore, in one embodiment, the gate length of the third MOS transistor M3 is equal to the gate length of the fourth MOS transistor M4, that is, the width-to-length ratio W / L of the third MOS transistor M3 is proportional to the width-to-length ratio W / L of the fourth MOS transistor M4. The fourth MOS transistor M4 can follow the third MOS transistor M3 in the first-order effect, and it can be considered that Vgs_M3-Vgs_M4 offsets the influence of the change of the process angle and the ambient temperature, that is, the process angle and temperature change of the current mirror unit 30 will not affect the output voltage Vreg.

[0064] Furthermore, in one embodiment, in a deep N well (DNW) process, the body end of the third MOS tube M3 is connected to the first end, and the body end of the fourth MOS tube M4 is connected to the first end, thereby eliminating the body effect. The first end of the MOS tube, the current mirror tube, and the switch tube involved in the present invention is the source, the second end is the drain, and the control end is the gate.

[0065] like Figure 2 As shown, the current mirror unit 30 in one embodiment further includes a filtering unit. The filtering unit includes a first resistor R1 and a first capacitor C1. The first resistor R1 and the first capacitor C1 form a low-pass filter for filtering low-frequency noise.

[0066] Furthermore, a first end of the first resistor R1 is connected to the control end of the third MOS tube M3, a second end is connected to the control end of the fourth MOS tube M4, a first end of the first capacitor C1 is connected to the control end of the fourth MOS tube M4, and a second end is connected to the reference potential Vss.

[0067] like Figure 3 As shown in (a), the delay unit 40 is composed of a plurality of cascaded inverters.

[0068] like Figure 3As shown in (b), each inverter includes a first PMOS tube Minv_1 and a first NMOS tube Minv_0, wherein the first end of the first PMOS tube Minv_1 is connected to the output voltage Vreg, the second end of the first PMOS tube Minv_1 is connected to the second end of the first NMOS tube Minv_0 and generates the output signal of the inverter of this stage or the delayed clock signal SYSREF_out, the control end is connected to the control end of the first NMOS tube Minv_0 and receives the output signal of the inverter of the previous stage or the input clock signal SYSREF_in, and the first end of the first NMOS tube Minv_0 is connected to the reference potential Vss.

[0069] Further, in one embodiment, the gate length of the first MOS transistor M1 is equal to the gate length of the first NMOS transistor Minv_0, that is, the width-to-length ratio W / L of the first MOS transistor M1 is proportional to the width-to-length ratio W / L of the first NMOS transistor Minv_0. The gate length of the second MOS transistor M2 is equal to the gate length of the first PMOS transistor Minv_1, that is, the width-to-length ratio W / L of the second MOS transistor M2 is proportional to the width-to-length ratio W / L of the first PMOS transistor Minv_1.

[0070] It can be understood that the first MOS tube M1 can follow the first NMOS tube Minv_0 in the first-order effect, that is, when the temperature changes, the electron mobility of the first MOS tube M1 and the first NMOS tube Minv_0 is equal, and the degree of change of the threshold voltage is the same. Similarly, the second MOS tube M2 can follow the first PMOS tube Minv_1 in the first-order effect. When the temperature changes, the electron mobility of the second MOS tube M2 and the first PMOS tube Minv_1 is equal, and the degree of change of the threshold voltage is the same.

[0071] It can be considered that “Vgs_M1+|Vgs_M2|” in the formula offsets “Vgs_Minv_0+|Vgs_Minv_1|”, that is, in the first-order PVT relationship, the delayed clock signal SYSREF_out is approximately not affected by the process corner and ambient temperature of the first PMOS transistor Minv_1 and the first NMOS transistor Minv_0.

[0072] like Figure 2 As shown, the delay circuit in one embodiment further includes a bypass capacitor Cbyp, and the bypass capacitor Cbyp is connected between the output voltage Vreg and the reference potential Vss to suppress ripple voltage noise.

[0073] like Figure 4 As shown, the variable current source in one embodiment includes a first branch 11 and a plurality of second branches.

[0074] The first branch 11 is connected between the power supply voltage VDD and the reference potential Vss and includes a first bias resistor R B, a plurality of first current mirror tubes and a reference current source I B2 , the first branch 11 is used to generate a reference current. In this embodiment, the first current mirror tube includes a first current mirror tube M X1 and the first current mirror tube M X2 , the first current mirror tube M X1 and the first current mirror tube M X2 All of them are P-channel MOS tubes, and form a set of common source and common gate (Cascode) bias circuits. Specifically, the first current mirror tube M X1 The first end is connected to the power supply voltage VDD, and the second end is connected to the first current mirror tube M X2 The first end is connected to the control end of the first current mirror tube M X2 The second end is connected to .

[0075] The first current mirror tube M X2 The second end of the first bias resistor R B The first end of the control terminal is connected to the first bias resistor R B The second end of the first bias resistor R B The second terminal is connected to the reference current source I B2 The first end is connected to the reference current source I B2 The second end of is connected to the reference potential Vss.

[0076] The second branch includes a plurality of second current mirror tubes and switch tubes. The second current mirror tubes and the first current mirror tubes form a current mirror to copy the reference current. The control end of the switch tube receives the control word, the first end is connected to the second current mirror tube, and the second end is connected to the current mirror unit 30. The second ends of the plurality of switch tubes are connected to form a variable current output end, and the variable current output end is used to output the variable current I DAC The switch is used based on the control word S <0> ~S <7> Controls itself on or off to adjust variable current.

[0077] Further, the number of second branches corresponds to the number of bits of the control word. For example, in this embodiment, the value of the variable current is controlled by an 8-bit control word, and a total of 8 groups of second branches are set. It can be understood that for the current replication ratio between each second branch and the first branch (i.e., the ratio of the gate width of the second current mirror tube to the gate width of the first current mirror tube), those skilled in the art can set it based on design requirements. For example, the gate width of the second current mirror tube on the 8 groups of second branches can be set to 1 times, 2 times, 4 times, 8 times, 16 times, 32 times, 64 times, and 128 times the gate width of the first current mirror tube on the first branch (the gate lengths of the first current mirror tube and the second current mirror tube are equal).

[0078] In this embodiment, the corresponding control word can be generated by a register, for example, S<7:0> is 01101111, wherein the seventh and fourth control bits are 0 (low potential), and the corresponding switch tube M S7 And switch tube M S4 On, variable current I DAC For the switch tube M S7 And switch tube M S4 When the control word S<7:0> is all 1, all the switch tubes are turned off, and the variable current I DAC The delay of the delayed clock signal SYSREF_out is the largest. On the contrary, when the control word S<7:0> is all 0, all the switches are turned on, and the variable current I DAC maximum, and the delay of the delayed clock signal SYSREF_out is minimum.

[0079] by Figure 4 Taking the second branch 12 in the embodiment as an example, the second current mirror tube in this embodiment includes a second current mirror tube M 7C1 and the second current mirror tube M 7C2 , the second current mirror tube M 7C1 and the second current mirror tube M 7C2 Both are P-channel MOS tubes, the second current mirror tube M 7C1 With the first current mirror tube M X1 A set of current mirrors is formed, and the second current mirror tube M 7C1 The first end is connected to the power supply voltage VDD, and the second end is connected to the second current mirror tube M 7C2 The first end is connected to the control end of the first current mirror tube M X2 The second current mirror tube M 7C2 With the first current mirror tube M X2 A set of current mirrors is formed, and the second current mirror tube M 7C2 The second end of the switch tube M S7 The first end is connected to the control end of the first current mirror tube M X2 connected.

[0080] The second end of the switch tube MS7 is connected to the current mirror unit 30, and the control end receives the control word S <7> It can be understood that the sum of the currents flowing through the eight switch tubes constitutes the variable current I DAC Through different combinations of control words S<7:0>, the variable current I DAC The size of I DAC =k1*S<7:0>*I B2 The first proportional coefficient k1 represents the mirror ratio of the current mirror (ie, the current mirror formed by the second current mirror tube and the first current mirror tube).

[0081] In one embodiment, the reference current I B2 The bandgap reference voltage Vbg output by the bandgap reference voltage source (Bandgap) is generated by the polysilicon resistor Rpoly, that is, I B2 =k2*Vbg / Rpoly, k2 is the proportionality coefficient, and the bandgap reference voltage Vbg is a constant. Therefore, it can be considered that the reference current I B2 is a zero temperature coefficient current.

[0082] You can get I DAC =k1*S<7:0>*I B2 =k1*(k2*Vbg / Rpoly)*S<7:0>. By setting the second bias resistor R0 to the Rpoly type and the third proportional coefficient to k3, I DAC *R0=k1*k2*k3*Vbg / Rpoly*S<7:0>. The second bias resistor R0 and the first bias resistor R B The resistors are of the same type to offset the temperature effect, i.e., the voltage I DAC *R0 is a constant temperature voltage and does not change with temperature.

[0083] like Figure 5 As shown, in another embodiment, the reference current I B2 The reference current source includes a positive temperature coefficient current Iptat and a zero temperature coefficient current Iconst. The reference current source includes a first sub-current source and a second sub-current source.

[0084] The first sub-current source is used to generate a positive temperature coefficient current Iptat, and the second sub-current source is used to generate a zero temperature coefficient current Iconst.

[0085] The reference current I in this embodiment B2 Disassembled into two parts, namely the reference current I B2 =k4*Iptat+(1-k4)*Iconst. By setting different fourth proportional coefficients k4 by register, the reference current I can be adjusted. B2 The temperature coefficient of the variable current I DAC The temperature coefficient of the output voltage Vreg is adjusted accordingly. When the output voltage Vreg cannot completely follow the influence of the ambient temperature change of the delay unit 40, the reference current I B2 The fourth proportional coefficient k4 offsets the temperature effect and maintains the stability of the delay size.

[0086] By adjusting the variable current I DAC The output voltage Vreg of the delay unit 40 is adjusted by using the control word of the delay unit 40, and the operation of the SYSREF clock will not be interrupted, and the adjustment method has the advantage of being glitch-less.

[0087] Based on the above analysis, it can be seen that the delay unit 40 delays the input clock signal SYSREF_in based on the output voltage Vreg to generate the delayed clock signal SYSREF_out, and the delay accuracy is affected by the output voltage Vreg and the first PMOS transistor Minv_1 and the first NMOS transistor Minv_0 in the inverter.

[0088] Output voltage Vreg=Vgs_M1+|Vgs_M2|+(I fix +I DAC )*R0+Vgs_M3-Vgs_M4. Based on the above analysis, it can be known that “Vgs_M1+|Vgs_M2|” in the formula cancels out the first PMOS tube Minv_1 and the first NMOS tube Minv_0, thereby eliminating the influence of the process angle and the ambient temperature on the first PMOS tube Minv_1 and the first NMOS tube Minv_0.

[0089] In certain specific proportions, the gate-source voltages Vgs of the third MOS transistor M3 and the fourth MOS transistor M4 are considered equal, and "Vgs_M3-Vgs_M4" can be considered 0. In addition, (I fix +I DAC )*R0 is the constant temperature voltage.

[0090] Therefore, the output voltage Vreg can follow the changes of the process angle and the ambient temperature of the delay unit 40, and the delay time of the delayed clock signal is not affected by the process angle and the ambient temperature.

[0091] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0092] The present invention provides an output voltage for a delay unit by setting a first bias unit and a second bias unit, and the influence of the current mirror unit on the output voltage is offset by following the changes of the process angle and the ambient temperature, so that the output voltage can follow the process angle and the ambient temperature changes of the delay unit, avoiding the delayed clock signal following the temperature change, and avoiding the delayed clock signal following the power supply voltage change, thereby reducing the delay change of the delay circuit;

[0093] The present invention adjusts the output voltage Vreg of the delay circuit through a control word, thereby adjusting the delay time of the delayed clock signal, and will not interrupt the operation of the SYSREF clock, thus having the advantage of no burrs.

[0094] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0095] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A delay circuit, characterized in that: include: A first bias unit, connected to a power supply voltage, and configured to generate a first bias current; A second bias unit, connected to the reference potential, for generating a bias voltage; A current mirror unit, connected between the first bias unit and the second bias unit and connected to a power supply voltage, for generating an output voltage based on a first bias current and a bias voltage; The delay unit includes a plurality of cascaded inverters connected between an output voltage and a reference potential, and is used for delaying an input clock signal based on the output voltage to generate a delayed clock signal.

2. The delay circuit according to claim 1, characterized in that The first bias unit includes a fixed current source and a variable current source, the fixed current source is used to generate a fixed current, and the variable current source is used to generate a variable current based on a control word.

3. The delay circuit according to claim 2, characterized in that The variable current source includes a first branch and a plurality of second branches; wherein, The first branch is connected between the power supply voltage and the reference potential, and includes a first bias resistor, a plurality of first current mirror tubes and a reference current source, and the first branch is used to generate a reference current; The second branch includes a plurality of second current mirror tubes and a switch tube. The second current mirror tube and the first current mirror tube form a current mirror to copy a reference current. The control end of the switch tube receives a control word, and the first end is connected to the second current mirror tube. The second ends of the plurality of switch tubes are connected to form a variable current output end. The switch tube is used to control its own on or off based on the control word to adjust the variable current.

4. The delay circuit according to claim 3, characterized in that: The reference current source includes a first sub-current source and a second sub-current source; wherein, The first sub-current source is used to generate a positive temperature coefficient current, the second sub-current source is used to generate a zero temperature coefficient current, and the reference current includes a positive temperature coefficient current and a zero temperature coefficient current.

5. The delay circuit according to claim 1, characterized in that: The second bias unit includes a first MOS transistor and a second MOS transistor; wherein, The first end of the first MOS tube is connected to the reference potential, and the second end is short-circuited with the control end; The first end of the second MOS tube is directly or indirectly connected to the current mirror unit, the second end is short-circuited with the control end, and the second end is connected to the control end of the first MOS tube.

6. The delay circuit according to claim 5, characterized in that The second bias unit further includes a second bias resistor, a first end of the second bias resistor is connected to the current mirror unit, and a second end of the second bias resistor is connected to the first end of the second MOS tube.

7. The delay circuit according to claim 1, characterized in that: The current mirror unit includes a third MOS tube and a fourth MOS tube; wherein, The second end of the third MOS tube is short-circuited with the control end, the second end is connected to the first bias unit, the first end is connected to the second bias unit, and the control end is directly or indirectly connected to the control end of the fourth MOS tube; The first end of the fourth MOS tube is connected to the delay unit and generates an output voltage, and the second end is connected to the power supply voltage.

8. The delay circuit according to claim 7, characterized in that: The body end of the third MOS tube is connected to the first end, and the body end of the fourth MOS tube is connected to the first end; and / or, The gate length of the third MOS tube is equal to the gate length of the fourth MOS tube.

9. The delay circuit according to claim 7, characterized in that: The current mirror unit also includes a filtering unit for filtering out low-frequency noise; wherein, The filtering unit includes a first resistor and a first capacitor, wherein a first end of the first resistor is connected to a control end of a third MOS tube, and a second end is connected to a control end of a fourth MOS tube, a first end of the first capacitor is connected to a control end of the fourth MOS tube, and a second end is connected to a reference potential.

10. The delay circuit according to claim 5, characterized in that The inverter comprises a first PMOS tube and a first NMOS tube, wherein the first end of the first PMOS tube is connected to the output voltage, the second end is connected to the second end of the first NMOS tube, the control end is connected to the control end of the first NMOS tube, and the first end of the first NMOS tube is connected to the reference potential; The gate length of the first MOS transistor is equal to the gate length of the first NMOS transistor; and / or, The gate length of the second MOS tube is equal to the gate length of the first PMOS tube.

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