System for turning off power consumption of auxiliary starting circuit

Abstract

The invention discloses a system for turning off power consumption of an auxiliary starting circuit, a to-be-started circuit is a circuit with a degenerate point and can output reference current, a crystal oscillator generates a switch control signal according to the reference current output by the to-be-started circuit to generate a working clock of the circuit, and when the to-be-started circuit works normally, the circuit is turned off. The RC oscillator generates frequency and sends the frequency to the switch control signal generation circuit, through fixed clock signal counting, the switch control signal generation circuit outputs a switch control signal to control and close the normally open current power consumption of the auxiliary starting circuit, meanwhile, the switch control signal generation circuit stops counting the clock, and the RC oscillator works normally. The auxiliary starting circuit can assist a to-be-started circuit with a degenerate bias point in normal power-on, and meanwhile, the power consumption of the auxiliary starting circuit can be closed after the power-on of the to-be-started circuit is completed.

Description

Technical Field

[0001] The invention relates to integrated circuit design technology, and in particular to a system for closing power consumption of an auxiliary starting circuit. Background Art

[0002] With the rapid development of portable devices, higher requirements are placed on the power consumption of circuits. Under the same power conditions, low-power chips can work longer and will have more advantages in the same products.

[0003] Since the bias current reference circuit (BIAS), bandgap reference circuit (BGR) and other circuits have "degenerate" bias points (there are at least two balanced operating points in the circuit, one of which is the zero point, that is, the current in each branch of the core module is zero, the circuit is turned off and can remain in the off state indefinitely; the other is the normal operating point), the circuit may not work after the power is turned on. This problem is called the startup problem of the circuit; this requires an auxiliary startup circuit to assist the above circuit to get rid of the bias point during the power-on process, so that the circuit with the "degenerate" bias point after the power is turned on can work normally. Since the auxiliary startup circuit only works during the power-on process of the circuit to be started, it is hoped that the power consumption of the auxiliary startup circuit is as small as possible or zero.

[0004] There is a resistor type auxiliary starting circuit such as Figure 1 As shown, the bias current reference circuit (BIAS) is composed of the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, the zeroth NMOS transistor NM0, the first NMOS transistor NM1 and the first resistor R1, and its function is to provide a reference current IREF to other circuit modules; the zeroth PMOS transistor PM0, the first PMOS transistor PM1 and the second resistor R2 form an auxiliary startup circuit, the zeroth PMOS transistor PM0 is a current mirror transistor, and the mirror current is provided by the bias current reference circuit (BIAS); the first PMOS transistor PM1 is a switch transistor, during the power-on process of the working voltage VDD, the potential of the VN point is low, the first PMOS transistor PM1 is turned on, the voltage of the VM point is pulled up, and the bias current reference circuit (BIAS) is started normally. After startup, the bias current reference circuit (BIAS) current mirrored by the zeroth PMOS transistor PM0 flows through the second resistor R2 to raise the potential of the VN point, at which time the first PMOS transistor PM1 is turned off, and the auxiliary startup circuit is completed.

[0005] After the reference circuit (BIAS) is started, the zeroth PMOS tube PM0 remains turned on, and the current I1 flows through the second resistor R2 to maintain the VN point at a high potential to turn off the first PMOS tube PM1. Since the VN point potential is obtained by resistor voltage division, the VN point voltage is less than the working voltage VDD. Under certain conditions, the VN point voltage is too much less than the working voltage VDD, which may cause the first PMOS tube PM1 to be mistakenly turned on, affecting the bias current reference circuit (BIAS). The existence of the current I1 can be tolerated in non-low-power circuit design, but under the requirements of low-power design, it is hoped that the current I1 is as small as possible or zero power consumption. Usually, the current I1 is reduced by increasing the second resistor R2. In the high-voltage (greater than 3V, such as 5V) process, the resistance value of the second resistor R2 needs to become very large.

[0006] In view of the power consumption problem of the existing resistor-type auxiliary starting circuit and the problem that the voltage at the VN point is too much lower than the working voltage VDD, a capacitor-type auxiliary starting circuit is currently available. Figure 2 As shown, the circuit replaces the second resistor R2 in the existing resistor-type auxiliary starting circuit with the first capacitor C1, and utilizes the first capacitor C1. The voltage of the upper and lower plates during the power-on process cannot suddenly change. During the power-on process, the voltage at the VN point is kept low. After the power-on is completed, the zeroth PMOS tube PM0 is turned on, and the voltage at the VN point is kept at a high level to turn off the first PMOS tube PM1. After the power-on is completed, the current I1 is extremely small and close to zero power consumption. The capacitor-type auxiliary starting circuit performs well when the power is quickly powered on, but in the slow power-on process, the voltage at the VN point cannot be well maintained at a low level, which will cause the starting circuit to fail. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide a system for shutting down the power consumption of the auxiliary starting circuit, which can assist the normal power-on of the circuit to be started with a "degenerate" bias point, and at the same time shut down the power consumption of the auxiliary starting circuit after the circuit to be started is powered on, thereby reducing power consumption.

[0008] In order to solve the above technical problems, the present invention provides a system for shutting down the power consumption of an auxiliary startup circuit, wherein the auxiliary startup circuit includes a zeroth PMOS tube PM0, a first PMOS tube PM1, a second resistor R2 and a second switch tube M2;

[0009] The source terminals of the zeroth PMOS transistor PM0 and the first PMOS transistor PM1 are connected to the working voltage VDD;

[0010] The source end of the zeroth PMOS tube PM0 is used as the VN point;

[0011] The second resistor R2 is connected in series between the VN point and the ground;

[0012] The gate terminal of the first PMOS tube PM1 is connected to the VN point, and the drain terminal receives the auxiliary starting terminal of the starting circuit;

[0013] The gate terminal of the zeroth PMOS tube PM0 is connected to the voltage sampling point VR of the circuit to be started;

[0014] When power is applied and the voltage applied to the auxiliary start-up terminal is 0.7 to 1 times of the working voltage VDD, the circuit to be started can work normally, and the voltage at the voltage sampling point is 0.7 to 1 times of the working voltage VDD;

[0015] The gate terminal of the second switch tube M2 is connected to the switch control signal SLEEP;

[0016] One end of the source and drain of the second switch tube M2 is connected to one end of the second resistor R2, and the other end is grounded, and the other end of the second resistor R2 is connected to the VN point; or,

[0017] One end of the source and drain of the second switch tube M2 is connected to one end of the second resistor R2, and the other end is connected to the point VN. The other end of the second resistor R2 is grounded.

[0018] Preferably, the circuit to be started is a circuit having a "degenerate" bias point and capable of outputting a reference current (IREF).

[0019] Preferably, the circuit to be started is a bias current reference circuit or a bandgap reference circuit.

[0020] Preferably, the auxiliary starting circuit further includes a switch control signal generating circuit;

[0021] The switch control signal generating circuit outputs a switch control signal SLEEP when the circuit to be started operates normally.

[0022] Preferably, the auxiliary starting circuit further includes a crystal oscillator;

[0023] The crystal oscillator generates a working clock CLKOUT of the switch control signal generating circuit according to the reference current IREF output by the circuit to be started.

[0024] Preferably, the crystal oscillator is an RC type crystal oscillator.

[0025] Preferably, the second switch tube M2 is an NMOS tube;

[0026] The drain end of the source-drain of the second switch tube M2 is connected to one end of the second resistor R2, the source end is grounded, and the other end of the second resistor R2 is connected to the VN point; or,

[0027] The source terminal of the second switch tube M2 is connected to one end of the second resistor R2, the drain terminal is connected to the VN point, and the other end of the second resistor R2 is grounded.

[0028] Preferably, the switch control signal generating circuit includes an AND gate and two D flip-flops;

[0029] The first D flip-flop The D terminal and the clock input terminal Clk of the second D flip-flop are short-circuited, and the second D flip-flop The terminal and the D terminal are short-circuited and serve as the output terminal of the switch control signal SLEEP;

[0030] The switch control signal SLEEP and the working clock CLKOUT are used as two inputs of an AND gate, and the output terminal of the AND gate is connected to the clock input terminal Clk of the first D flip-flop.

[0031] Preferably, the circuit to be started is a bias current reference circuit;

[0032] The bias current reference circuit includes a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a zeroth NMOS transistor NM0, a first NMOS transistor NM1 and a first resistor R1;

[0033] The source terminals of the second PMOS transistor PM2, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are connected to the operating voltage VDD;

[0034] The drain end of the third PMOS tube PM3 serves as a voltage sampling point VR of the circuit to be started;

[0035] The gate terminal of the second PMOS transistor PM2, the gate terminal of the third PMOS transistor PM3, the gate terminal of the fourth PMOS transistor PM4 and the drain terminal of the first NMOS transistor NM1 are connected to the voltage sampling point VR;

[0036] The gate terminal of the first NMOS tube NM1, the drain terminal of the zeroth NMOS tube NM0 and the drain terminal of the second PMOS tube PM2 are connected to the VM point, and the VM point serves as an auxiliary starting terminal of the circuit to be started;

[0037] The drain terminal of the first NMOS transistor NM1 and the gate terminal of the zeroth NMOS transistor NM0 are connected to one end of the first resistor R1;

[0038] The other end of the first resistor R1 and the source end of the zeroth NMOS transistor NM0 are grounded;

[0039] The drain terminal of the fourth PMOS transistor PM4 is used to output a reference current IREF.

[0040] The system for shutting down the power consumption of the auxiliary starting circuit of the present invention adds a second switch tube M2 to the existing auxiliary starting circuit, and the gate terminal of the second switch tube M2 is connected to the switch control signal SLEEP; it can assist the circuit to be started with a "degenerate" bias point to power on normally, and at the same time, it can shut down the power consumption of the auxiliary starting circuit after the circuit to be started is powered on, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 It is an existing resistor type auxiliary starting circuit;

[0043] Figure 2 It is an existing capacitor type auxiliary starting circuit;

[0044] Figure 3 1 is a circuit diagram of a system for shutting down the power consumption of an auxiliary starting circuit according to an embodiment of the present invention;

[0045] Figure 4 is a circuit diagram of a switch control signal generating circuit of a system for shutting down power consumption of an auxiliary startup circuit according to an embodiment of the present invention;

[0046] Figure 5 The invention is an overall system of an embodiment of a system for shutting down power consumption of an auxiliary starting circuit according to the present invention. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] The words "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprises" and similar terms mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "front", "back" and the like are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0049] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0050] Embodiment 1

[0051] A system for shutting down power consumption of an auxiliary startup circuit Figure 3 As shown, the auxiliary startup circuit includes a zeroth PMOS transistor PM0, a first PMOS transistor PM1, a second resistor R2 and a second switch tube M2;

[0052] The source terminals of the zeroth PMOS transistor PM0 and the first PMOS transistor PM1 are connected to the working voltage VDD;

[0053] The source end of the zeroth PMOS tube PM0 is used as the VN point;

[0054] The second resistor R2 is connected in series between the VN point and the ground;

[0055] The gate terminal of the first PMOS tube PM1 is connected to the VN point, and the drain terminal receives the auxiliary starting terminal of the starting circuit;

[0056] The gate terminal of the zeroth PMOS tube PM0 is connected to the voltage sampling point VR of the circuit to be started;

[0057] When power is applied and the voltage applied to the auxiliary start-up terminal is 0.7 to 1 times of the working voltage VDD, the circuit to be started can work normally, and the voltage at the voltage sampling point is 0.7 to 1 times of the working voltage VDD;

[0058] The gate terminal of the second switch tube M2 is connected to the switch control signal SLEEP;

[0059] One end of the source and drain of the second switch tube M2 is connected to one end of the second resistor R2, and the other end is grounded, and the other end of the second resistor R2 is connected to the VN point; or,

[0060] One end of the source and drain of the second switch tube M2 is connected to one end of the second resistor R2, and the other end is connected to the point VN. The other end of the second resistor R2 is grounded.

[0061] Preferably, the circuit to be started is a circuit having a "degenerate" bias point such as a bias current reference circuit (BIAS) or a bandgap reference circuit (BGR), and can output a reference current (IREF).

[0062] The system for shutting down the power consumption of the auxiliary startup circuit of the first embodiment has an auxiliary startup circuit in which a second switch tube M2 is added to the existing auxiliary startup circuit, and the gate terminal of the second switch tube M2 is connected to the switch control signal SLEEP; it can assist the circuit to be started with a "degenerate" bias point to be powered on normally, and at the same time, it can shut down the power consumption of the auxiliary startup circuit after the circuit to be started is powered on, thereby reducing power consumption.

[0063] Embodiment 2

[0064] Based on the system for shutting down the power consumption of the auxiliary startup circuit in the first embodiment, the auxiliary startup circuit further includes a switch control signal generating circuit;

[0065] The switch control signal generating circuit outputs a switch control signal SLEEP when the circuit to be started operates normally.

[0066] Embodiment 3

[0067] Based on the system for shutting down the power consumption of the auxiliary starting circuit in the second embodiment, Figure 5 As shown, the auxiliary startup circuit also includes a crystal oscillator (OSC);

[0068] The crystal oscillator generates a working clock CLKOUT of the switch control signal SLEEP generating circuit according to the reference current IREF output by the circuit to be started.

[0069] Preferably, the crystal oscillator is an RC type crystal oscillator.

[0070] Embodiment 4

[0071] A system for shutting down the power consumption of the auxiliary starting circuit based on the second or third embodiment, such as Figure 4 As shown, the switch control signal generating circuit includes an AND gate and two D flip-flops;

[0072] The first D flip-flop The D terminal and the clock input terminal Clk of the second D flip-flop are short-circuited, and the second D flip-flop The terminal and the D terminal are short-circuited and serve as the output terminal of the switch control signal SLEEP;

[0073] The switch control signal SLEEP and the working clock CLKOUT are used as two inputs of an AND gate, and the output terminal of the AND gate is connected to the clock input terminal Clk of the first D flip-flop.

[0074] In the system for shutting down the power consumption of the auxiliary startup circuit in the fourth embodiment, the switch control signal generating circuit for providing the switch control signal SLEEP is a 2-rising-edge adder counter, and the second D flip-flop The terminal outputs the switch control signal SLEEP, and its functional state is shown in Table 1. Q1 is the Q terminal state of the first D flip-flop, and Q2 is the Q terminal state of the second D flip-flop. When powered on, the initial states of Q1 and Q2 are 0, and the initial state of the second D flip-flop when powered on is The terminal is high level, the switch control signal SLEEP is set high when powered on, so the second switch tube M2 is turned on when powered on, the potential of the VN point is pulled down, the first PMOS tube PM1 is turned on, so that the voltage applied to the auxiliary start-up terminal of the circuit to be started is close to the working voltage VDD, and the circuit to be started can work normally. The voltage at the voltage sampling point is 0.7 to 1 times the working voltage VDD, and the zeroth PMOS tube PM0 remains open (conducted); after two pulse rising edges of the working clock CLKOUT, the switch control signal SLEEP is set low, the second switch tube M2 is turned off, and the current power consumption of the auxiliary start-up circuit flowing through the second resistor R2 is eliminated. At the same time, the switch control signal SLEEP closes the working clock CLKOUT through the AND gate and enters the D trigger, turning off the clock pulse of the D trigger, so that the switch control signal SLEEP continues to be low level. Since the zeroth PMOS tube PM0 is in the on state, the potential of the VN point is pulled close to the working voltage VDD, so that the first PMOS tube PM1 is turned off, the auxiliary start-up circuit is turned off, and the auxiliary start-up circuit no longer generates power consumption after the circuit to be started is successfully powered on.

[0075] In the system for shutting down the power consumption of the auxiliary startup circuit of the fourth embodiment, the switch control signal SLEEP is powered on to follow the working voltage VDD. After the startup circuit works normally for 2 clock pulses, the switch control signal SLEEP is set low and the auxiliary startup circuit is shut down. The switch control signal SLEEP control is only related to the logic function and has nothing to do with the speed of powering up the power supply.

[0076] Table 1

[0077]

[0078] Embodiment 5

[0079] Based on the system for shutting down the power consumption of the auxiliary startup circuit in the fourth embodiment, the circuit to be started is a bias current reference circuit (BIAS);

[0080] The bias current reference circuit includes a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a zeroth NMOS transistor NM0, a first NMOS transistor NM1 and a first resistor R1;

[0081] The source terminals of the second PMOS transistor PM2, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are connected to the operating voltage VDD;

[0082] The drain end of the third PMOS tube PM3 serves as a voltage sampling point VR of the circuit to be started;

[0083] The gate terminal of the second PMOS transistor PM2, the gate terminal of the third PMOS transistor PM3, the gate terminal of the fourth PMOS transistor PM4 and the drain terminal of the first NMOS transistor NM1 are connected to the voltage sampling point VR;

[0084] The gate terminal of the first NMOS tube NM1, the drain terminal of the zeroth NMOS tube NM0 and the drain terminal of the second PMOS tube PM2 are connected to the VM point, and the VM point serves as an auxiliary starting terminal of the circuit to be started;

[0085] The drain terminal of the first NMOS transistor NM1 and the gate terminal of the zeroth NMOS transistor NM0 are connected to one end of the first resistor R1;

[0086] The other end of the first resistor R1 and the source end of the zeroth NMOS transistor NM0 are grounded;

[0087] The drain terminal of the fourth PMOS transistor PM4 is used to output a reference current IREF.

[0088] In the system for shutting down the power consumption of the auxiliary startup circuit of the fifth embodiment, the bias current reference circuit (BIAS) provides a reference current IREF to other circuit modules; the zeroth PMOS tube PM0 is a current mirror tube, and the mirror current is provided by the bias current reference circuit (BIAS); during the power-on process of the working voltage VDD, the voltage at the point VN is low, the first PMOS tube PM1 is turned on, the voltage at the point VM is pulled up, and the bias current reference circuit (BIAS) is started normally. After startup, the bias current reference circuit (BIAS) current mirrored by the zeroth PMOS tube PM0 flows through the second resistor R2 to raise the voltage at the point VN.

[0089] Embodiment 6

[0090] Based on the system for shutting down the power consumption of the auxiliary startup circuit in the first embodiment, the second switch tube M2 is an NMOS tube;

[0091] The drain end of the source-drain of the second switch tube M2 is connected to one end of the second resistor R2, the source end is grounded, and the other end of the second resistor R2 is connected to the VN point; or,

[0092] The source terminal of the second switch tube M2 is connected to one end of the second resistor R2, the drain terminal is connected to the VN point, and the other end of the second resistor R2 is grounded.

[0093] When the switch control signal SLEEP is at a high level (greater than 0.7V), the second switch tube M2 is turned on (source and drain are connected); when the switch control signal SLEEP is at a low level (0V), the second switch tube M2 is turned off.

[0094] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A system for shutting down power consumption of an auxiliary startup circuit, characterized in that: The auxiliary startup circuit includes a zeroth PMOS tube (PM0), a first PMOS tube (PM1), a second resistor (R2) and a second switch tube (M2); The source terminals of the zeroth PMOS tube (PM0) and the first PMOS tube (PM1) are connected to a working voltage (VDD); The source end of the zeroth PMOS tube (PM0) is used as the VN point; The second resistor (R2) is connected in series between the VN point and the ground; The gate terminal of the first PMOS tube (PM1) is connected to the VN point, and the drain terminal receives the auxiliary starting terminal of the starting circuit; The gate terminal of the zeroth PMOS tube (PM0) is connected to the voltage sampling point (VR) of the circuit to be started; When power is applied and the voltage applied to the auxiliary start-up terminal is 0.7 to 1 times of the working voltage (VDD), the circuit to be started can work normally, and the voltage at the voltage sampling point is 0.7 to 1 times of the working voltage (VDD); The gate terminal of the second switch tube (M2) is connected to a switch control signal (SLEEP); One end of the source and drain of the second switch tube (M2) is connected to one end of the second resistor (R2), and the other end is grounded, and the other end of the second resistor (R2) is connected to the VN point; or, One end of the source and drain of the second switch tube (M2) is connected to one end of the second resistor (R2), and the other end is connected to the VN point. The other end of the second resistor (R2) is grounded.

2. The system for shutting down the power consumption of the auxiliary startup circuit according to claim 1, characterized in that: The circuit to be started is a circuit having a "degenerate" bias point and capable of outputting a reference current (IREF).

3. The auxiliary starting circuit according to claim 2, characterized in that: The circuit to be started is a bias current reference circuit or a bandgap reference circuit.

4. The system for shutting down the power consumption of the auxiliary startup circuit according to claim 3, characterized in that: The auxiliary startup circuit also includes a switch control signal generating circuit; The switch control signal generating circuit outputs a switch control signal (SLEEP) when the circuit to be started operates normally.

5. The system for shutting down the power consumption of the auxiliary startup circuit according to claim 4, characterized in that: The auxiliary starting circuit also includes a crystal oscillator; The crystal oscillator generates a working clock (CLKOUT) of the switch control signal generating circuit according to the reference current (IREF) output by the circuit to be started.

6. The system for shutting down the power consumption of the auxiliary startup circuit according to claim 5, characterized in that: The crystal oscillator is an RC type crystal oscillator, and its reference current comes from the circuit to be started.

7. The system for shutting down the power consumption of the auxiliary starting circuit according to claim 4, 5 or 6, characterized in that: The switch control signal generating circuit includes an AND gate and two D flip-flops; The first D flip-flop The D terminal and the clock input terminal (Clk) of the second D flip-flop are short-circuited. The D terminal and the D terminal are short-circuited and serve as the output terminal of the switch control signal (SLEEP); The switch control signal (SLEEP) and the working clock (CLKOUT) are used as two inputs of an AND gate, and the output end of the AND gate is connected to the clock input end (Clk) of the first D flip-flop.

8. The system for shutting down the power consumption of the auxiliary startup circuit according to claim 1, characterized in that: The circuit to be started is a bias current reference circuit; The bias current reference circuit comprises a second PMOS transistor (PM2), a third PMOS transistor (PM3), a fourth PMOS transistor (PM4), a zeroth NMOS transistor (NM0), a first NMOS transistor (NM1) and a first resistor (R1); The source terminals of the second PMOS tube (PM2), the third PMOS tube (PM3) and the fourth PMOS tube (PM4) are connected to the operating voltage (VDD); The drain end of the third PMOS tube (PM3) serves as a voltage sampling point (VR) of the circuit to be started; The gate terminal of the second PMOS tube (PM2), the gate terminal of the third PMOS tube (PM3), the gate terminal of the fourth PMOS tube (PM4) and the drain terminal of the first NMOS tube (NM1) are connected to a voltage sampling point (VR); The gate terminal of the first NMOS tube (NM1), the drain terminal of the zeroth NMOS tube (NM0) and the drain terminal of the second PMOS tube (PM2) are connected to the VM point, and the VM point serves as an auxiliary starting terminal of the circuit to be started; The drain terminal of the first NMOS tube (NM1) and the gate terminal of the zeroth NMOS tube (NM0) are connected to one end of the first resistor (R1); The other end of the first resistor (R1) and the source end of the zeroth NMOS transistor (NM0) are grounded; The drain terminal of the fourth PMOS tube (PM4) is used to output a reference current (IREF).

9. The system for shutting down power consumption of an auxiliary startup circuit according to claim 1, characterized in that: The second switch tube (M2) is an NMOS tube; The drain end of the second switch tube (M2) is connected to one end of the second resistor (R2), the source end is grounded, and the other end of the second resistor (R2) is connected to the VN point; or, The source end of the second switch tube (M2) is connected to one end of the second resistor (R2), the drain end is connected to the VN point, and the other end of the second resistor (R2) is grounded.

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