Common-mode noise reduction level shifting circuit

Abstract

The present invention discloses a common-mode noise reduction level shift circuit in the field of power supply circuit technology, including a common-mode circuit module, a voltage stabilizing module, an RC delay module, a gate circuit module, a trigger and an inverter module; the common-mode circuit module is used to filter the common-mode signal, and the electromagnetic interference of the level shift circuit can be reduced by filtering the common-mode signal; the input end of the common-mode circuit module is electrically connected to the output end of the voltage stabilizing module, and the voltage stabilizing module is used to stabilize the input end voltage of the common-mode circuit module, which is beneficial to improving the stability of the voltage of the input common-mode circuit module. The present invention effectively suppresses dv / dt noise by setting a common-mode level shift circuit under high transient voltage, which can effectively reduce noise and effectively solve the logic error problem caused by noise coupling when the high-side ground VS quickly jumps from low voltage to high voltage.

Description

Technical Field

[0001] The invention relates to the technical field of power supply circuits, in particular to a common-mode noise reduction level shift circuit. Background Art

[0002] In the design process of integrated circuits, level shift technology is often used to convert low-voltage signals into high-voltage signals, thereby achieving control of high-voltage output stages by low-voltage logic.

[0003] As a circuit structure of an integrated circuit, the structure of the pulse generating circuit includes an inverter X1, a first pulse unit XA, and a second pulse unit XB. The level shift circuit includes a first high-voltage tube HN1, a second high-voltage tube HN2, a resistor R1, a resistor R2, and a filter circuit. The input end of the inverter X1 is connected to the input end of the first pulse unit XA, and the output end of the inverter X1 is connected to the input end of the second pulse unit XB. The first pulse unit XA and the second pulse unit XB generate a pulse signal XA and a pulse signal XB respectively. The two pulse signals XA and XB control the high-voltage signals HN1 and HN2 respectively. The two high-voltage tubes and the load resistors R1 and R2 connected to them together form a level shift circuit for level shift conversion, and then are connected to the output end of the circuit through a filter circuit. However, the traditional level shift circuit has two shortcomings:

[0004] On the one hand, the traditional level shift circuit has a weak ability to suppress dv / dt noise. When the VS voltage connected to the filter circuit quickly jumps from low voltage to high voltage, the noise will be coupled to the internal circuit, causing errors in the internal logic.

[0005] On the other hand, the existence of filtering circuits in traditional level shift circuits results in long transmission delays and slow signal conversion speeds in the circuits, which limits the operating frequency and restricts the use of level shift circuits. Summary of the invention

[0006] The purpose of the present invention is to provide a common-mode noise reduction level shift circuit, which effectively suppresses dv / dt noise by setting a common-mode level shift circuit under high transient voltage, effectively reduces noise, and effectively solves the logic error problem caused by noise coupling when the high-side ground VS quickly jumps from low voltage to high voltage.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] In a first aspect, the present invention provides a common-mode noise reduction level shift circuit, which is used to suppress high transient voltage noise. The common-mode noise reduction level shift circuit includes a common-mode circuit module, a voltage stabilization module, an RC delay module, a gate circuit module, a trigger and an inverter module;

[0009] The common-mode circuit module is used to filter the common-mode signal, and the electromagnetic interference of the level shift circuit can be reduced by filtering the common-mode signal; the input end of the common-mode circuit module is electrically connected to the output end of the voltage stabilizing module, and the voltage stabilizing module is used to stabilize the input voltage of the common-mode circuit module, which is beneficial to improving the stability of the voltage of the input common-mode circuit module; the output end of the common-mode circuit module is electrically connected to the input end of the RC delay module, and the RC delay module is used for delaying signals and filtering; the output end of the RC delay module is electrically connected to the input end of the gate circuit module, and the output end of the gate circuit module is electrically connected to the input end of the trigger, and the output end of the trigger is electrically connected to the input end of the inverter module, and the output end of the inverter serves as the high-voltage output signal end OUT, and the trigger flips the stable state of the common-mode noise reduction level shift circuit by receiving a trigger signal.

[0010] As a further solution of the present invention: the common-mode circuit module includes a first common-mode unit M1 and a second common-mode unit M2, the first common-mode unit M1 includes a first current source I1 and a second current source I2, the output end of the first current source I1 is electrically connected to the input end of the second current source I2, the second common-mode unit M2 includes a third current source I3 and a fourth current source I4, the output end of the third current source I3 is electrically connected to the input end of the fourth current source I4, and the output end of the fourth current source I4 forms a high-side ground VS.

[0011] As a further solution of the present invention: the voltage stabilizing module includes a first switch unit, a first voltage stabilizing unit, a second switch unit and a second voltage stabilizing unit, one end of the first switch unit is electrically connected to the input end of the first voltage stabilizing unit, the output end of the first voltage stabilizing unit is electrically connected to the input end of the first common mode unit M1, one end of the second switch unit is electrically connected to the input end of the second voltage stabilizing unit, and the output end of the second voltage stabilizing unit is electrically connected to the input end of the second common mode unit M2.

[0012] As a further solution of the present invention: the first switch unit is a first NMOS transistor HN1, the first voltage stabilizing unit is a first voltage stabilizing diode D1, the second switch unit is a second NMOS transistor HN2, the second voltage stabilizing unit is a second voltage stabilizing diode D2, the gate of the first NMOS transistor HN1 receives the pulse signal Pulse_F, the source of the first NMOS transistor HN1 is grounded, the drain of the first NMOS transistor HN1 is electrically connected to the anode of the first voltage stabilizing diode D1, a connection end of the first common mode unit M1 and the second common mode unit M2, and forms a potential point FA at the connection intersection of the three, the cathode of the first voltage stabilizing diode D1 forms a high-side power supply point VB, and the potential point FA is used to control the current at the second current source I2 in the first common mode unit M1 and the current at the third current source I3 in the second common mode unit M2;

[0013] The cathode of the first voltage zener diode D1 is electrically connected to the input end of the first current source I1, the gate of the second NMOS tube HN2 is used to receive the pulse signal Pulse_R, the source of the second NMOS tube HN2 is grounded, and the drain of the second NMOS tube HN2 is electrically connected to the anode of the second voltage zener diode D2, a connection end of the first common mode unit M1 and the second common mode unit M2 to form an RA potential point at the connection intersection of the three, and the RA potential point is used to control the current at the first current source I1 in the first common mode unit M1 and the current at the fourth current source I4 in the second common mode unit M2.

[0014] As a further solution of the present invention: the first voltage stabilizing diode D1 and / or the second voltage stabilizing diode D2 is a Zener diode, and the first voltage stabilizing diode D1 and the second voltage stabilizing diode D2 have a clamping protection function.

[0015] As a further solution of the present invention: the RC delay module includes a first RC delay module, a second RC delay module, a first current detection unit, a second current detection unit, a third switch unit and a fourth switch unit, the first RC delay module and the third switch unit are respectively connected in parallel at both ends of the first common mode unit M1, the third switch unit and the input end of the first common mode unit M1 are connected with the first current detection unit, the second RC delay module and the fourth switch unit are respectively connected in parallel at both ends of the second common mode unit M2, and the second current detection unit is connected between one end of the fourth switch unit and the input end of the second common mode unit M2.

[0016] As a further solution of the present invention: the first RC delay module includes a first resistor R1 and a first capacitor C1 connected in parallel with both ends of the first resistor R1, the third switch unit is a first medium voltage / low voltage NMOS tube N1, the gate of the first medium voltage / low voltage NMOS tube N1 is electrically connected to one end of the first capacitor C1, the source of the first medium voltage / low voltage NMOS tube N1 is electrically connected to the output end of the second current source I2, the drain of the first medium voltage / low voltage NMOS tube N1 is electrically connected to the output end of the first current detection unit, and the first current detection unit is a fifth current source I5;

[0017] The second RC delay module includes a second resistor R2 and a second capacitor C2 connected in parallel with both ends of the second resistor R2. The fourth switch unit is a second medium voltage / low voltage NMOS tube N2. The gate of the second medium voltage / low voltage NMOS tube N2 is electrically connected to one end of the second capacitor C2. The source of the second medium voltage / low voltage NMOS tube N2 is electrically connected to the output end of the fourth current source I4. The drain of the second medium voltage / low voltage NMOS tube N2 is electrically connected to the output end of the second current detection unit. The second current detection unit is the sixth current source I6.

[0018] As a further solution of the present invention: the gate circuit module includes a second digital unit inverter X2, a third digital unit inverter X3, a fourth digital unit NAND gate X4 and a fifth digital unit NAND gate X5, and the input end of the second digital unit inverter X2 is electrically connected to the first input end of the fifth digital unit NAND gate X5;

[0019] The output end of the second digital unit inverter X2 is electrically connected to the first input end of the fourth digital unit NAND gate X4, the second input end of the fourth digital unit NAND gate X4 is electrically connected to the input end of the third digital unit inverter X3, and the output end of the third digital unit inverter X3 is electrically connected to the second input end of the fifth digital unit NAND gate X5;

[0020] An input end of the second digital unit inverter X2 is electrically connected to the drain of the first medium voltage / low voltage NMOS transistor N1 , and an input end of the third digital unit inverter X3 is electrically connected to the drain of the second medium voltage / low voltage NMOS transistor N2 .

[0021] As a further solution of the present invention: the trigger is an RS trigger, the trigger includes a sixth digital unit NAND gate X6 and a seventh digital unit NAND gate X7, the first input end of the sixth digital unit NAND gate X6 is electrically connected to the output end of the fourth digital unit NAND gate X4, the second input end of the sixth digital unit NAND gate X6 is electrically connected to the output end of the seventh digital unit NAND gate X7, and the output end of the sixth digital unit NAND gate X6 is electrically connected to the first input end of the seventh digital unit NAND gate X7;

[0022] As a further solution of the present invention: the inverter module is an eighth digital unit inverter X8, the input end of the eighth digital unit inverter X8 is electrically connected to the output end of the seventh digital unit NAND gate X7, and the output end of the eighth digital unit inverter X8 serves as the signal output end of the common-mode noise reduction level shift circuit.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] 1. The present invention effectively suppresses dv / dt noise by setting a common-mode level shift circuit under high transient voltage, and effectively solves the logic error problem caused by noise coupling when the high-side ground VS quickly jumps from low voltage to high voltage.

[0025] 2. The circuit of the present invention has a low operating voltage. When the VBS voltage is constant, the negative voltage of the high-side ground VS can be as high as -10V. On the other hand, the common-mode level shift circuit proposed by the present invention has a low transmission delay and can operate under high frequency conditions, which is conducive to expanding the application scenarios of the common-mode level shift circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Circuit diagram for conventional high voltage pulse generation;

[0027] Figure 2 It is a module diagram of the common mode noise reduction level shift circuit of the present invention;

[0028] Figure 3 It is a structural diagram of a common-mode noise reduction level shift circuit unit of the present invention;

[0029] Figure 4 is a simulation circuit diagram of an embodiment of the present invention;

[0030] Figure 5 It is a normal working timing diagram of the present invention;

[0031] Figure 6 This is the working timing diagram of the present invention with dv / dt=200 / ns;

[0032] Figure 7 This is a timing diagram of the high side ground negative pressure operation of the present invention.

[0033] In the figure: 1. Common mode circuit module; 2. Voltage regulator module; 3. RC delay module; 4. Gate circuit module; 5. Trigger; 6. Inverter module. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] Example:

[0036] See also Figure 2-Figure 7 In an embodiment of the present invention, a common-mode noise reduction level shift circuit is provided. The common-mode noise reduction level shift circuit is used to suppress high transient (dv / dt) voltage noise. The common-mode noise reduction level shift circuit includes a common-mode circuit module 1, a voltage stabilization module 2, an RC delay module 3, a gate circuit module 4, a trigger 5 and an inverter module 6;

[0037] Among them, the common-mode circuit module 1 is used to filter the common-mode signal, and by filtering the common-mode signal, the electromagnetic interference of the level shift circuit can be reduced; the input end of the common-mode circuit module 1 is electrically connected to the output end of the voltage stabilizing module 2, and the voltage stabilizing module 2 is used to stabilize the input voltage of the common-mode circuit module 1, which is beneficial to improving the stability of the voltage of the input common-mode circuit module 1; the output end of the common-mode circuit module 1 is electrically connected to the input end of the RC delay module 3, and the RC delay module 3 is used for delaying signals and filtering; the output end of the RC delay module 3 is electrically connected to the input end of the gate circuit module 4, and the output end of the gate circuit module 4 is electrically connected to the input end of the trigger 5, and the output end of the trigger 5 is electrically connected to the input end of the inverter module 6, and the output end of the inverter module 6 serves as the high-voltage output signal end OUT, and the trigger 5 flips the stable state of the common-mode noise reduction level shift circuit by receiving the trigger signal.

[0038] Preferably, the common-mode circuit module 1 includes a first common-mode unit M1 and a second common-mode unit M2, the first common-mode unit M1 includes a first current source I1 and a second current source I2, the output end of the first current source I1 is electrically connected to the input end of the second current source I2, the second common-mode unit M2 includes a third current source I3 and a fourth current source I4, the output end of the third current source I3 is electrically connected to the input end of the fourth current source I4, and the output end of the fourth current source I4 forms a high-side ground VS.

[0039] Preferably, the voltage stabilizing module 2 includes a first switch unit, a first voltage stabilizing unit, a second switch unit and a second voltage stabilizing unit, one end of the first switch unit is electrically connected to the input end of the first voltage stabilizing unit, the output end of the first voltage stabilizing unit is electrically connected to the input end of the first common mode unit M1, one end of the second switch unit is electrically connected to the input end of the second voltage stabilizing unit, and the output end of the second voltage stabilizing unit is electrically connected to the input end of the second common mode unit M2.

[0040] Preferably, the first switch unit is a first NMOS transistor HN1, the first voltage stabilizing unit is a first voltage stabilizing diode D1, the second switch unit is a second NMOS transistor HN2, the second voltage stabilizing unit is a second voltage stabilizing diode D2, the gate of the first NMOS transistor HN1 receives the pulse signal Pulse_F, the source of the first NMOS transistor HN1 is grounded, the drain of the first NMOS transistor HN1 is electrically connected to the anode of the first voltage stabilizing diode D1, a connection end of the first common mode unit M1 and the second common mode unit M2, and forms a FA potential point at the connection intersection of the three, the cathode of the first voltage stabilizing diode D1 forms a high-side power supply point VB, and the FA potential point is used to control the current at the second current source I2 in the first common mode unit M1 and the current at the third current source I3 in the second common mode unit M2;

[0041] The cathode of the first voltage zener diode D1 is electrically connected to the input end of the first current source I1, the gate of the second NMOS tube HN2 is used to receive the pulse signal Pulse_R, the source of the second NMOS tube HN2 is grounded, and the drain of the second NMOS tube HN2 is electrically connected to the anode of the second voltage zener diode D2, a connection end of the first common mode unit M1 and the second common mode unit M2 to form an RA potential point at the connection intersection of the three, and the RA potential point is used to control the current at the first current source I1 in the first common mode unit M1 and the current at the fourth current source I4 in the second common mode unit M2.

[0042] Preferably, the first voltage stabilizing diode D1 and / or the second voltage stabilizing diode D2 is a Zener diode.

[0043] Preferably, the RC delay module 3 includes a first RC delay module, a second RC delay module, a first current detection unit, a second current detection unit, a third switch unit and a fourth switch unit, the first RC delay module and the third switch unit are respectively connected in parallel at both ends of the first common mode unit M1, the third switch unit and the input end of the first common mode unit M1 are connected with a first power supply unit, the second RC delay module and the fourth switch unit are respectively connected in parallel at both ends of the second common mode unit M2, and a second current detection unit is connected between one end of the fourth switch unit and the input end of the second common mode unit M2.

[0044] Preferably, the first RC delay module includes a first resistor R1 and a first capacitor C1 connected in parallel with both ends of the first resistor R1, the third switch unit is a first medium voltage / low voltage NMOS tube N1, the gate of the first medium voltage / low voltage NMOS tube N1 is electrically connected to one end of the first capacitor C1, the source of the first medium voltage / low voltage NMOS tube N1 is electrically connected to the output end of the second current source I2, the drain of the first medium voltage / low voltage NMOS tube N1 is electrically connected to the output end of the first power supply unit, and the first current detection unit is a fifth current source I5;

[0045] The second RC delay module includes a second resistor R2 and a second capacitor C2 connected in parallel with both ends of the second resistor R2. The fourth switch unit is a second medium voltage / low voltage NMOS tube N2. The gate of the second medium voltage / low voltage NMOS tube N2 is electrically connected to one end of the second capacitor C2. The source of the second medium voltage / low voltage NMOS tube N2 is electrically connected to the output end of the fourth current source I4. The drain of the second medium voltage / low voltage NMOS tube N2 is electrically connected to the output end of the second current detection unit. The second current detection unit is the sixth current source I6.

[0046] Preferably, the gate circuit module 4 includes a second digital unit inverter X2, a third digital unit inverter X3, a fourth digital unit NAND gate X4 and a fifth digital unit NAND gate X5, and the input end of the second digital unit inverter X2 is electrically connected to the first input end of the fifth digital unit NAND gate X5;

[0047] The output end of the second digital unit inverter X2 is electrically connected to the first input end of the fourth digital unit NAND gate X4, the second input end of the fourth digital unit NAND gate X4 is electrically connected to the input end of the third digital unit inverter X3, and the output end of the third digital unit inverter X3 is electrically connected to the second input end of the fifth digital unit NAND gate X5;

[0048] An input end of the second digital unit inverter X2 is electrically connected to the drain of the first medium voltage / low voltage NMOS transistor N1 , and an input end of the third digital unit inverter X3 is electrically connected to the drain of the second medium voltage / low voltage NMOS transistor N2 .

[0049] As a further solution of the present invention: the trigger 5 is an RS trigger, the trigger 5 includes a sixth digital unit NAND gate X6 and a seventh digital unit NAND gate X7, the first input end of the sixth digital unit NAND gate X6 is electrically connected to the output end of the fourth digital unit NAND gate X4, the second input end of the sixth digital unit NAND gate X6 is electrically connected to the output end of the seventh digital unit NAND gate X7, and the output end of the sixth digital unit NAND gate X6 is electrically connected to the first input end of the seventh digital unit NAND gate X7;

[0050] The inverter module 6 is an eighth digital unit inverter X8, the input end of the eighth digital unit inverter X8 is electrically connected to the output end of the seventh digital unit NAND gate X7, and the output end of the eighth digital unit inverter X8 serves as the signal output end of the common mode noise reduction level shift circuit.

[0051] In this embodiment, when the input signal IN is at a low level, the pulse signals Pulse_R and Pulse_F output a low level, and the first NMOS transistor HN1 and the second NMOS transistor HN2 are turned off. At this time, the signals at the RA potential point and the FA potential point are pulled to a high level VB by the first common mode unit M1 and the second common mode unit M2 circuits to form a high-side power point VB. Since the RA potential point and the FA potential point control the electrical signals at the second current source I2, the third current source I3 and the first current source I1, and the fourth current source I4, respectively, the first current source I1 and the second current source I2 in the first common mode unit M1 and the second common mode unit M2 in No current is generated at the third current source I3 and the fourth current source I4. In addition, since one end of the first resistor R1 and the second resistor R2 are connected to the high-side ground VS, the signals at RC and FC are pulled to VS, the first medium voltage / low voltage NMOS tube N1 and the second medium voltage / low voltage NMOS tube N2 are turned off, and the inputs of the second digital unit inverter X2 and the third digital unit inverter X3 are pulled to the high level VB by the fifth current source I5 and the sixth current source I6 respectively, and the RH and FH signals are high-level electrical signals respectively. Since the sixth digital unit NAND gate X6 and the seventh digital unit NAND gate X7 form an RS trigger, OUT outputs a low level.

[0052] When the input signal IN changes from a low level to a high level, the second pulse unit generates a Pulse_R high level signal to turn on the second NMOS transistor HN2, and the second NMOS transistor HN2 is turned on.

[0053] Since the pulse signal Pulse_F is at a low level at this time, the FA signal is pulled to a high level VB by the first common mode unit M1, the second current source I2 and the third current source I3 do not generate current, and the FC signal is pulled to a low level by the second resistor R2. Since the second NMOS tube HN2 is turned on, the RA signal is pulled to a low level (the low level is the VB voltage minus the voltage stabilization value of the second voltage stabilizing diode D2), and at this time the first current source I1 generates a pull-up current, and the fourth current source I4 generates a pull-down current. The pull-down current of the fourth current source I4 continues to pull FC to a low level, the second medium voltage / low voltage NMOS tube N2 continues to be turned off, and the input of the third digital unit inverter X3 continues to be pulled to a high level VB by the sixth current source I6; the first current source I1 generates a pull-up current, and the first current source I 1 charges the first capacitor C1, and the voltage of the RC signal gradually increases. When the charging voltage of the RC signal is greater than the threshold voltage of the first medium voltage / low voltage NMOS tube N1, the first medium voltage / low voltage NMOS tube N1 is turned on, and the input end of the second digital unit inverter X2 is pulled to a low level. Since the input end of the third digital unit inverter X3 is at a high level, the FH signal is at a high level. At this time, the RH signal outputs a low level, the seventh digital unit NAND gate X7 outputs a low level, OUT outputs a high level, and the output is turned on.

[0054] When the pulse signal Pulse_R changes from a high level to a low level, the second NMOS tube HN2 is turned off, the RA signal is gradually pulled to a high level VB by the second common mode unit M2 circuit, the first current source I1 and the fourth current source I4 generate no current, the RC signal is gradually discharged to a low level through the first resistor R1, the first medium voltage / low voltage NMOS tube N1 is turned off, the input end of the second digital unit inverter X2 is pulled to a high level by the fifth current source I5, and RH outputs a high level. Since the seventh digital unit NAND gate X7 outputs a low level at the previous moment and the sixth digital unit NAND gate X6 and the seventh digital unit NAND gate X7 form an RS trigger, the seventh digital unit NAND gate X7 continues to output a low level, and the OUT output maintains a high level.

[0055] When the input signal IN changes from a high level to a low level, the pulse first unit generates a Pulse_F high level signal to turn on the first NMOS tube HN1, and the first NMOS tube HN1 is turned on. Since Pulse_R is a low level at this time, the RA signal is pulled to a high level VB by the second common mode unit M2 circuit, the first current source I1 and the fourth current source I4 have no current generated, and the RC signal is pulled to a low level by the first resistor R1.

[0056] Since the first NMOS transistor HN1 is turned on, the FA signal is pulled to a low level (the low level is the VB voltage minus the voltage regulation value of the Zener transistor D1). At this time, the third current source I3 generates a pull-up current, and the second current source I2 generates a pull-down current. The pull-down current of the second current source I2 continues to pull RC to a low level, and the first medium voltage / low voltage NMOS transistor N1 continues to be turned off. The input of the second digital unit inverter X2 is continued to be pulled to a high level VB by the fifth current source I5; the third current source I3 generates a pull-up current, and the pull-up current of the third current source I3 is given to the second current source I3. The capacitor C2 is charged, and the voltage of the FC signal gradually increases. When the charging voltage of the FC signal is greater than the threshold voltage of the second medium voltage / low voltage NMOS tube N2, the second medium voltage / low voltage NMOS tube N2 is turned on, and the input end of the third digital unit inverter X3 is pulled to a low level. Since the input end of the second digital unit inverter X2 is at a high level, the RH signal is at a high level. At this time, the FH signal outputs a low level, the seventh digital unit NAND gate X7 outputs a high level, the sixth digital unit NAND gate X6 outputs a low level, OUT outputs a low level, and the output is turned off.

[0057] When the pulse signal Pulse_F changes from a high level to a low level, the first NMOS tube HN1 is turned off, the FA signal is gradually pulled to a high level VB by the first common mode unit M1 circuit, the second current source I2 and the third current source I3 generate no current, the FC signal is gradually discharged to a low level through the second resistor R2, the second medium voltage / low voltage NMOS tube N2 is turned off, the input end of the third digital unit inverter X3 is pulled to a high level by the fourth resistor R4, and FH outputs a high level. Since the sixth digital unit NAND gate X6 outputs a low level at the previous moment and the sixth digital unit NAND gate X6 and the seventh digital unit NAND gate X7 form an RS trigger, the seventh digital unit NAND gate X7 continues to output a high level, and the OUT output maintains a low level.

[0058] By changing the circuit parameters in the first common-mode unit M1 and the second common-mode unit M2 , the charging current and the transmission delay of the first capacitor C1 and the second capacitor C2 can be adjusted.

[0059] like Figure 5-Figure 6 As shown, from Figure 6 It can be seen from the circuit simulation waveform that the high-side ground VS signal jumps from 0V to 200V in 1ns, the logic signal has no errors, and the OUT output has no abnormal phenomena, indicating that this common-mode noise reduction level shift circuit architecture has high dv / dt capability.

[0060] like Figure 7 As shown, from Figure 7 It can be seen from the circuit simulation waveform that when the voltage of VBS is constant, the working negative voltage of VS can be as high as -10V.

[0061] In summary, this high transient voltage common-mode noise reduction level shift circuit architecture has a strong ability to suppress dv / dt noise, and can effectively solve the logic error problem caused by noise coupling when the high-side ground VS quickly jumps from low voltage to high voltage; it has a low operating voltage, and when the VBS voltage is constant, the negative voltage of the high-side ground VS can be as high as -10V; the transmission delay is low, and it can work under high frequency conditions.

[0062] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A common mode noise reduction level shifting circuit, characterized in that: The common-mode noise reduction level shifting circuit is used to suppress high transient voltage noise, and the common-mode noise reduction level shifting circuit comprises: A common mode circuit module, the common mode circuit module is used to filter the common mode signal, the common mode circuit module includes a first common mode unit and a second common mode unit, the first common mode unit includes a first current source and a second current source, the output end of the first current source is electrically connected to the input end of the second current source, the second common mode unit includes a third current source and a fourth current source, the output end of the third current source is electrically connected to the input end of the fourth current source, and the output end of the fourth current source forms a high-side ground VS; A voltage stabilizing module, wherein the input end of the common mode circuit module is electrically connected to the output end of the voltage stabilizing module, and the voltage stabilizing module is used to stabilize the input end voltage of the common mode circuit module; An RC delay circuit module, wherein the output end of the common mode circuit module is electrically connected to the input end of the RC delay circuit module, and the RC delay circuit module is used for signal delay and filtering; A gate circuit module, wherein the output end of the RC delay circuit module is electrically connected to the input end of the gate circuit module; A trigger, the output end of the gate circuit module is electrically connected to the input end of the trigger, the output end of the trigger is electrically connected to the inverter module, the output end of the inverter serves as the high-voltage output signal end OUT, and the trigger flips the stable state of the common-mode noise reduction level shift circuit by receiving a trigger signal.

2. The common mode noise reduction level shifting circuit according to claim 1, characterized in that: The voltage stabilizing module includes a first switch unit, a first voltage stabilizing unit, a second switch unit and a second voltage stabilizing unit, one end of the first switch unit is electrically connected to the input end of the first voltage stabilizing unit, the output end of the first voltage stabilizing unit is electrically connected to the input end of the first common mode unit, one end of the second switch unit is electrically connected to the input end of the second voltage stabilizing unit, and the output end of the second voltage stabilizing unit is electrically connected to the input end of the second common mode unit.

3. The common mode noise reduction level shifting circuit according to claim 2, characterized in that: The first switch unit is a first NMOS tube, the first voltage stabilizing unit is a first voltage stabilizing diode, the second switch unit is a second NMOS tube, the second voltage stabilizing unit is a second voltage stabilizing diode, the gate of the first NMOS tube receives the pulse signal Pulse_F, the source of the first NMOS tube is grounded, the drain of the first NMOS tube is electrically connected to the anode of the first voltage stabilizing diode, a connection end of the first common mode unit M1 and the second common mode unit M2, and forms a potential point FA at the connection intersection of the three, and the cathode of the first voltage stabilizing diode forms a high-side power supply point VB; The cathode of the first zener diode is electrically connected to the input end of the first current source, the gate of the second NMOS tube is used to receive the pulse signal Pulse_R, the source of the second NMOS tube is grounded, and the drain of the second NMOS tube is electrically connected to the anode of the second zener diode, a connection end of the first common mode unit M1 and the second common mode unit M2 to form an RA potential point at the connection intersection of the three.

4. The common mode noise reduction level shifting circuit according to claim 3, characterized in that: The first voltage stabilizing diode and / or the second voltage stabilizing diode is a Zener diode.

5. The common mode noise reduction level shifting circuit according to claim 4, characterized in that: The RC delay circuit module includes a first RC delay module, a second RC delay module, a first current detection unit, a second current detection unit, a third switch unit and a fourth switch unit. The first RC delay module and the third switch unit are respectively connected in parallel at both ends of the first common mode unit, the third switch unit and the input end of the first common mode unit are connected with the first current detection unit, the second RC delay module and the fourth switch unit are respectively connected in parallel at both ends of the second common mode unit, and the second current detection unit is connected between one end of the fourth switch unit and the input end of the second common mode unit.

6. The common mode noise reduction level shifting circuit according to claim 5, characterized in that: The first RC delay module includes a first resistor and a first capacitor connected in parallel with both ends of the first resistor, the third switch unit is a first medium voltage / low voltage NMOS tube, the gate of the first medium voltage / low voltage NMOS tube is electrically connected to one end of the first capacitor, the source of the first medium voltage / low voltage NMOS tube is electrically connected to the output end of the second current source, the drain of the first medium voltage / low voltage NMOS tube is electrically connected to the output end of the first current detection unit, and the first current detection unit is a fifth current source; The second RC delay module includes a second resistor and a second capacitor connected in parallel with both ends of the second resistor, the fourth switch unit is a second medium voltage / low voltage NMOS tube, the gate of the second medium voltage / low voltage NMOS tube is electrically connected to one end of the second capacitor, the source of the second medium voltage / low voltage NMOS tube is electrically connected to the output end of the fourth current source, the drain of the second medium voltage / low voltage NMOS tube is electrically connected to the output end of the second current detection unit, and the second power supply unit is a sixth current source.

7. The common mode noise reduction level shifting circuit according to claim 6, characterized in that: The gate circuit module includes a second digital unit inverter, a third digital unit inverter, a fourth digital unit NAND gate and a fifth digital unit NAND gate, and the input end of the second digital unit inverter is electrically connected to the first input end of the fifth digital unit NAND gate; The output end of the second digital unit inverter is electrically connected to the first input end of the fourth digital unit NAND gate, the second input end of the fourth digital unit NAND gate is electrically connected to the input end of the third digital unit inverter, and the output end of the third digital unit inverter is electrically connected to the second input end of the fifth digital unit NAND gate; The input end of the second digital unit inverter is electrically connected to the drain of the first medium voltage / low voltage NMOS tube, and the input end of the third digital unit inverter is electrically connected to the drain of the second medium voltage / low voltage NMOS tube.

8. The common mode noise reduction level shifting circuit according to claim 1, characterized in that: The trigger is an RS trigger, which includes a sixth digital unit NAND gate and a seventh digital unit NAND gate, wherein the first input end of the sixth digital unit NAND gate is electrically connected to the output end of the fourth digital unit NAND gate, the second input end of the sixth digital unit NAND gate is electrically connected to the output end of the seventh digital unit NAND gate, and the output end of the sixth digital unit NAND gate is electrically connected to the first input end of the seventh digital unit NAND gate.

9. The common mode noise reduction level shifting circuit according to claim 8, characterized in that: The inverter module is an eighth digital unit inverter, the input end of the eighth digital unit inverter is electrically connected to the output end of the seventh digital unit NAND gate, and the output end of the eighth digital unit inverter serves as the signal output end of the common mode noise reduction level shift circuit.

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