Clock feedthrough elimination circuit applied to decision feedback equalizer
The problem of clock feedthrough interference is solved by using capacitively coupled clock signals in the latch of the decision feedback equalizer and an amplifier with opposite polarity in the amplifier compensation branch, and improving the signal quality of the system.
Patent Information
- Application Number
- CN202410520938.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-28
- Publication Date
- 2025-02-28
AI Technical Summary
It is judged that there is clock feedthrough interference in the feedback equalizer, resulting in interference at the latch and amplifier output, affecting the normal operation of the system.
A clock feed-through cancellation circuit is designed to cancel the clock feed-through interference by coupling the clock signal to the output using two capacitors in the latch and using an amplifier with the same structure but opposite output polarity in the amplifier compensation branch.
It effectively reduces the clock feedthrough interference of the latch, thereby reducing interference at the amplifier output, and improving the signal quality of the system.
Smart Images
Figure CN119543914A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuits, and in particular to a clock feedthrough elimination circuit applied to a decision feedback equalizer. Background Art
[0002] Decision Feedback Equalizer (DFE) is a technique used in digital communication systems to mitigate the effects of inter-symbol interference (ISI). ISI occurs when symbols sent in a digital communication system interfere with each other due to channel characteristics, causing errors in the received signal. DFE is often used in communication systems with severe ISI, such as systems with multipath propagation or high data rates. The basic idea of DFE is to use the feedback of previously detected symbols to cancel the interference of subsequent symbols, thereby improving the accuracy of symbol detection. When the clock signal passes through the circuit, it may cause a response from some nonlinear elements in the DFE circuit, or cause unexpected changes in other signals through the signal lines in the DFE circuit. This may cause components of the clock signal to appear on non-clock signals, thereby interfering with other parts of the system, that is, generating clock feedthrough. Summary of the invention
[0003] The purpose of the present application is to provide a clock feedthrough elimination circuit applied to a decision feedback equalizer, which can reduce the clock feedthrough interference of the latch in the decision feedback equalizer, thereby reducing the interference at the output end of the amplifier.
[0004] The present application discloses a clock feedthrough elimination circuit applied to a decision feedback equalizer, comprising:
[0005] A latch, the latch comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, a first inverter, a second inverter, a third inverter and a fourth inverter, wherein: sources of the first transistor and the second transistor are both connected to a voltage source, a drain of the first transistor, a drain of the third transistor, an input terminal of the third inverter, an output terminal of the fourth inverter and one terminal of the first capacitor are connected to a first node, a drain of the second transistor, a drain of the fourth transistor, an output terminal of the third inverter, an input terminal of the fourth inverter and one terminal of the second capacitor are connected to a second node, the other terminal of the first capacitor and the other terminal of the second capacitor are both coupled to a clock signal, a gate of the first transistor and an input terminal of the second inverter are connected to a first comparison signal, a gate of the second transistor and an input terminal of the first inverter are connected to a second comparison signal, and a source of the third transistor and a source of the fourth transistor are both connected to a ground terminal; and
[0006] An amplifier, the amplifier comprising a first resistor, a second resistor, a fifth transistor, a sixth transistor and a first current source, one end of the first resistor and one end of the second resistor are connected to the voltage source, the other end of the first resistor is connected to the drain of the fifth transistor and outputs a first amplified signal, the gate of the fifth transistor is connected to the first node, the other end of the second resistor is connected to the drain of the sixth transistor and outputs a second amplified signal, the gate of the sixth transistor is connected to the second node, and the source of the fifth transistor and the source of the sixth transistor are both connected to the first current source.
[0007] In a preferred example, when the clock signal is at a high level, the first node and the second node of the latch output the first latch signal and the second latch signal of high level and low level respectively, and the amplifier outputs the first amplified signal and the second amplified signal of high level and low level respectively according to the first latch signal and the second latch signal; when the clock signal is at a low level, the first node and the second node of the latch both output the first latch signal and the second latch signal of high level, the first amplified signal and the second amplified signal output by the amplifier remain unchanged, the first capacitor is used to offset the upward disturbance in the first amplified signal, and the second capacitor is used to offset the upward disturbance in the second amplified signal.
[0008] In a preferred example, it also includes: an amplifier compensation branch, the amplifier compensation branch includes a seventh transistor, an eighth transistor and a second current source, the drain of the seventh transistor is connected to the other end of the second resistor, the gate of the seventh transistor is connected to the second node, the drain of the eighth transistor is connected to the other end of the first resistor, the gate of the eighth transistor is connected to the first node, and the source of the seventh transistor and the source of the eighth transistor are both connected to the second current source.
[0009] In a preferred example, the amplifier compensation branch is used to offset the upper and lower disturbances in the first amplified signal and the second amplified signal.
[0010] In a preferred embodiment, the device further comprises: a comparator, wherein the comparator comprises a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor and a seventeenth transistor, wherein:
[0011] The sources of the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor are all connected to the voltage source, the gates of the ninth transistor, the twelfth transistor and the seventeenth transistor are all coupled to the clock signal, the drain of the ninth transistor, the drain of the tenth transistor, the drain of the thirteenth transistor, the gate of the eleventh transistor and the gate of the twelfth transistor are connected and output the second comparison signal, the drain of the eleventh transistor, the drain of the twelfth transistor, the drain of the fourteenth transistor, the gate of the tenth transistor and the gate of the thirteenth transistor are connected and output the first comparison signal, the source of the thirteenth transistor is connected to the drain of the fifteenth transistor, the gate of the fifteenth transistor is coupled to the positive phase input signal, the source of the fourteenth transistor is connected to the drain of the sixteenth transistor, the gate of the sixteenth transistor is coupled to the negative phase input signal, the sources of the fifteenth transistor and the sixteenth transistor are all connected to the drain of the seventeenth transistor, and the source of the seventeenth transistor is connected to the ground terminal.
[0012] In a preferred example, the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor are all PMOS transistors, and the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor and the seventeenth transistor are all NMOS transistors.
[0013] In a preferred example, the first transistor and the second transistor are both PMOS transistors, and the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all NMOS transistors.
[0014] In the implementation manner of the present application, the clock signal is coupled to the output of the latch through two capacitors. When the clock signal changes from a high level to a low level, it will be coupled to the output of the latch, reducing the clock feedthrough interference of the latch and thereby reducing the interference at the output end of the amplifier.
[0015] Furthermore, through an amplifier compensation branch with the same structure, the same input signal but opposite output polarity, when clock feedthrough interference occurs at the amplifier input, the two groups of amplifiers will generate interference signals of the same magnitude but opposite polarity, thereby canceling each other out and reducing interference.
[0016] The specification of the present application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of the present application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of the present application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been recorded because it is technically infeasible, and the solution of A+B+C+E should be regarded as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 It is a structural schematic diagram of a clock feedthrough elimination circuit applied to a decision feedback equalizer according to an embodiment of the present application.
[0018] Figure 2 It is a schematic diagram of the structure of a comparator according to an embodiment of the present application.
[0019] Figure 3 It is a schematic diagram of the structure of a traditional decision feedback equalizer.
[0020] Figure 4 A timing diagram of a clock feedthrough elimination circuit applied to a decision feedback equalizer according to an embodiment of the present application. DETAILED DESCRIPTION
[0021] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.
[0022] Description of some concepts:
[0023] Clock Feedthrough: In digital circuits, changes in the clock signal (clock) at the input port produce an unexpected response on the non-clock signal output port in the circuit. This unexpected response may cause the clock signal to appear on the non-clock signal, thereby affecting the normal operation of the system. Clock feedthrough is usually caused by coupling or incomplete isolation in the circuit. The existence of clock feedthrough is an important consideration for the design and analysis of digital circuits, especially in high-speed digital systems, where the frequency and amplitude of the clock signal are high, which is more likely to cause unexpected effects. Therefore, it is crucial for designers of digital circuits to understand and manage clock feedthrough.
[0024] Latch: Used to store and maintain the state of an input signal at a specific moment, and is typically used in applications such as data storage, signal synchronization, and timing control.
[0025] Amplifier: An electronic device or circuit used to increase the amplitude, voltage, current or power of an input signal and produce a similar but amplified output signal.
[0026] Comparator: Used to compare two input signals and generate an output signal, indicating which input signal has a higher voltage. It is usually used in digital and analog circuits to perform various comparison and decision-making functions.
[0027] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.
[0028] One embodiment of the present application relates to a clock feedthrough elimination circuit applied to a decision feedback equalizer, and its structure is as follows: Figure 1 As shown, the structure includes a latch 101, a CML amplifier 102 and a CML amplifier compensation branch 103. The latch 101, the amplifier 102 and the amplifier compensation branch 103 are coupled in sequence. The latch 101 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, a second capacitor C2, a first inverter INV1, a second inverter INV2, a third inverter INV3 and a fourth inverter INV4. The CML amplifier 102 includes a first resistor R1, a second resistor R2, a fifth transistor M5, a sixth transistor M6 and a first current source Itap.
[0029] In one embodiment, the source of the first transistor M1 and the source of the second transistor M2 are both connected to the voltage source VDD, and the drain of the first transistor M1, the drain of the third transistor M3, the input of the third inverter INV3, the output of the fourth inverter INV4, and one end of the first capacitor C1 are connected to the first node S1. The drain of the second transistor M2, the drain of the fourth transistor M4, the output of the third inverter INV3, the input of the fourth inverter INV4, and one end of the second capacitor C2 are connected to the second node S2. The other end of the first capacitor C1 and the other end of the second capacitor C2 are both coupled to the clock signal CLK. The gate of the first transistor M1 and the input of the second inverter INV2 are connected to the first comparison signal TP. The gate of the second transistor M2 and the input of the first inverter INV1 are connected to the second comparison signal TN. The source of the third transistor M3 and the source of the fourth transistor M4 are both connected to the ground terminal. The latch 101 obtains a first latch signal TP2 at a first node S1 and a second latch signal TN2 at a second node S2 according to the clock signal CLK, the first comparison signal TP and the second comparison signal TN.
[0030] In one embodiment, the first transistor M1 and the second transistor M2 are both PMOS transistors.
[0031] In one embodiment, the CML amplifier 102 includes a first resistor R1, a second resistor R2, a fifth transistor M5, a sixth transistor M6, and a first current source Itap. One end of the first resistor R1 and one end of the second resistor R2 are connected to a voltage source VDD, and the other end of the first resistor R1 is connected to the drain of the fifth transistor M5 and outputs a first amplified signal OP. The gate of the fifth transistor M5 is connected to a first node S1, and the other end of the second resistor R2 is connected to the drain of the sixth transistor M6 and outputs a second amplified signal ON. The gate of the sixth transistor M6 is connected to a second node S2. The source of the fifth transistor M5 and the source of the sixth transistor M6 are both connected to the first current source Itap.
[0032] In one embodiment, the fifth transistor M5 and the sixth transistor M6 are both NMOS transistors.
[0033] In one embodiment, when the clock signal CLK is at a high level, the first node S1 of the latch 101 outputs a first latch signal TP2 at a high level, and the second node S2 outputs a second latch signal TN2 at a low level, and the amplifier 102 outputs a first amplified signal OP at a high level and a second amplified signal ON at a low level according to the first latch signal TP2 and the second latch signal TN2. When the clock signal CLK is at a low level, the first node S1 and the second node S2 of the latch 101 output the first latch signal TP2 and the second latch signal TN2 at a high level, respectively, and the first amplified signal OP and the second amplified signal ON output by the amplifier 102 remain unchanged. It should be understood that the first capacitor C1 can be used to offset the upward disturbance in the first amplified signal OP, and the second capacitor C2 can be used to offset the upward disturbance in the second amplified signal ON, thereby reducing the clock feedthrough interference of the latch. Specifically, the first capacitor C1 and the second capacitor C2 couple the clock signal CLK to the output of the latch 101 . When the clock signal CLK changes from high to low, it will couple to the output of the latch 101 , reducing the clock feedthrough interference of the latch, thereby reducing the interference at the output of the CML amplifier 102 .
[0034] In one embodiment, the amplifier compensation branch 103 of the clock feedthrough elimination circuit includes a seventh transistor M7, an eighth transistor M8 and a second current source Ic, the drain of the seventh transistor M7 is connected to the other end of the second resistor R2, the gate of the seventh transistor M7 is connected to the second node S2, the drain of the eighth transistor M8 is connected to the other end of the first resistor R1, the gate of the eighth transistor M8 is connected to the first node S1, and the source of the seventh transistor M7 and the source of the eighth transistor M8 are both connected to the second current source Ic. In one embodiment, the amplifier compensation branch 103 can be used to offset the upper and lower disturbances in the first amplified signal OP and the second amplified signal ON. It should be noted that the input signals of the CML amplifier compensation branch 103 and the CML amplifier 102 are the same but the output polarities are opposite. When clock feedthrough interference occurs at the input of the amplifier, the two groups of CML amplifiers will generate interference signals of the same magnitude but opposite polarities, thereby offsetting each other and reducing interference.
[0035] In one embodiment, the seventh transistor M7 and the eighth transistor M8 are both NMOS transistors.
[0036] refer to Figure 2As shown, the clock feedthrough elimination circuit further includes a comparator 104, which is used to generate a comparison result according to the differential input signal, and obtain a first comparison signal TP and a second comparison signal TN to the latch 101. Specifically, the comparator includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17.
[0037] In one embodiment, the sources of the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are all connected to the voltage source VDD, the gates of the ninth transistor M9, the twelfth transistor M12, and the seventeenth transistor M17 are all coupled to the clock signal CLK, the drain of the ninth transistor M9, the drain of the tenth transistor M10, the drain of the thirteenth transistor M13, the gate of the eleventh transistor M11, and the gate of the twelfth transistor M12 are connected and output the second comparison signal TN, the drain of the eleventh transistor M11, the drain of the twelfth transistor M12, the fourteenth transistor M17 are connected to the clock signal CLK, and the gates of the eleventh transistor M11, the twelfth transistor M12, and the fourteenth transistor M17 are connected to the clock signal CLK. The drain of M14, the gate of the tenth transistor M11 and the gate of the thirteenth transistor M13 are connected and output the first comparison signal TP, the source of the thirteenth transistor M13 is connected to the drain of the fifteenth transistor M15, the gate of the fifteenth transistor M15 is coupled to the positive phase input signal INP, the source of the fourteenth transistor M14 is connected to the drain of the sixteenth transistor M16, the gate of the sixteenth transistor M16 is coupled to the negative phase input signal INN, the sources of the fifteenth transistor M15 and the sixteenth transistor M16 are both connected to the drain of the seventeenth transistor M17, and the source of the seventeenth transistor M17 is connected to the ground.
[0038] In one embodiment, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11 and the twelfth transistor M12 are all PMOS transistors, and the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16 and the seventeenth transistor M17 are all NMOS transistors.
[0039] like Figure 3 The figure shows the common data latch and tap module in the decision feedback equalizer. The comparator on the far left is responsible for amplifying the differential input signal and converting it into a full-swing digital signal output, which is latched by the latch in the middle and drives the CML amplifier on the far right.
[0040] like Figure 4 Shown Figure 3The working waveform of the circuit in the figure shows that when the high level of the clock signal CLK arrives, the comparator will compare the signal size of the differential input signal INP / INN and output the digital comparison signal TP / TN. When the low level of the clock signal CLK arrives, the digital comparison signal TP / TN will be reset to a high level at the same time, but at this time, the latch will maintain the current level to maintain the input signal level of the right CML amplifier unchanged. When the high level of the clock signal CLK arrives next time, the previous working process will be repeated, but this structure has a problem of clock feedthrough. When the clock signal changes from high to low, the digital comparison signal TP / TN will become a high level at the same time, and the signal change of the digital comparison signal TP / TN will be coupled to the output terminal TP2 / TN2 through the parasitic capacitance of PM1 / PM2, and coupled to the output OP / ON of the amplifier through the parasitic capacitance of the input MOS tube of the CML amplifier, causing periodic disturbances and affecting the signal quality of the amplifier.
[0041] The present invention reduces this interference by two methods. The first method is to use two capacitors (such as Figure 1 The first capacitor C1 and the second capacitor C2 shown in FIG. 1 couple the clock signal CLK to the output of the latch 101. When the clock signal CLK changes from high to low, it will be coupled to the output of the latch 101, reducing the clock feedthrough interference of the latch, thereby reducing the interference at the output of the CML amplifier 102. The second method uses a CML amplifier with the same structure, the same input signal but opposite output polarity (i.e. Figure 1 The amplifier compensation branch 103 shown in FIG. 1 is used to compensate for the interference of the amplifier. When clock feedthrough interference occurs at the input of the amplifier, the two groups of CML amplifiers will generate interference signals of the same magnitude but opposite polarity, thereby canceling each other out and reducing interference. Figure 4 It can be seen that the interference on the amplified signal waveform with the clock feedthrough elimination circuit is greatly reduced.
[0042] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.
[0043] The term "coupled to" and its derivatives may be used herein. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.
[0044] This specification includes combinations of the various embodiments described herein. Individual references to an embodiment (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated as mutually exclusive or it is clear to a person skilled in the art that they are mutually exclusive. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.
[0045] All documents mentioned in this specification are considered to be included in the disclosure of this application as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.
Claims
1. A clock feedthrough elimination circuit for a decision feedback equalizer, characterized in that: include: A latch, the latch comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, a first inverter, a second inverter, a third inverter and a fourth inverter, wherein: the sources of the first transistor and the second transistor are both connected to a voltage source, the drain of the first transistor, the drain of the third transistor, the input end of the third inverter, the output end of the fourth inverter and one end of the first capacitor are connected to a first node, the drain of the second transistor, the drain of the fourth transistor, the output end of the third inverter, the input end of the fourth inverter and one end of the second capacitor are connected to a second node, the other end of the first capacitor and the other end of the second capacitor are both coupled to a clock signal, the gate of the first transistor and the input end of the second inverter are connected to a first comparison signal, the gate of the second transistor and the input end of the first inverter are connected to a second comparison signal, and the source of the third transistor and the source of the fourth transistor are both connected to a ground terminal; as well as An amplifier, the amplifier comprising a first resistor, a second resistor, a fifth transistor, a sixth transistor and a first current source, one end of the first resistor and one end of the second resistor are connected to the voltage source, the other end of the first resistor is connected to the drain of the fifth transistor and outputs a first amplified signal, the gate of the fifth transistor is connected to the first node, the other end of the second resistor is connected to the drain of the sixth transistor and outputs a second amplified signal, the gate of the sixth transistor is connected to the second node, and the source of the fifth transistor and the source of the sixth transistor are both connected to the first current source.
2. The clock feedthrough elimination circuit according to claim 1, characterized in that: When the clock signal is at a high level, the first node and the second node of the latch output the first latch signal and the second latch signal of high level and low level respectively, and the amplifier outputs the first amplified signal and the second amplified signal of high level and low level respectively according to the first latch signal and the second latch signal; when the clock signal is at a low level, the first node and the second node of the latch both output the first latch signal and the second latch signal of high level, the first amplified signal and the second amplified signal output by the amplifier remain unchanged, the first capacitor is used to offset the upward disturbance in the first amplified signal, and the second capacitor is used to offset the upward disturbance in the second amplified signal.
3. The clock feedthrough elimination circuit according to claim 2, characterized in that: Also includes: An amplifier compensation branch, the amplifier compensation branch comprising a seventh transistor, an eighth transistor and a second current source, the drain of the seventh transistor being connected to the other end of the second resistor, the gate of the seventh transistor being connected to the second node, the drain of the eighth transistor being connected to the other end of the first resistor, the gate of the eighth transistor being connected to the first node, and the source of the seventh transistor and the source of the eighth transistor being both connected to the second current source.
4. The clock feedthrough elimination circuit according to claim 3, characterized in that: The amplifier compensation branch is used to offset the upper and lower disturbances in the first amplified signal and the second amplified signal.
5. The clock feedthrough elimination circuit according to claim 1, characterized in that: Also includes: A comparator, the comparator comprising a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor and a seventeenth transistor, wherein: The sources of the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor are all connected to the voltage source, the gates of the ninth transistor, the twelfth transistor and the seventeenth transistor are all coupled to the clock signal, the drain of the ninth transistor, the drain of the tenth transistor, the drain of the thirteenth transistor, the gate of the eleventh transistor and the gate of the twelfth transistor are connected and output the second comparison signal, the drain of the eleventh transistor, the drain of the twelfth transistor, the drain of the fourteenth transistor, the gate of the tenth transistor and the gate of the thirteenth transistor are connected and output the first comparison signal, the source of the thirteenth transistor is connected to the drain of the fifteenth transistor, the gate of the fifteenth transistor is coupled to the positive phase input signal, the source of the fourteenth transistor is connected to the drain of the sixteenth transistor, the gate of the sixteenth transistor is coupled to the negative phase input signal, the sources of the fifteenth transistor and the sixteenth transistor are all connected to the drain of the seventeenth transistor, and the source of the seventeenth transistor is connected to the ground terminal.
6. The clock feedthrough elimination circuit according to claim 5, characterized in that: The ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor are all PMOS transistors, and the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor and the seventeenth transistor are all NMOS transistors.
7. The clock feedthrough elimination circuit according to claim 1, characterized in that: The first transistor and the second transistor are both PMOS transistors, and the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all NMOS transistors.