A low noise differential sampling phase-locked loop system and method with high linearity sampling

Abstract

The application provides a low-noise differential sampling phase-locked loop system and method with high linear sampling, which comprises at least a single-to-dual circuit, a differential sampling phase detector, a voltage offsetter and a multiphase clock generation circuit. The single-to-dual circuit converts an input single-ended reference signal into a differential reference signal. The differential reference signal is input into the differential sampling phase detector. The voltage offsetter provides an offset voltage for the differential sampling phase detector. The multiphase clock generation circuit is used to generate three-phase non-overlapping clocks as a sampling clock of the differential sampling phase detector, an offset control clock of the voltage offsetter and a hold clock of the voltage offsetter. The method is based on the above system. By presetting whether the multiphase clock generation circuit enables the digital clock, adjusting the proportion of the offset capacitor of the voltage offsetter in the total sampling capacitor, and allowing the voltage offsetter to flexibly generate different offset voltages, the application effectively alleviates the phase noise deterioration caused by the current source thermal noise injection and improves the sampling voltage linearity.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of radio frequency integrated circuit design, and in particular to a low-noise differential sampling phase-locked loop system and method with high linear sampling. BACKGROUND

[0002] The statements in this section merely provide background information related to the present disclosure and do not necessarily constitute the prior art.

[0003] A phase-locked loop frequency synthesizer (PLL) is mainly used to generate a stable and accurate output frequency, and is usually used to synchronize the frequency of an input signal with the frequency of a reference signal. The basic principle is to compare the phase difference between the input signal and the reference signal, and to adjust the frequency of the output signal through feedback control, so that it remains in phase synchronization with the reference signal.

[0004] As a core module of wireless communication and internal clock, with the demand for low voltage, low power consumption and high integration, a phase-locked loop with pure spectrum, high frequency resolution, wide output frequency coverage and fast locking has become a bottleneck restricting the overall performance of integrated wireless communication. Therefore, it is of great significance to study a high-performance phase-locked loop system. The urgent demand for high-performance phase-locked loops in wireless communication has given rise to the research and development of several new types of phase-locked loop circuit structures.

[0005] Traditional phase-locked loops usually need to have the same sampling rate as the input signal to achieve accurate phase detection and frequency synthesis. As one of the types of phase-locked loops, a subsampling phase-locked loop (SSPLL) operates at a lower rate than the input signal sampling rate. The basic principle is to use the high-frequency components of the input signal, obtain a low-frequency signal after subsampling, and then perform phase-locked operation on the low-frequency signal. Therefore, the subsampling phase-locked loop greatly suppresses the in-band phase noise with high phase detection gain and no frequency divider power consumption, but the phase detection gain is less robust to process, power voltage and temperature changes and is difficult to calibrate. Therefore, the frequency divider circuit in the main loop of the sampling phase-locked loop is retained in the traditional phase-locked loop circuit, which can ensure the accuracy and programmability of the phase detection gain while achieving high phase detection gain.

[0006] However, the voltage sampling type phase detector has poor linearity, and the high-frequency quantization noise aliasing in fractional mode causes phase noise and spurious performance to deteriorate; although the charge-discharge type sampling phase detector can greatly improve the linearity and avoid high-frequency quantization noise aliasing in fractional mode, its working range is limited and introduces current source thermal noise dominant phase detector phase noise.

[0007] In addition, the existing single-ended sampling phase-locked loop is very sensitive to common-mode noise caused by power supply noise and buffer. Differential sampling can naturally resist common-mode noise, but the charging and discharging type sampling phase discriminator has a narrow working range and does not support differential working mode. SUMMARY

[0008] The present application aims to provide a low-noise differential sampling phase-locked loop system and method with high linear sampling. By presetting whether the digital clock of the multi-phase clock generation circuit is enabled, the proportion of the offset capacitor of the voltage offset device in the total sampling capacitor is adjusted, so that the voltage offset device can flexibly generate different offset voltages, and then generate different current source conduction times, effectively alleviating the phase noise deterioration caused by current source thermal noise injection and improving the sampling voltage linearity. The differential sampling phase discriminator can be configured in differential mode, thereby further suppressing in-band noise by two times of phase discrimination gain, and the system has good common-mode disturbance resistance.

[0009] The technical solutions for achieving the object of the present application are as follows:

[0010] In one aspect, the present application provides a low-noise differential sampling phase-locked loop system with high linear sampling, comprising: a single-to-dual circuit, a differential sampling phase discriminator, a voltage offset device, and a multi-phase clock generation circuit.

[0011] The single-to-dual circuit converts the input single-ended reference signal into a differential reference signal.

[0012] The differential sampling phase discriminator is connected to the single-to-dual circuit, and the differential reference signal output by the single-to-dual circuit is input to the differential sampling phase discriminator.

[0013] The voltage offset device is connected to the differential sampling phase discriminator, and the voltage offset device provides an offset voltage for the differential sampling phase discriminator. The offset voltage improves the phase noise by reducing the conduction time of the current source in the differential sampling phase discriminator, and makes the differential sampling phase discriminator work in a range with better linearity.

[0014] The multi-phase clock generation circuit is used to generate three-phase non-overlapping clocks as the sampling clock of the differential sampling phase discriminator, the offset control clock of the voltage offset device, and the hold clock of the voltage offset device.

[0015] Based on one aspect, in one embodiment of the present application, it further comprises a transconductance amplifier, a low-pass filter, a voltage-controlled oscillator, and a multi-mode frequency divider.

[0016] The transconductance amplifier converts the hold voltage signal output by the voltage offset device and containing loop phase error information into a current signal.

[0017] The low-pass filter converts the current signal output by the transconductance amplifier into a voltage signal and filters high-frequency noise of the voltage signal to output a control voltage;

[0018] The voltage-controlled oscillator outputs an output signal of a corresponding frequency according to the control voltage output by the low-pass filter and a voltage-controlled gain of itself;

[0019] The multi-modulus frequency divider divides the output signal output by the voltage-controlled oscillator to obtain a divided frequency signal;

[0020] The multiphase clock generation circuit generates three-phase non-overlapping clocks according to the divided frequency signal output by the multi-modulus frequency divider.

[0021] Based on one aspect, in an embodiment of the present application, the differential sampling phase detector comprises a bias circuit, a charging-type sampling phase detector and a discharging-type sampling phase detector;

[0022] The bias circuit receives the bias voltage generated by the single-to-dual circuit as a P-end bias voltage of the charging-type sampling phase detector, and generates an N-end bias voltage of the discharging-type sampling phase detector through self-biasing of the bias circuit;

[0023] The charging-type sampling phase detector is configured to compare a phase difference between the P-end bias voltage and the clock output by the multiphase clock generation circuit, and convert the phase difference into a first voltage;

[0024] The discharging-type sampling phase detector is configured to compare a phase difference between the N-end bias voltage and the clock output by the multiphase clock generation circuit, and convert the phase difference into a second voltage.

[0025] Based on one aspect, in an embodiment of the present application, the bias circuit comprises a PMOS transistor Mp1, a PMOS transistor Mp2, an NMOS transistor Mn1, an NMOS transistor Mn2, a decoupling capacitor C P and a decoupling capacitor C N ;

[0026] The source of the PMOS transistor Mp1 is connected to a power supply voltage, the gate of the PMOS transistor Mp1 is connected to a ground potential, and the drain of the PMOS transistor Mp1 is connected to the PMOS transistor Mp2;

[0027] The source of the NMOS transistor Mn1 is connected to a power supply voltage, the gate of the NMOS transistor Mn1 is connected to a ground potential, and the drain of the NMOS transistor Mn1 is connected to the NMOS transistor Mn2;

[0028] The PMOS transistor Mp2 is configured to generate a bias current, the gate of the PMOS transistor Mp2 is connected to a bias voltage VB generated by an external bandgap reference circuit, and the gate of the PMOS transistor Mp4 is connected to the PMOS transistor Mp2 to generate a charging current;​​

[0029] NMOS transistor Mn2 is used to generate a bias voltage, the drain of NMOS transistor Mn2 is connected to the drain of PMOS transistor Mp2, the gate and the drain of NMOS transistor Mn2 are shorted in a diode connection to generate a gate bias voltage of NMOS transistor Mn4;

[0030] decoupling capacitor C P , the second end of decoupling capacitor C N is connected to a ground potential, the first end of decoupling capacitor C P , the first end of decoupling capacitor C N is connected to the gate of PMOS transistor Mp2 and the gate of NMOS transistor Mn2 respectively, for stabilizing bias voltage VB and bias voltage IBN and filtering the noise of PMOS transistor Mp2 and NMOS transistor Mn2 respectively.

[0031] Based on one aspect, in an embodiment of the present application, the charging type sampling phase detector comprises: PMOS transistor Mp3, PMOS transistor Mp4, NMOS transistor Mn5, capacitor C S,P , switch S 1P ;

[0032] The source of PMOS transistor Mp3 is connected to a power supply voltage, the drain of PMOS transistor Mp3 is connected to the source of PMOS transistor Mp4, and the gate of PMOS transistor Mp3 is connected to a P-end reference voltage REFP;

[0033] The gate of PMOS transistor Mp4 is connected to a bias voltage VB generated by an external bandgap reference circuit,

[0034] The drain of NMOS transistor Mn5 is connected to the drain of PMOS transistor Mp4, the gate of NMOS transistor Mn5 is connected to a P-end reference voltage REFP, and the source of NMOS transistor Mn5 is connected to a ground potential;

[0035] The second end of capacitor C S,P is connected to a ground potential, and the first end of capacitor C S,P is connected to the drain of current source transistor Mp4 and the output sampling voltage V 1P through switch S S,P .

[0036] Based on one aspect, in an embodiment of the present application, the discharging type sampling phase detector comprises: NMOS transistor Mn3, NMOS transistor Mn4, PMOS transistor Mp5, capacitor C S,N and switch S 1N ;

[0037] The source of NMOS transistor Mn3 is connected to a ground potential, the drain of NMOS transistor Mn3 is connected to the source of NMOS transistor Mn4, and the gate of NMOS transistor Mn3 is connected to a P-end reference voltage REFN;

[0038] The gate and drain of the NMOS transistor Mn2 are short-circuited into a diode connection to generate a gate bias voltage for the NMOS transistor Mn4;

[0039] The source of the PMOS transistor Mp5 is connected to the power supply voltage, the drain of the PMOS transistor Mp5 is connected to the drain of the NMOS transistor Mn4, and the gate of the PMOS transistor Mp5 is connected to the P-terminal reference voltage REFN;

[0040] Capacitor C S,N The second end of the capacitor C S,N The first end is connected to the switch S 1N Connect the drain of NMOS tube Mn4 and the output sampling voltage V S,N .

[0041] The PMOS transistor Mp2, the NMOS transistor Mn2, the PMOS transistor Mp4, and the NMOS transistor Mn4 of the present invention are respectively current source transistors.

[0042] Based on one aspect, in one embodiment of the present invention, the voltage shifter includes: a first voltage shift circuit and a first holder, a second voltage shift circuit and a second holder;

[0043] The first voltage shift circuit outputs the multi-phase clock according to the Clocks are generated in different configurations Three voltage offsets, VDD is the power supply voltage;

[0044] The first keeper is output from the multi-phase clock generating circuit When the clock is high, the first voltage and Any offset voltage is transferred to the holding capacitor;

[0045] The second voltage shift circuit outputs the multi-phase clock according to the Different clock configurations can generate Three voltage offsets, VDD represents the power supply voltage;

[0046] The second keeper is output from the multi-phase clock generating circuit. When the clock is high, the second voltage and Any offset voltage is transferred to the holding capacitor.

[0047] Based on one aspect, in one embodiment of the present invention, the first voltage shift circuit and the first keeper are a P-end two-bit voltage shift circuit and a keeper; the second voltage shift circuit and the second keeper are an N-end two-bit voltage shift circuit and a keeper;

[0048] The P-terminal two-bit voltage offset circuit and holder comprises NMOS tube Mn1, PMOS tube Mp1, NMOS tube Mn3, PMOS tube Mp3, capacitor C O1,P O2,P 2P H,P ;

[0049] The N-terminal two-bit voltage offset circuit and holder comprises NMOS tube Mn2, PMOS tube Mp2, NMOS tube Mn4, PMOS tube Mp4, capacitor C O1,N O2,N 2N H,N ;

[0050] The first end of capacitor C O1,P O2,P is connected to sampling voltage V S,P , the second end of capacitor C O1,P is connected to the source of NMOS tube Mn1 and the drain of PMOS tube Mp1 respectively, and the second end of capacitor C O2,P is connected to the source of NMOS tube Mn3 and the drain of PMOS tube Mp3 respectively; the first end of capacitor C O1,N O2,N is connected to sampling voltage V S,N , the second end of capacitor C O1,N is connected to the source of NMOS tube Mn2 and the drain of PMOS tube Mp2 respectively, and the second end of capacitor C O2,N is connected to the source of NMOS tube Mn4 and the drain of PMOS tube Mp4 respectively; the first end of capacitor C H,P H,N is connected to ground potential, and the first end of capacitor C H,P is connected to output holding voltage V H,P , and the first end of capacitor C H,N is connected to output holding voltage V H,N .

[0051] In another aspect, the application provides a low-noise differential sampling phase-locked loop method with high linear sampling, comprising:

[0052] Converting a single-ended reference signal into a differential reference signal inputting a differential sampling phase detector;

[0053] One of the three-phase non-overlapping clocks generated by a multiphase clock generation circuit is used as a sampling clock of the differential sampling phase detector;

[0054] A voltage offsetter provides an offset voltage for the differential sampling phase detector;

[0055] ​​​​​​​​​Two of the three-phase non-overlapping clocks generated by the multi-phase clock generating circuit are used as the offset control clock and the hold clock of the voltage offset device.

[0056] According to another aspect, in one embodiment of the present application, it further comprises:

[0057] When the rising edge of the P-end reference clock and the falling edge of the N-end reference clock generated by the multi-phase clock generating circuit arrive, the differential sampling phase detector starts sampling, the PMOS transistor Mp4 starts charging the capacitor C S,P , the NMOS transistor Mn4 starts discharging the capacitor C S,N , the P-end sampling node voltage V S,P starts rising, and the N-end sampling node voltage V S,N starts falling.

[0058] As the sampling clock of the differential sampling phase detector When the falling edge arrives, the sampling ends, the P-end sampling node voltage V S,P and the N-end sampling node voltage V S,N are held.

[0059] As the offset control clock of the voltage offset device When the rising edge arrives, the charge is injected into the capacitor C O1,P , the capacitor C O1,N , the capacitor C O2,P , the capacitor C O2,N , the P-end sampling node voltage V S,P generates an upward voltage step, and the N-end sampling node voltage V S,N generates a downward voltage step.

[0060] As the hold clock of the voltage offset device When the rising edge arrives, the P-end sampling node voltage V S,P is transferred to the hold capacitor C H,P , the N-end sampling node voltage V S,N is transferred to the hold capacitor C H,N .

[0061] As the sampling clock of the differential sampling phase detector When the rising edge arrives, the P-end sampling node voltage V S,P and the N-end sampling node voltage V S,N are held and start to reset.

[0062] Compared with the prior art, the present application has the following beneficial effects:

[0063] The application adjusts the proportion of the offset capacitor of the voltage offset device in the total sampling capacitor by presetting whether the digital clock of the multi-phase clock generation circuit is enabled, so that the voltage offset device flexibly generates different offset voltages, and then generates different current source on-time, effectively alleviates the phase noise deterioration caused by current source thermal noise injection, improves the sampling voltage linearity, and makes the differential sampling phase detector be configured in a differential working mode, so as to further suppress the in-band noise with twice the phase detection gain, and make the system have good common-mode disturbance resistance. BRIEF DESCRIPTION OF DRAWINGS

[0064] Figure 1 A low-noise differential sampling phase-locked loop system circuit structure with high linear sampling provided for an embodiment of the application;

[0065] Figure 2 A circuit diagram of the differential sampling phase detector provided for an embodiment of the application;

[0066] Figure 3 A circuit diagram of the voltage offset device provided for an embodiment of the application;

[0067] Figure 4 A circuit diagram of the switch unit provided for an embodiment of the application;

[0068] Figure 5 A working timing diagram of the differential sampling phase detector and the voltage offset device provided for an embodiment of the application. DETAILED DESCRIPTION

[0069] The application will be described in detail below in conjunction with the embodiments shown in the drawings, but it should be noted that these embodiments are not a limitation on the application, and equivalent transformations or substitutions of functions, methods, or structures made by those skilled in the art based on these embodiments are within the protection scope of the application.

[0070] Please refer to Figure 1 , Figure 1A low-noise differential sampling phase-locked loop system circuit structure with high linear sampling is provided for the embodiment of the present application. The low-noise differential sampling phase-locked loop system with high linear sampling provided by the embodiment of the present application comprises a single-to-dual circuit, a differential sampling phase detector, a voltage offsetter, a trans-impedance amplifier, a low-pass filter, a voltage-controlled oscillator, a multi-modulus divider and a multi-phase clock generation circuit. The single-to-dual circuit converts an input single-ended reference signal into a differential reference signal. The differential sampling phase detector is connected to the single-to-dual circuit, and the differential reference signal output by the single-to-dual circuit is input into the differential sampling phase detector. The voltage offsetter is connected to the differential sampling phase detector, and the voltage offsetter provides an offset voltage for the differential sampling phase detector. The offset voltage improves the phase noise by reducing the conduction time of the current source in the differential sampling phase detector, and enables the differential sampling phase detector to work in a range with better linearity. The multi-phase clock generation circuit is used to generate three-phase non-overlapping clocks as the sampling clock of the differential sampling phase detector, the offset control clock of the voltage offsetter and the hold clock of the voltage offsetter. The trans-impedance amplifier converts the hold voltage signal output by the voltage offsetter and containing loop phase error information into a current signal. The low-pass filter converts the current signal output by the trans-impedance amplifier into a voltage signal, and filters the high-frequency noise of the voltage signal to output a control voltage. The voltage-controlled oscillator outputs an output signal with a corresponding frequency according to the control voltage output by the low-pass filter and the voltage-controlled gain of the voltage-controlled oscillator. The multi-modulus divider divides the output signal output by the voltage-controlled oscillator to obtain a divided signal, and the multi-phase clock generation circuit generates three-phase non-overlapping clocks according to the divided signal output by the multi-modulus divider.

[0071] The differential sampling phase detector described above in the embodiment of the present application comprises a bias circuit, a charging-type sampling phase detector and a discharging-type sampling phase detector. The bias circuit receives the bias voltage generated by the single-to-dual circuit as the P-end bias voltage of the charging-type sampling phase detector, and generates the N-end bias voltage of the discharging-type sampling phase detector through self-biasing of the bias circuit. The charging-type sampling phase detector is used to compare the phase difference between the P-end bias voltage and the clock output by the multi-phase clock generation circuit, and convert the phase difference into a first voltage. The discharging-type sampling phase detector is used to compare the phase difference between the N-end bias voltage and the clock output by the multi-phase clock generation circuit, and convert the phase difference into a second voltage. The differential sampling phase detector described above in the embodiment of the present application comprises a bias circuit, a charging-type sampling phase detector and a discharging-type sampling phase detector. The bias circuit receives the bias voltage generated by the single-to-dual circuit as the P-end bias voltage of the charging-type sampling phase detector, and generates the N-end bias voltage of the discharging-type sampling phase detector through self-biasing of the bias circuit. The charging-type sampling phase detector is used to compare the phase difference between the P-end bias voltage and the clock output by the multi-phase clock generation circuit, and convert the phase difference into a first voltage. The discharging-type sampling phase detector is used to compare the phase difference between the N-end bias voltage and the clock output by the multi-phase clock generation circuit, and convert the phase difference into a second voltage.

[0072] Please refer to Figure 2 , Figure 2 The circuit diagram of the differential sampling phase detector provided for the embodiment of the present application is shown in the figure. The bias circuit described above comprises PMOS tubes Mp1 and Mp2, NMOS tubes Mn1 and Mn2, decoupling capacitors C P and C N ​The source of the PMOS transistor Mp1 is connected to the power supply voltage, the gate of the PMOS transistor Mp1 is grounded, and the drain of the PMOS transistor Mp1 is connected to the PMOS transistor Mp2; the source of the NMOS transistor Mn1 is connected to the power supply voltage, the gate of the NMOS transistor Mn1 is grounded, and the drain of the NMOS transistor Mn1 is connected to the NMOS transistor Mn2; the PMOS transistor Mp2 is used to generate a bias current, the gate of the PMOS transistor Mp2 is connected to the bias voltage VB generated by the external bandgap reference circuit, and is connected to the gate of the PMOS transistor Mp4 to generate a charging current; the NMOS transistor Mn2 is used to generate a bias voltage, the drain of the NMOS transistor Mn2 is connected to the drain of the PMOS transistor Mp2, and the gate and drain of the NMOS transistor Mn2 are short-circuited in a diode connection to generate a gate bias voltage for the NMOS transistor Mn4; the decoupling capacitor C P , decoupling capacitor C N The second end of the decoupling capacitor C P , decoupling capacitor C N The first ends are connected to the gates of the PMOS transistor Mp2 and the NMOS transistor Mn2 respectively, and are used to stabilize the bias voltage VB and the bias voltage IBN and filter out noise of the PMOS transistor Mp2 and the NMOS transistor Mn2 respectively.

[0073] See also Figure 2 , Figure 2 The circuit diagram of the differential sampling phase detector provided by the embodiment of the present invention, the charging type sampling phase detector includes: PMOS tube Mp3, PMOS tube Mp4, NMOS tube Mn5, capacitor C S,P , switch S 1P The source of the PMOS transistor Mp3 is connected to the power supply voltage, the drain of the PMOS transistor Mp3 is connected to the source of the PMOS transistor Mp4, and the gate of the PMOS transistor Mp3 is connected to the P-terminal reference voltage REFP; the gate of the PMOS transistor Mp4 is connected to the bias voltage VB generated by the external bandgap reference circuit, the drain of the NMOS transistor Mn5 is connected to the drain of the PMOS transistor Mp4, the gate of the NMOS transistor Mn5 is connected to the P-terminal reference voltage REFP, and the source of the NMOS transistor Mn5 is grounded; the capacitor C S,P The second end of the capacitor C S,P The first end is connected to the switch S 1P The drain of the current source tube Mp4 and the output sampling voltage V S,P .

[0074] See also Figure 2 , Figure 2 The circuit diagram of the differential sampling phase detector provided by the embodiment of the present invention, the above-mentioned discharge type sampling phase detector includes: NMOS tube Mn3, NMOS tube Mn4, PMOS tube Mp5, capacitor C S,N and switch S 1NThe source of the NMOS transistor Mn3 is connected to the ground potential, the drain of the NMOS transistor Mn3 is connected to the source of the NMOS transistor Mn4, and the gate of the NMOS transistor Mn3 is connected to the P-terminal reference voltage REFN; the gate and drain of the NMOS transistor Mn2 are short-circuited into a diode connection to generate a gate bias voltage for the NMOS transistor Mn4; the source of the PMOS transistor Mp5 is connected to the power supply voltage, the drain of the PMOS transistor Mp5 is connected to the drain of the NMOS transistor Mn4, and the gate of the PMOS transistor Mp5 is connected to the P-terminal reference voltage REFN; the capacitor C S,N The second end of the capacitor C S,N The first end is connected to the switch S 1N Connect the drain of NMOS tube Mn4 and the output sampling voltage V S,N .

[0075] It should be noted that the PMOS transistor Mp2, the NMOS transistor Mn2, the PMOS transistor Mp4, and the NMOS transistor Mn4 in the embodiment of the present invention are current source transistors.

[0076] Please continue reading Figure 1 To illustrate how the low-noise differential sampling phase-locked loop system according to an embodiment of the present invention improves linearity and phase noise, the open-loop transfer function G(s) and closed-loop transfer function H(s) of the low-noise differential sampling phase-locked loop system according to an embodiment of the present invention can be expressed as follows:

[0077]

[0078]

[0079] Then its loop bandwidth BW and phase margin PM can be approximately expressed as:

[0080]

[0081]

[0082] Among them, K DSPD represents the phase gain of the differential sampling phase detector, gm represents the transconductance of the transconductance amplifier, Z LF represents the impedance of the loop filter, K VCO represents the voltage-controlled gain, N represents the frequency division ratio, BW represents the loop bandwidth, R represents the loop filter compensation resistor, ω c 、ω z 、ω p3 are the wideband bandwidth, zero position, and non-zero third pole position in angular frequency form, respectively.

[0083] For a single-ended sampling phase detector, the phase detector gain expression is:

[0084]

[0085] Among them, SR REF Indicates the sampling voltage slew rate, t res Indicates the remaining charge and discharge time under the locked state, that is, the current source conduction time, f REF Indicates the reference frequency.

[0086] For the differential sampling phase detector, the phase detector gain expression is:

[0087]

[0088] For a differential sampling phase detector, its phase noise is mainly composed of two parts: current thermal noise and sampling circuit KT / C noise. Here, K is the Boltzmann constant, T is the Kelvin temperature, and C is the capacitance.

[0089] For the KT / C noise of differential two-stage master-slave sampling, if the total size of the sampling capacitor and offset capacitor at the P and N terminals is C S , keep the capacitance value C H , sampling clock and offset controlled clock Inject C S The noise voltage is equal to (KT / C S ) 1 / 2 , corresponding to the charge (KTC S ) 1 / 2 , the noise charge in When the clock edge arrives, it is shared to capacitor C H , generating noise voltage (KT / C S ) 1 / 2 / (C S +C H ), the square of the noise voltage plus the noise from the sampler Clock Injection C H The noise of the master and slave samplers is summed up to get the total KT / C noise. The thermal noise of the differential sampling phase detector is determined by the remaining charge and discharge time t after locking. res Therefore, the total output noise can be expressed as:

[0090]

[0091] According to the closed-loop transfer function of the differential sampling phase-locked loop in equation (2), the noise transfer function from the differential sampling phase detector noise to the output can be expressed as:

[0092]

[0093] Therefore, the noise contributed by the differential sampling phase detector at the output of the phase-locked loop can be expressed as:

[0094]

[0095] Similarly, the noise contributed by the trans-impedance amplifier at the output of the PLL can be expressed as:

[0096]

[0097] From equations (4) and (5), the phase detection gain of the differential sampling is twice that of the single-ended sampling, so the phase noise of the differential sampling phase detector and its back-end circuit is optimized by 6dB. Since the differential sampling doubles the noise source of the phase detector, the noise of the differential sampling phase detector is improved by 3dB.

[0098] The two-stage master-slave sampler actually constitutes a switched-capacitor filter, which introduces an additional pole, seriously affecting the loop stability. According to the charge conservation relationship, the voltage transfer relationship of V S and V H nodes can be expressed as:

[0099]

[0100] For the exact solution of this pole, the z-domain analysis method must be used. If the total capacitance of the sampling node and the holding node satisfies V S and V H nodes can be rewritten as:

[0101]

[0102] Therefore, the introduced pole can be expressed as ω p,s = -ln(l-α)·f s , then the phase margin of the differential sampling PLL should be rewritten as:

[0103]

[0104] To ensure that the introduced additional pole does not affect the phase margin, it must satisfy ω p,s > 10ω c , then the total capacitance C S of the sampling node and the total capacitance C H of the holding node must satisfy C S >> C H . Therefore, the KT / C noise of the differential sampling phase detector is mainly determined by the holding capacitance C H , and the total noise can be approximately expressed as:

[0105]

[0106] For the sampling circuit, a certain sampling accuracy must be ensured. The switched-capacitor sampling circuit charges the capacitor through the on-resistance of the switch, producing an exponential response The time needed to reach the final value within 0.1% error is called 0.1% settling time t s To ensure 0.1% settling time, t S ≈7R on C S must be satisfied, so half a clock cycle must be more than 7 times the time constant R on C S To obtain low noise, a large capacitor must be used, but the settling time is thus lengthened, i.e. the sampling accuracy is reduced, so the value of the total sampling node capacitance is a compromise between sampling accuracy and noise.

[0107] When the bias control clock is not enabled, the bias capacitor is equivalent to ground; when the bias control clock is enabled, the bias control clock injects charge into the bias capacitor when the edge arrives. According to the charge conservation relation, we can obtain:

[0108] C O ·VDD=C S ·ΔV (15)

[0109] Where C O is the effective bias capacitor, C S is the total sampling node capacitance, and VDD is the power supply voltage. If the ratio of the effective bias capacitor C O to the total sampling node capacitance C S is expressed as then the bias voltage can be expressed as ΔV=β·VDD. If the sampling capacitor and the bias capacitor satisfy the ratio (C S,P =C S,N ):(C O1,P =C O1,N ):(C O2,P =C O2,N )=5:2:1, [1:0] two-bit enable ends are configured as (0, 1), (1, 0), (1, 1) respectively, the offset voltage is respectively

[0110] In the locked state, the voltage of the sampling node can be expressed as If the offset voltage is , the remaining charge and discharge time t res is reduced by half, and the noise of the differential sampling phase detector is improved by 6dB. If the switch S 1P and the switch S 1N are always closed during the sampling node rises or falls to , the voltage of the node V S,P increases, and the voltage of the node V S,NThe voltage of the current source tube Mp4 and the current source tube Mn4 is reduced, and the drain-source voltage of the current source tube Mp4 and the current source tube Mn4 is reduced, so that the current source tube Mp4 and the current source tube Mn4 are easily in the linear region. Therefore, the bias technology avoids the current source tube Mp4 and the current source tube Mn4 from entering the linear region, so that the linearity of the differential sampling phase detector is greatly improved.

[0111] The voltage offset device provided by the embodiment of the present application comprises a first voltage offset circuit and a first holder, a second voltage offset circuit and a second holder; the first voltage offset circuit generates three kinds of voltage offsets according to different configurations of the clock output by a multiphase clock generation circuit The second voltage offset circuit generates three kinds of voltage offsets according to different configurations of the clock output by the multiphase clock generation circuit VDD represents a power voltage; the second holder transmits the second voltage and any one of the offset voltages to a holding capacitor when the clock output by the multiphase clock generation circuit is at a high level. The second voltage offset circuit generates three kinds of voltage offsets according to different configurations of the clock output by the multiphase clock generation circuit VDD represents a power voltage; the second holder transmits the second voltage and any one of the offset voltages to a holding capacitor when the clock output by the multiphase clock generation circuit is at a high level. The second voltage offset circuit generates three kinds of voltage offsets according to different configurations of the clock output by the multiphase clock generation circuit

[0112] Please refer to Figure 3 , Figure 3 the circuit diagram of the voltage offset device provided by the embodiment of the present application. The first voltage offset circuit and the first holder are a P-terminal two-bit voltage offset circuit and a holder; the second voltage offset circuit and the second holder are an N-terminal two-bit voltage offset circuit and a holder; wherein: the P-terminal two-bit voltage offset circuit and the holder comprise: an NMOS tube Mn1, a PMOS tube Mp1, an NMOS tube Mn3, a PMOS tube Mp3, a capacitor C O1,P , a capacitor C O2,P , a switch S 2P and a capacitor C H,P ; the N-terminal two-bit voltage offset circuit and the holder comprise: an NMOS tube Mn2, a PMOS tube Mp2, an NMOS tube Mn4, a PMOS tube Mp4, a capacitor C O1,N , a capacitor C O2,N , a switch S 2N and a capacitor C H,N ; the first end of the capacitor C O1,P , the capacitor C O2,P is connected to a sampling voltage V S,P , the second end of the capacitor C O1,P is connected to the source of the NMOS tube Mn1 and the drain of the PMOS tube Mp1, respectively, and the capacitor C O2,P ​​​The second end of the capacitor C is connected to the source of the NMOS tube Mn3 and the drain of the PMOS tube Mp3 respectively; O1,N , capacitor C O2,N The first end is connected to the sampling voltage V S,N , capacitor C O1,N The second end of the capacitor C is connected to the source of the NMOS tube Mn2 and the drain of the PMOS tube Mp2. O2,N The second end of the capacitor C is connected to the source of the NMOS transistor Mn4 and the drain of the PMOS transistor Mp4 respectively; H,P , capacitor C H,N The second end of the capacitor C is connected to the ground potential. H,P The first end is connected to the output holding voltage V H,P , capacitor C H,N The first end is connected to the output holding voltage V H,N .

[0113] See also Figure 4 , Figure 4 A circuit diagram of a switch unit provided in an embodiment of the present invention. Figure 4 The switch unit is Figure 3 Switch S 2P and switch S 2N ,use Figure 4 The symbol of the switch unit replaces Figure 3 Switch S 2P and switch S 2N . Figure 4 The switch unit uses PMOS tubes of the same size connected in parallel and NMOS tubes connected in series to make the effective size ratio of the two 3:1, thereby enhancing the ability of the PMOS tube to transmit high voltage. The redundant NMOS tubes serve as dummy tubes to offset clock feedthrough and charge injection, and serve as capacitors to balance the clock loads driving the NMOS tubes and the PMOS tubes. The switch circuit includes: PMOS tubes Mp1, PMOS tubes Mp2 and PMOS tubes Mp3, and NMOS tubes Mn1, NMOS tubes Mn2 and NMOS tubes Mn3; wherein the gate of the PMOS tube Mp2 is connected to the gate of the PMOS tube Mp1 and the gate of the PMOS tube Mp3. They are all connected to the clock signal CKB, the drain of the PMOS transistor Mp2 is connected to the source of the PMOS transistor Mp3 and the source of the PMOS transistor Mp1, that is, the input A terminal, and the source of the PMOS transistor Mp2 is connected to the drain of the PMOS transistor Mp1 and the drain of the PMOS transistor Mp3, that is, the output B terminal; the gate of the NMOS transistor Mn2 and the gate of the NMOS transistor Mn2 and the PMOS transistor Mn3 are all connected to the clock signal CK, the source of the NMOS transistor Mn2 is connected to the drain and source of the NMOS transistor Mn1, that is, the input A terminal, and the drain of the NMOS transistor Mn2 is connected to the source and drain of the NMOS transistor Mn3, that is, the output B terminal.

[0114] SeeFigure 5 , Figure 5 The working timing chart of the differential sampling phase discriminator and the voltage offset device provided by the embodiment of the present application is shown in the following table. When the rising edge of the P-end reference clock and the falling edge of the N-end reference clock arrive, the differential sampling phase discriminator starts sampling, the current source tube Mp4 starts charging the capacitor C S,P , the current source tube Mn4 starts discharging the capacitor C S,N , the voltage V S,P of the P-end sampling node starts rising, and the voltage V S,N of the N-end sampling node starts falling; when the sampling clock falls, the sampling ends, the voltage V S,P of the P-end sampling node and the voltage V S,N of the N-end sampling node remain; when the voltage offset control clock rises, the charge is injected into the offset capacitor C O1,P , C O1,N , C O2,P , C O2,N , the voltage V S,P of the P-end sampling node generates an upward voltage step, and the voltage V S,N of the N-end sampling node generates a downward voltage step; when the holding clock rises, the voltage V S,P of the P-end sampling node is transferred to the holding capacitor C H,P , and the voltage V S,N of the N-end sampling node is transferred to the holding capacitor C H,N ; when the sampling clock rises, the voltage V S,P of the P-end sampling node and the voltage V S,N of the N-end sampling node start resetting.

[0115] The embodiment of the present application further provides a low-noise differential sampling phase-locked loop method with high linear sampling, which comprises the following steps: converting a single-end reference signal into a differential reference signal to input a differential sampling phase discriminator; taking one of three-phase non-overlapping clocks generated by a multi-phase clock generating circuit as a sampling clock of the differential sampling phase discriminator; taking two of the three-phase non-overlapping clocks generated by the multi-phase clock generating circuit as an offset control clock and a holding clock of a voltage offset device; and taking the voltage offset device as an offset voltage of the differential sampling phase discriminator.

[0116] When the rising edge of the P-end reference clock and the falling edge of the N-end reference clock generated by the multi-phase clock generating circuit arrive, the differential sampling phase discriminator starts sampling, the PMOS tube Mp4 starts charging the capacitor C S,P , and the NMOS tube Mn4 starts discharging the capacitor C S,N , the voltage V S,P of the P-end sampling node starts rising, and the voltage V S,NStart down; sample clock as differential sample phase discriminator When the falling edge comes, the sampling ends, the P end sampling node voltage V S,P And the N end sampling node voltage V S,N Hold; offset control clock as voltage offsetter When the rising edge comes, the charge injection capacitor C O1,P , capacitor C O1,N , capacitor C O2,P , capacitor C O2,N The P end sampling node voltage V S,P Generate an upward voltage step, the N end sampling node voltage V S,N Generate a downward voltage step; hold clock as voltage offsetter When the rising edge comes, the P end sampling node voltage V S,P Transferred to the hold capacitor C H,P , the N end sampling node voltage V S,N Transferred to the hold capacitor C H,N ; sample clock as differential sample phase discriminator When the rising edge comes, the P end sampling node voltage V S,P And the N end sampling node voltage V S,N Hold start reset.

[0117] The embodiment of the present application adjusts the proportion of the offset capacitor of the voltage offsetter in the total sampling capacitor by presetting whether the digital clock of the multiphase clock generation circuit is enabled, so that the voltage offsetter flexibly generates different offset voltages, and then generates different current source conduction times, effectively alleviates the phase noise deterioration caused by current source thermal noise injection, improves the sampling voltage linearity, and makes the differential sampling phase discriminator be configured in a differential working mode, so as to further suppress the in-band noise by two times of the phase discrimination gain, and make the system have good common-mode disturbance resistance.

[0118] The terms "first", "second", etc. in the specification are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0119] In the description of the application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the application. In the description of the application, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate different embodiments or examples described in the specification.

[0120] Although the application is described herein in conjunction with various embodiments, it is understood that other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from an inspection of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite articles "a" or "an" do not exclude a plurality. A single processor or other unit can fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0121] The above is a further detailed description of the application in conjunction with specific preferred embodiments, and cannot be deemed to limit the specific implementation of the application to these descriptions. For those skilled in the art to which the application belongs, a number of simple deductions or substitutions can be made without departing from the concept of the application, and all should be regarded as falling within the protection scope of the application.

Claims

1. A low noise differential sampling phase-locked loop system with high linearity sampling, characterized by, The application relates to a single-to-differential circuit, a differential sampling phase detector, a voltage offset device, a multi-phase clock generation circuit, a trans-impedance amplifier, a low-pass filter, a voltage-controlled oscillator and a multi-modulus divider. The single-to-differential circuit converts an input single-ended reference signal into a differential reference signal; The voltage offset device is connected to the differential sampling phase detector, and the voltage offset device provides an offset voltage for the differential sampling phase detector, the offset voltage improves phase noise by reducing the on-time of a current source in the differential sampling phase detector, and the differential sampling phase detector works in a range with better linearity; the voltage offset device comprises a first voltage offset circuit and a first keeper, a second voltage offset circuit and a second keeper; The differential sampling phase detector is connected with the single-to-dual circuit, and a differential reference signal output by the single-to-dual circuit is input into the differential sampling phase detector; the differential sampling phase detector comprises a bias circuit, a charging-type sampling phase detector and a discharging-type sampling phase detector; the bias circuit receives a bias voltage generated by the single-to-dual circuit as a P-end bias voltage of the charging-type sampling phase detector, and generates an N-end bias voltage of the discharging-type sampling phase detector through self-biasing of the bias circuit; the charging-type sampling phase detector is used for comparing a phase difference between the P-end bias voltage and a plurality of clocks output by the multi-phase clock generation circuit, and converting the phase difference into a first voltage; and the discharging-type sampling phase detector is used for comparing a phase difference between the N-end bias voltage and the plurality of clocks output by the multi-phase clock generation circuit, and converting the phase difference into a second voltage. The differential sampling phase detector is connected with the single-to-dual circuit, and a differential reference signal output by the single-to-dual circuit is input into the differential sampling phase detector; the differential sampling phase detector comprises a bias circuit, a charging-type sampling phase detector and a discharging-type sampling phase detector; the bias circuit receives a bias voltage generated by the single-to-dual circuit as a P-end bias voltage of the charging-type sampling phase detector, and generates an N-end bias voltage of the discharging-type sampling phase detector through self-biasing of the bias circuit; the charging-type sampling phase detector is used for comparing a phase difference between the P-end bias voltage and a plurality of clocks output by the multi-phase clock generation circuit, and converting the phase difference into a first voltage; and the discharging-type sampling phase detector is used for comparing a phase difference between the N-end bias voltage and the plurality of clocks output by the multi-phase clock generation circuit, and converting the phase difference into a second voltage. The differential sampling phase detector is connected with the single-to-dual circuit, and a differential reference signal output by the single-to-dual circuit is input into the differential sampling phase detector; the differential sampling phase detector comprises a bias circuit, a charging-type sampling phase detector and a discharging-type sampling phase detector; the bias circuit receives a bias voltage generated by the single-to-dual circuit as a P-end bias voltage of the charging-type sampling phase detector, and generates an N-end bias voltage of the discharging-type sampling phase detector through self The multi-phase clock generation circuit is used for generating three-phase non-overlapping clocks as a sampling clock of the differential sampling phase detector, an offset control clock of the voltage offset device and a holding clock of the voltage offset device; The first voltage offset circuit generates three voltage offsets according to the different configurations of the clock outputted by the multi-phase clock generating circuit , , , three voltage offsets, VDD represents the power voltage; the second holding unit transmits the second voltage and any one of the offset voltages to the holding capacitor when the clock outputted by the multi-phase clock generating circuit is at high level , , , three voltage offsets, VDD represents the power voltage; the second holding unit transmits the second voltage and any one of the offset voltages to the holding capacitor when the clock outputted by the multi-phase clock generating circuit is at high level , , , three voltage offsets, VDD represents the power voltage; the second holding unit transmits the second voltage and any one of the offset voltages to the holding capacitor when the clock outputted by the multi-phase clock generating circuit is at high level , , , ​ The trans-impedance amplifier converts a holding voltage signal containing loop phase error information output by the voltage offset device into a current signal; The low-pass filter converts the current signal output by the trans-impedance amplifier into a voltage signal, filters high-frequency noise of the voltage signal and outputs a control voltage; The voltage-controlled oscillator outputs an output signal with a corresponding frequency according to the control voltage output by the low-pass filter and a voltage-controlled gain of the voltage-controlled oscillator; The multi-modulus divider divides the output signal output by the voltage-controlled oscillator to obtain a divided signal; The multi-phase clock generation circuit generates three-phase non-overlapping clocks according to the divided signal output by the multi-modulus divider. The source of the PMOS transistor Mp1 is connected to a power supply voltage, the gate of the PMOS transistor Mp1 is connected to a ground potential, and the drain of the PMOS transistor Mp1 is connected to the PMOS transistor Mp2; 2. A low noise differential sampled phase locked loop system with high linearity sampling as claimed in claim 1, wherein, The bias circuit comprises a PMOS transistor Mp1, a PMOS transistor Mp2, an NMOS transistor Mn1, an NMOS transistor Mn2, a decoupling capacitor C P and a decoupling capacitor C N ; The source of the NMOS transistor Mn1 is connected to the power supply voltage, the gate of the NMOS transistor Mn1 is connected to the ground potential, and the drain of the NMOS transistor Mn1 is connected to the NMOS transistor Mn2; The PMOS transistor Mp2 is used for generating a bias current, the gate of the PMOS transistor Mp2 is connected to a bias voltage VB generated by an external bandgap reference circuit, and the gate of the PMOS transistor Mp2 is connected to the gate of the PMOS transistor Mp4 to generate a charging current; The NMOS transistor Mn2 is used for generating a bias voltage, the drain of the NMOS transistor Mn2 is connected to the drain of the PMOS transistor Mp2, and the gate and the drain of the NMOS transistor Mn2 are connected in a diode connection mode to generate a gate bias voltage of the NMOS transistor Mn4; The source of the PMOS transistor Mp3 is connected to the power supply voltage, the drain of the PMOS transistor Mp3 is connected to the source of the PMOS transistor Mp4, and the gate of the PMOS transistor Mp3 is connected to a P-end reference voltage REFP; Decoupling capacitor C P , decoupling capacitor C N The second end of the decoupling capacitor C P , decoupling capacitor C N The first ends are connected to the gates of the PMOS transistor Mp2 and the NMOS transistor Mn2 respectively, and are used to stabilize the bias voltage VB and the bias voltage IBN and filter out noise of the PMOS transistor Mp2 and the NMOS transistor Mn2 respectively.

3. A low noise differential sampling phase locked loop system with high linearity sampling as claimed in claim 1, wherein, The charge type sampling phase discriminator comprises a PMOS tube Mp3, a PMOS tube Mp4, an NMOS tube Mn5, a capacitor C S,P , and a switch S 1P . The gate of the PMOS transistor Mp4 is connected to the bias voltage VB generated by the external bandgap reference circuit, The drain of the NMOS transistor Mn5 is connected to the drain of the PMOS transistor Mp4, the gate of the NMOS transistor Mn5 is connected to the P-end reference voltage REFP, and the source of the NMOS transistor Mn5 is connected to the ground potential; The source of the NMOS transistor Mn3 is connected to the ground potential, the drain of the NMOS transistor Mn3 is connected to the source of the NMOS transistor Mn4, and the gate of the NMOS transistor Mn3 is connected to a P-end reference voltage REFN. The second end of the capacitor C S,P is grounded, and the first end of the capacitor C S,P is connected to the drain of the current source transistor Mp4 through the switch S 1P , and the output sampling voltage V S,P is output.

4. A low noise differential sampling phase locked loop system with high linearity sampling as claimed in claim 1, wherein, The discharge type sampling phase discriminator comprises an NMOS tube Mn3, an NMOS tube Mn4, a PMOS tube Mp5, a capacitor C S,N and a switch S 1N ​ ​ The gate and the drain of the NMOS transistor Mn2 are shorted in a diode connection form to generate a gate bias voltage of the NMOS transistor Mn4; The source of the PMOS transistor Mp5 is connected to a power voltage, the drain of the PMOS transistor Mp5 is connected to the drain of the NMOS transistor Mn4, and the gate of the PMOS transistor Mp5 is connected to a P-end reference voltage REFN; The second end of the capacitor C S,N is grounded, and the first end of the capacitor C S,N is connected to the drain of the NMOS transistor Mn4 through the switch S 1N and outputs the sampling voltage V S,N .

5. A low noise differential sampling phase locked loop system with high linearity sampling as claimed in claim 1, wherein, The first voltage offset circuit and the first keeper are a P-end two-bit voltage offset circuit and a keeper; The second voltage offset circuit and the second keeper are an N-end two-bit voltage offset circuit and a keeper; The P-terminal two-bit voltage shift circuit and keeper include: NMOS tube Mn1, PMOS tube Mp1, NMOS tube Mn3, PMOS tube Mp3, capacitor C O1,P , capacitor C O2,P , switch S 2P and capacitor C H,P ; The N-terminal two-bit voltage offset circuit and holder comprises: NMOS tube Mn2, PMOS tube Mp2, NMOS tube Mn4, PMOS tube Mp4, capacitor C O1,N , capacitor C O2,N , switch S 2N and capacitor C H,N ; Capacitor C O1,P Capacitor C O2,P a first end of capacitor C S,P a second end of capacitor C O1,P a source of NMOS transistor Mn1 and a drain of PMOS transistor Mp1, respectively; a second end of capacitor C O2,P a source of NMOS transistor Mn3 and a drain of PMOS transistor Mp3, respectively; a second end of capacitor C O1,N Capacitor C O2,N a first end of capacitor C S,N a second end of capacitor C O1,N a source of NMOS transistor Mn2 and a drain of PMOS transistor Mp2, respectively; a second end of capacitor C O2,N a source of NMOS transistor Mn4 and a drain of PMOS transistor Mp4, respectively; a second end of capacitor C H,P Capacitor C H,N a second end of capacitor C H,P a first end of capacitor C H,P a first end of capacitor C H,N a first end of capacitor C H,N a first end of capacitor C 6. A low noise differential sampling phase-locked loop method with high linearity sampling, based on the low noise differential sampling phase-locked loop system with high linearity sampling of any one of claims 1-5, characterized in that, The low-noise differential sampling phase-locked loop method comprises: A single-ended reference signal is converted into a differential reference signal to input a differential sampling phase detector; One of three-phase non-overlapping clocks generated by a multi-phase clock generation circuit is used as a sampling clock of the differential sampling phase detector; A voltage offset circuit provides an offset voltage for the differential sampling phase detector; Two of the three-phase non-overlapping clocks generated by the multi-phase clock generation circuit are used as an offset control clock and a holding clock of the voltage offset circuit.

7. The method of claim 6, wherein the low noise differential sampling phase-locked loop with high linearity sampling is characterized by, The low-noise differential sampling phase-locked loop method further comprises: When the rising edge of the P terminal reference clock and the falling edge of the N terminal reference clock generated by the multi-phase clock generating circuit come, the differential sampling phase discriminator starts sampling, and the PMOS transistor Mp4 starts charging the capacitor When the rising edge of the P terminal reference clock and the falling edge of the N terminal reference clock generated by the multi-phase clock generating circuit come, the differential sampling phase discriminator starts sampling, and the PMOS transistor Mp4 starts charging the capacitor When the rising edge of the P terminal reference clock and the falling edge of the N terminal reference clock generated by the multi-phase clock generating circuit come, the differential sampling phase discriminator starts sampling, and the PMOS transistor Mp4 starts charging the capacitor When the rising edge of the P terminal reference clock and the falling edge of the N terminal reference clock generated by the multi-phase clock generating circuit come, the differential sampling phase discriminator starts sampling, and the PMOS transistor Mp4 starts charging the capacitor When the rising edge of the P terminal Sampled clock as a differential sample phase discriminator At the falling edge, the sampling ends, the P end sampling node voltage and the N end sampling node voltage Hold; Offset control clock as voltage offsetter Rising edge comes, charge injection capacitor Capacitor Capacitor Capacitor P terminal sampling node voltage Upward voltage step generation, N terminal sampling node voltage Downward voltage step generation; Holding clock as voltage shifter When the rising edge arrives, the voltage of the sampling node at the P end Transferred to the holding capacitor C H,P , N-terminal sampling node voltage Transferred to the holding capacitor C H,N ; Sampled clock as a differential sample phase discriminator The P end sample node voltage And the N end sample node voltage Hold start reset.

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