Phase-locked loop charge pump circuit
By designing a phase-locked loop charge pump circuit, the pull-up and pull-up current changes are achieved using LDO and resistors, the problems of long current establishment time and flickering noise in the traditional charge pump circuit are solved, and the quality of the phase-locked loop output clock signal is improved.
Patent Information
- Application Number
- CN202411668218.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-21
- Publication Date
- 2025-02-28
AI Technical Summary
The charge pump circuit of the traditional current mirror architecture has problems such as long current establishment time and low frequency flicker noise, which affects the quality of the phase-locked loop output clock signal.
A phase-locked loop charge pump circuit is designed, and LDO is composed of an operational amplifier OP, Power MOS tube M0 and resistors R1 and R1’. The pull-up and pull-up current is changed using control signals and resistors R, R/2, R/4, R/8, R’, R/2’, R/4’, R/8’. The current is directly generated by VCTRL/R, avoiding the current establishment time.
This charge pump circuit avoids flickering noise from traditional current mirror charge pumps, and only the thermal noise of the resistor contributes to the phase lock loop, improving the quality of the output clock signal.
Smart Images
Figure CN119543927A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a phase-locked loop charge pump circuit. Background Art
[0002] The development of smart devices has led to a surge in the amount of information data. High Speed Serial Link has been widely used in data transmission due to its unique advantages.
[0003] In high-speed serial links, both the serializer and the deserializer require a high-quality clock signal to provide a synchronization signal for the transmitted data, so the phase-locked loop (PLL) technology is widely used in high-speed serial links.
[0004] The performance of the PLL determines the quality of the transmitted signal. In a high-speed, low-noise PLL, the charge pump's own noise determines the noise level within the PLL's bandwidth, thus affecting the quality of the output clock signal. The charge pump circuit of the traditional current mirror architecture has problems such as long current settling time and low-frequency flicker noise. Summary of the invention
[0005] The object of the present invention is to provide a phase-locked loop charge pump circuit to solve the problems in the background technology.
[0006] In order to solve the above technical problems, the present invention provides a phase-locked loop charge pump circuit, including: an operational amplifier OP, a resistor R1, a resistor R1', a Power MOS tube M0, a PMOS tube P0, a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, an NMOS tube N0, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3, a resistor R, a resistor R / 2, a resistor R / 4, a resistor R / 8, a resistor R', a resistor R / 2', a resistor R / 4', and a resistor R / 8'; The drain end of the Power MOS tube M0 is connected to the power supply voltage VDD, and the source end is connected to the first end of the resistor R1; the second end of the resistor R1 is connected to the first end of the resistor R1', and the second end of the resistor R1' is grounded; the positive input end of the operational amplifier OP is connected to the output voltage VCTRL, the negative input end is connected to the second end of the resistor R1 and the first end of the resistor R1', and the output end is connected to the gate end of the Power MOS tube M0; The source end of PMOS tube P0, the source end of PMOS tube P1, the source end of PMOS tube P2, and the source end of PMOS tube P3 are all connected to the source end of Power MOS tube M0, and the gate end of PMOS tube P0, the gate end of PMOS tube P1, the gate end of PMOS tube P2, and the gate end of PMOS tube P3 are connected to the control signal The drain end of the PMOS tube P0, the drain end of the PMOS tube P1, the drain end of the PMOS tube P2, and the drain end of the PMOS tube P3 are connected to the output voltage VCTRL through the resistor R, the resistor R / 2, the resistor R / 4, and the resistor R / 8 respectively; the source end of the NMOS tube N0, the source end of the NMOS tube N1, the source end of the NMOS tube N2, and the source end of the NMOS tube N3 are all grounded, the gate end of the NMOS tube N0, the gate end of the NMOS tube N1, the gate end of the NMOS tube N2, and the gate end of the NMOS tube N3 are commonly connected to the control signal DN, and the drain end of the NMOS tube N0, the drain end of the NMOS tube N1, the drain end of the NMOS tube N2, and the drain end of the NMOS tube N3 are connected to the output voltage VCTRL through the resistor R', the resistor R / 2', the resistor R / 4', and the resistor R / 8' respectively.
[0007] In one embodiment, the operational amplifier OP, the Power MOS tube M0 and the resistors R1 and R1' form an LDO, and the PMOS tubes P0, P1, P2, P3, the NMOS tubes N0, N1, N2, N3 and the resistors R, R / 2, R / 4, R / 8, the resistor R', the resistor R / 2', the resistor R / 4', and the resistor R / 8' form a charge pump circuit; the control signal , DN comes from the phase frequency detector module of the phase-locked loop, and the output voltage VCTRL is sent to the filter module of the phase-locked loop.
[0008] In one implementation, the output VL=2*VCTRL of the LDO is the power supply required by the charge pump circuit.
[0009] In one embodiment, when the control signal DN=1, NMOS tubes N0, N1, N2, and N3 are all turned on, and the pull-down current IDN=15*VCTRL / R; when the control signal =1, PMOS tubes P0, P1, P2, and P3 are all turned on, and the pull-up current IUP=15*VCTRL / R. The pull-up and pull-down currents of the charge pump circuit are changed by changing the conduction of NMOS tubes N0, N1, N2, N3 and PMOS tubes P0, P1, P2, and P3.
[0010] The present invention provides a phase-locked loop charge pump circuit. Since the circuit has only resistors and switches, current is directly generated by VCTRL / R, and no current establishment time is required. Meanwhile, only thermal noise of the resistor contributes to the phase-locked loop, thereby avoiding flicker noise of a traditional current mirror charge pump. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 The present invention provides a schematic diagram of a phase-locked loop charge pump circuit structure. DETAILED DESCRIPTION
[0012] The following is a further detailed description of a phase-locked loop charge pump circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0013] The present invention provides a phase-locked loop charge pump circuit, the structure of which is as follows Figure 1 As shown, it includes an operational amplifier OP, a resistor R1, a resistor R1', a Power MOS tube M0, a PMOS tube P0, a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, an NMOS tube N0, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3, a resistor R, a resistor R / 2, a resistor R / 4, a resistor R / 8, a resistor R', a resistor R / 2', a resistor R / 4', and a resistor R / 8'; The operational amplifier OP, the Power MOS tube M0 and the resistors R1 and R1' form an LDO, the drain end of the Power MOS tube M0 is connected to the power supply voltage VDD, and the source end is connected to the first end of the resistor R1; the second end of the resistor R1 is connected to the first end of the resistor R1', and the second end of the resistor R1' is grounded; the positive input end of the operational amplifier OP is connected to the output voltage VCTRL, the negative input end is connected to the second end of the resistor R1 and the first end of the resistor R1', and the output end is connected to the gate end of the Power MOS tube M0. The output voltage is VCTRL, and the LDO output VL=2*VCTRL is the power supply required by the charge pump.
[0014] The source end of PMOS tube P0, the source end of PMOS tube P1, the source end of PMOS tube P2, and the source end of PMOS tube P3 are all connected to the source end of Power MOS tube M0, and the gate end of PMOS tube P0, the gate end of PMOS tube P1, the gate end of PMOS tube P2, and the gate end of PMOS tube P3 are connected to the control signal , the drain of PMOS tube P0, the drain of PMOS tube P1, the drain of PMOS tube P2, and the drain of PMOS tube P3 are connected to the output voltage VCTRL through resistors R, R / 2, R / 4, and R / 8 respectively; the PMOS tube is turned on at 0, so UP=1, that is, = 0. The source end of NMOS tube N0, the source end of NMOS tube N1, the source end of NMOS tube N2, and the source end of NMOS tube N3 are all grounded, the gate end of NMOS tube N0, the gate end of NMOS tube N1, the gate end of NMOS tube N2, and the gate end of NMOS tube N3 are commonly connected to the control signal DN, and the drain end of NMOS tube N0, the drain end of NMOS tube N1, the drain end of NMOS tube N2, and the drain end of NMOS tube N3 are connected to the output voltage VCTRL through resistor R', resistor R / 2', resistor R / 4', and resistor R / 8' respectively.
[0015] PMOS tubes P0, P1, P2, P3, NMOS tubes N0, N1, N2, N3 and resistors R, R / 2, R / 4, R / 8, resistor R', resistor R / 2', resistor R / 4', resistor R / 8' form a charge pump circuit. , DN control signal comes from the phase detector (PFD) module of PLL, and the output voltage VCTRL is sent to the filter (LPF) module of PLL. When DN=1, NMOS tubes N0, N1, N2, and N3 are all turned on, the pull-down current IDN=15*VCTRL / R. =1, when PMOS tubes P0, P1, P2, and P3 are all turned on, the pull-up current IUP=15*VCTRL / R.
[0016] The phase-locked loop charge pump circuit of the present invention realizes changing the pull-up and pull-down currents of the charge pump circuit by changing whether the NMOS tubes N0, N1, N2, N3 and the PMOS tubes P0, P1, P2, P3 are turned on or off, and the charge pump is powered by an LDO circuit using VCTRL as a reference, thereby ensuring that VL-VCTRL=VCTRL and realizing IUP=IDN. In addition, since the circuit only has resistors and switches, the current is directly generated by VCTRL / R, and no current establishment time is required. At the same time, only the thermal noise of the resistor contributes to the PLL, thereby avoiding the flicker noise of the traditional current mirror charge pump.
[0017] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A phase-locked loop charge pump circuit, characterized in that: include: Operational amplifier OP, resistor R1, resistor R1', PowerMOS tube M0, PMOS tube P0, PMOS tube P1, PMOS tube P2, PMOS tube P3, NMOS tube N0, NMOS tube N1, NMOS tube N2, NMOS tube N3, resistor R, resistor R / 2, resistor R / 4, resistor R / 8, resistor R', resistor R / 2', resistor R / 4', resistor R / 8'; The drain end of the Power MOS tube M0 is connected to the power supply voltage VDD, and the source end is connected to the first end of the resistor R1; the second end of the resistor R1 is connected to the first end of the resistor R1', and the second end of the resistor R1' is grounded; the positive input end of the operational amplifier OP is connected to the output voltage VCTRL, the negative input end is connected to the second end of the resistor R1 and the first end of the resistor R1', and the output end is connected to the gate end of the Power MOS tube M0; The source end of PMOS tube P0, the source end of PMOS tube P1, the source end of PMOS tube P2, and the source end of PMOS tube P3 are all connected to the source end of PowerMOS tube M0, and the gate end of PMOS tube P0, the gate end of PMOS tube P1, the gate end of PMOS tube P2, and the gate end of PMOS tube P3 are connected to the control signal The drain end of the PMOS tube P0, the drain end of the PMOS tube P1, the drain end of the PMOS tube P2, and the drain end of the PMOS tube P3 are connected to the output voltage VCTRL through the resistor R, the resistor R / 2, the resistor R / 4, and the resistor R / 8 respectively; the source end of the NMOS tube N0, the source end of the NMOS tube N1, the source end of the NMOS tube N2, and the source end of the NMOS tube N3 are all grounded, the gate end of the NMOS tube N0, the gate end of the NMOS tube N1, the gate end of the NMOS tube N2, and the gate end of the NMOS tube N3 are commonly connected to the control signal DN, and the drain end of the NMOS tube N0, the drain end of the NMOS tube N1, the drain end of the NMOS tube N2, and the drain end of the NMOS tube N3 are connected to the output voltage VCTRL through the resistor R', the resistor R / 2', the resistor R / 4', and the resistor R / 8' respectively.
2. The phase-locked loop charge pump circuit according to claim 1, characterized in that: The operational amplifier OP, the Power MOS tube M0 and the resistors R1 and R1' form an LDO, and the PMOS tubes P0, P1, P2, P3, the NMOS tubes N0, N1, N2, N3 and the resistors R, R / 2, R / 4, R / 8, the resistor R', the resistor R / 2', the resistor R / 4' and the resistor R / 8' form a charge pump circuit; the control signal , DN comes from the phase frequency detector module of the phase-locked loop, and the output voltage VCTRL is sent to the filter module of the phase-locked loop.
3. The phase-locked loop charge pump circuit according to claim 2, characterized in that: The output VL=2*VCTRL of the LDO is the power required by the charge pump circuit.
4. The phase-locked loop charge pump circuit according to claim 2, characterized in that: When the control signal DN=1, NMOS tubes N0, N1, N2, and N3 are all turned on, and the pull-down current IDN=15*VCTRL / R; when the control signal =1, PMOS tubes P0, P1, P2, and P3 are all turned on, and the pull-up current IUP=15*VCTRL / R. The pull-up and pull-down currents of the charge pump circuit are changed by changing the conduction of NMOS tubes N0, N1, N2, N3 and PMOS tubes P0, P1, P2, and P3.