T trigger, multimode frequency divider and phase-locked loop

Abstract

The invention provides a T trigger, a multimode frequency divider and a phase-locked loop, and relates to the technical field of electronic circuits, the output end of a first D trigger is connected with the grid electrode and the drain electrode of a first triode, the reverse output end of the first D trigger is connected with the grid electrode and the drain electrode of a second triode, and the grid electrode of a sixth triode is connected with the signal input end of the T trigger; the drain electrode and the grid electrode of the third triode are connected with the source electrode of the first triode and the inverted input control end of the T trigger, the source electrode is connected with the source electrode of a fourth triode and the drain electrode of a fifth triode, the grid electrode of the fourth triode is connected with the input control end, and the grid electrode of the fifth triode is connected to the signal inverted input end of the T trigger; the drain electrode of the tail current tube is connected with the source electrode of the sixth triode and the source electrode of the fifth triode, the grid electrode is connected with bias voltage, and the source electrode is grounded; the output ends and the reverse output ends of the two-stage first D flip-flops are correspondingly connected with the input ends and the reverse input ends of the two-stage first D flip-flops, so that multi-bit mode control can be realized, and a continuous and programmable frequency division value is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a T trigger, a multi-mode frequency divider and a phase-locked loop. Background Art

[0002] Most of the D flip-flops used in traditional frequency dividers are as follows Figure 1 The CML-MS (current mode logic) master-slave D flip-flop shown in Figure 1 is a master-slave D flip-flop. Figure 1 It can be seen that the trigger is composed of a master-slave latch and a logic gate, in which the D latch unit adopts a current-type logic structure. Figure 1 M1 in the middle right is the tail current tube, biased in the saturation region, M2-M7 are three pairs of differential tubes, of which M2-M5 are switch tubes, and R1 and R2 are resistive loads. When CLK is high, M2 is turned on, M3 is turned off, M4-M5 differential tubes work, M6-M7 differential tubes do not work, and the input signal is transmitted to the output; when CLK is low, M2 is turned off, M3 is turned on, M4-M5 differential tubes do not work, and M6-M7 differential tubes are cross-coupled tubes, forming a positive feedback loop, which converts the output Q and State latch. The trigger input and output signals are differential signals, which can effectively suppress the influence of common mode noise, and the circuit can be applied to high-speed clock circuits, but there is static power consumption.

[0003] Figure 2 The 2 / 3 divider is composed of 2 Figure 1 The circuit is composed of a D flip-flop, an AND gate, and an OR gate. When the mode control terminal is 1, the output of the OR gate is always 1, the first D flip-flop fails, and the circuit is equivalent to a 2-frequency division circuit; when the mode control terminal is 0, Q1 is directly connected to one input of the AND gate, and the circuit is equivalent to a 3-frequency division circuit. Therefore, the circuit can achieve 2 or 3 frequency division of the input clock by setting the mode control terminal to 0 or 1. The maximum operating frequency of the circuit depends on the path delay of the AND gate, plus the path delay and setup time of the next-stage D flip-flop, because it is necessary to ensure that all nodes affected by the previous clock are established before the next clock arrives.

[0004] Figure 3 The 8 / 9 divider is composed of a 2 / 3 divider and two 2 dividers in series, where the 2 divider also uses Figure 1 D flip-flop. When the mode control is 1, the 2 / 3 divider achieves 2-division, and three 2-dividers are connected in series to achieve 8-division; when the mode control is 0, the 2 / 3 divider achieves 3-division, and the overall frequency division is 9. Similarly, when more 2-dividers are connected in series in the above structure, a dual-mode divider with a higher division ratio can be achieved, but at the same time, the maximum operating frequency of the input also decreases with the increase of cascaded logic gates.

[0005] It can be seen that the above two dual-mode dividers can only achieve limited frequency division ratios due to the 1-bit mode control bit, which limits the application scenarios of this dual-mode divider. Furthermore, when more D flip-flops are connected in series, more logic gates are required for control, which leads to an increase in feedback path delay, thereby limiting the maximum input frequency of the divider. In addition, since multiple stages of D flip-flops are connected in series instead of being synchronously triggered by the input clock, the output clock of this dual-mode divider will accumulate multiple stages of clock jitter and delay. Summary of the invention

[0006] In view of the problems existing in the prior art, the present invention provides a T trigger, comprising two-stage trigger circuits, each stage of the trigger circuit comprising:

[0007] A first D flip-flop, an output end of which is connected to the gate and drain of the first triode, a reverse output end of which is connected to the gate and drain of the second triode, and a gate of the sixth triode of the first D flip-flop is connected to a signal input end of the T flip-flop;

[0008] A third triode, the drain and the gate are respectively connected to the source of the first triode and the inverting input control terminal of the T flip-flop, the source of the third triode is respectively connected to the source of the fourth triode and the drain of the fifth triode, the gate of the fourth triode is connected to the input control terminal, and the gate of the fifth triode is connected to the signal inverting input terminal of the T flip-flop;

[0009] A tail current tube, the drain of which is respectively connected to the source of the sixth transistor of the first D flip-flop and the source of the fifth transistor, the gate of the tail current tube is connected to a bias voltage, and the source of the tail current tube is grounded;

[0010] The output terminal and the inverting output terminal of the first D flip-flop of the trigger circuit of the previous stage are respectively used as the input terminal and the inverting input terminal of the first D flip-flop of the trigger circuit of the next stage;

[0011] The output end and the reverse output end of the first D trigger of the trigger circuit of the next stage serve as the inverting input end and the input end of the first D trigger of the trigger circuit of the previous stage respectively, and are connected to the reverse output end and the output end of the T trigger respectively.

[0012] Preferably, it further comprises an input control word, wherein the input control word is connected to the reverse input control terminal through a first NOT gate, and the output of the first NOT gate is connected to the input control terminal through a second NOT gate.

[0013] Preferably, the inverting output end of the first D flip-flop of the trigger circuit of the next stage is connected to the output end of the T flip-flop through a third NOT gate and a fourth NOT gate connected in series;

[0014] The output end of the first D trigger of the trigger circuit of the next stage is connected to the inverting output end of the T trigger through the fifth NOT gate and the sixth NOT gate connected in series.

[0015] Preferably, the first D flip-flop comprises:

[0016] a seventh triode, wherein the drain of the seventh triode is connected to the inverting output terminal of the first D flip-flop and is connected to the working power supply through the first resistor, the source of the seventh triode is respectively connected to the source of the eighth triode and the drain of the ninth triode, the gate of the seventh triode is connected to the input terminal of the first D flip-flop, the drain of the eighth triode is connected to the working power supply through the second resistor, the gate of the eighth triode is connected to the inverting input terminal of the first D flip-flop, and the source of the ninth triode is connected to the drain of the sixth triode;

[0017] a thirteenth transistor, wherein the drain of the thirteenth transistor is connected to the inverting output terminal of the first D flip-flop and the gate of the eleventh transistor, and the gate of the thirteenth transistor is connected to the output terminal of the first D flip-flop and the drain of the eleventh transistor;

[0018] a twelfth triode, the drain of the twelfth triode being connected to the source of the thirteenth triode and the source of the eleventh triode respectively, and the source of the twelfth triode being connected to the drain of the sixth triode;

[0019] The gate of the ninth transistor of the first D trigger of the previous stage and the gate of the twelfth transistor of the first D trigger of the next stage are connected to the reverse clock end of the T trigger, and the gate of the twelfth transistor of the first D trigger of the previous stage and the gate of the ninth transistor of the first D trigger of the next stage are connected to the clock end of the T trigger.

[0020] The present invention also provides a multi-mode frequency divider, comprising the above-mentioned T flip-flop, wherein the T flip-flops are multiple, the multiple T flip-flops are connected in series in sequence, and the input control terminals of the respective T flip-flops are connected to the respective bits of the input control word from low to high in sequence in the series connection order;

[0021] The reverse output terminal of the first T flip-flop is connected to the clock terminal of the second T flip-flop, and the clock terminal of the first T flip-flop is connected to the external clock signal;

[0022] It also includes a second D flip-flop, the output end of the second D flip-flop is the output end of the multi-mode frequency divider, the inverting output end of the second D flip-flop and the output ends of each of the T flip-flops are used as inputs of an AND gate circuit, and the output of the AND gate circuit is connected to the input end of the second D flip-flop;

[0023] The clock terminal of the second D flip-flop is connected to the external clock signal, and the inverting output terminal of the second D flip-flop is connected to the signal input terminal of each of the T flip-flops.

[0024] Preferably, the number of the T flip-flops is n, and the multi-mode frequency divider implements 2 to 2 n -1 continuous division.

[0025] Preferably, it further comprises a multiplexer, wherein a data input end of the multiplexer is connected to an output end of the second D flip-flop, an output end of the multiplexer is an output end of the multi-mode frequency divider, and the multiplexer is also connected to the external clock signal;

[0026] Each bit of the input control terminal is connected to the selection input terminal of the multiplexer through a logic signal processing circuit;

[0027] The logic signal processing circuit is used for outputting 1 when only the lowest bit is 1, and outputting 0 otherwise.

[0028] Preferably, the logic signal processing circuit comprises:

[0029] a seventh NOT gate, wherein an input of the seventh NOT gate is connected to the least significant bit;

[0030] The NOR gate circuit is connected to the output of the seventh NOT gate and the remaining bits except the lowest bit, and is used to perform an OR operation on the output of the seventh NOT gate and the remaining bits except the lowest bit, and then connect the result of the NOR operation to the selection input end of the multiplexer.

[0031] Preferably, the number of the T triggers is n, and the multi-mode frequency divider implements 1 to 2 n -1 continuous division.

[0032] The present invention also provides a phase-locked loop, comprising the above-mentioned multi-mode frequency divider, wherein the multi-mode frequency divider comprises an R frequency divider and an N frequency divider, and the outputs of the R frequency divider and the N frequency divider are connected to a frequency detector and a phase detector;

[0033] The frequency detector and phase detector are used to receive a reference frequency obtained by dividing the reference frequency provided by the connected crystal oscillator by R and an output frequency close to the reference frequency output by the N frequency divider, and process the error voltage signal obtained according to the phase difference between the reference frequency and the output frequency and output it to the connected loop filter;

[0034] The loop filter is used to filter the error voltage signal and then output it to the control end of the connected voltage controlled oscillator, so that the voltage controlled oscillator outputs a stable frequency signal;

[0035] The N frequency divider is connected to the output end of the voltage controlled oscillator and is used for dividing the frequency signal by N to obtain the output frequency which is fed back to the frequency detector and phase detector.

[0036] The above technical solution has the following advantages or beneficial effects:

[0037] 1) The T flip-flop based on the present invention can realize multi-bit mode control, thereby realizing continuous and programmable frequency division value;

[0038] 2) The maximum input frequency of the multi-mode divider of the present invention depends on the delay of the feedback path formed by the AND gate circuit and the second trigger, and the delay is only the path delay of the first-level D trigger and the logic AND gate and the setup time of the D trigger. The delay will not increase with the increase of T flip-flops in series, so its maximum input frequency will not be affected. Under the 40nm process, the maximum input frequency of the multi-mode divider can reach 6.5GHz.

[0039] 3) The multi-mode frequency divider of the present invention can realize continuous frequency division from 1 to 255.

[0040] 4) The final stage of the multi-mode frequency divider of the present invention resamples the output signal with the input clock through the second D flip-flop to eliminate the jitter and delay of the cascaded multi-stage clocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is the circuit schematic diagram of the existing CML-MS master-slave D flip-flop;

[0042] Figure 2 It is the circuit block diagram of the existing 2 / 3 frequency divider;

[0043] Figure 3 It is the circuit block diagram of the existing 8 / 9 frequency divider;

[0044] Figure 4 A circuit schematic diagram of a T trigger in a preferred embodiment of the present invention;

[0045] Figure 5 FIG. 1 is an equivalent schematic diagram of a T flip-flop in a preferred embodiment of the present invention;

[0046] Figure 6 A circuit block diagram of a multi-mode frequency divider in a preferred embodiment of the present invention;

[0047] Figure 7 A circuit block diagram of a three-mode frequency divider in a preferred embodiment of the present invention;

[0048] Figure 8 A circuit block diagram of a logic signal processing circuit in a preferred embodiment of the present invention;

[0049] Fig. 9 FIG. 1 is a circuit block diagram of a phase-locked loop in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0050] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and other embodiments may also fall within the scope of the present invention as long as they conform to the gist of the present invention.

[0051] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a T trigger is provided. Figure 4 and Figure 5 As shown, it includes two-stage trigger circuits, and each stage of the trigger circuit includes:

[0052] The first D flip-flop D1, the output end is connected to the gate and drain of the first transistor M1, the reverse output end is connected to the gate and drain of the second transistor M2, and the gate of the sixth transistor M6 of the first D flip-flop D1 is connected to the signal input end T of the T flip-flop;

[0053] The drain and gate of the third transistor M3 are respectively connected to the source of the first transistor M1 and the inverting input control terminal of the T trigger. The source of the third transistor M3 is connected to the source of the fourth transistor M4 and the drain of the fifth transistor M5 respectively, the gate of the fourth transistor M4 is connected to the input control terminal W, and the gate of the fifth transistor M5 is connected to the signal inverting input terminal of the T trigger

[0054] The tail current tube M has its drain connected to the source of the sixth transistor M6 and the source of the fifth transistor M5 of the first D flip-flop D1, and the gate of the tail current tube M is connected to the bias voltage V bias , the source of the tail current tube M is grounded;

[0055] The output terminal and the inverting output terminal of the first D flip-flop D1 of the previous stage trigger circuit are respectively used as the input terminal and the inverting input terminal of the first D flip-flop D1 of the next stage trigger circuit;

[0056] The output terminal and the reverse output terminal of the first D flip-flop D1 of the next stage trigger circuit are respectively used as the inverting input terminal and the input terminal of the first D flip-flop D1 of the previous stage trigger circuit, and are respectively connected to the reverse output terminal of the T flip-flop. and output terminal Q.

[0057] In a preferred embodiment of the present invention, it also includes an input control word Wn, and the input control word Wn is connected to the reverse input control terminal through the first NOT gate N1. The output of the first NOT gate N1 is connected to the input control terminal W through the second NOT gate N2.

[0058] In a preferred embodiment of the present invention, the inverting output terminal of the first D flip-flop D1 of the subsequent trigger circuit is connected to the output terminal Q of the T flip-flop through the third NOT gate N3 and the fourth NOT gate N4 connected in series;

[0059] The output end of the first D flip-flop of the next stage trigger circuit is connected to the reverse output end of the T flip-flop through the fifth NOT gate N5 and the sixth NOT gate N6 connected in series.

[0060] In a preferred embodiment of the present invention, the first D flip-flop D1 comprises:

[0061] a seventh transistor M7, wherein the drain of the seventh transistor M7 is connected to the inverting output terminal of the first D flip-flop D1 and is connected to the working power supply through the first resistor R1, the source of the seventh transistor M7 is respectively connected to the source of the eighth transistor M8 and the drain of the ninth transistor M9, the gate of the seventh transistor M7 is connected to the input terminal of the first D flip-flop D1, the drain of the eighth transistor M8 is connected to the working power supply VDD through the second resistor R2, the gate of the eighth transistor M8 is connected to the inverting input terminal of the first D flip-flop D1, and the source of the ninth transistor M9 is connected to the drain of the sixth transistor M6;

[0062] a thirteenth transistor M10, wherein the drain of the thirteenth transistor M10 is connected to the inverting output terminal of the first D flip-flop D1 and the gate of the eleventh transistor M11, and the gate of the thirteenth transistor M10 is connected to the output terminal of the first D flip-flop D1 and the drain of the eleventh transistor M11;

[0063] a twelfth triode M12, wherein the drain of the twelfth triode M12 is respectively connected to the source of the thirteenth triode M10 and the source of the eleventh triode M11, and the source of the twelfth triode M12 is connected to the drain of the sixth triode M6;

[0064] The gate of the ninth transistor M9 of the first D flip-flop D1 of the previous stage and the gate of the twelfth transistor M12 of the first D flip-flop D1 of the next stage are connected to the reverse clock terminal of the T flip-flop. The gate of the twelfth transistor M12 of the first D flip-flop D1 of the previous stage and the gate of the ninth transistor M9 of the first D flip-flop D1 of the next stage are connected to the clock terminal CLK of the T flip-flop.

[0065] Specifically, in this embodiment, the T flip-flop of the present invention is modified and innovated based on the traditional CML master-slave D flip-flop. This T flip-flop is also the basic unit of the high-speed continuous programmable frequency divider. Figure 4 In the CLK and are a pair of input clocks with opposite phases, and T and is a pair of input signals with opposite phases, Wn is the input control word, Q and is a pair of opposite output signals, the tail current tube M is a bias current tube, working in the saturation region. When the input signal T = 1, When the sixth transistors M6 of the two first D flip-flops D1 are turned on, the fifth transistors M5 in the previous trigger circuit and the next trigger circuit are turned off, so Figure 4 The circuit in the dotted box is activated and acts as a traditional D latch. At this time, the T flip-flop can be equivalent to a CML master-slave D flip-flop. Because the output signal of the first D flip-flop D1 of the next stage is connected to the gates of the seventh transistor M7 and the eighth transistor M8 of the first D flip-flop of the previous stage (i.e., the D input terminal of the traditional D flip-flop), the T flip-flop can be equivalent to a 2-frequency division circuit composed of D flip-flops. When the input signal T=0, When the sixth transistors M6 of the two first D triggers D1 are turned off, the fifth transistors M5 in the previous trigger circuit and the next trigger circuit are turned on, so Figure 4 The circuit in the dotted box is closed. At this time, the output of the T flip-flop will not change with the change of the input clock CLK, but is directly determined by the input control word Wn. When the input control word Wn is 1, the output Q is 0; when the input control word Wn is 0, the output Q is 1. Among them, the first transistor M1 and the second transistor M2 in the first D flip-flop of the previous stage and the first D flip-flop of the next stage are diode-connected transistors, which are used to balance the voltage drops of the seventh transistor M7, the eighth transistor M8, the tenth transistor M10 and the eleventh transistor M11 in the corresponding first D flip-flop D1. Therefore, the functional equivalent diagram of the T flip-flop of the present invention is as follows Figure 5 As shown, when the input signal Tn of the T flip-flop is 0, the T flip-flop is equivalent to the input control word Wn accessing the output signal Qn of the T flip-flop through a NOT gate, that is, the output of the T flip-flop is determined by the input control word. When the input signal Tn of the T flip-flop is 1, the T flip-flop is equivalent to a CML master-slave D flip-flop, and the inverting output terminal of the CML master-slave D flip-flop is connected to the D input terminal.

[0066] Based on this T trigger, a multi-mode frequency divider can be constructed, which is a high-speed, continuously programmable frequency divider. Specifically, the present invention also provides a multi-mode frequency divider, such as Figure 6 As shown, it includes the above-mentioned T flip-flop, there are multiple T flip-flops, the multiple T flip-flops are connected in series in sequence, and the input control terminal W of each T flip-flop is connected to each bit of the input control word Wn from low to high in sequence according to the series connection order;

[0067] The inverting output terminal of the previous T flip-flop The clock terminal CLK of the next T flip-flop is connected, and the clock terminal CLK of the first T flip-flop is connected to the external clock signal CP;

[0068] The second D flip-flop D2 has an output terminal OUT ， The output terminal of the multi-mode frequency divider and the inverting output terminal of the second D flip-flop D2 And the output terminal Q of each T flip-flop is used as the input of the AND gate circuit, and the output of the AND gate circuit is connected to the input terminal of the second D flip-flop D2;

[0069] The clock terminal CLK of the second D flip-flop D2 is connected to the external clock signal CP, and the inverting output terminal of the second D flip-flop D2 is connected to the external clock signal CP. Connect to the signal input terminal T of each T flip-flop.

[0070] Specifically, in this implementation, the specific circuit structure of the AND gate circuit is not limited, and it is only necessary to realize the ability to perform the operation on each odd bit (the first bit W 0、 The third bit W 2， and so on) connected to the output signal Q of the T flip-flop and the inverting output terminal of the second D flip-flop D2 When n=3, we only need to AND the first bit W. 0、 The output signal Q of the T flip-flop connected to the third bit W2 and Just perform an AND operation.

[0071] In a preferred embodiment of the present invention, there are n T flip-flops, and the multi-mode frequency divider realizes 2 to 2 n -1 continuous division.

[0072] Specifically, in this embodiment, taking n=3 as an example, Figure 7 As shown, the three-mode frequency divider can achieve continuous frequency division from 2 to 7. The input control word Wn corresponds to three bits, namely W2W1W0, the external clock signal CP is the input clock, Q0 and Q2 are the output of the T flip-flop connected to W0 and the output of the T flip-flop connected to W2, respectively, and OUT is the output of the three-mode frequency divider. Figure 7 The second D flip-flop D2 in the final stage of the circuit outputs OUT through the external clock signal CP. ， Resampling is performed to eliminate the time jitter accumulated in the link. The output of the three-mode divider It is then fed back to the input of the AND gate to form a feedback loop. The path delay of this feedback loop (i.e., the path delay of the signal through an AND gate, a D flip-flop and the setup time of the D flip-flop) determines the maximum frequency of the normal operation of the three-mode divider.

[0073] The following will introduce the functions of the above three-mode frequency divider in detail in conjunction with the state change table. To achieve the 2-frequency division of the input clock, the input control word W2W1W0 can be set to 010, and assuming that the initial state of the output signal OUT is 1, the states of each node of the three-mode frequency divider are shown in Table 1 below. Each row in Table 1 represents the output result of each node when a rising edge of the external clock signal CP arrives.

[0074] Table 1 When W2W1W0=010, the status table of each node of the three-mode divider

[0075]

[0076] As can be seen from Table 1, the output OUT of the three-mode frequency divider flips from 0 to 1 with the rising edge of the input external clock signal CP, thereby realizing the frequency division of the input clock by 2. When the input control word W2W1W0=011, and assuming that the initial state of the output signal OUT is 1, similarly, the states of each node of the three-mode frequency divider can be obtained as shown in Table 2. As can be seen from Table 2, when the input external clock signal CP has the fourth rising edge, the output OUT of the three-mode frequency divider changes back to the initial state 1, and the states of each node in the circuit are consistent with the first rising edge, thereby realizing the frequency division of the input clock by 3.

[0077] Table 2 When W2W1W0=011, the status table of each node of the 3-level divider

[0078]

[0079] When the input control word W2W1W0=100, and assuming that the initial state of the output signal OUT is 1, the states of the nodes of the three-mode frequency divider are shown in Table 3. As can be seen from Table 3, when the fifth rising edge appears on the input, the output OUT of the three-mode frequency divider returns to the initial state 1, and the states of the nodes in the circuit are consistent with the first rising edge, thereby achieving a 4-frequency division of the input clock.

[0080] Table 3 When W2W1W0=100, the status table of each node of the 3-level divider

[0081]

[0082] When the input control words W2W1W0=101, W2W1W0=110 and W2W1W0=111, this three-mode frequency divider can achieve 5, 6, and 7 frequency divisions respectively. The specific analysis method is the same as above and will not be repeated here.

[0083] According to the above analysis, when more T flip-flops are connected in series, more frequency division values ​​can be achieved. When n T flip-flops are connected in series, 2 to 2 n -1 continuous division.

[0084] Furthermore, in a preferred embodiment of the present invention, a multiplexer MUX is further included, wherein a data input terminal of the multiplexer MUX is connected to an output terminal of the second D flip-flop D2, an output terminal of the multiplexer MUX is an output terminal OUT of the multi-mode frequency divider, and the multiplexer MUX is also connected to an external clock signal CP;

[0085] Each bit of the input control terminal Wn is connected to the selection input terminal MUX_SEL of the multiplexer MUX through a logic signal processing circuit;

[0086] The logic signal processing circuit is used to output 1 when only the lowest bit is 1, otherwise it outputs 0.

[0087] Specifically, Figure 7 different, Figure 6 In the example, a multiplexer MUX is connected in series after the second D flip-flop D2, preferably a 21 selector. When only the last bit W0 of the input control word Wn is 1 and the rest are all 0, MUX_SEL=1, so the 21 selector selects CP output to achieve 1 frequency division. Finally, the frequency divider can achieve 1 to 2 n -1 continuous division.

[0088] In a preferred embodiment of the present invention, Figure 8 As shown, the logic signal processing circuit includes:

[0089] A seventh NOT gate N7, an input of which is connected to the least significant bit W0;

[0090] The NOR gate circuit is connected to the output of the seventh NOT gate N7 and the remaining bits except the lowest bit W0, and is used to perform an OR operation on the output of the seventh NOT gate N7 and the remaining bits except the lowest bit W0, and then connect the result of the NOR operation to the selection input terminal MUX_SEL of the multiplexer.

[0091] Specifically, Figure 8 The NOR gate circuit includes bit W1 and bit W0 as inputs of an AND gate, bit W2 and bit W3 as inputs of an AND gate, and so on, and the outputs of each AND gate are used as inputs of the next level AND gate, until the outputs of the two AND gates of the last level are used as inputs of a NAND gate, and the outputs of the NAND gate are connected to the selection input terminal MUX_SEL of the multiplexer. It can be understood that the above only gives one circuit structure of the NOR gate circuit, but it is not limited to this.

[0092] In a preferred embodiment of the present invention, there are n T flip-flops, and the multi-mode frequency divider implements 1 to 2 n -1 continuous division.

[0093] The present invention also provides a phase-locked loop, such as Fig. 9 As shown, it includes the above-mentioned multi-mode frequency divider, the multi-mode frequency divider includes an R frequency divider and an N frequency divider, and the outputs of the R frequency divider and the N frequency divider are connected to the frequency detector and phase detector;

[0094] The frequency detector is used to receive the reference frequency f provided by the crystal oscillator connected to the R divider. osc The reference frequency f obtained by dividing by R ref , and the N divider output is close to the reference frequency f ref The output frequency f fb , and according to the reference frequency f ref and the output frequency f fb The phase difference between them is processed to obtain an error voltage signal which is output to a connected loop filter;

[0095] The loop filter is used to filter the error voltage signal and output it to the control end of the connected voltage controlled oscillator, so that the voltage controlled oscillator outputs a stable frequency signal f out ;

[0096] The N divider is connected to the output of the voltage controlled oscillator to convert the frequency signal f out Divide by N to get the output frequency f fb Feedback to the frequency detector.

[0097] Specifically, the frequency divider plays an important role in the phase-locked loop. Fig. 9 The R divider and the N divider can both adopt the high-speed, continuously programmable multi-mode divider designed by the present invention. The R divider can divide the crystal oscillator frequency, and the output frequency obtained by the frequency division is used as the reference frequency of the phase-locked loop, while the N divider can directly divide the high-frequency VCO signal to a frequency close to the reference signal.

[0098] Since the maximum input frequency of the multi-mode frequency divider of the present invention depends on the delay of the feedback path, and the delay is only the path delay of the first-level D flip-flop and the logic AND gate and the setup time of the D flip-flop. Its delay will not increase with the increase of T flip-flops in series, so its maximum input frequency will not be affected basically. Under the 40nm process, the maximum input frequency of the multi-mode frequency divider of the present invention can reach 6.5GHz, and continuous programmable frequency division can be achieved, so the multi-mode frequency divider of the present invention can be used in the phase-locked loop system of the radio frequency front end of communication such as BLE, WiFi, Sub-1G. In addition, for clock chips that require multiple frequency points, the multi-mode frequency divider of the present invention can also meet any frequency division requirements>1. Under the above conditions, continuous frequency division from 1 to 255 can be achieved.

[0099] Furthermore, the final stage of the multi-mode frequency divider of the present invention resamples the output signal using the input clock through a D flip-flop to eliminate the jitter and delay of the cascaded multi-stage clocks.

[0100] The multi-mode frequency divider of the present invention is very easy to use, and only needs to configure the input control word to achieve the corresponding frequency division of the input clock.

[0101] The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. A T trigger, characterized in that: It includes two stages of trigger circuits, each stage of the trigger circuit includes: A first D flip-flop, an output end of which is connected to the gate and drain of the first triode, a reverse output end of which is connected to the gate and drain of the second triode, and a gate of the sixth triode of the first D flip-flop is connected to a signal input end of the T flip-flop; A third triode, the drain and the gate are respectively connected to the source of the first triode and the inverting input control terminal of the T flip-flop, the source of the third triode is respectively connected to the source of the fourth triode and the drain of the fifth triode, the gate of the fourth triode is connected to the input control terminal, and the gate of the fifth triode is connected to the signal inverting input terminal of the T flip-flop; A tail current tube, the drain of which is respectively connected to the source of the sixth transistor of the first D flip-flop and the source of the fifth transistor, the gate of the tail current tube is connected to a bias voltage, and the source of the tail current tube is grounded; The output terminal and the inverting output terminal of the first D flip-flop of the trigger circuit of the previous stage are respectively used as the input terminal and the inverting input terminal of the first D flip-flop of the trigger circuit of the next stage; The output end and the reverse output end of the first D trigger of the trigger circuit of the next stage serve as the inverting input end and the input end of the first D trigger of the trigger circuit of the previous stage respectively, and are connected to the reverse output end and the output end of the T trigger respectively.

2. The T flip-flop according to claim 1, characterized in that: It also includes an input control word, the input control word is connected to the reverse input control terminal through a first NOT gate, and the output of the first NOT gate is connected to the input control terminal through a second NOT gate.

3. The T flip-flop according to claim 1, characterized in that: The inverting output end of the first D flip-flop of the trigger circuit of the next stage is connected to the output end of the T flip-flop through a third NOT gate and a fourth NOT gate connected in series; The output end of the first D trigger of the trigger circuit of the next stage is connected to the inverting output end of the T trigger through the fifth NOT gate and the sixth NOT gate connected in series.

4. The T flip-flop according to claim 1, characterized in that: The first D flip-flop comprises: a seventh triode, wherein the drain of the seventh triode is connected to the inverting output terminal of the first D flip-flop and is connected to the working power supply through the first resistor, the source of the seventh triode is respectively connected to the source of the eighth triode and the drain of the ninth triode, the gate of the seventh triode is connected to the input terminal of the first D flip-flop, the drain of the eighth triode is connected to the working power supply through the second resistor, the gate of the eighth triode is connected to the inverting input terminal of the first D flip-flop, and the source of the ninth triode is connected to the drain of the sixth triode; a thirteenth transistor, wherein the drain of the thirteenth transistor is connected to the inverting output terminal of the first D flip-flop and the gate of the eleventh transistor, and the gate of the thirteenth transistor is connected to the output terminal of the first D flip-flop and the drain of the eleventh transistor; a twelfth triode, the drain of the twelfth triode being connected to the source of the thirteenth triode and the source of the eleventh triode respectively, and the source of the twelfth triode being connected to the drain of the sixth triode; The gate of the ninth transistor of the first D trigger of the previous stage and the gate of the twelfth transistor of the first D trigger of the next stage are connected to the reverse clock end of the T trigger, and the gate of the twelfth transistor of the first D trigger of the previous stage and the gate of the ninth transistor of the first D trigger of the next stage are connected to the clock end of the T trigger.

5. A multi-mode frequency divider, characterized in that: The method comprises a T flip-flop as claimed in any one of claims 1 to 4, wherein the number of the T flip-flops is multiple, the multiple T flip-flops are connected in series in sequence, and the input control terminals of the respective T flip-flops are connected to the respective bits of the input control word from low to high in sequence in the series connection order; The reverse output terminal of the first T flip-flop is connected to the clock terminal of the second T flip-flop, and the clock terminal of the first T flip-flop is connected to the external clock signal; It also includes a second D flip-flop, the output end of the second D flip-flop is the output end of the multi-mode frequency divider, the inverting output end of the second D flip-flop and the output ends of each of the T flip-flops are used as inputs of an AND gate circuit, and the output of the AND gate circuit is connected to the input end of the second D flip-flop; The clock terminal of the second D flip-flop is connected to the external clock signal, and the inverting output terminal of the second D flip-flop is connected to the signal input terminal of each of the T flip-flops.

6. The multi-mode frequency divider according to claim 5, characterized in that: The number of the T flip-flops is n, and the multi-mode frequency divider realizes 2 to 2 n -1 continuous division.

7. The multi-mode frequency divider according to claim 5, characterized in that: It also includes a multiplexer, wherein a data input end of the multiplexer is connected to an output end of the second D flip-flop, an output end of the multiplexer is an output end of the multi-mode frequency divider, and the multiplexer is also connected to the external clock signal; Each bit of the input control terminal is connected to the selection input terminal of the multiplexer through a logic signal processing circuit; The logic signal processing circuit is used for outputting 1 when only the lowest bit is 1, and outputting 0 otherwise.

8. The multi-mode frequency divider according to claim 7, characterized in that: The logic signal processing circuit comprises: a seventh NOT gate, wherein an input of the seventh NOT gate is connected to the least significant bit; The NOR gate circuit is connected to the output of the seventh NOT gate and the remaining bits except the lowest bit, and is used to perform an OR operation on the output of the seventh NOT gate and the remaining bits except the lowest bit, and then connect the result of the NOR operation to the selection input end of the multiplexer.

9. The multi-mode frequency divider according to claim 7, characterized in that: The number of the T flip-flops is n, and the multi-mode frequency divider implements 1 to 2 n -1 continuous division.

10. A phase-locked loop, characterized in that: The multi-mode frequency divider comprises the multi-mode frequency divider as claimed in claim 5, wherein the multi-mode frequency divider comprises an R frequency divider and an N frequency divider, and the outputs of the R frequency divider and the N frequency divider are connected to a frequency detector and a phase detector; The frequency detector and phase detector are used to receive a reference frequency obtained by dividing the reference frequency provided by the connected crystal oscillator by R and an output frequency close to the reference frequency output by the N frequency divider, and process the error voltage signal obtained according to the phase difference between the reference frequency and the output frequency and output it to the connected loop filter; The loop filter is used to filter the error voltage signal and then output it to the control end of the connected voltage controlled oscillator, so that the voltage controlled oscillator outputs a stable frequency signal; The N frequency divider is connected to the output end of the voltage controlled oscillator and is used for dividing the frequency signal by N to obtain the output frequency which is fed back to the frequency detector and phase detector.

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