Multi-sampling SS-ADC circuit and module based on slope noise adaptation

Abstract

The present invention relates to the technical field of image sensor design, and in particular to a multi-sampling SS-ADC circuit and module based on slope noise adaptation. The SS-ADC circuit of the present invention comprises: a common slope generating unit DAC_H, a low-noise slope generating unit DAC_L, a comparator unit COMP, a judgment logic unit LOGIC, two counting units COUNTER1~COUNTER2, and a selection output unit SELECT. The present invention adds a low-noise slope generating unit DAC_L to provide a quantization ramp signal RAMP_L used in low-light conditions, and selects different quantization ramp signals to execute CCMS technology by judging the lighting conditions, thereby effectively reducing the horizontal noise generated by the slope noise in the quantization process in low-light conditions. The present invention solves the problem that the existing CCMS technology cannot reduce the horizontal noise when applied to ADC.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensor design, and more specifically to: 1. a multi-sampling SS-ADC circuit based on slope noise adaptation; 2. a multi-sampling SS-ADC module based on slope noise adaptation. Background Art

[0002] Image sensors (CMOS image sensors, CIS) have the advantages of easy integration and small size, and are widely used in smart phones, security monitoring, medical imaging and other fields. In recent years, the performance requirements of CIS in different usage scenarios have become increasingly higher. Especially in low-light environments, CIS needs to have extremely high noise suppression capabilities to ensure image quality. The analog-to-digital converter (ADC) is an important component of CIS, so noise reduction of CIS can be converted into noise reduction of ADC.

[0003] Existing noise reduction technologies for ADC mainly focus on sampling technologies, such as Correlated Double Sampling (CDS) technology and Correlated Multiple Sampling (CMS) technology.

[0004] Among them, CDS technology is to convert the voltage signal V generated by the pixel signal in the reset stage and the exposure stage rst 、V sig By sampling and subtracting, CDS can eliminate the fixed pattern noise (FPN) caused by the process and the thermal noise caused by pixel reset. Since CDS technology has limited noise reduction effect, CMS technology came into being. CMS technology is a V rst and V sig Multiple sampling is averaged and then the difference is made. Compared with CDS technology, CMS technology can not only eliminate FPN and KTC noise in pixels, but also effectively reduce thermal noise, flicker noise (its noise power is inversely proportional to the frequency, so it is also called 1 / f noise) and random telegraph signal (RTS) noise. However, CMS technology increases the number of sampling times and also increases the quantization time of ADC, thus reducing the frame rate of CIS.

[0005] Therefore, the inventors considered applying the Conditional Correlated Multiple Sampling (CCMS) technology to the ADC, but found that the following problems would exist:

[0006] CCMS technology will first determine whether the external environment is strong light or weak light. In weak light, due to the actual pixel signal V pixel The change in is small, and the random noise has a greater impact on the signal. Therefore, a short-time small voltage range ramp is used to sample and quantize the pixel signal multiple times; in strong light conditions, the noise is mainly photon shot noise, which cannot be reduced by CMS technology, so a long full voltage range ramp is used to sample and quantize the pixel signal once. However, CCMS technology cannot reduce the global random noise of the ramp signal. The ramp noise is irrelevant during each sampling and quantization of the pixel signal, so the operation of averaging multiple samples cannot reduce the ramp noise. This results in: in low light conditions, the ramp noise will cause different offsets in the quantization signal of each column of ADC, which will cause the image to produce horizontal stripes of varying light and dark, seriously damaging the image quality. This inter-column signal inconsistency caused by ramp noise in low light conditions is also called horizontal noise. In strong light conditions, the noise is mainly photon shot noise, and horizontal noise can be ignored compared to photon shot noise. Summary of the invention

[0007] Based on this, it is necessary to provide a multi-sampling SS-ADC circuit and module based on slope noise adaptation to address the problem that the existing CCMS technology cannot reduce horizontal noise in ADC.

[0008] The present invention is implemented by the following technical solutions:

[0009] In a first aspect, the present invention provides a multi-sampling SS-ADC circuit based on slope noise adaptation, for IN The changes after the pixel reset stage, judgment stage, and pixel exposure stage are quantized to 10 bits.

[0010] The multi-sampling SS-ADC circuit based on slope noise adaptation includes: a normal slope generating unit DAC_H, a low noise slope generating unit DAC_L, a comparator unit COMP, a judgment logic unit LOGIC, two counting units COUNTER1~COUNTER2, and a selection output unit SELECT.

[0011] DAC_H is used to provide a quantized ramp signal RAMP_H used in strong light conditions;

[0012] DAC_L is used to provide a quantized ramp signal RAMP_L used in low light conditions;

[0013] COMP is used to: In the pixel reset phase, RAMP_H, RAMP_L and V IN Compare and obtain the control signal CN1; in the judgment stage, the reference voltage V REF With VIN Compare and obtain the judgment signal CN2; in the pixel exposure stage, RAMP_H or RAMP_L is compared with V IN Compare and obtain the control signal CN3;

[0014] LOGIC is used to determine the quantization ramp signal used by COMP in the pixel exposure stage according to CN2, and generate the control signal Logic1 for COUNTER1 and the control signal Logic2 for COUNTER2;

[0015] COUNTER1 is used to combine CN1, CN3, and Logic1 for 10-bit quantization to obtain the reference quantization value D1[9:0] in low-light conditions;

[0016] COUNTER2 is used to combine CN1, CN3, and Logic2 to perform 10-bit quantization to obtain the reference quantization value D2[9:0] under strong light conditions;

[0017] SELECT is used to selectively process D1[9:0] and D2[9:0] according to Logic1 to output the final 10-bit quantization result OUT[9:0].

[0018] The implementation of the multi-sampling SS-ADC circuit based on slope noise adaptation is a method or process according to an embodiment of the present disclosure.

[0019] In a second aspect, the present invention discloses a multi-sampling SS-ADC module based on slope noise adaptation, which adopts the layout of a multi-sampling SS-ADC circuit based on slope noise adaptation disclosed in the first aspect.

[0020] The implementation of the multi-sampling SS-ADC module based on slope noise adaptation is a method or process according to an embodiment of the present disclosure.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] 1. The present invention designs a low-noise ramp generating unit DAC_L to provide a quantized ramp signal RAMP_L used in weak light conditions, and designs a judgment logic unit LOGIC to select different quantized ramp signals and a counting unit to perform CCMS technology according to the comparison results of the light conditions, which effectively reduces the slope noise and can better perform CCMS operations.

[0023] 2. The SS-ADC circuit of the present invention is based on the slope noise adaptive mechanism to the input signal V IN The processing can effectively reduce the random telegraph signal and horizontal noise of the readout circuit; compared with the traditional multi-sampling technology, the present invention also shortens the quantization time. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0025] Figure 1 A signal flow diagram of a multi-sampling SS-ADC circuit based on slope noise adaptation provided in Embodiment 1 of the present invention;

[0026] Figure 2 for Figure 1 The circuit connection diagram of DAC_H in the figure;

[0027] Figure 3 for Figure 1 The circuit connection diagram of DAC_L in the figure;

[0028] Figure 4 for Figure 1 The circuit connection diagram of LOGIC;

[0029] Figure 5 for Figure 1 The circuit connection diagram of COUNTER1 in the figure;

[0030] Figure 6 for Figure 1 The circuit connection diagram of COUNTER2 in the figure;

[0031] Figure 7 for Figure 5 , Figure 6 The circuit connection diagram of the bitwise inversion unit in FIG.

[0032] Figure 8 for Figure 1 Circuit connection diagram of SELECT in the figure;

[0033] Fig. 9 for Figure 1 The signal timing diagram of the SS-ADC circuit in weak light conditions;

[0034] Fig.10 for Figure 1 The signal timing diagram of the SS-ADC circuit under strong light conditions;

[0035] Fig.11 A noise distribution diagram of RAMP_L provided in Example 1 of the present invention;

[0036] Fig.12 This is a noise distribution diagram of RAMP_H provided in Example 1 of the present invention. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0040] Example 1

[0041] See also Figure 1 , Figure 1 The circuit architecture diagram of a multi-sampling SS-ADC circuit based on slope noise adaptation provided in this embodiment 1 is shown, which includes: 1 ordinary slope generating unit DAC_H, 1 low-noise slope generating unit DAC_L, 1 comparator unit COMP, 1 judgment logic unit LOGIC, 2 counting units COUNTER1~COUNTER2, and 1 selection output unit SELECT.

[0042] First of all, it should be noted that this SS-ADC circuit is designed to IN The changes after the pixel reset stage, judgment stage, and pixel exposure stage are quantized to 10 bits.

[0043] V IN Characterizes a single column pixel signal: V IN During the pixel reset phase, V RST ; V IN In the judgment stage and pixel exposure stage, V SIG ; That is, V IN The change in V SIG -VRST ; V SIG >V RST .

[0044] Among them, V SIG Indicates V sig The signal is reversely amplified by the column-level programmable gain amplifier PGA; V RST Indicates V rst The signal obtained by reverse amplification of PGA; V sig 、V rst is the original signal from the pixel unit, which reflects the actual pixel signal V pixel Changes in V rst >V sig That is, V pixel The change in V rst -V sig .

[0045] In other words, V IN is the output signal of PGA and the actual pixel signal V pixel are in opposite phase.

[0046] Next, see Figure 1 Introduce the various parts of this SS-ADC circuit:

[0047] 1. DAC_H is used to provide a quantized ramp signal RAMP_H used in strong light conditions.

[0048] Among them, the voltage range of RAMP_H is 0~V RH , whose slope is k ; V RH Indicates full scale.

[0049] See also Figure 2 DAC_H can be designed to include: a current source array 1, a differential switch array 1, a 10-bit counter Counter1, a segment decoder Segment_Decoder1, an operational amplifier A1, and a load resistor sub-part 1.

[0050] Specific:

[0051] The timing control terminal of Counter1 is connected to the timing signal CLK, the reset terminal is connected to the reset signal DACH_RB, and the output terminal is used to output 10-bit binary digital signals G0~G9. Among them, DACH_RB is used to control the start and reset of RAMP_H.

[0052] The input end of Segment_Decoder1 is used to input G0~G9, and the output end is used to output control signals e0~e7, u0~u 125; Among them, e0~e7 are the lower 4 bits of binary code; u0~u 125 Encodes the upper 6 bits of the thermometer.

[0053] The current source array 1 includes: 67 class A current sources; 4 class A current sources are low 4-bit binary current sources, and their currents are I0, 2I0, 4I0, and 8I0 respectively; the other 63 class A current sources are high 6-bit thermometer current sources, and their currents are all 16I0; I0 represents the standard current.

[0054] The differential switch array 1 includes: 67 pairs of differential switches 1, whose input terminals are connected to 67 class I current sources in a one-to-one correspondence; 4 pairs of differential switches 1 are controlled by e0~e7 in a one-to-one correspondence; and the other 63 pairs of differential switches 1 are controlled by u0~u 125 One-to-one control.

[0055] See also Figure 2 , where the four pairs of differential switches include: {E0, E1}, {E2, E3}…, {E6, E7}; where E0~E7 all represent switches, which are controlled by e0~e7 one by one, that is, e0 controls E0,…, e7 controls E7.

[0056] The other 63 pairs of differential switches include: {U0, U1}, {U2, U3}..., {U 124 ,U 125}; Among them, U0~U 125 All represent switches, from u0 to u 125 One-to-one control - that is, u0 controls U0, ..., u 125 Control U 125 .

[0057] It should be noted that each pair of differential switches is a pair of complementary differential switches, which are controlled by a pair of complementary differential signals; that is, only one switch of a pair of differential switches can be turned on at the same time.

[0058] Load resistor sub-section 1 includes: 3 resistors R out1 , R dummy1 , R S ; R S The first end of R is grounded; S The second end is connected to R out1 The first end, R dummy1 For any pair of differential switches, the output of one of the switches is connected to R out1 The second end of the other switch output is connected to R dummy1 The second end.

[0059] The non-inverting input of A1 is connected to R out1The output end of A1 is connected to its inverting input end for outputting RAMP_H.

[0060] In general, Segment_Decoder1 generates a control signal to control the differential switch array 1 to realize that the corresponding current source in the current source array 1 is output to the load resistor sub-section 1; the load resistor sub-section 1 is divided into two branches, of which R out1 The branch passes through the resistor R out1 Complete the current-to-voltage conversion and cooperate with A1 to generate a gradually rising full-scale RAMP_H.

[0061] Of course, DAC_H can also be designed with other structures, but it needs to be able to generate RAMP_H that meets the above requirements.

[0062] 2. DAC_L is used to provide a quantized ramp signal RAMP_L used in low-light conditions.

[0063] Among them, the voltage range of RAMP_L is 0~V RH / 4, and its slope is k .

[0064] That is to say, the voltage range of RAMP_L is 1 / 4 of RAMP_H, the slope is the same as RAMP_H, and the noise is theoretically half of RAMP_H.

[0065] See also Figure 3 DAC_L can be designed to include: a current source array 2, a differential switch array 2, a bidirectional counter Counter2, a segment decoder Segment_Decoder2, an operational amplifier A2, a load resistor sub-part 2, and a capacitor array.

[0066] Specific:

[0067] The timing control terminal of Counter2 is connected to the timing signal CLK, the reset terminal is connected to the reset signal DACH_RB, the count control terminal is connected to the control signal UP_DOWN, the hold control terminal is connected to the hold signal HOLD, and the output terminal is used to output 8-bit binary digital signals F0~F7.

[0068] To simplify the timing design, Counter2 uses a bidirectional counter: DACH_RB is used to control the start and reset of RAMP_L; UP_DOWN is used to control the counting direction; and HOLD is used to hold the state.

[0069] Specifically, when Counter2 counts to all 1s or all 0s, HOLD changes from 0 to 1 and maintains this state; then the UP_DOWN signal flips, HOLD changes back to 0, and Counter2 counts in reverse; this can control the generated ramp waveform, which is convenient for subsequent timing design.

[0070] The input end of Segment_Decoder2 is used to input F0~F7, and the output end is used to output control signals b0~b7, t0~t 29 ; Among them, b0~b7 are the lower 4 bits of binary code; t0~t 29 Encodes the upper 4 bits of the thermometer.

[0071] The current source array 2 includes: 19 class II current sources; 4 class II current sources are low 4-bit binary current sources, and their currents are I1, 2I1, 4I1, and 8I1 respectively; the other 15 class II current sources are high 6-bit thermometer current sources, and their currents are all 16I1; among them, I1 represents 4 times the standard current, I1=4I0.

[0072] The differential switch array 2 includes: 19 pairs of differential switches 2, whose input terminals are connected to 19 class II current sources in a one-to-one correspondence; 4 pairs of differential switches 2 are controlled by b0~b7 in a one-to-one correspondence; the other 15 pairs of differential switches 2 are controlled by t0~t 29 One-to-one control.

[0073] See also Figure 3 , where the four pairs of differential switches include: {B0, B1}, {B2, B3}…, {B6, B7}; where B0~B7 all represent switches, which are controlled by b0~b7 one by one, that is, b0 controls B0,…, b7 controls B7.

[0074] The other 15 pairs of differential switches include: {T0, T1}, {T2, T3}..., {T 28 ,T 29}; Among them, T0~T 29 All represent switches, from t0 to t 29 One-to-one control - that is, t0 controls T0, ..., t 29 Control T 29 .

[0075] Similar to the differential switch array 1, each pair of differential switches 2 is a pair of complementary differential switches controlled by a pair of complementary differential signals; that is, only one switch of a pair of differential switches 2 can be turned on at the same time.

[0076] The load resistor sub-section 2 includes: 2 resistors R out2 , R dummy2 ; R out2 The first end of R is grounded; dummy2The first end of is grounded; for any pair of differential switches, the output end of one of the switches is connected to R out2 The second end of the other switch output is connected to R dummy2 The second end of

[0077] The capacitor array includes: 4 capacitors C1~C4, 1 switch S4; the upper plate of C4 is connected to R out2 The second end of the lower plate is connected to the upper plate of C3; the lower plate of C3 is connected to the upper plate of C2; the lower plate of C2 is connected to the upper plate of C1; the lower plate of C2 is connected to the reference voltage V through S4 S ; S4 is turned on or off by control signal s4; the lower plate of C1 is grounded;

[0078] The non-inverting input terminal of A2 is connected to the lower plate of C2; the output terminal of A2 is connected to its inverting input terminal for outputting RAMP_L.

[0079] In general, the principle of DAC_L is the same as DAC_H, the difference between the two is:

[0080] DAC_H is a common 10-bit current-steering DAC; DAC_L is an 8-bit current-steering DAC; therefore, the unit current I0 of DAC_H is 1 / 4 of the unit current I1 of DAC_L; then, for R out2 The voltage RAMP1 at the second end has a voltage value four times that of RAMP_H, and a noise four times that of RAMP_H.

[0081] RAMP1 is divided into 1 / 4 by C1~C4, and a voltage RAMP2 is formed at the non-inverting input terminal of A2. Its voltage value is 1 / 4 times that of RAMP1 and its noise is 1 / 4 times that of RAMP1.

[0082] Before RAMP_L starts, S4 first controls S4 to conduct and charge C1 to V S ; S4 then controls S4 to disconnect, so that RAMP_L is from V S Start to rise.

[0083] Therefore, the voltage range of RAMP_L is 1 / 4 of RAMP_H, and the slope is the same as RAMP_H. The noise is theoretically reduced to half of RAMP_H, thus reducing the slope noise.

[0084] Of course, DAC_L can also be designed with other structures, but it needs to be able to generate RAMP_L that meets the above requirements.

[0085] 3. COMP is used for:

[0086] ① In the pixel reset phase, RAMP_H, RAMP_L and V IN (This stage is VRST ) to compare and obtain the control signal CN1;

[0087] ②In the judgment stage, the reference voltage V REF With V IN (This stage is V SIG ) to compare and obtain the judgment signal CN2;

[0088] ③ During the pixel exposure phase, the reference voltage V REF With V IN (This stage is V SIG ) are compared to obtain the control signal CN3.

[0089] See also Figure 1 , COMP can be designed to include: 1 comparator Comp0 and 3 switches S1~S3.

[0090] The inverting input of Comp0 is connected to V IN ;

[0091] RAMP_L is connected to the positive input of Comp0 through S1;

[0092] V REF Connect the non-inverting input of Comp0 through S2;

[0093] RAMP_H is connected to the positive input of Comp0 through S3;

[0094] Among them, S1 is controlled to be turned on or off by a control signal s1; S2 is controlled to be turned on or off by a control signal s2; and S3 is controlled to be turned on or off by a control signal s3.

[0095] It should be noted that, in this embodiment 1, V RH / 4 is the dividing line for distinguishing light intensity, that is: V REF =V RH / 4. If V SIG <V RH / 4, for low light conditions; if V SIG >V RH / 4, for strong light conditions.

[0096] Specific:

[0097] ① In the pixel reset stage: first turn on S3, turn off S1~S2, and make RAMP_H and V IN Compare once; then turn on S1, turn off S2~S3, and make RAMP_L and V IN Compare 4 times; the output of Comp0 is synchronized with CN1.

[0098] ②In the judgment stage: disconnect S1 and S3, turn on S2, and make VREF With V IN For comparison, the output terminal of Comp0 outputs CN2.

[0099] Specific:

[0100] If V IN <V REF , CN2 is 1, which is a weak light situation;

[0101] If V IN >V REF , CN2 is 0, which is a strong light situation.

[0102] ③In the pixel exposure stage:

[0103] If CN2 is 1, S2~S3 are disconnected and S1 is turned on, so that RAMP_L is connected to V IN Compare 4 times, and the output of Comp0 is synchronized with CN3;

[0104] If CN2 is 0, S1~S2 are disconnected and S3 is turned on, so that RAMP_H is connected to V IN After one comparison, the output of Comp0 is synchronized with CN3.

[0105] Among them, CN1 and CN3 are used to control COUNTER1 and COUNTER2 to stop counting; CN2 is used to determine the selection and control of LOGIC.

[0106] It should be noted that if the output signal of the output terminal of Comp0 is uniformly set to CN, then CN1 is the CN of the pixel reset stage; CN2 is the CN of the judgment stage; and CN3 is the CN of the pixel exposure stage. For the convenience of explanation, CN is represented by CN1~CN3 respectively.

[0107] Similarly, if the input signal of the non-inverting input terminal of Comp0 is uniformly set to V RAMP , then according to the above control method, V RAMP There will be RAMP_L, RAMP_H, V REF And other specific status.

[0108] Of course, COMP can also be designed with other structures, but it needs to be able to generate CN1, CN2, and CN3 that meet the above requirements.

[0109] 4. LOGIC is used to determine the quantization ramp signal used by COMP in the pixel exposure stage according to CN2, and to generate the control signal Logic1 for COUNTER1 and the control signal Logic2 for COUNTER2.

[0110] See also Figure 4, LOGIC can be designed to include: 1 D flip-flop DFF1, 1 NAND gate NAND1, 1 delay unit DELAY, and 2 AND gates AND1~AND2.

[0111] The clk terminal of DFF1 is connected to the input control signal Latch_ctrl, the D terminal is used to input CN2, the SB terminal is connected to the reset signal LOGIC_SB, and the Q terminal is used to output Logic1;

[0112] The input of DELAY is connected to Latch_ctrl;

[0113] Input 1 of NAND1 is connected to the output of DELAY, input 2 is connected to Logic1, and the output is used to output Logic2;

[0114] Input terminal 1 of AND1 is connected to Logic1, input terminal 2 is connected to timing signal X1, and the output terminal is used to output s1;

[0115] Input terminal 1 of AND2 is connected to Logic2, input terminal 2 is connected to timing signal Y1, and the output terminal is used to output s3.

[0116] Among them, Latch_ctrl is the control signal of DFF1: when the rising edge of Latch_ctrl arrives, DFF1 reads V SIG and V REF The comparison result CN2 is output as Logic1.

[0117] LOGIC_SB is used to control the DFF1 reset - making Logic1 1 before the cycle starts.

[0118] X1 and Y1 are both external timing signals: these two signals are ANDed with Logic1 and Logic2 to generate s1 and s3.

[0119] Logic1 is used to control COUNTER1 to start counting; Logic2 is used to control COUNTER2 to start counting.

[0120] Specifically,

[0121] If CN2 is 1, Logic1 is 1; s1 is high level (corresponding to controlling S1 to be turned on), s3 is low level (corresponding to controlling S3 to be turned off); s2 switches to low level, S2 is turned off; that is, COMP selects RAMP_L for comparison during the pixel exposure stage.

[0122] If CN2 is 0, Logic1 is 0; 1 is low level (corresponding to control S1 off), s3 is high level (corresponding to control S3 on); s2 switches to low level, S2 is off; that is, COMP selects RAMP_H for comparison during the pixel exposure stage.

[0123] Of course, LOGIC can also be designed with other structures, but it needs to be able to meet the above functional design.

[0124] It should be noted that LOGIC only works for a short period of time (CN2 acts on LOGIC only when the rising edge of Latch_ctrl arrives) to obtain the judgment result, and does not significantly increase the overall ADC quantization time.

[0125] 5. COUNTER1 is used to combine CN1, CN3, and Logic1 for 10-bit quantization to obtain the reference quantization value D1[9:0] in low-light conditions.

[0126] COUNTER2 is used to perform 10-bit quantization in combination with CN1, CN3, and Logic2 to obtain the reference quantization value D2[9:0] under strong light conditions.

[0127] COUNTER1 and COUNTER2 are both asynchronous clock counters: they first quantize the V RST , and then quantize the V of the pixel exposure stage SIG , and perform subtraction to obtain V IN The amount of change.

[0128] In this embodiment 1, D1[9:0] represents 4 (V SIG -V RST ) quantized value; D2[9:0] represents V SIG -V RST Quantified value of .

[0129] COUNTER1 and COUNTER2 use the same circuit structure design, with only slightly different input and output signals.

[0130] 501, see Figure 5 COUNTER1 can be designed to include: 1 inverter INV101, 1 NAND gate NAND102, 2 AND gates AND103~AND104, 10 counting units Bit 1,0 ~Bit 1,9 .

[0131] The input terminal of INV101 is used to input CN1 in the pixel reset stage and input CN3 in the pixel exposure stage.

[0132] Input terminal 1 of AND103 is connected to the timing signal CLK, and input terminal 2 is connected to Logic1;

[0133] Input terminal 1 of AND104 is connected to the reset signal Count_RB, and input terminal 2 is connected to Logic1;

[0134] Input terminal 1 of NAND102 is connected to the output terminal of INV101, input terminal 2 is connected to the timing signal Count_pulse, and input terminal 3 is connected to the output terminal of AND103;

[0135] Bit 1,0 ~Bit 1,9 The reset terminal is connected to the output terminal of AND104, the control terminal 1 is connected to the inverted signal BW1, and the control terminal 2 is connected to the inverted signal BW2; 1,0 The input end is connected to the output end of NAND102; the n+1th counting unit Bit 1,n+1 The input end is connected to the nth counting unit Bit 1,n Output terminal; n∈[1,8]; Bit 1,m The output terminal is used to output the m+1th bit D of D1[9:0]. 1,m ; m∈[1,9].

[0136] Among them, CN1 is the output of Comp0 in the pixel reset stage, which is used to control COUNTER1 to stop counting in the pixel reset stage;

[0137] CN3 is the output of Comp0 in the pixel exposure stage, which is used to control COUNTER1 to stop counting in the pixel exposure stage;

[0138] Logic1 is used to control COUNTER1 to start counting; Count_RB is used to reset COUNTER1;

[0139] BW1 and BW2 are used to control the bitwise inversion of COUNTER1: when BW1 is 0 and BW2 is 1 (i.e., BW1 and BW2 are "0, 1"), COUNTER1 is in the counting state; when BW1 and BW2 change from "1, 0" to "0, 0", COUNTER1 performs the inversion operation on each bit; when BW1 and BW2 are in other situations, COUNTER1 is in the holding state.

[0140] 503, see Figure 6 COUNTER2 can be designed to include: 1 inverter INV201, 1 NAND gate NAND202, 2 AND gates AND203~AND204, 10 counting units Bit 2,0 ~Bit 2,9 ;

[0141] The input terminal of INV201 is used to input CN1 in the pixel reset phase and CN3 in the pixel exposure phase;

[0142] Input terminal 1 of AND203 is connected to the timing signal CLK, and input terminal 2 is connected to Logic2;

[0143] Input terminal 1 of AND204 is connected to the reset signal Count_RB, and input terminal 2 is connected to Logic2;

[0144] Input terminal 1 of NAND202 is connected to the output terminal of INV201, input terminal 2 is connected to the timing signal Count_pulse, and input terminal 3 is connected to the output terminal of AND203;

[0145] Bit 2,0 ~Bit 2,9 The reset terminal is connected to the output terminal of AND204, the control terminal 1 is connected to the inverted signal BW1, and the control terminal 2 is connected to the inverted signal BW2; 2,0 The input end is connected to the output end of NAND202; the n+1th counting unit Bit 2,n+1 The input end is connected to the nth counting unit Bit 2,n Output terminal of Bit 2,m The output terminal is used to output the m+1th bit D of D2[9:0]. 2,m .

[0146] Among them, CN1 is the output of Comp0 in the pixel reset stage, which is used to control COUNTER2 to stop counting in the pixel reset stage;

[0147] CN3 is the output of Comp0 in the pixel exposure stage, which is used to control COUNTER2 to stop counting in the pixel exposure stage;

[0148] Logic2 is used to control COUNTER2 to start counting; Count_RB is used to reset COUNTER2;

[0149] BW1 and BW2 are used to control the bitwise inversion of COUNTER2: when BW1 is 0 and BW2 is 1 (i.e., BW1 and BW2 are "0, 1"), COUNTER2 is in the counting state; when BW1 and BW2 change from "1, 0" to "0, 0", COUNTER2 performs the inversion operation on each bit; when BW1 and BW2 are in other situations, COUNTER2 is in the holding state.

[0150] It should be noted that the above Bit 1,0 ~Bit 1,9 、Bit 2,0 ~Bit 2,9All adopt the same circuit structure design.

[0151] See also Figure 5 , Figure 6 The counting unit includes: a bitwise inversion unit BWI and a trigger DFF. Figure 7 , BWI includes: 3 PMOS tubes P1~P3 and 3 NMOS tubes M4~M6.

[0152] First, in any bitwise negation unit:

[0153] The gates of P1 and M5 serve as the In terminal of the bitwise inversion unit; the gates of P3 and M4 serve as the control terminal 1 of the bitwise inversion unit; the gates of P2 and M6 serve as the control terminal 2 of the bitwise inversion unit; the sources of P1 and P2 are connected to the power supply VDD; the source of P3 is connected to the drains of P1 and P2; the drain of P3 is connected to the drains of M4 and M5 and serves as the Out terminal of the bitwise inversion unit; the source of M4 is grounded; the source of M5 is connected to the drain of M6; the source of M6 is grounded.

[0154] Then, in any counting cell:

[0155] The In terminal of BWI serves as the input terminal of the counting unit; the control terminal 1 of BWI serves as the control terminal 1 of the counting unit; the control terminal 2 of BWI serves as the control terminal 2 of the counting unit; the Out terminal of BWI is connected to the clk terminal of DFF; the Reset terminal of DFF serves as the reset terminal of the counting unit; the D terminal of DFF is connected to its inverting Q terminal and serves as the output terminal of the counting unit.

[0156] The following is a detailed introduction to the working process of COUNTER1 and COUNTER2:

[0157] ①In the pixel reset stage:

[0158] LOGIC_SB is initially low, Logic1 and Logic2 are both 1, BW1 and BW2 are "0, 1", and COUNTER1 and COUNTER2 are both in the counting state: under the control of CN1, COUNTER1 counts 4 times (equivalent to quantizing 4*V RST ), COUNTER2 counts once, which is equivalent to quantizing V RST ).

[0159] ②In the judgment stage:

[0160] Although the judgment phase lasts for a short time, BW1 and BW2 experience a state change from "0, 1" to "1, 0" to "0, 0", and COUNTER1 and COUNTER2 perform a bitwise inversion operation (i.e. COUNTER1 quantizes -4*V RST, COUNTER2 quantifies -V RST ).

[0161] It should be noted that before the next count, BW1 and BW2 are restored to "0" and "1", and COUNTER1 and COUNTER2 start counting again.

[0162] ③In the pixel exposure stage:

[0163] If it is judged as weak light, CN2 is 1, then Logic1 is 1, Logic2 is 0; COUNTER1 counts normally, and counts 4 times under the control of CN3 (which is equivalent to the new quantization of 4*V SIG ), then COUNTER1 is finally quantized to 4*(V SIG -V RST ); COUNTER2 does not count and is reset to all 1s;

[0164] If it is judged as strong light, CN2 is 0, Logic1 is 0, Logic2 is 1; COUNTER2 counts normally and counts once under the control of CN3 (which is equivalent to the new quantization of V SIG ), then COUNTER2 finally quantizes V SIG -V RST ; COUNTER1 does not count and is reset to all 1s.

[0165] 6. SELECT is used to selectively process D1[9:0] and D2[9:0] according to Logic1 to output the final 10-bit quantization result OUT[9:0].

[0166] That is, SELECT is responsible for selectively processing D1[9:0] and D2[9:0] and outputting latch OUT[9:0].

[0167] See also Figure 8 , SELECT can be designed to include: 10 two-to-one selectors MUX0~MUX9, and 10 D flip-flops DFF0~DFF9.

[0168] The selection terminals of MUX0~MUX9 are used to input CN2;

[0169] The clk terminals of DFF0~DFF9 are all connected to the timing signal Latch_EN;

[0170] MUX p Input terminal 1 is used to input the p+3th bit D1[p+2] of D1[9:0], and input terminal 2 is used to input the p+1th bit D2[p] of D2[9:0]; DFF p The D terminal is connected to MUX pThe output terminal Q is used to output the p+1th bit OUT[p] of OUT[9:0]; p∈[0,7];

[0171] MUX q Input terminal 1 of DFF is used to input 0, and input terminal 2 is used to input the q+1th bit D2[q] of D2[9:0]; q The D terminal is connected to MUX q The output terminal Q is used to output the q+1th bit OUT[q] of OUT[9:0]; q∈[8,9].

[0172] Specifically,

[0173] In low light conditions, CN2 is 1 and Latch_EN is 0. At this time, the upper 8 bits of D1[9:0] (D1[2]~D1[9]) are selected as the lower 8 bits of OUT[9:0] (i.e., OUT[0]~OUT[7]): OUT[0] is D1[2], OUT[1] is D1[3], ..., OUT[7] is D1[9]; the upper 2 bits of OUT[9:0] (i.e., OUT[8]~OUT[9]) are both filled with 0: OUT[8] is 0 and OUT[9] is 0.

[0174] If it is a strong light situation, CN2 is 0 and Latch_EN is 0. At this time, the 10 bits of D2[9:0] (i.e., D2[0]~D2[9]) are selected to correspond to the 10 bits of OUT[9:0] (OUT[0]~OUT[9]): OUT[0] is D2[0], OUT[2] is D2[1], ..., OUT[9] is D2[9].

[0175] Then Latch_EN changes from 0 to 1, and DFF0~DFF9 latch OUT[0]~OUT[9].

[0176] In summary, the working mode of the SS ADC circuit based on the above structure is briefly described as follows:

[0177] Turn on DAC_L to generate RAMP_L, turn on DAC_H to generate RAMP_H;

[0178] ① In the pixel reset stage, LOGIC_SB is initially low, Logic1 and Logic2 are both 1, and COUNTER1 and COUNTER2 are both in the counting state;

[0179] S3 is turned on and connected to a section of RAMP_H, that is, RAMP_H and V IN Comparison 1, COUNTER1 counts 1 time under CN1 control - quantifies V RST ;

[0180] S1 is turned on and connected to 4 sections of RAMP_L, that is, RAMP_L and V IN Comparison 4 times, COUNTER2 counts 4 times under CN1 control - quantized 4*V RST .

[0181] ②In the judgment stage, S2 is turned on and connected to V REF ; V REF With V IN Compare:

[0182] If V IN <V REF , CN2 is 1, which is a weak light situation;

[0183] If V IN >V REF , CN2 is 0, which is a strong light situation.

[0184] BW1 and BW2 experience a state change of "0, 1" → "1, 0" → "0, 0", and COUNTER1 and COUNTER2 perform a bitwise inversion operation (i.e. COUNTER1 quantizes -4*V RST , COUNTER2 quantifies -V RST ).

[0185] ③In the pixel exposure stage:

[0186] 301, if CN2 is 1, Latch_ctrl changes from 0 to 1, Logic1 is 1, Logic2 is 0; COMP selects RAMP_L and V IN Make comparisons;

[0187] RAMP_L vs. V IN Compare 4 times, only COUNTER1 counts 4 times under CN3 control - newly quantized 4*V SIG That is, D1[9:0] is 4*(V SIG -V RST ) quantitative results;

[0188] Then, SELECT selects the upper 8 bits of output D1[9:0], and on this basis fills the 9th and 10th bits with 0, thus obtaining OUT[9:0] in low light conditions.

[0189] 302, if CN2 is 0, Latch_ctrl changes from 0 to 1, Logic1 is 0, Logic2 is 1; COMP selects RAMP_H and V IN Make comparisons;

[0190] RAMP_H vs. V INCompare 1 times, COUNTER2 counts 1 times under CN3 control - newly quantified V SIG That is, the value of D2[9:0] is V SIG -V RST Quantitative results of

[0191] Then, SELECT selects 10 bits of output D2[9:0], that is, OUT[9:0] is obtained under strong light conditions.

[0192] In addition, see Fig. 9 , Fig.10 : Fig. 9 The signal timing of the SS-ADC circuit in low-light conditions is shown; Fig.10 The signal timing of the SS-ADC circuit under strong light conditions is shown. It can be seen that the ADC processing time of the two is the same, and the long quantization time in weak light conditions is avoided.

[0193] Simulation Verification

[0194] In order to prove the noise reduction effect of DAC_L proposed in the present invention, a noise simulation is performed on it and DAC_H. The results are shown in Fig.11 , Fig.12 .

[0195] Both of them selected 24 sampling points (i.e. Number=24) to examine their noise distribution: the horizontal axis represents the sum of the ramp voltage and the noise voltage Values, and the unit is mV; the standard deviation Std Dev of the Values ​​distribution can be considered to represent the size of the ramp noise; the vertical axis represents the number of points.

[0196] Specifically, Fig.11 The noise distribution of RAMP_L is shown: the mean of the sum of the ramp voltage and the noise voltage of RAMP_L is 229.423mV and the standard deviation is 207.287μV. Fig.12 The noise distribution of RAMP_H is shown: the mean of the sum of the ramp voltage and the noise voltage of RAMP_H is 267.189mV and the standard deviation is 307.577μV.

[0197] It should be noted that the simulated value of noise is easily affected by non-ideal factors and may result in errors. Although RAMP_L does not achieve the theoretical noise reduction of half compared to RAMP_H, it can still be considered to significantly reduce the noise, that is, it can reduce the horizontal noise in the above SS-ADC and better perform CCMS operation.

[0198] Example 2

[0199] This embodiment 2 discloses a multi-sampling SS-ADC module based on slope noise adaptation, which adopts the layout of a multi-sampling SS-ADC circuit based on slope noise adaptation disclosed in embodiment 1. The mode of packaging into a module makes it easier to promote and apply the above circuit.

[0200] This embodiment 2 also discloses a CMOS module, which includes the above disclosed multi-sampling SS-ADC module based on slope noise adaptation. Integrating the above multi-sampling SS-ADC module based on slope noise adaptation into the CMOS module also facilitates the promotion and application of the above circuit.

[0201] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0202] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A multi-sampling SS-ADC circuit based on slope noise adaptation, which is used to IN The change amount after the pixel reset stage, judgment stage, and pixel exposure stage is quantized by 10 bits; the characteristic is that, It includes: a common slope generating unit DAC_H, a low noise slope generating unit DAC_L, a comparator unit COMP, a judgment logic unit LOGIC, two counting units COUNTER1~COUNTER2, and a selection output unit SELECT; DAC_H is used to provide a quantized ramp signal RAMP_H used in strong light conditions; DAC_L is used to provide a quantized ramp signal RAMP_L used in low light conditions; COMP is used to: In the pixel reset phase, RAMP_H, RAMP_L and V IN Compare and obtain the control signal CN1; in the judgment stage, the reference voltage V REF With V IN Compare and obtain the judgment signal CN2; in the pixel exposure stage, RAMP_H or RAMP_L is compared with V IN Compare and obtain the control signal CN3; In the pixel reset stage: first make RAMP_H and V IN Compare once, and then make RAMP_L and V IN Compare 4 times; COMP output is synchronously output to CN1; In the judgment stage: make V REF With V IN For comparison, the output terminal of COMP outputs CN2; if V IN <V REF , CN2 is 1, which is a weak light situation; if V IN >V REF , CN2 is 0, which is a strong light situation; In the pixel exposure stage: if CN2 is 1, RAMP_L and V IN Compare 4 times, COMP output terminal synchronously outputs CN3; if CN2 is 0, RAMP_H and V IN After one comparison, the output terminal of COMP synchronously outputs CN3; LOGIC is used to determine the quantization ramp signal used by COMP in the pixel exposure stage according to CN2, and generate the control signal Logic1 for COUNTER1 and the control signal Logic2 for COUNTER2; COUNTER1 is used to combine CN1, CN3, and Logic1 for 10-bit quantization to obtain the reference quantization value D1[9:0] in low-light conditions; COUNTER2 is used to combine CN1, CN3, and Logic2 for 10-bit quantization to obtain the reference quantization value D2[9:0] under strong light conditions; CN1 and CN3 are used to control COUNTER1 and COUNTER2 to stop counting; CN2 is used to determine the selection and control of LOGIC; SELECT is used to selectively process D1[9:0] and D2[9:0] according to Logic1 to output the final 10-bit quantization result OUT[9:0].

2. The multi-sampling SS-ADC circuit based on slope noise adaptation according to claim 1, characterized in that: V IN During the pixel reset phase, V RST ; V IN In the judgment stage and pixel exposure stage, V SIG ; Among them, V SIG Indicates V sig The signal is reversely amplified by the column-level programmable gain amplifier PGA; V RST Indicates V rst The signal obtained by reverse amplification of PGA; V sig 、V rst is the original signal from the pixel unit; V rst >V sig , V SIG >V RST .

3. The multi-sampling SS-ADC circuit based on slope noise adaptation according to claim 1, characterized in that: DAC_H includes: a current source array 1, a differential switch array 1, a 10-bit counter Counter1, a segment decoder Segment_Decoder1, an operational amplifier A1, and a load resistor sub-part 1; The timing control terminal of Counter1 is connected to the timing signal CLK, the reset terminal is connected to the reset signal DACH_RB, and the output terminal is used to output 10-bit binary digital signals G0~G9; The input end of Segment_Decoder1 is used to input G0~G9, and the output end is used to output control signals e0~e7, u0~u 125 ; Among them, e0~e7 are the lower 4 bits of binary code; u0~u 125 Encode the upper 6 bits of the thermometer; The current source array 1 includes: 67 class I current sources; 4 class I current sources are lower 4-bit binary current sources; and the other 63 class I current sources are upper 6-bit thermometer current sources; The differential switch array 1 includes: 67 pairs of differential switches 1, whose input terminals are connected to 67 class I current sources in a one-to-one correspondence; 4 pairs of differential switches 1 are controlled by e0~e7 in a one-to-one correspondence; and the other 63 pairs of differential switches 1 are controlled by u0~u 125 One-to-one control; Load resistor sub-section 1 includes: 3 resistors R out1 , R dummy1 , R S ; R S The first end of R is grounded; S The second end is connected to R out1 The first end, R dummy1 For any pair of differential switches, the output of one of the switches is connected to R out1 The second end of the other switch output is connected to R dummy1 The second end of The non-inverting input of A1 is connected to R out1 The output end of A1 is connected to its inverting input end for outputting RAMP_H; Among them, the voltage range of RAMP_H is 0~V RH , the slope is k ; V RH Indicates full scale.

4. The multi-sampling SS-ADC circuit based on slope noise adaptation according to claim 1, characterized in that: DAC_L includes: a current source array 2, a differential switch array 2, a bidirectional counter Counter2, a segment decoder Segment_Decoder2, an operational amplifier A2, a load resistor sub-part 2, and a capacitor array; The timing control terminal of Counter2 is connected to the timing signal CLK, the reset terminal is connected to the reset signal DACH_RB, the count control terminal is connected to the control signal UP_DOWN, the hold control terminal is connected to the hold signal HOLD, and the output terminal is used to output 8-bit binary digital signals F0~F7; The input end of Segment_Decoder2 is used to input F0~F7, and the output end is used to output control signals b0~b7, t0~t 29 ; Among them, b0~b7 are the lower 4 bits of binary code; t0~t 29 Encode the upper 4 bits of the thermometer; The current source array 2 includes: 19 class II current sources; 4 class II current sources are lower 4-bit binary current sources; and the other 15 class II current sources are upper 6-bit thermometer current sources; The differential switch array 2 includes: 19 pairs of differential switches 2, whose input terminals are connected to 19 class II current sources in a one-to-one correspondence; 4 pairs of differential switches 2 are controlled by b0~b7 in a one-to-one correspondence; the other 15 pairs of differential switches 2 are controlled by t0~t 29 One-to-one control; The load resistor sub-section 2 includes: 2 resistors R out2 , R dummy2 ; R out2 The first end of R is grounded; dummy2 The first end of is grounded; for any pair of differential switches, the output end of one of the switches is connected to R out2 The second end of the other switch output is connected to R dummy2 The second end of The capacitor array includes: 4 capacitors C1~C4, 1 switch S4; the upper plate of C4 is connected to R out2 The second end of the lower plate is connected to the upper plate of C3; the lower plate of C3 is connected to the upper plate of C2; the lower plate of C2 is connected to the upper plate of C1; the lower plate of C2 is connected to the reference voltage V through S4 S ; S4 is turned on or off by control signal s4; the lower plate of C1 is grounded; The in-phase input terminal of A2 is connected to the lower plate of C2; the output terminal of A2 is connected to its inverting input terminal for outputting RAMP_L; Among them, the voltage range of RAMP_L is 0~V RH / 4, the slope is k ; V RH Indicates full scale.

5. The multi-sampling SS-ADC circuit based on slope noise adaptation according to claim 1, characterized in that: COMP includes: 1 comparator Comp0, 3 switches S1~S3; The inverting input of Comp0 is connected to V IN ; RAMP_L is connected to the positive input of Comp0 through S1; V REF Connect the non-inverting input of Comp0 through S2; RAMP_H is connected to the positive input of Comp0 through S3; Among them, V REF =V RH / 4; V RH Indicates full scale; S1 is turned on or off by control signal s1; S2 is turned on or off by control signal s2; S3 is turned on or off by control signal s3.

6. The multi-sampling SS-ADC circuit based on slope noise adaptation according to claim 1, characterized in that: LOGIC includes: 1 D flip-flop DFF1, 1 NAND gate NAND1, 1 delay unit DELAY, 2 AND gates AND1~AND2; The clk terminal of DFF1 is connected to the input control signal Latch_ctrl, the D terminal is used to input CN2, the SB terminal is connected to the reset signal LOGIC_SB, and the Q terminal is used to output Logic1; The input of DELAY is connected to Latch_ctrl; Input 1 of NAND1 is connected to the output of DELAY, input 2 is connected to Logic1, and the output is used to output Logic2; Input terminal 1 of AND1 is connected to Logic1, input terminal 2 is connected to timing signal X1, and the output terminal is used to output s1; Input terminal 1 of AND2 is connected to Logic2, input terminal 2 is connected to timing signal Y1, and the output terminal is used to output s3.

7. The multi-sampling SS-ADC circuit based on slope noise adaptation according to claim 6, characterized in that: COUNTER1 includes: 1 inverter INV101, 1 NAND gate NAND102, 2 AND gates AND103~AND104, 10 counting units Bit 1,0 ~Bit 1,9 ; The input terminal of INV101 is used to input CN1 in the pixel reset phase and CN3 in the pixel exposure phase; Input terminal 1 of AND103 is connected to the timing signal CLK, and input terminal 2 is connected to Logic1; Input terminal 1 of AND104 is connected to the reset signal Count_RB, and input terminal 2 is connected to Logic1; Input terminal 1 of NAND102 is connected to the output terminal of INV101, input terminal 2 is connected to the timing signal Count_pulse, and input terminal 3 is connected to the output terminal of AND103; Bit 1,0 ~Bit 1,9 The reset terminal is connected to the output terminal of AND104, the control terminal 1 is connected to the inverted signal BW1, and the control terminal 2 is connected to the inverted signal BW2; 1,0 The input end is connected to the output end of NAND102; the n+1th counting unit Bit 1,n+1 The input end is connected to the nth counting unit Bit 1,n Output terminal; n∈[1,8]; Bit 1,m The output terminal is used to output the m+1th bit D of D1[9:0]. 1,m ; m∈[1,9]; COUNTER2 includes: 1 inverter INV201, 1 NAND gate NAND202, 2 AND gates AND203~AND204, 10 counting units Bit 2,0 ~Bit 2,9 ; The input terminal of INV201 is used to input CN1 in the pixel reset phase and CN3 in the pixel exposure phase; Input terminal 1 of AND203 is connected to the timing signal CLK, and input terminal 2 is connected to Logic2; Input terminal 1 of AND204 is connected to the reset signal Count_RB, and input terminal 2 is connected to Logic2; Input terminal 1 of NAND202 is connected to the output terminal of INV201, input terminal 2 is connected to the timing signal Count_pulse, and input terminal 3 is connected to the output terminal of AND203; Bit 2,0 ~Bit 2,9 The reset terminal is connected to the output terminal of AND204, the control terminal 1 is connected to the inverted signal BW1, and the control terminal 2 is connected to the inverted signal BW2; 2,0 The input end is connected to the output end of NAND202; the n+1th counting unit Bit 2,n+1 The input end is connected to the nth counting unit Bit 2,n Output terminal of Bit 2,m The output terminal is used to output the m+1th bit D of D2[9:0]. 2,m .

8. The multi-sampling SS-ADC circuit based on slope noise adaptation according to claim 7, characterized in that: Bit 1,0 ~Bit 1,9 、Bit 2,0 ~Bit 2,9 The circuit structures are the same, and both include: a bitwise inversion unit BWI and a trigger DFF; wherein, BWI includes: three PMOS tubes P1~P3 and three NMOS tubes M4~M6; In any bitwise inversion unit: the gates of P1 and M5 serve as the In terminal of the bitwise inversion unit; the gates of P3 and M4 serve as the control terminal 1 of the bitwise inversion unit; the gates of P2 and M6 serve as the control terminal 2 of the bitwise inversion unit; the sources of P1 and P2 are connected to the power supply VDD; the source of P3 is connected to the drains of P1 and P2; the drain of P3 is connected to the drains of M4 and M5 and serves as the Out terminal of the bitwise inversion unit; the source of M4 is grounded; the source of M5 is connected to the drain of M6; the source of M6 is grounded; In any counting unit: the In terminal of BWI serves as the input terminal of the counting unit; the control terminal 1 of BWI serves as the control terminal 1 of the counting unit; the control terminal 2 of BWI serves as the control terminal 2 of the counting unit; the Out terminal of BWI is connected to the clk terminal of DFF; the Reset terminal of DFF serves as the reset terminal of the counting unit; the D terminal of DFF is connected to its inverting Q terminal and serves as the output terminal of the counting unit.

9. The multi-sampling SS-ADC circuit based on slope noise adaptation according to claim 1, characterized in that: SELECT includes: 10 two-to-one selectors MUX0~MUX9, 10 D flip-flops DFF0~DFF9; The selection terminals of MUX0~MUX9 are used to input CN2; The clk terminals of DFF0~DFF9 are all connected to the timing signal Latch_EN; MUX p Input terminal 1 is used to input the p+3th bit D1[p+2] of D1[9:0], and input terminal 2 is used to input the p+1th bit D2[p] of D2[9:0]; DFF p The D terminal is connected to MUX p The output terminal Q is used to output the p+1th bit OUT[p] of OUT[9:0]; p∈[0,7]; MUX q Input terminal 1 of DFF is used to input 0, and input terminal 2 is used to input the q+1th bit D2[q] of D2[9:0]; q The D terminal is connected to MUX q The output terminal Q is used to output the q+1th bit OUT[q] of OUT[9:0]; q∈[8,9].

10. A multi-sampling SS-ADC module based on slope noise adaptation, characterized in that: It adopts the layout of a multi-sampling SS-ADC circuit based on slope noise adaptation as described in any one of claims 1-9.

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