Comparator with high performance and use method thereof

Abstract

The invention provides a comparator with high performance and a use method thereof, the comparator comprises a signal amplification module and a latch comparison module, the signal amplification module carries out cascade amplification on a differential input signal to obtain a differential transition signal so as to meet the signal input range of the subsequent latch comparison module, and the signal input range of the latch comparison module is improved. And the differential transition signal is latched through the latch comparison module, so that the signal processing speed of the comparator is improved, and a differential output signal is output to the outside. According to the comparator provided by the invention, the input signal is firstly amplified, the amplified input signal is input to the latch comparator, rapid and efficient comparison is completed, the output end outputs high and low levels respectively, and meanwhile, the requirements of speed and precision are met.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuits, and in particular to a high-performance comparator and a method for using the same. Background Art

[0002] With the continuous development of the current information age, the position of analog-to-digital converter (ADC) in modern science and technology has become increasingly prominent. Successive approximation analog-to-digital converters have been widely used in various applications due to their high precision, low power consumption and better adaptability to mixed analog-digital circuits under advanced processes. The high-precision comparator is the core part of the successive approximation analog-to-digital converter (SAR ADC). By comparing the input voltage at both ends of the comparator with the reference voltage and obtaining the logic level for subsequent circuit judgment. The minimum resolution of the comparator directly reflects the minimum input signal difference that the converter can recognize. In addition to the capacitor array, the comparator is another important analog circuit module that limits the performance of the high-precision SAR ADC. Therefore, in the design of the high-precision SAR ADC, the design of the high-precision comparator is a crucial link. In the related art, the comparator structure mostly adopts a single-stage amplifier or a latch comparator, but these structures have certain limitations in terms of accuracy, speed and power consumption, and cannot meet the use of SAR ADC in some high-speed and high-precision scenarios.

[0003] Therefore, how to provide a comparator with high precision, high speed and low power consumption is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present invention provides a technical solution of a comparator with high performance to solve at least one of the above-mentioned technical problems.

[0005] In order to achieve the above-mentioned purpose and other related purposes, the technical solution provided by this application is as follows.

[0006] According to a first aspect of an embodiment of the present application, a high-performance comparator is provided, comprising:

[0007] A signal amplification module receives a differential input signal and a calibration signal, performs cascade amplification on the differential input signal to obtain a differential transition signal, and corrects mismatch information generated by the cascade amplification based on the calibration signal;

[0008] The latch comparison module receives the differential transition signal and performs latch processing on the differential transition signal to obtain a differential output signal.

[0009] In one embodiment of the present application, the signal amplification module includes a single or multiple cascaded differential amplifiers, and the differential amplifier includes a sampling subunit, an amplification subunit and a calibration subunit. The sampling subunit is connected to the differential input signal and samples the differential input signal. The amplification subunit is connected to the sampling subunit and amplifies the differential input signal sampled by the sampling subunit to obtain a differential transition signal. The calibration subunit is connected to the output end of the amplification subunit, the information storage signal and the first reset signal, and corrects the mismatch information of the signal amplification module according to the information storage signal and the first reset signal.

[0010] In one embodiment of the present application, the sampling subunit includes a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube, the source of the first PMOS tube is connected to the source of the second PMOS tube, the source of the first PMOS tube is also connected to a first reference voltage, the drain of the first PMOS tube is connected to the source of the third PMOS tube, the drain of the second PMOS tube is connected to the source of the fourth PMOS tube, the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube, and the gate of the third PMOS tube is also connected to a second reference voltage, wherein the gate of the first PMOS tube and the gate of the second PMOS tube cooperate to input the differential input signal, and the drain of the third PMOS tube and the drain of the fourth PMOS tube output the differential transition signal to the outside.

[0011] In one embodiment of the present application, the amplifying subunit includes a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube, the gate of the first NMOS tube is connected to the gate of the third NMOS tube, the gate of the third NMOS tube is also connected to the drain of the third NMOS tube, the drain of the first NMOS tube is connected to the drain of the fourth NMOS tube, the source of the first NMOS tube is grounded, the source of the third NMOS tube is connected to the source of the first NMOS tube, the drain of the second NMOS tube is connected to the drain of the third NMOS tube, the gate of the second NMOS tube is connected to the gate of the fourth NMOS tube, the gate of the fourth NMOS tube is also connected to the drain of the fourth NMOS tube, the source of the second NMOS tube is connected to the source of the first NMOS tube, and the source of the fourth NMOS tube is connected to the source of the first NMOS tube, wherein the gate of the first NMOS tube and the gate of the second NMOS tube cooperate to input the differential transition signal, and the drain of the third NMOS tube and the drain of the fourth NMOS tube output the differential transition signal to the outside.

[0012] In an embodiment of the present application, the transconductance of the first NMOS transistor and the second NMOS transistor is smaller than the transconductance of the third NMOS transistor and the fourth NMOS transistor.

[0013] In one embodiment of the present application, the calibration subunit includes a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a first capacitor, a second capacitor, and a first reset switch, wherein a first end of the first reset switch is connected to the drain of the fifth NMOS tube, the drain of the fifth NMOS tube is also connected to the drain of the sixth NMOS tube, the source of the fifth NMOS tube is connected to the gate of the sixth NMOS tube, the source of the fifth NMOS tube is also connected to the first end of the first capacitor, the second end of the first capacitor is connected to the source of the sixth NMOS tube, the source of the sixth NMOS tube is grounded, and the second end of the first reset switch is connected to the seventh NMOS The drain of the fifth NMOS tube is connected to the drain of the differential transition signal, the drain of the seventh NMOS tube is also connected to the drain of the eighth NMOS tube, the source of the seventh NMOS tube is connected to the gate of the eighth NMOS tube, the source of the seventh NMOS tube is also connected to the first end of the second capacitor, the second end of the second capacitor is connected to the source of the eighth NMOS tube, and the source of the eighth NMOS tube is grounded, wherein the drain of the fifth NMOS tube is connected to the first end of the differential transition signal, the drain of the seventh NMOS tube is connected to the second end of the differential transition signal, the gate of the fifth NMOS tube and the gate of the seventh NMOS tube are connected to the information storage signal, and the control end of the first reset switch is connected to the first reset signal.

[0014] In one embodiment of the present application, the latch comparison module includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a ninth NMOS tube, a tenth NMOS tube, a first sampling switch, a second sampling switch, and a second reset switch. The source of the fifth PMOS tube is connected to the power supply voltage, the drain of the fifth PMOS tube is connected to the source of the sixth PMOS tube, the source of the sixth PMOS tube is also connected to the source of the seventh PMOS tube, the gate of the sixth PMOS tube is connected to the drain of the seventh PMOS tube, the gate of the seventh PMOS tube is connected to the drain of the sixth PMOS tube, the first end of the first sampling switch is connected to the drain of the sixth PMOS tube, the drain of the sixth PMOS tube is also connected to the drain of the ninth NMOS tube, the drain of the ninth NMOS tube is connected to the gate of the tenth NMOS tube, and the drain of the seventh PMOS tube is connected to the second sampling switch. The first end of the second sampling switch is connected to the drain of the ninth NMOS tube, the drain of the tenth NMOS tube is also connected to the gate of the ninth NMOS tube, the source of the ninth NMOS tube is connected to the source of the tenth NMOS tube, the source of the tenth NMOS tube is grounded, the first end of the second reset switch is connected to the drain of the ninth NMOS tube, the second end of the second reset switch is connected to the drain of the tenth NMOS tube, wherein the second end of the first sampling switch and the second end of the second sampling switch cooperate to input the differential transition signal, the drain of the ninth NMOS tube and the drain of the tenth NMOS tube output the differential output signal to the outside, the gate of the fifth PMOS tube is connected to the clock signal, the control end of the first sampling switch and the control end of the second sampling switch are connected to the sampling signal, and the control end of the second reset switch is connected to the second reset signal.

[0015] According to a second aspect of an embodiment of the present application, a method for using a high-performance comparator is provided, and the method for using the high-performance comparator described above includes:

[0016] cascade amplifying the differential input signal to obtain the differential transition signal, and then correcting the mismatch information based on the calibration signal;

[0017] The differential transition signal is latched to obtain the differential output signal.

[0018] In one embodiment of the present application, the calibration signal includes an information storage signal and a first reset signal, and the mismatch information is corrected based on the calibration signal, including: generating a mismatch voltage corresponding to the mismatch information based on the information storage signal; connecting two differential output terminals of the signal amplification module according to the first reset signal, and resetting the two differential output terminals according to the mismatch voltage.

[0019] In an embodiment of the present application, after latching the differential transition signal, the method further includes: resetting the output end of the latch comparison module according to a second reset signal.

[0020] The present application provides a high-performance comparator and a method for using the same. The comparator includes a signal amplification module and a latch comparison module. The signal amplification module performs cascade amplification on a differential input signal to obtain a differential transition signal to meet the signal input range of a subsequent latch comparison module. The latch comparison module performs latch processing on the differential transition signal to improve the signal processing speed of the comparator and output a differential output signal to the outside. The comparator provided by the present application first amplifies the input signal, and the amplified input signal is input to the latch comparator to complete a fast and efficient comparison. The output end outputs high and low levels respectively, while meeting the requirements of speed and accuracy.

[0021] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0023] Figure 1 is a block diagram of a high-performance comparator shown in an exemplary embodiment of the present invention;

[0024] Figure 2 is a specific circuit structure of a differential amplifier shown in an exemplary embodiment of the present invention;

[0025] Figure 3 It is a specific circuit structure of a latch comparison module shown in an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will describe the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, not for limiting the scope of protection of the present invention.

[0027] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0028] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0029] With the continuous development of the current information age, the position of analog-to-digital converter (ADC) in modern science and technology has become increasingly prominent. The analog-to-digital converter can convert analog signals such as sound and images in reality into digital signals, and then these digital signals are processed by electronic devices to realize circuit functions. ADC can be divided into several types, such as successive approximation register (SAR ADC), pipeline analog-to-digital converter (PipeLine ADC), flash analog-to-digital converter (FLash ADC) and high-resolution analog-to-digital converter (Sigma DeLtaADC). SAR ADC has a relatively simple structure of its analog circuit part. Compared with analog-to-digital converters of other structures, the successive approximation analog-to-digital converter has been widely used in various applications due to its high precision, low power consumption and more adaptability to digital-analog hybrid circuits under advanced processes.

[0030] The high-precision comparator is the core part of the high-precision SAR ADC. By comparing the input voltage at both ends of the comparator with the reference voltage, the logic level is obtained for the judgment of the subsequent circuit. The minimum resolution of the comparator directly reflects the minimum input signal difference that the converter can recognize. In addition to the capacitor array DAC, the comparator is another important analog circuit module that limits the performance of the high-precision SAR ADC. Therefore, in the design of the high-precision SAR ADC, the high-precision comparator is the key to the design. Generally, a high-speed and high-precision comparator needs to have the characteristics of small offset voltage, high gain and fast comparison speed. In the existing SAR ADC, the comparator structure mostly adopts a single-stage amplifier or a latch comparator, but these structures have certain limitations in terms of accuracy, speed and power consumption. Therefore, it is necessary to study the design of high-speed and high-precision comparators.

[0031] Commonly used comparator structures include open-loop comparators and latch comparators. Open-loop comparators have high precision and can distinguish smaller input signals, but the comparison speed is slow; latch comparators have fast comparison speeds but low precision and can only distinguish larger input signals. In high-speed and high-precision applications, each comparator cannot meet the requirements when used alone.

[0032] To solve the above problems, the present application provides a comparator which has high precision and fast comparison speed. The comparator includes a signal amplification module and a latch comparison module. The signal amplification module cascades the differential input signal to obtain a differential transition signal to meet the signal input range of the subsequent latch comparison module. The latch comparison module latches the differential transition signal to improve the signal processing speed of the comparator and outputs the differential output signal to the outside.

[0033] like Figure 1 As shown, the present application provides a comparator with high performance, comprising:

[0034] Signal amplifier module, connected to differential input signal (V INN -V INP ) and calibration signal, for differential input signal (V INN -V INP ) is cascaded to obtain the differential transition signal (V DN -V DP ), correcting the mismatch information generated by the cascade amplification based on the calibration signal;

[0035] Latch comparison module, connected to the differential transition signal (V DN -V DP ), for the differential transition signal (V DN -V DP ) is latched to obtain a differential output signal (V OUTN -V OUTP ).

[0036] In detail, the calibration signal includes an information storage signal and a first reset signal. The signal amplification module includes a single or multiple cascaded differential amplifiers (ANMP_A1...ANMP_AN). The differential amplifier includes a sampling subunit, an amplification subunit and a calibration subunit. The sampling subunit is connected to a differential input signal (V INN -V INP ), for differential input signals (V INN -V INP ) for sampling; the amplifying subunit is connected to the sampling subunit, and the differential input signal (V INN -V INP ) is amplified to obtain the differential transition signal (V DN -VDP ); the calibration subunit is connected to the output end of the amplification subunit, the information storage signal and the first reset signal, and the calibration subunit corrects the mismatch information of the signal amplification module according to the information storage signal and the first reset signal.

[0037] like Figure 2 As shown, the sampling subunit includes a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3 and a fourth PMOS tube MP4, the source of the first PMOS tube MP1 is connected to the source of the second PMOS tube MP2, the source of the first PMOS tube MP1 is also connected to the first reference voltage Vbias1, the drain of the first PMOS tube MP1 is connected to the source of the third PMOS tube MP3, the drain of the second PMOS tube MP2 is connected to the source of the fourth PMOS tube MP4, the gate of the third PMOS tube MP3 is connected to the gate of the fourth PMOS tube MP4, and the gate of the third PMOS tube MP3 is also connected to the second reference voltage Vbias2, wherein the gate of the first PMOS tube MP1 and the gate of the second PMOS tube MP2 cooperate to input a differential input signal (V INN -V INP ), the drain of the third PMOS tube MP3 and the drain of the fourth PMOS tube MP4 output a differential transition signal (V DN -V DP ).

[0038] like Figure 2 As shown, the amplifying subunit includes a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3 and a fourth NMOS tube MN4. The gate of the first NMOS tube MN1 is connected to the gate of the third NMOS tube MN3, the gate of the third NMOS tube MN3 is also connected to the drain of the third NMOS tube MN3, the drain of the first NMOS tube MN1 is connected to the drain of the fourth NMOS tube MN4, the source of the first NMOS tube MN1 is grounded, the source of the third NMOS tube MN3 is connected to the source of the first NMOS tube MN1, The drain of the second NMOS transistor MN2 is connected to the drain of the third NMOS transistor MN3, the gate of the second NMOS transistor MN2 is connected to the gate of the fourth NMOS transistor MN4, the gate of the fourth NMOS transistor MN4 is also connected to the drain of the fourth NMOS transistor MN4, the source of the second NMOS transistor MN2 is connected to the source of the first NMOS transistor MN1, the source of the fourth NMOS transistor MN4 is connected to the source of the first NMOS transistor MN1, wherein the gate of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2 cooperate with the input differential transition signal (V DN -V DP ), the drain of the third NMOS transistor MN3 and the drain of the fourth NMOS transistor MN4 output a differential transition signal (V DN -V DP ).

[0039] In more detail, the transconductance of the first NMOS transistor MN1 and the second NMOS transistor MN2 is smaller than the transconductance of the third NMOS transistor MN3 and the fourth NMOS transistor MN4.

[0040] In detail, Figure 2 As shown, the calibration subunit includes a fifth NMOS tube, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, a first capacitor C1, a second capacitor C2, and a first reset switch Reset1. The first end of the first reset switch Reset1 is connected to the drain of the fifth NMOS tube, the drain of the fifth NMOS tube is also connected to the drain of the sixth NMOS tube MN6, the source of the fifth NMOS tube is connected to the gate of the sixth NMOS tube MN6, the source of the fifth NMOS tube is also connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected to the sixth NMOS tube MN6. 6, the source of the sixth NMOS transistor MN6 is grounded, the second end of the first reset switch Reset1 is connected to the drain of the seventh NMOS transistor MN7, the drain of the seventh NMOS transistor MN7 is also connected to the drain of the eighth NMOS transistor MN8, the source of the seventh NMOS transistor MN7 is connected to the gate of the eighth NMOS transistor MN8, the source of the seventh NMOS transistor MN7 is also connected to the first end of the second capacitor C2, the second end of the second capacitor C2 is connected to the source of the eighth NMOS transistor MN8, the source of the eighth NMOS transistor MN8 is grounded, wherein the drain of the fifth NMOS tube is connected to the first end V DN The drain of the seventh MOS tube is connected to the second end V of the differential transition signal DP The gate of the fifth NMOS tube and the gate of the seventh NMOS tube MN7 are connected to the information storage signal Cal, and the control end of the first reset switch Reset1 is connected to the first reset signal.

[0041] In more detail, Figure 3As shown, the latch comparison module includes a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, a ninth NMOS tube MN9, a tenth NMOS tube MN10, a first sampling switch SW1, a second sampling switch SW2, and a second reset switch Reset2. The source of the fifth PMOS tube MP5 is connected to the power supply voltage VDD, the drain of the fifth PMOS tube MP5 is connected to the source of the sixth PMOS tube MP6, the source of the sixth PMOS tube MP6 is also connected to the source of the seventh PMOS tube MP7, the gate of the sixth PMOS tube MP6 is connected to the drain of the seventh PMOS tube MP7, the gate of the seventh PMOS tube MP7 is connected to the drain of the sixth PMOS tube MP6, the first end of the first sampling switch SW1 is connected to the drain of the sixth PMOS tube MP6, the drain of the sixth PMOS tube MP6 is also connected to the ninth The drain of the NMOS tube MN9, the drain of the ninth NMOS tube MN9 is connected to the gate of the tenth NMOS tube MN10, the drain of the seventh PMOS tube MP7 is connected to the first end of the second sampling switch SW2, the drain of the seventh PMOS tube MP7 is also connected to the drain of the tenth NMOS tube MN10, the drain of the tenth NMOS tube MN10 is also connected to the gate of the ninth NMOS tube MN9, the source of the ninth NMOS tube MN9 is connected to the source of the tenth NMOS tube MN10, the source of the tenth NMOS tube MN10 is grounded, the first end of the second reset switch Reset2 is connected to the drain of the ninth NMOS tube MN9, the second end of the second reset switch Reset2 is connected to the drain of the tenth NMOS tube MN10, wherein the second end of the first sampling switch SW1 and the second end of the second sampling switch SW2 cooperate with the input differential transition signal (V DN -V DP ), the drain of the ninth NMOS transistor MN9 and the drain of the tenth NMOS transistor MN10 output a differential output signal (V OUTN -V OUTP ), the gate of the fifth PMOS transistor MP5 is connected to the clock signal CLK, the control end of the first sampling switch SW1 and the control end of the second sampling switch SW2 are connected to the sampling signal, and the control end of the second reset switch Reset2 is connected to the second reset signal.

[0042] like Figure 1-Figure 3 As shown, the working principle of the comparator provided by this application is as follows:

[0043] The differential input signal (V INN -V INP ) for multi-stage amplification or single-stage amplification to obtain a differential transition signal (V DN -V DP ), the latch comparison module compares the differential transition signal (V DN -V DP ) to latch and compare the output, and obtain the differential output signal (VOUTN -V OUTP ).

[0044] If the successive approximation analog-to-digital converter is 16 bits and the power supply voltage is 5V, in order to achieve the output accuracy requirement, the resolution of the comparator must be able to distinguish at least 1 / 2LSB of the voltage value, that is, the resolution must be at least 38μV. In order to achieve such accuracy and the sampling rate requirement of 2MSPS while avoiding excessive power consumption, two differential amplifiers are required.

[0045] The sampling subunit samples the differential input signal (V INN -V INP ) is collected, and the input and output ends of the differential amplifier are isolated through the third PMOS tube MP3 and the fourth PMOS tube MP4 to reduce the kickback noise. The first PMOS tube MP1 and the second PMOS tube MP2 adopt preset sizes, which are conducive to improving matching, reducing offset, and reducing the impact of input noise on the circuit. A weak positive feedback connection is formed by the first NMOS tube MN1 and the second NMOS tube MN2 in the amplifying subunit, and the third NMOS tube MN3 and the fourth NMOS tube MN4 form a negative feedback connection. The transconductance of the first NMOS tube MN1 and the second NMOS tube MN2 is greater than the transconductance of the third NMOS tube MN3 and the fourth NMOS tube MN4, so that the negative feedback is stronger than the positive feedback, and the amplifying subunit responds to the differential input signal (V INN -V INP ) is amplified, and the differential transition signal of the first stage is input externally. After the differential transition signal has been sampled by the differential amplifier or latch comparison module of the next stage, the gate input information storage signal Cal of the fifth NMOS tube MN5 and the seventh NMOS tube MN7 in the calibration subunit is used to record the mismatch information of the signal amplification module through the first capacitor C1 and the second capacitor C2 respectively. When the mismatch voltage corresponding to the mismatch information (the voltage value stored in the first capacitor C1 and the second capacitor C2) is equal to or greater than the preset threshold voltage, the first reset switch Reset1 is closed through the first reset signal, and the sixth NMOS tube MN6 and the eighth NMOS tube MN8 are turned on, so as to correct the mismatch information of the signal amplification module and pull the output terminal voltage of the signal amplification module down to the ground. Similarly, the working principle of the second stage differential amplifier is the same and will not be repeated here.

[0046] First, a low-level clock signal CLK and a high-level sampling signal are input, the fifth PMOS tube MP5 in the latch comparison module is turned on, the first sampling switch SW1 and the second sampling switch SW2 are closed, and the latch comparison unit samples the differential transition signal output by the signal amplification unit. The latch comparison module is in a sampling state, and the static power consumption is zero; secondly, the clock signal CLK jumps to a high level, the sampling signal jumps to a low level, the fifth PMOS tube MP5 is turned off, the first sampling switch SW1 and the second sampling switch SW2 are turned off, the latch comparison module compares and latches the differential transition signal, and the output signal of the latch comparison module is independent of the input signal, and a differential output signal (V OUTN -V OUTP ); Finally, when the output end of the latch comparison module generates a high level, a high level second reset signal is immediately generated to reset the latch comparison module, pull the voltage of the output end down to the ground, and wait for the next clock signal to perform latch processing.

[0047] The present application also provides a method for using a high-performance comparator, comprising:

[0048] For differential input signals (V INN -V INP ) performs cascade amplification to obtain a differential transition signal, and corrects the mismatch information based on the calibration signal;

[0049] The differential transition signal is latched to obtain a differential output signal.

[0050] In detail, the calibration signal includes an information storage signal and a first reset signal, and the mismatch information is corrected based on the calibration signal, including: generating a mismatch voltage corresponding to the mismatch information based on the information storage signal Cal; connecting the two differential output terminals of the signal amplification module according to the first reset signal, and resetting the two differential output terminals according to the mismatch voltage. Specifically, the mismatch information of the output terminal of the amplification comparison module is stored by the information storage signal, that is, the mismatch information is stored on the first capacitor C1 and the second capacitor C2. When the mismatch voltage of the first capacitor C1 and the second capacitor C2 is equal to or greater than the preset threshold voltage, the first reset switch is turned on according to the first reset signal, and the output terminal of the amplification comparison module is reset to eliminate the mismatch information of the amplification comparison module, so as to facilitate the subsequent amplification output of the signal and improve the accuracy of the comparator.

[0051] In more detail, after the differential transition signal is latched, the method further includes: resetting the output end of the latch comparison module according to the second reset signal. Specifically, when the output end of the latch comparison module generates a high level, a high-level second reset signal is generated, and the second reset switch Reset2 is closed to reset the output end of the latch comparison module, thereby pulling the voltage of the output end down to the ground.

[0052] The present application provides a high-performance comparator and a method for using the same. The comparator includes a signal amplification module and a latch comparison module. The signal amplification module performs cascade amplification on a differential input signal to obtain a differential transition signal to meet the signal input range of a subsequent latch comparison module. The latch comparison module performs latch processing on the differential transition signal to improve the signal processing speed of the comparator and output a differential output signal to the outside. The comparator provided by the present application first amplifies the input signal, and the amplified input signal is input to the latch comparator to complete a fast and efficient comparison. The output terminal outputs high and low levels respectively, which meets the requirements of speed and accuracy at the same time, and is low in cost.

[0053] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A comparator with high performance, characterized in that: include: A signal amplification module receives a differential input signal and a calibration signal, performs cascade amplification on the differential input signal to obtain a differential transition signal, and corrects mismatch information generated by the cascade amplification based on the calibration signal; The latch comparison module receives the differential transition signal and performs latch processing on the differential transition signal to obtain a differential output signal.

2. The high performance comparator according to claim 1, characterized in that: The calibration signal includes an information storage signal and a first reset signal. The signal amplification module includes a single or multiple cascaded differential amplifiers. The differential amplifier includes a sampling subunit, an amplification subunit and a calibration subunit. The sampling subunit is connected to the differential input signal to sample the differential input signal; the amplification subunit is connected to the sampling subunit to amplify the differential input signal sampled by the sampling subunit to obtain a differential transition signal; the calibration subunit is connected to the output end of the amplification subunit, the information storage signal and the first reset signal, and resets and corrects the output end of the amplification subunit according to the information storage signal and the first reset signal.

3. The high performance comparator according to claim 2, characterized in that: The sampling subunit includes a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube, wherein the source of the first PMOS tube is connected to the source of the second PMOS tube, the source of the first PMOS tube is also connected to a first reference voltage, the drain of the first PMOS tube is connected to the source of the third PMOS tube, the drain of the second PMOS tube is connected to the source of the fourth PMOS tube, the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube, and the gate of the third PMOS tube is also connected to a second reference voltage, wherein the gate of the first PMOS tube and the gate of the second PMOS tube cooperate to input the differential input signal, and the drain of the third PMOS tube and the drain of the fourth PMOS tube output the differential transition signal to the outside.

4. The high performance comparator according to claim 2, characterized in that: The amplifying subunit includes a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube, wherein the gate of the first NMOS tube is connected to the gate of the third NMOS tube, the gate of the third NMOS tube is also connected to the drain of the third NMOS tube, the drain of the first NMOS tube is connected to the drain of the fourth NMOS tube, the source of the first NMOS tube is grounded, the source of the third NMOS tube is connected to the source of the first NMOS tube, the drain of the second NMOS tube is connected to the drain of the third NMOS tube, the gate of the second NMOS tube is connected to the gate of the fourth NMOS tube, the gate of the fourth NMOS tube is also connected to the drain of the fourth NMOS tube, the source of the second NMOS tube is connected to the source of the first NMOS tube, and the source of the fourth NMOS tube is connected to the source of the first NMOS tube, wherein the gate of the first NMOS tube and the gate of the second NMOS tube cooperate to input the differential transition signal, and the drain of the third NMOS tube and the drain of the fourth NMOS tube output the differential transition signal to the outside.

5. The high performance comparator according to claim 4, characterized in that: The transconductance of the first NMOS tube and the second NMOS tube is smaller than the transconductance of the third NMOS tube and the fourth NMOS tube.

6. The high performance comparator according to claim 2, characterized in that: The calibration subunit includes a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a first capacitor, a second capacitor, and a first reset switch. The first end of the first reset switch is connected to the drain of the fifth NMOS tube, the drain of the fifth NMOS tube is also connected to the drain of the sixth NMOS tube, the source of the fifth NMOS tube is connected to the gate of the sixth NMOS tube, the source of the fifth NMOS tube is also connected to the first end of the first capacitor, the second end of the first capacitor is connected to the source of the sixth NMOS tube, the source of the sixth NMOS tube is grounded, the second end of the first reset switch is connected to the drain of the seventh NMOS tube, and the The drain of the seventh NMOS tube is also connected to the drain of the eighth NMOS tube, the source of the seventh NMOS tube is connected to the gate of the eighth NMOS tube, the source of the seventh NMOS tube is also connected to the first end of the second capacitor, the second end of the second capacitor is connected to the source of the eighth NMOS tube, and the source of the eighth NMOS tube is grounded, wherein the drain of the fifth NMOS tube is connected to the first end of the differential transition signal, the drain of the seventh NMOS tube is connected to the second end of the differential transition signal, the gate of the fifth NMOS tube and the gate of the seventh NMOS tube are connected to the information storage signal, and the control end of the first reset switch is connected to the first reset signal.

7. The high performance comparator according to claim 1, characterized in that: The latch comparison module includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a ninth NMOS tube, a tenth NMOS tube, a first sampling switch, a second sampling switch, and a second reset switch. The source of the fifth PMOS tube is connected to the power supply voltage, the drain of the fifth PMOS tube is connected to the source of the sixth PMOS tube, the source of the sixth PMOS tube is also connected to the source of the seventh PMOS tube, the gate of the sixth PMOS tube is connected to the drain of the seventh PMOS tube, the gate of the seventh PMOS tube is connected to the drain of the sixth PMOS tube, the first end of the first sampling switch is connected to the drain of the sixth PMOS tube, the drain of the sixth PMOS tube is also connected to the drain of the ninth NMOS tube, the drain of the ninth NMOS tube is connected to the gate of the tenth NMOS tube, and the drain of the seventh PMOS tube is connected to the first end of the second sampling switch. The drain of the seventh PMOS tube is also connected to the drain of the tenth NMOS tube, the drain of the tenth NMOS tube is also connected to the gate of the ninth NMOS tube, the source of the ninth NMOS tube is connected to the source of the tenth NMOS tube, the source of the tenth NMOS tube is grounded, the first end of the second reset switch is connected to the drain of the ninth NMOS tube, the second end of the second reset switch is connected to the drain of the tenth NMOS tube, wherein the second end of the first sampling switch and the second end of the second sampling switch cooperate to input the differential transition signal, the drain of the ninth NMOS tube and the drain of the tenth NMOS tube output the differential output signal to the outside, the gate of the fifth PMOS tube is connected to the clock signal, the control end of the first sampling switch and the control end of the second sampling switch are connected to the sampling signal, and the control end of the second reset switch is connected to the second reset signal.

8. A method for using a high performance comparator, characterized in that: A high performance comparator as claimed in any one of claims 1 to 7, comprising: cascade amplifying the differential input signal to obtain the differential transition signal, and then correcting the mismatch information based on the calibration signal; The differential transition signal is latched to obtain the differential output signal.

9. The method for using a high-performance comparator according to claim 8, characterized in that: The calibration signal includes an information storage signal and a first reset signal, and correcting the mismatch information based on the calibration signal includes: generating a mismatch voltage corresponding to the mismatch information based on the information storage signal; The two output ends of the signal amplification module are connected according to the first reset signal, and the two output ends are reset according to the mismatch voltage.

10. The method for using a high-performance comparator according to claim 8, characterized in that: After latching the differential transition signal, the method further includes: resetting the output end of the latch comparison module according to a second reset signal.

Images